[llvm] [llvm][SPIRV] Allow casts between AS9 and other AS (PR #194650)

[via llvm-commits]

github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

<details>
<summary>
You can test this locally with the following command:
</summary>

``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp --diff_from_common_commit
``````````

:warning:
The reproduction instructions above might return results for more than one PR
in a stack if you are using a stacked PR workflow. You can limit the results by
changing `origin/main` to the base branch/commit you want to compare against.
:warning:

</details>

<details>
<summary>
View the diff from clang-format here.
</summary>

``````````diff
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index ed0dc1970..74b3aa3fb 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -2599,7 +2599,8 @@ bool SPIRVInstructionSelector::selectAddrSpaceCast(Register ResVReg,
                    ? static_cast<uint32_t>(SPIRV::Opcode::GenericCastToPtr)
                    : 0);
 
-    // Handle CodeSectionINTEL in constant context with SPV_INTEL_function_pointers.
+    // Handle CodeSectionINTEL in constant context with
+    // SPV_INTEL_function_pointers.
     if (STI.canUseExtension(SPIRV::Extension::SPV_INTEL_function_pointers) &&
         !SpecOpcode) {
       if (SrcSC == SPIRV::StorageClass::CodeSectionINTEL &&
@@ -2610,28 +2611,38 @@ bool SPIRVInstructionSelector::selectAddrSpaceCast(Register ResVReg,
         SpecOpcode = static_cast<uint32_t>(SPIRV::Opcode::GenericCastToPtr);
       } else if (SrcSC == SPIRV::StorageClass::CodeSectionINTEL &&
                  DstSC != SPIRV::StorageClass::CodeSectionINTEL) {
-        // For P9 -> other address spaces, cast through Generic via two OpSpecConstantOp.
-        Register GenericTypeReg = getUcharPtrTypeReg(I, SPIRV::StorageClass::Generic);
-        Register IntermediateReg = MRI->createVirtualRegister(&SPIRV::IDRegClass);
-
-        buildSpecConstantOp(I, IntermediateReg, SrcPtr, GenericTypeReg,
-                            static_cast<uint32_t>(SPIRV::Opcode::PtrCastToGeneric))
+        // For P9 -> other address spaces, cast through Generic via two
+        // OpSpecConstantOp.
+        Register GenericTypeReg =
+            getUcharPtrTypeReg(I, SPIRV::StorageClass::Generic);
+        Register IntermediateReg =
+            MRI->createVirtualRegister(&SPIRV::IDRegClass);
+
+        buildSpecConstantOp(
+            I, IntermediateReg, SrcPtr, GenericTypeReg,
+            static_cast<uint32_t>(SPIRV::Opcode::PtrCastToGeneric))
             .constrainAllUses(TII, TRI, RBI);
-        buildSpecConstantOp(I, ResVReg, IntermediateReg, getUcharPtrTypeReg(I, DstSC),
-                            static_cast<uint32_t>(SPIRV::Opcode::GenericCastToPtr))
+        buildSpecConstantOp(
+            I, ResVReg, IntermediateReg, getUcharPtrTypeReg(I, DstSC),
+            static_cast<uint32_t>(SPIRV::Opcode::GenericCastToPtr))
             .constrainAllUses(TII, TRI, RBI);
         return true;
       } else if (DstSC == SPIRV::StorageClass::CodeSectionINTEL &&
                  SrcSC != SPIRV::StorageClass::CodeSectionINTEL) {
-        // For other address spaces -> P9, cast through Generic via two OpSpecConstantOp.
-        Register GenericTypeReg = getUcharPtrTypeReg(I, SPIRV::StorageClass::Generic);
-        Register IntermediateReg = MRI->createVirtualRegister(&SPIRV::IDRegClass);
-
-        buildSpecConstantOp(I, IntermediateReg, SrcPtr, GenericTypeReg,
-                            static_cast<uint32_t>(SPIRV::Opcode::PtrCastToGeneric))
+        // For other address spaces -> P9, cast through Generic via two
+        // OpSpecConstantOp.
+        Register GenericTypeReg =
+            getUcharPtrTypeReg(I, SPIRV::StorageClass::Generic);
+        Register IntermediateReg =
+            MRI->createVirtualRegister(&SPIRV::IDRegClass);
+
+        buildSpecConstantOp(
+            I, IntermediateReg, SrcPtr, GenericTypeReg,
+            static_cast<uint32_t>(SPIRV::Opcode::PtrCastToGeneric))
             .constrainAllUses(TII, TRI, RBI);
-        buildSpecConstantOp(I, ResVReg, IntermediateReg, getUcharPtrTypeReg(I, DstSC),
-                            static_cast<uint32_t>(SPIRV::Opcode::GenericCastToPtr))
+        buildSpecConstantOp(
+            I, ResVReg, IntermediateReg, getUcharPtrTypeReg(I, DstSC),
+            static_cast<uint32_t>(SPIRV::Opcode::GenericCastToPtr))
             .constrainAllUses(TII, TRI, RBI);
         return true;
       }
@@ -2716,9 +2727,10 @@ bool SPIRVInstructionSelector::selectAddrSpaceCast(Register ResVReg,
     // Any address space <-> P9, cast through Generic as intermediary.
     if (SrcSC == SPIRV::StorageClass::CodeSectionINTEL &&
         DstSC != SPIRV::StorageClass::CodeSectionINTEL) {
-      SPIRVTypeInst GenericPtrTy =
-          GR.changePointerStorageClass(SrcPtrTy, SPIRV::StorageClass::Generic, I);
-      Register Tmp = createVirtualRegister(GenericPtrTy, &GR, MRI, MRI->getMF());
+      SPIRVTypeInst GenericPtrTy = GR.changePointerStorageClass(
+          SrcPtrTy, SPIRV::StorageClass::Generic, I);
+      Register Tmp =
+          createVirtualRegister(GenericPtrTy, &GR, MRI, MRI->getMF());
       BuildMI(BB, I, DL, TII.get(SPIRV::OpPtrCastToGeneric))
           .addDef(Tmp)
           .addUse(GR.getSPIRVTypeID(GenericPtrTy))
@@ -2734,9 +2746,10 @@ bool SPIRVInstructionSelector::selectAddrSpaceCast(Register ResVReg,
 
     if (DstSC == SPIRV::StorageClass::CodeSectionINTEL &&
         SrcSC != SPIRV::StorageClass::CodeSectionINTEL) {
-      SPIRVTypeInst GenericPtrTy =
-          GR.changePointerStorageClass(SrcPtrTy, SPIRV::StorageClass::Generic, I);
-      Register Tmp = createVirtualRegister(GenericPtrTy, &GR, MRI, MRI->getMF());
+      SPIRVTypeInst GenericPtrTy = GR.changePointerStorageClass(
+          SrcPtrTy, SPIRV::StorageClass::Generic, I);
+      Register Tmp =
+          createVirtualRegister(GenericPtrTy, &GR, MRI, MRI->getMF());
       BuildMI(BB, I, DL, TII.get(SPIRV::OpPtrCastToGeneric))
           .addDef(Tmp)
           .addUse(GR.getSPIRVTypeID(GenericPtrTy))

``````````

</details>


https://github.com/llvm/llvm-project/pull/194650