[llvm] [AArch64][llvm] Redefine some insns as an alias of `SYS` (PR #187004)

via llvm-commits llvm-commits at lists.llvm.org
Tue Apr 28 07:27:41 PDT 2026


================
@@ -526,6 +533,45 @@ foo:
   sys #4, c8, c7, #6, x31
 ; CHECK: tlbi vmalls12e1
 
+  sys #3, c7, c2, #7, x2
+; CHECK-ITE: trcit x2
+; CHECK-NO-ITE: sys #3, c7, c2, #7, x2
+
+  sys #3, c7, c7, #2, x20
+; CHECK-GCS: gcsss1 x20
+; CHECK-NO-GCS: sys #3, c7, c7, #2, x20
+  sysl x23, #3, c7, c7, #3
+; CHECK-GCS: gcsss2 x23
+; CHECK-NO-GCS: sysl x23, #3, c7, c7, #3
+  sys #3, c7, c7, #0, x24
+; CHECK-GCS: gcspushm x24
+; CHECK-NO-GCS: sys #3, c7, c7, #0, x24
+  sysl xzr, #3, c7, c7, #1
+; CHECK-GCS: gcspopm
+; CHECK-NO-GCS: sysl xzr, #3, c7, c7, #1
+  sysl x24, #3, c7, c7, #1
+; CHECK-GCS: gcspopm x24
+; CHECK-NO-GCS: sysl x24, #3, c7, c7, #1
+  sys #0, c7, c7, #4
+; CHECK-GCS: gcspushx
+; CHECK-NO-GCS: sys #0, c7, c7, #4
+  sys #0, c7, c7, #5
+; CHECK-GCS: gcspopcx
+; CHECK-NO-GCS: sys #0, c7, c7, #5
+  sys #0, c7, c7, #6
+; CHECK-GCS: gcspopx
+; CHECK-NO-GCS: sys #0, c7, c7, #6
+
+  sys #1, c7, c2, #4
+; CHECK-BRBE: brb iall
+; CHECK-NO-BRBE: sys #1, c7, c2, #4
+  sys #1, c7, c2, #5
+; CHECK-BRBE: brb inj
----------------
CarolineConcatto wrote:

In llvm/test/MC/AArch64/brbe.s should these instructions:
```
brb iall
brb inj
```
be decoded to SYS if +brbe is not available? 
If you look at gcspopx it is being decoded to sys when the feature is not available 
```
gcspopx
// CHECK-INST: gcspopx
// CHECK-ENCODING: encoding: [0xdf,0x77,0x08,0xd5]
// CHECK-ERROR: error: instruction requires: gcs
// CHECK-UNKNOWN:  d50877df sys #0, c7, c7, #6
```

https://github.com/llvm/llvm-project/pull/187004


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