[llvm] [PowerPC] Fix assert which caused by PR 190606 (PR #194040)

[Lei Huang via llvm-commits]

================
@@ -15886,20 +15887,23 @@ SDValue PPCTargetLowering::combineSignExtendSetCC(SDNode *N,
 
   SDLoc dl(N);
   SelectionDAG &DAG = DCI.DAG;
-  EVT VT = N->getValueType(0);
   SDValue X = isNullConstant(LHS) ? RHS : LHS;
   EVT XVT = X.getValueType(); // The type of x in the setcc x, 0, eq.
 
+  if (!Subtarget.isPPC64() && XVT == MVT::i64)
+    return SDValue();
+
   // On PPC64, i32 carry operations use the full 64-bit XER register,
   // so we must use i64 operations to avoid incorrect results.
   // Use i64 operations and truncate the result if needed.
   EVT OpVT = VT;
-  if (Subtarget.isPPC64() && VT == MVT::i32)
+  if (Subtarget.isPPC64()) {
     OpVT = MVT::i64;
 
-  // Zero-extend if input type differs from operation type.
-  if (XVT != OpVT)
-    X = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, X);
+    if (XVT != OpVT)
+      // Zero-extend if input type is not 64bits.
+      X = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, X);
+  }
----------------
lei137 wrote:

nit: I don't think OpVT is needed here.  It's more clear and direct if we just use MVT directly

```suggestion
  // Zero-extend if input type is not 64bits.
  if (Subtarget.isPPC64() && XVT != MVT::i64)
      X = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, X);
```

https://github.com/llvm/llvm-project/pull/194040