[llvm] [AArch64] Add C1-Nano scheduling model (PR #182316)

[via llvm-commits]

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@@ -61,13 +61,19 @@ let FunctionMapper = "AArch64_AM::getShiftType" in {
 // Generic predicates.
 
 // Check for ZR in a register operand.
+def CheckIsReg0Zero : CheckAll<
+                        [CheckIsRegOperand<0>,
+                         CheckAny<
+                           [CheckRegOperand<0, WZR>,
+                            CheckRegOperand<0, XZR>]>]>;
 foreach I = {1-3} in {
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walkerkd wrote:

Sorry I missed your comments in the patch I pushed yesterday.

Now done

https://github.com/llvm/llvm-project/pull/182316