[llvm] e459ce5 - Revert "[PowerPC] Enable using HwMode for instructions (#191051)" (#194464)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 28 06:35:43 PDT 2026
Author: Kai Nacke
Date: 2026-04-28T09:35:38-04:00
New Revision: e459ce50775d9f5923282da3e1c49a90409db270
URL: https://github.com/llvm/llvm-project/commit/e459ce50775d9f5923282da3e1c49a90409db270
DIFF: https://github.com/llvm/llvm-project/commit/e459ce50775d9f5923282da3e1c49a90409db270.diff
LOG: Revert "[PowerPC] Enable using HwMode for instructions (#191051)" (#194464)
This reverts commit 2a83068537786696d4950ce694e7d34480631f48.
It causes test suite failures in the 7zip benchmark.
Added:
Modified:
llvm/lib/Target/PowerPC/P10InstrResources.td
llvm/lib/Target/PowerPC/PPCBack2BackFusion.def
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/lib/Target/PowerPC/PPCMacroFusion.def
llvm/lib/Target/PowerPC/PPCRegisterClasses.td
llvm/lib/Target/PowerPC/PPCRegisterInfo.td
llvm/lib/Target/PowerPC/PPCScheduleP7.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/PowerPC/P10InstrResources.td b/llvm/lib/Target/PowerPC/P10InstrResources.td
index ad4f97e382223..842174239cc4c 100644
--- a/llvm/lib/Target/PowerPC/P10InstrResources.td
+++ b/llvm/lib/Target/PowerPC/P10InstrResources.td
@@ -989,7 +989,8 @@ def : InstRW<[P10W_FX_3C, P10W_DISP_ANY, P10FX_Read, P10FX_Read],
CR6UNSET, CRUNSET, CRXOR,
DST, DST64, DSTT, DSTT64,
DSTST, DSTST64, DSTSTT, DSTSTT64,
- EQV,EQV_rec,
+ EQV, EQV8,
+ EQV8_rec, EQV_rec,
FCPSGND, FCPSGNS,
NAND, NAND8,
NAND8_rec, NAND_rec,
diff --git a/llvm/lib/Target/PowerPC/PPCBack2BackFusion.def b/llvm/lib/Target/PowerPC/PPCBack2BackFusion.def
index 3289bf75dd0ca..043c9e485f122 100644
--- a/llvm/lib/Target/PowerPC/PPCBack2BackFusion.def
+++ b/llvm/lib/Target/PowerPC/PPCBack2BackFusion.def
@@ -69,6 +69,8 @@ FUSION_FEATURE(GeneralBack2Back, hasBack2BackFusion, -1,
CNTTZW8_rec,
CNTTZW_rec,
EQV,
+ EQV8,
+ EQV8_rec,
EQV_rec,
EXTSB,
EXTSB8,
@@ -591,6 +593,8 @@ FUSION_FEATURE(GeneralBack2Back, hasBack2BackFusion, -1,
DSTT,
DSTT64,
EQV,
+ EQV8,
+ EQV8_rec,
EQV_rec,
EXTSB,
EXTSB8,
diff --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
index b54721e934e7d..9b56f958b4c6a 100644
--- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -642,6 +642,9 @@ defm ORC8 : XForm_6r<31, 412, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),
"orc", "$RA, $RST, $RB", IIC_IntSimple,
[(set i64:$RA, (or i64:$RST, (not i64:$RB)))]>;
let isCommutable = 1 in {
+defm EQV8 : XForm_6r<31, 284, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),
+ "eqv", "$RA, $RST, $RB", IIC_IntSimple,
+ [(set i64:$RA, (not (xor i64:$RST, i64:$RB)))]>;
defm XOR8 : XForm_6r<31, 316, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),
"xor", "$RA, $RST, $RB", IIC_IntSimple,
[(set i64:$RA, (xor i64:$RST, i64:$RB))]>;
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index 5674d08fb4473..be78e336b3f3d 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2599,9 +2599,9 @@ defm ORC : XForm_6r<31, 412, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB),
"orc", "$RA, $RST, $RB", IIC_IntSimple,
[(set i32:$RA, (or i32:$RST, (not i32:$RB)))]>;
let isCommutable = 1 in {
-defm EQV : XForm_6r<31, 284, (outs gprc:$RA), (ins gxrc:$RST, gxrc:$RB),
+defm EQV : XForm_6r<31, 284, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB),
"eqv", "$RA, $RST, $RB", IIC_IntSimple,
- [(set XLenVT:$RA, (not (xor XLenVT:$RST, XLenVT:$RB)))]>;
+ [(set i32:$RA, (not (xor i32:$RST, i32:$RB)))]>;
defm XOR : XForm_6r<31, 316, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB),
"xor", "$RA, $RST, $RB", IIC_IntSimple,
[(set i32:$RA, (xor i32:$RST, i32:$RB))]>;
diff --git a/llvm/lib/Target/PowerPC/PPCMacroFusion.def b/llvm/lib/Target/PowerPC/PPCMacroFusion.def
index d96ac795df713..1a61ae23e5d72 100644
--- a/llvm/lib/Target/PowerPC/PPCMacroFusion.def
+++ b/llvm/lib/Target/PowerPC/PPCMacroFusion.def
@@ -54,15 +54,15 @@ FUSION_FEATURE(ArithLogical, hasAddLogicalFusion, -1,
// {and, andc, eqv, nand, nor, or, orc, xor} - {add, subf}
FUSION_FEATURE(LogicalArith, hasLogicalAddFusion, -1,
FUSION_OP_SET(AND, ANDC, EQV, NAND, NOR, OR, ORC, XOR, AND8,
- ANDC8, NAND8, NOR8, OR8, ORC8, XOR8),
+ ANDC8, EQV8, NAND8, NOR8, OR8, ORC8, XOR8),
FUSION_OP_SET(ADD4, ADD8, SUBF, SUBF8))
// Either of {and, andc, eqv, nand, nor, or, orc, xor}
FUSION_FEATURE(Logical, hasLogicalFusion, -1,
FUSION_OP_SET(AND, ANDC, EQV, NAND, NOR, OR, ORC, XOR, AND8,
- ANDC8, NAND8, NOR8, OR8, ORC8, XOR8),
+ ANDC8, EQV8, NAND8, NOR8, OR8, ORC8, XOR8),
FUSION_OP_SET(AND, ANDC, EQV, NAND, NOR, OR, ORC, XOR, AND8,
- ANDC8, NAND8, NOR8, OR8, ORC8, XOR8))
+ ANDC8, EQV8, NAND8, NOR8, OR8, ORC8, XOR8))
// vaddudm - vaddudm
FUSION_FEATURE(VecAdd, hasArithAddFusion, -1, FUSION_OP_SET(VADDUDM),
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterClasses.td b/llvm/lib/Target/PowerPC/PPCRegisterClasses.td
index a08a8a844ad12..dac74eb352d8c 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterClasses.td
+++ b/llvm/lib/Target/PowerPC/PPCRegisterClasses.td
@@ -69,7 +69,7 @@ class PPCGPRRegisterClass<list<ValueType> regTypes, int alignment, dag regList,
// Usage: def spe4rc : PPCRegOperandOnly<"GPRC">;
// Creates: spe4rc RegisterOperand wrapping GPRC, using PPCRegGPRCAsmOperand.
class PPCRegOperandOnly<string regClassName>
- : RegisterOperand<!cast<RegisterClassLike>(regClassName)> {
+ : RegisterOperand<!cast<RegisterClass>(regClassName)> {
let ParserMatchClass =
!cast<AsmOperandClass>(!strconcat("PPCReg", regClassName, "AsmOperand"));
}
@@ -95,7 +95,7 @@ multiclass PPCRegOperand<string predicate, string operandName = ""> {
// Define the RegisterOperand with custom name if provided,
// otherwise use lowercase of NAME.
def !if(!eq(operandName, ""), !tolower(NAME), operandName)
- : RegisterOperand<!cast<RegisterClassLike>(NAME)> {
+ : RegisterOperand<!cast<RegisterClass>(NAME)> {
let ParserMatchClass = !cast<AsmOperandClass>("PPCReg"#NAME#"AsmOperand");
}
}
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
index af11e3b213c24..90c7be4297935 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
@@ -462,12 +462,6 @@ def G8pRC : PPCRegisterClassWithSize<[untyped], 128,
}];
}
-// Register class for operations valid in 32 and 64 bit mode.
-def XLenVT : ValueTypeByHwMode<[PPC32, PPC64],
- [i32, i64]>;
-def GxRC : RegClassByHwMode<[PPC32, PPC64],
- [GPRC, G8RC]>;
-
//===----------------------------------------------------------------------===//
// PowerPC Register Operand Definitions.
@@ -484,7 +478,6 @@ def GxRC : RegClassByHwMode<[PPC32, PPC64],
defm GPRC : PPCRegOperand<"isRegNumber">;
defm G8RC : PPCRegOperand<"isRegNumber">;
-defm GxRC : PPCRegOperand<"isRegNumber">;
defm GPRC_NOR0 : PPCRegOperand<"isRegNumber">;
defm G8RC_NOX0 : PPCRegOperand<"isRegNumber">;
defm SPERC : PPCRegOperand<"isRegNumber">;
@@ -522,6 +515,18 @@ def ptr_rc_nor0 : RegisterOperand<ptr_rc_nor0_by_hwmode> {
let ParserMatchClass = PPCRegGxRCNoR0Operand;
}
+// A version of ptr_rc usable with the asm parser.
+def PPCRegGxRCOperand : AsmOperandClass {
+ let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
+}
+
+def ptr_rc_idx_by_hwmode : RegClassByHwMode<[PPC32, PPC64],
+ [GPRC, G8RC]>;
+
+def ptr_rc_idx : RegisterOperand<ptr_rc_idx_by_hwmode> {
+ let ParserMatchClass = PPCRegGxRCOperand;
+}
+
include "PPCRegisterInfoMMA.td"
include "PPCRegisterInfoDMR.td"
@@ -547,7 +552,7 @@ def memri : Operand<iPTR> {
}
def memrr : Operand<iPTR> {
let PrintMethod = "printMemRegReg";
- let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, gxrc:$offreg);
+ let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg);
let OperandType = "OPERAND_MEMORY";
}
def memrix : Operand<iPTR> { // memri where the imm is 4-aligned.
diff --git a/llvm/lib/Target/PowerPC/PPCScheduleP7.td b/llvm/lib/Target/PowerPC/PPCScheduleP7.td
index 45fa3da97556a..bf7f2f7a9c999 100644
--- a/llvm/lib/Target/PowerPC/PPCScheduleP7.td
+++ b/llvm/lib/Target/PowerPC/PPCScheduleP7.td
@@ -189,7 +189,7 @@ let SchedModel = P7Model in {
NEG, NEG8, NEG8_rec, NEG_rec, NEG8O, NEGO,
ANDI_rec, ANDIS_rec, AND, AND8, AND_rec, AND8_rec,
NAND, NAND8, NAND_rec, NAND8_rec, NOR, NOR8, NOR_rec, NOR8_rec,
- EQV, EQV_rec, ANDC, ANDC8, ANDC_rec, ANDC8_rec,
+ EQV, EQV8, EQV_rec, EQV8_rec, ANDC, ANDC8, ANDC_rec, ANDC8_rec,
ORC, ORC8, ORC_rec, ORC8_rec
)>;
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