[llvm] [AMDGPU] Add amdgcn.av.global.(load|store).b128 intrinsics (PR #191390)

[Sameer Sahasrabuddhe via llvm-commits]

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@@ -1718,6 +1718,27 @@ void SITargetLowering::getTgtMemIntrinsic(SmallVectorImpl<IntrinsicInfo> &Infos,
     Infos.push_back(Info);
     return;
   }
+  case Intrinsic::amdgcn_av_global_load_b128:
+  case Intrinsic::amdgcn_av_global_store_b128: {
+    bool IsStore = IntrID == Intrinsic::amdgcn_av_global_store_b128;
+    Info.opc = IsStore ? ISD::INTRINSIC_VOID : ISD::INTRINSIC_W_CHAIN;
+    Info.memVT = MVT::v4i32;
+    Info.ptrVal = CI.getArgOperand(0);
+    Info.flags |=
+        IsStore ? MachineMemOperand::MOStore : MachineMemOperand::MOLoad;
+    // Pretend to be atomic so that SIMemoryLegalizer::expandStore sets cache
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ssahasra wrote:

I looked into it. The current behaviour is not bad, and it keeps this change simple. There may be room to factor out a common mechanism to manage scopes and cache bits, but that can be taken up as a separate change. In particular, the cache scope used when the syncscope is "workgroup" depends on whether CU mode is enabled or not. It's best to reason about all of this separately and make a common lowering facility.

https://github.com/llvm/llvm-project/pull/191390