[llvm] [SelectionDAG] optimize sdiv with positive divisor and positive magic (PR #189287)
Takashi Idobe via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 28 05:17:37 PDT 2026
https://github.com/Takashiidobe updated https://github.com/llvm/llvm-project/pull/189287
>From d045de9b6af7167a8d7caa93c982fcf610a5ee7f Mon Sep 17 00:00:00 2001
From: Takashiidobe <idobetakashi at gmail.com>
Date: Sat, 11 Apr 2026 20:40:06 -0400
Subject: [PATCH] Optimize sdiv-by-constant when magic is positive and divisor
is positive.
emit SRA + SRA(N0, EltBits-1) + SUB instead of SRL(N0, EltBits-1) + AND + ADD
for non-vector cases.
---
.../CodeGen/SelectionDAG/TargetLowering.cpp | 18 +-
llvm/test/CodeGen/AArch64/alias_mask.ll | 2 +-
.../CodeGen/AArch64/alias_mask_scalable.ll | 2 +-
llvm/test/CodeGen/AArch64/combine-sdiv.ll | 28 +-
llvm/test/CodeGen/AArch64/rem-by-const.ll | 92 ++--
llvm/test/CodeGen/AArch64/srem-lkk.ll | 12 +-
.../AArch64/srem-seteq-illegal-types.ll | 28 +-
llvm/test/CodeGen/AArch64/srem-vector-lkk.ll | 26 +-
...amdgpu-codegenprepare-fold-binop-select.ll | 16 +-
.../AMDGPU/amdgpu-codegenprepare-idiv.ll | 215 ++++----
.../CodeGen/AMDGPU/div-rem-by-constant-64.ll | 184 ++++---
llvm/test/CodeGen/AMDGPU/sdiv.ll | 48 +-
.../AMDGPU/srem-seteq-illegal-types.ll | 18 +-
llvm/test/CodeGen/AMDGPU/srem.ll | 30 +-
llvm/test/CodeGen/AMDGPU/trunc-combine.ll | 24 +-
.../CodeGen/ARM/srem-seteq-illegal-types.ll | 36 +-
llvm/test/CodeGen/Mips/mips64muldiv.ll | 4 +-
.../CodeGen/Mips/srem-seteq-illegal-types.ll | 30 +-
llvm/test/CodeGen/PowerPC/machine-pre.ll | 4 +-
llvm/test/CodeGen/PowerPC/srem-lkk.ll | 38 +-
.../PowerPC/srem-seteq-illegal-types.ll | 62 +--
llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll | 480 +++++++++---------
llvm/test/CodeGen/RISCV/div-by-constant.ll | 200 ++++----
llvm/test/CodeGen/RISCV/div.ll | 70 +--
.../CodeGen/RISCV/rvv/extractelt-int-rv32.ll | 12 +-
.../CodeGen/RISCV/rvv/extractelt-int-rv64.ll | 16 +-
.../RISCV/rvv/fixed-vectors-extract.ll | 56 +-
llvm/test/CodeGen/RISCV/srem-lkk.ll | 12 +-
.../CodeGen/RISCV/srem-seteq-illegal-types.ll | 234 ++++-----
llvm/test/CodeGen/RISCV/srem-vector-lkk.ll | 102 ++--
llvm/test/CodeGen/SPARC/predictable-select.ll | 30 +-
llvm/test/CodeGen/SystemZ/int-div-06.ll | 17 +-
.../CodeGen/Thumb/srem-seteq-illegal-types.ll | 4 +-
.../Thumb2/srem-seteq-illegal-types.ll | 6 +-
llvm/test/CodeGen/VE/Scalar/div.ll | 8 +-
llvm/test/CodeGen/VE/Scalar/rem.ll | 4 +-
.../CodeGen/X86/bypass-slow-division-32.ll | 34 +-
llvm/test/CodeGen/X86/divide-by-constant.ll | 35 +-
llvm/test/CodeGen/X86/freeze-binary.ll | 90 ++--
.../test/CodeGen/X86/load-scalar-as-vector.ll | 24 +-
llvm/test/CodeGen/X86/pr14088.ll | 11 +-
llvm/test/CodeGen/X86/pr34080-2.ll | 39 +-
llvm/test/CodeGen/X86/pr44812.ll | 17 +-
.../CodeGen/X86/shrink-wrap-chkstk-x86_64.ll | 12 +-
llvm/test/CodeGen/X86/srem-lkk.ll | 11 +-
.../CodeGen/X86/srem-seteq-illegal-types.ll | 266 +++++-----
llvm/test/CodeGen/X86/srem-vector-lkk.ll | 60 +--
llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll | 102 ++--
llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll | 132 ++---
llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll | 130 ++---
50 files changed, 1576 insertions(+), 1555 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 6e4c385c72edb..99dd23dfd5760 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -6675,6 +6675,8 @@ SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
SmallVector<SDValue, 16> MagicFactors, Factors, Shifts, ShiftMasks;
+ bool UseInputSign = true;
+
auto BuildSDIVPattern = [&](ConstantSDNode *C) {
if (C->isZero())
return false;
@@ -6699,6 +6701,9 @@ SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
NumeratorFactor = -1;
}
+ UseInputSign &=
+ Divisor.isStrictlyPositive() && magics.Magic.isStrictlyPositive();
+
MagicFactors.push_back(
DAG.getConstant(magics.Magic.zext(SVTBits), dl, SVT));
Factors.push_back(DAG.getSignedConstant(NumeratorFactor, dl, SVT));
@@ -6772,8 +6777,19 @@ SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
Q = DAG.getNode(ISD::SRA, dl, VT, Q, Shift);
Created.push_back(Q.getNode());
- // Extract the sign bit, mask it and add it to the quotient.
+ // Extract the sign bit, mask it and add/subtract it from the quotient.
SDValue SignShift = DAG.getConstant(EltBits - 1, dl, ShVT);
+
+ // sign(MULHS(N0, M) >> sh) == sign(N0) iff M > 0 and d > 0.
+ // TODO: a hook would let targets like AArch64 opt out of this fold, allowing
+ // us to remove the conservative vector guard. some targets fuse SRL+ADD into
+ // one instruction, making the default path cheaper. restrict to scalar until
+ // then.
+ if (UseInputSign && !VT.isVector()) {
+ SDValue T = DAG.getNode(ISD::SRA, dl, VT, N0, SignShift);
+ Created.push_back(T.getNode());
+ return DAG.getNode(ISD::SUB, dl, VT, Q, T);
+ }
SDValue T = DAG.getNode(ISD::SRL, dl, VT, Q, SignShift);
Created.push_back(T.getNode());
T = DAG.getNode(ISD::AND, dl, VT, T, ShiftMask);
diff --git a/llvm/test/CodeGen/AArch64/alias_mask.ll b/llvm/test/CodeGen/AArch64/alias_mask.ll
index d3e6513c83cd6..3db903c5c6ada 100644
--- a/llvm/test/CodeGen/AArch64/alias_mask.ll
+++ b/llvm/test/CodeGen/AArch64/alias_mask.ll
@@ -446,7 +446,7 @@ define <16 x i1> @whilewr_badimm(i64 %a, i64 %b) {
; CHECK-NEXT: sub x9, x1, x0
; CHECK-NEXT: movk x8, #21846
; CHECK-NEXT: smulh x8, x9, x8
-; CHECK-NEXT: add x8, x8, x8, lsr #63
+; CHECK-NEXT: sub x8, x8, x9, asr #63
; CHECK-NEXT: cmp x8, #1
; CHECK-NEXT: csinv x8, x8, xzr, ge
; CHECK-NEXT: whilelo p0.b, xzr, x8
diff --git a/llvm/test/CodeGen/AArch64/alias_mask_scalable.ll b/llvm/test/CodeGen/AArch64/alias_mask_scalable.ll
index def691db9cd8a..6427f31aa2107 100644
--- a/llvm/test/CodeGen/AArch64/alias_mask_scalable.ll
+++ b/llvm/test/CodeGen/AArch64/alias_mask_scalable.ll
@@ -300,7 +300,7 @@ define <vscale x 16 x i1> @whilewr_badimm(i64 %a, i64 %b) {
; CHECK-NEXT: sub x9, x1, x0
; CHECK-NEXT: movk x8, #21846
; CHECK-NEXT: smulh x8, x9, x8
-; CHECK-NEXT: add x8, x8, x8, lsr #63
+; CHECK-NEXT: sub x8, x8, x9, asr #63
; CHECK-NEXT: cmp x8, #1
; CHECK-NEXT: csinv x8, x8, xzr, ge
; CHECK-NEXT: whilelo p0.b, xzr, x8
diff --git a/llvm/test/CodeGen/AArch64/combine-sdiv.ll b/llvm/test/CodeGen/AArch64/combine-sdiv.ll
index fbb33db3fb7a9..a3ed3694a8817 100644
--- a/llvm/test/CodeGen/AArch64/combine-sdiv.ll
+++ b/llvm/test/CodeGen/AArch64/combine-sdiv.ll
@@ -1565,9 +1565,9 @@ define i8 @combine_i8_sdiv_const100(i8 %x) {
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: sxtb w8, w0
; CHECK-SD-NEXT: mov w9, #41 // =0x29
-; CHECK-SD-NEXT: mul w8, w8, w9
-; CHECK-SD-NEXT: asr w9, w8, #12
-; CHECK-SD-NEXT: add w0, w9, w8, lsr #31
+; CHECK-SD-NEXT: mul w9, w8, w9
+; CHECK-SD-NEXT: asr w9, w9, #12
+; CHECK-SD-NEXT: sub w0, w9, w8, asr #7
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: combine_i8_sdiv_const100:
@@ -1589,9 +1589,9 @@ define i16 @combine_i16_sdiv_const7(i16 %x) {
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: sxth w8, w0
; CHECK-SD-NEXT: mov w9, #18725 // =0x4925
-; CHECK-SD-NEXT: mul w8, w8, w9
-; CHECK-SD-NEXT: asr w9, w8, #17
-; CHECK-SD-NEXT: add w0, w9, w8, lsr #31
+; CHECK-SD-NEXT: mul w9, w8, w9
+; CHECK-SD-NEXT: asr w9, w9, #17
+; CHECK-SD-NEXT: sub w0, w9, w8, asr #15
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: combine_i16_sdiv_const7:
@@ -1613,9 +1613,9 @@ define i16 @combine_i16_sdiv_const100(i16 %x) {
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: sxth w8, w0
; CHECK-SD-NEXT: mov w9, #5243 // =0x147b
-; CHECK-SD-NEXT: mul w8, w8, w9
-; CHECK-SD-NEXT: asr w9, w8, #19
-; CHECK-SD-NEXT: add w0, w9, w8, lsr #31
+; CHECK-SD-NEXT: mul w9, w8, w9
+; CHECK-SD-NEXT: asr w9, w9, #19
+; CHECK-SD-NEXT: sub w0, w9, w8, asr #15
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: combine_i16_sdiv_const100:
@@ -1658,15 +1658,15 @@ define i32 @combine_i32_sdiv_const7(i32 %x) {
ret i32 %1
}
+
define i32 @combine_i32_sdiv_const100(i32 %x) {
; CHECK-SD-LABEL: combine_i32_sdiv_const100:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: mov w8, #34079 // =0x851f
; CHECK-SD-NEXT: movk w8, #20971, lsl #16
; CHECK-SD-NEXT: smull x8, w0, w8
-; CHECK-SD-NEXT: asr x9, x8, #37
-; CHECK-SD-NEXT: add x0, x9, x8, lsr #63
-; CHECK-SD-NEXT: // kill: def $w0 killed $w0 killed $x0
+; CHECK-SD-NEXT: asr x8, x8, #37
+; CHECK-SD-NEXT: sub w0, w8, w0, asr #31
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: combine_i32_sdiv_const100:
@@ -1690,8 +1690,8 @@ define i64 @combine_i64_sdiv_const7(i64 %x) {
; CHECK-SD-NEXT: movk x8, #37449, lsl #32
; CHECK-SD-NEXT: movk x8, #18724, lsl #48
; CHECK-SD-NEXT: smulh x8, x0, x8
-; CHECK-SD-NEXT: asr x9, x8, #1
-; CHECK-SD-NEXT: add x0, x9, x8, lsr #63
+; CHECK-SD-NEXT: asr x8, x8, #1
+; CHECK-SD-NEXT: sub x0, x8, x0, asr #63
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: combine_i64_sdiv_const7:
diff --git a/llvm/test/CodeGen/AArch64/rem-by-const.ll b/llvm/test/CodeGen/AArch64/rem-by-const.ll
index 1c6b241cb8f12..dc4b9490b472f 100644
--- a/llvm/test/CodeGen/AArch64/rem-by-const.ll
+++ b/llvm/test/CodeGen/AArch64/rem-by-const.ll
@@ -40,9 +40,9 @@ define i8 @si8_100(i8 %a, i8 %b) {
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: sxtb w8, w0
; CHECK-SD-NEXT: mov w9, #41 // =0x29
-; CHECK-SD-NEXT: mul w8, w8, w9
-; CHECK-SD-NEXT: asr w9, w8, #12
-; CHECK-SD-NEXT: add w8, w9, w8, lsr #31
+; CHECK-SD-NEXT: mul w9, w8, w9
+; CHECK-SD-NEXT: asr w9, w9, #12
+; CHECK-SD-NEXT: sub w8, w9, w8, asr #7
; CHECK-SD-NEXT: mov w9, #100 // =0x64
; CHECK-SD-NEXT: msub w0, w8, w9, w0
; CHECK-SD-NEXT: ret
@@ -129,9 +129,9 @@ define i16 @si16_7(i16 %a, i16 %b) {
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: sxth w8, w0
; CHECK-SD-NEXT: mov w9, #18725 // =0x4925
-; CHECK-SD-NEXT: mul w8, w8, w9
-; CHECK-SD-NEXT: asr w9, w8, #17
-; CHECK-SD-NEXT: add w8, w9, w8, lsr #31
+; CHECK-SD-NEXT: mul w9, w8, w9
+; CHECK-SD-NEXT: asr w9, w9, #17
+; CHECK-SD-NEXT: sub w8, w9, w8, asr #15
; CHECK-SD-NEXT: sub w8, w8, w8, lsl #3
; CHECK-SD-NEXT: add w0, w0, w8
; CHECK-SD-NEXT: ret
@@ -159,9 +159,9 @@ define i16 @si16_100(i16 %a, i16 %b) {
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: sxth w8, w0
; CHECK-SD-NEXT: mov w9, #5243 // =0x147b
-; CHECK-SD-NEXT: mul w8, w8, w9
-; CHECK-SD-NEXT: asr w9, w8, #19
-; CHECK-SD-NEXT: add w8, w9, w8, lsr #31
+; CHECK-SD-NEXT: mul w9, w8, w9
+; CHECK-SD-NEXT: asr w9, w9, #19
+; CHECK-SD-NEXT: sub w8, w9, w8, asr #15
; CHECK-SD-NEXT: mov w9, #100 // =0x64
; CHECK-SD-NEXT: msub w0, w8, w9, w0
; CHECK-SD-NEXT: ret
@@ -279,11 +279,11 @@ define i32 @si32_100(i32 %a, i32 %b) {
; CHECK-SD-LABEL: si32_100:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: mov w8, #34079 // =0x851f
+; CHECK-SD-NEXT: mov w9, #100 // =0x64
; CHECK-SD-NEXT: movk w8, #20971, lsl #16
; CHECK-SD-NEXT: smull x8, w0, w8
-; CHECK-SD-NEXT: asr x9, x8, #37
-; CHECK-SD-NEXT: add x8, x9, x8, lsr #63
-; CHECK-SD-NEXT: mov w9, #100 // =0x64
+; CHECK-SD-NEXT: asr x8, x8, #37
+; CHECK-SD-NEXT: sub w8, w8, w0, asr #31
; CHECK-SD-NEXT: msub w0, w8, w9, w0
; CHECK-SD-NEXT: ret
;
@@ -356,8 +356,8 @@ define i64 @si64_7(i64 %a, i64 %b) {
; CHECK-SD-NEXT: movk x8, #37449, lsl #32
; CHECK-SD-NEXT: movk x8, #18724, lsl #48
; CHECK-SD-NEXT: smulh x8, x0, x8
-; CHECK-SD-NEXT: asr x9, x8, #1
-; CHECK-SD-NEXT: add x8, x9, x8, lsr #63
+; CHECK-SD-NEXT: asr x8, x8, #1
+; CHECK-SD-NEXT: sub x8, x8, x0, asr #63
; CHECK-SD-NEXT: sub x8, x8, x8, lsl #3
; CHECK-SD-NEXT: add x0, x0, x8
; CHECK-SD-NEXT: ret
@@ -854,30 +854,30 @@ entry:
define <3 x i8> @sv3i8_100(<3 x i8> %d, <3 x i8> %e) {
; CHECK-SD-LABEL: sv3i8_100:
; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: // kill: def $w2 killed $w2 def $x2
+; CHECK-SD-NEXT: // kill: def $w1 killed $w1 def $x1
; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0
; CHECK-SD-NEXT: sxtb x8, w0
; CHECK-SD-NEXT: mov w9, #34079 // =0x851f
-; CHECK-SD-NEXT: // kill: def $w2 killed $w2 def $x2
-; CHECK-SD-NEXT: // kill: def $w1 killed $w1 def $x1
; CHECK-SD-NEXT: sxtb x10, w1
-; CHECK-SD-NEXT: movk w9, #20971, lsl #16
; CHECK-SD-NEXT: sxtb x11, w2
-; CHECK-SD-NEXT: sxtb w13, w0
+; CHECK-SD-NEXT: movk w9, #20971, lsl #16
+; CHECK-SD-NEXT: sxtb w12, w1
; CHECK-SD-NEXT: smull x8, w8, w9
+; CHECK-SD-NEXT: sxtb w13, w2
+; CHECK-SD-NEXT: mov w14, #100 // =0x64
; CHECK-SD-NEXT: smull x10, w10, w9
; CHECK-SD-NEXT: smull x9, w11, w9
-; CHECK-SD-NEXT: asr x11, x8, #37
-; CHECK-SD-NEXT: asr x12, x10, #37
-; CHECK-SD-NEXT: add x8, x11, x8, lsr #63
-; CHECK-SD-NEXT: asr x11, x9, #37
-; CHECK-SD-NEXT: add x10, x12, x10, lsr #63
-; CHECK-SD-NEXT: mov w12, #100 // =0x64
-; CHECK-SD-NEXT: add x9, x11, x9, lsr #63
-; CHECK-SD-NEXT: msub w0, w8, w12, w13
-; CHECK-SD-NEXT: sxtb w8, w1
-; CHECK-SD-NEXT: msub w1, w10, w12, w8
-; CHECK-SD-NEXT: sxtb w8, w2
-; CHECK-SD-NEXT: msub w2, w9, w12, w8
+; CHECK-SD-NEXT: sxtb w11, w0
+; CHECK-SD-NEXT: asr x8, x8, #37
+; CHECK-SD-NEXT: asr x10, x10, #37
+; CHECK-SD-NEXT: asr x9, x9, #37
+; CHECK-SD-NEXT: sub w8, w8, w11, asr #31
+; CHECK-SD-NEXT: sub w10, w10, w12, asr #31
+; CHECK-SD-NEXT: sub w9, w9, w13, asr #31
+; CHECK-SD-NEXT: msub w0, w8, w14, w11
+; CHECK-SD-NEXT: msub w1, w10, w14, w12
+; CHECK-SD-NEXT: msub w2, w9, w14, w13
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: sv3i8_100:
@@ -1736,24 +1736,24 @@ define <3 x i16> @sv3i16_100(<3 x i16> %d, <3 x i16> %e) {
; CHECK-SD-NEXT: mov w8, #34079 // =0x851f
; CHECK-SD-NEXT: smov x10, v0.h[1]
; CHECK-SD-NEXT: movk w8, #20971, lsl #16
+; CHECK-SD-NEXT: smov w12, v0.h[0]
; CHECK-SD-NEXT: smov x11, v0.h[2]
+; CHECK-SD-NEXT: smov w13, v0.h[1]
+; CHECK-SD-NEXT: mov w14, #100 // =0x64
; CHECK-SD-NEXT: smull x9, w9, w8
; CHECK-SD-NEXT: smull x10, w10, w8
; CHECK-SD-NEXT: smull x8, w11, w8
-; CHECK-SD-NEXT: smov w11, v0.h[0]
-; CHECK-SD-NEXT: asr x12, x9, #37
-; CHECK-SD-NEXT: asr x13, x10, #37
-; CHECK-SD-NEXT: add x9, x12, x9, lsr #63
-; CHECK-SD-NEXT: mov w12, #100 // =0x64
-; CHECK-SD-NEXT: add x10, x13, x10, lsr #63
-; CHECK-SD-NEXT: smov w13, v0.h[1]
-; CHECK-SD-NEXT: msub w9, w9, w12, w11
-; CHECK-SD-NEXT: asr x11, x8, #37
-; CHECK-SD-NEXT: msub w10, w10, w12, w13
-; CHECK-SD-NEXT: add x8, x11, x8, lsr #63
; CHECK-SD-NEXT: smov w11, v0.h[2]
+; CHECK-SD-NEXT: asr x9, x9, #37
+; CHECK-SD-NEXT: asr x10, x10, #37
+; CHECK-SD-NEXT: sub w9, w9, w12, asr #31
+; CHECK-SD-NEXT: asr x8, x8, #37
+; CHECK-SD-NEXT: sub w10, w10, w13, asr #31
+; CHECK-SD-NEXT: msub w9, w9, w14, w12
+; CHECK-SD-NEXT: sub w8, w8, w11, asr #31
+; CHECK-SD-NEXT: msub w10, w10, w14, w13
+; CHECK-SD-NEXT: msub w8, w8, w14, w11
; CHECK-SD-NEXT: fmov s0, w9
-; CHECK-SD-NEXT: msub w8, w8, w12, w11
; CHECK-SD-NEXT: mov v0.h[1], w10
; CHECK-SD-NEXT: mov v0.h[2], w8
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
@@ -2728,11 +2728,11 @@ define <2 x i64> @sv2i64_7(<2 x i64> %d, <2 x i64> %e) {
; CHECK-SD-NEXT: movk x8, #18724, lsl #48
; CHECK-SD-NEXT: smulh x11, x10, x8
; CHECK-SD-NEXT: smulh x8, x9, x8
-; CHECK-SD-NEXT: asr x12, x11, #1
-; CHECK-SD-NEXT: add x11, x12, x11, lsr #63
-; CHECK-SD-NEXT: asr x13, x8, #1
+; CHECK-SD-NEXT: asr x11, x11, #1
+; CHECK-SD-NEXT: sub x11, x11, x10, asr #63
+; CHECK-SD-NEXT: asr x8, x8, #1
; CHECK-SD-NEXT: sub x11, x11, x11, lsl #3
-; CHECK-SD-NEXT: add x8, x13, x8, lsr #63
+; CHECK-SD-NEXT: sub x8, x8, x9, asr #63
; CHECK-SD-NEXT: add x10, x10, x11
; CHECK-SD-NEXT: sub x8, x8, x8, lsl #3
; CHECK-SD-NEXT: fmov d0, x10
diff --git a/llvm/test/CodeGen/AArch64/srem-lkk.ll b/llvm/test/CodeGen/AArch64/srem-lkk.ll
index 6678fbc8f4b42..fe16042b30955 100644
--- a/llvm/test/CodeGen/AArch64/srem-lkk.ll
+++ b/llvm/test/CodeGen/AArch64/srem-lkk.ll
@@ -23,11 +23,11 @@ define i32 @fold_srem_positive_even(i32 %x) {
; CHECK-LABEL: fold_srem_positive_even:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #36849 // =0x8ff1
+; CHECK-NEXT: mov w9, #1060 // =0x424
; CHECK-NEXT: movk w8, #15827, lsl #16
; CHECK-NEXT: smull x8, w0, w8
-; CHECK-NEXT: asr x9, x8, #40
-; CHECK-NEXT: add x8, x9, x8, lsr #63
-; CHECK-NEXT: mov w9, #1060 // =0x424
+; CHECK-NEXT: asr x8, x8, #40
+; CHECK-NEXT: sub w8, w8, w0, asr #31
; CHECK-NEXT: msub w0, w8, w9, w0
; CHECK-NEXT: ret
%1 = srem i32 %x, 1060
@@ -93,13 +93,13 @@ define i64 @dont_fold_srem_i64(i64 %x) {
; CHECK-LABEL: dont_fold_srem_i64:
; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, #58849 // =0xe5e1
+; CHECK-NEXT: mov w9, #98 // =0x62
; CHECK-NEXT: movk x8, #48148, lsl #16
; CHECK-NEXT: movk x8, #33436, lsl #32
; CHECK-NEXT: movk x8, #21399, lsl #48
; CHECK-NEXT: smulh x8, x0, x8
-; CHECK-NEXT: asr x9, x8, #5
-; CHECK-NEXT: add x8, x9, x8, lsr #63
-; CHECK-NEXT: mov w9, #98 // =0x62
+; CHECK-NEXT: asr x8, x8, #5
+; CHECK-NEXT: sub x8, x8, x0, asr #63
; CHECK-NEXT: msub x0, x8, x9, x0
; CHECK-NEXT: ret
%1 = srem i64 %x, 98
diff --git a/llvm/test/CodeGen/AArch64/srem-seteq-illegal-types.ll b/llvm/test/CodeGen/AArch64/srem-seteq-illegal-types.ll
index bd4cc62255439..d8a477bbc455c 100644
--- a/llvm/test/CodeGen/AArch64/srem-seteq-illegal-types.ll
+++ b/llvm/test/CodeGen/AArch64/srem-seteq-illegal-types.ll
@@ -24,9 +24,9 @@ define i1 @test_srem_even(i4 %X) nounwind {
; CHECK-LABEL: test_srem_even:
; CHECK: // %bb.0:
; CHECK-NEXT: sbfx w8, w0, #0, #4
-; CHECK-NEXT: add w8, w8, w8, lsl #1
-; CHECK-NEXT: lsr w9, w8, #4
-; CHECK-NEXT: add w8, w9, w8, lsr #31
+; CHECK-NEXT: add w9, w8, w8, lsl #1
+; CHECK-NEXT: lsr w9, w9, #4
+; CHECK-NEXT: sub w8, w9, w8, lsr #3
; CHECK-NEXT: mov w9, #6 // =0x6
; CHECK-NEXT: msub w8, w8, w9, w0
; CHECK-NEXT: and w8, w8, #0xf
@@ -61,28 +61,30 @@ define <3 x i1> @test_srem_vec(<3 x i33> %X) nounwind {
; CHECK-NEXT: sbfx x8, x0, #0, #33
; CHECK-NEXT: sbfx x10, x1, #0, #33
; CHECK-NEXT: movk x9, #29127, lsl #16
-; CHECK-NEXT: mov x13, #-7282 // =0xffffffffffffe38e
+; CHECK-NEXT: mov x14, #-7282 // =0xffffffffffffe38e
; CHECK-NEXT: sbfx x12, x2, #0, #33
; CHECK-NEXT: movk x9, #50972, lsl #32
-; CHECK-NEXT: movk x13, #36408, lsl #16
+; CHECK-NEXT: movk x14, #36408, lsl #16
+; CHECK-NEXT: lsl x13, x0, #31
; CHECK-NEXT: movk x9, #7281, lsl #48
-; CHECK-NEXT: eon x13, x13, x13, lsl #33
+; CHECK-NEXT: eon x14, x14, x14, lsl #33
+; CHECK-NEXT: lsl x15, x1, #31
; CHECK-NEXT: smulh x11, x8, x9
; CHECK-NEXT: smulh x9, x10, x9
-; CHECK-NEXT: smulh x13, x12, x13
-; CHECK-NEXT: add x11, x11, x11, lsr #63
-; CHECK-NEXT: add x9, x9, x9, lsr #63
+; CHECK-NEXT: smulh x14, x12, x14
+; CHECK-NEXT: sub x11, x11, x13, asr #63
; CHECK-NEXT: add x11, x11, x11, lsl #3
-; CHECK-NEXT: add x9, x9, x9, lsl #3
+; CHECK-NEXT: sub x9, x9, x15, asr #63
; CHECK-NEXT: sub x8, x8, x11
-; CHECK-NEXT: sub x11, x13, x12
+; CHECK-NEXT: add x9, x9, x9, lsl #3
+; CHECK-NEXT: sub x13, x14, x12
; CHECK-NEXT: fmov d0, x8
+; CHECK-NEXT: asr x11, x13, #3
; CHECK-NEXT: mov x8, #8589934591 // =0x1ffffffff
; CHECK-NEXT: sub x9, x10, x9
-; CHECK-NEXT: asr x10, x11, #3
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: mov v0.d[1], x9
-; CHECK-NEXT: add x9, x10, x11, lsr #63
+; CHECK-NEXT: add x9, x11, x13, lsr #63
; CHECK-NEXT: add x8, x9, x9, lsl #3
; CHECK-NEXT: adrp x9, .LCPI3_0
; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI3_0]
diff --git a/llvm/test/CodeGen/AArch64/srem-vector-lkk.ll b/llvm/test/CodeGen/AArch64/srem-vector-lkk.ll
index 52b09565b73a5..5ef8663a0ded5 100644
--- a/llvm/test/CodeGen/AArch64/srem-vector-lkk.ll
+++ b/llvm/test/CodeGen/AArch64/srem-vector-lkk.ll
@@ -160,15 +160,15 @@ define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) {
; CHECK-NEXT: smulh x13, x11, x13
; CHECK-NEXT: add x8, x8, x10
; CHECK-NEXT: asr x14, x8, #4
-; CHECK-NEXT: asr x15, x12, #11
+; CHECK-NEXT: asr x12, x12, #11
; CHECK-NEXT: add x8, x14, x8, lsr #63
; CHECK-NEXT: mov w14, #23 // =0x17
-; CHECK-NEXT: add x12, x15, x12, lsr #63
+; CHECK-NEXT: sub x12, x12, x9, asr #63
; CHECK-NEXT: msub x8, x8, x14, x10
; CHECK-NEXT: asr x10, x13, #8
-; CHECK-NEXT: mov w14, #5423 // =0x152f
-; CHECK-NEXT: add x10, x10, x13, lsr #63
-; CHECK-NEXT: msub x9, x12, x14, x9
+; CHECK-NEXT: mov w13, #5423 // =0x152f
+; CHECK-NEXT: sub x10, x10, x11, asr #63
+; CHECK-NEXT: msub x9, x12, x13, x9
; CHECK-NEXT: mov w12, #654 // =0x28e
; CHECK-NEXT: msub x10, x10, x12, x11
; CHECK-NEXT: fmov d1, x8
@@ -285,14 +285,14 @@ define <2 x i64> @fold_srem_v2i64(<2 x i64> %x) {
; CHECK-NEXT: mov x8, #7378697629483820646 // =0x6666666666666666
; CHECK-NEXT: mov x9, v0.d[1]
; CHECK-NEXT: movk x8, #26215
+; CHECK-NEXT: mov w12, #10 // =0xa
; CHECK-NEXT: smulh x11, x10, x8
; CHECK-NEXT: smulh x8, x9, x8
-; CHECK-NEXT: asr x12, x11, #2
-; CHECK-NEXT: add x11, x12, x11, lsr #63
-; CHECK-NEXT: asr x13, x8, #2
-; CHECK-NEXT: mov w12, #10 // =0xa
+; CHECK-NEXT: asr x11, x11, #2
+; CHECK-NEXT: sub x11, x11, x10, asr #63
+; CHECK-NEXT: asr x8, x8, #2
; CHECK-NEXT: msub x10, x11, x12, x10
-; CHECK-NEXT: add x8, x13, x8, lsr #63
+; CHECK-NEXT: sub x8, x8, x9, asr #63
; CHECK-NEXT: msub x8, x8, x12, x9
; CHECK-NEXT: fmov d0, x10
; CHECK-NEXT: mov v0.d[1], x8
@@ -307,11 +307,11 @@ define <1 x i64> @fold_srem_v1i64(<1 x i64> %x) {
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: fmov x9, d0
; CHECK-NEXT: mov x8, #7378697629483820646 // =0x6666666666666666
+; CHECK-NEXT: mov w10, #10 // =0xa
; CHECK-NEXT: movk x8, #26215
; CHECK-NEXT: smulh x8, x9, x8
-; CHECK-NEXT: asr x10, x8, #2
-; CHECK-NEXT: add x8, x10, x8, lsr #63
-; CHECK-NEXT: mov w10, #10 // =0xa
+; CHECK-NEXT: asr x8, x8, #2
+; CHECK-NEXT: sub x8, x8, x9, asr #63
; CHECK-NEXT: msub x8, x8, x10, x9
; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll
index e34aaf205cb95..d28c7a636f14b 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll
@@ -268,10 +268,10 @@ define i32 @select_sdiv_rhs_opaque_const0_i32(i1 %cond) {
; GCN-NEXT: v_mov_b32_e32 v2, s4
; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
; GCN-NEXT: s_mov_b32 s4, 0x30c30c31
-; GCN-NEXT: v_mul_hi_i32 v0, v0, s4
-; GCN-NEXT: v_lshrrev_b32_e32 v1, 31, v0
-; GCN-NEXT: v_ashrrev_i32_e32 v0, 3, v0
-; GCN-NEXT: v_add_u32_e32 v0, vcc, v0, v1
+; GCN-NEXT: v_mul_hi_i32 v1, v0, s4
+; GCN-NEXT: v_ashrrev_i32_e32 v0, 31, v0
+; GCN-NEXT: v_ashrrev_i32_e32 v1, 3, v1
+; GCN-NEXT: v_sub_u32_e32 v0, vcc, v1, v0
; GCN-NEXT: s_setpc_b64 s[30:31]
%select = select i1 %cond, i32 ptrtoint (ptr addrspace(1) @gv to i32), i32 234234
%op = sdiv i32 %select, 42
@@ -298,10 +298,10 @@ define i32 @select_sdiv_rhs_opaque_const1_i32(i1 %cond) {
; GCN-NEXT: v_mov_b32_e32 v2, s4
; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GCN-NEXT: s_mov_b32 s4, 0x30c30c31
-; GCN-NEXT: v_mul_hi_i32 v0, v0, s4
-; GCN-NEXT: v_lshrrev_b32_e32 v1, 31, v0
-; GCN-NEXT: v_ashrrev_i32_e32 v0, 3, v0
-; GCN-NEXT: v_add_u32_e32 v0, vcc, v0, v1
+; GCN-NEXT: v_mul_hi_i32 v1, v0, s4
+; GCN-NEXT: v_ashrrev_i32_e32 v0, 31, v0
+; GCN-NEXT: v_ashrrev_i32_e32 v1, 3, v1
+; GCN-NEXT: v_sub_u32_e32 v0, vcc, v1, v0
; GCN-NEXT: s_setpc_b64 s[30:31]
%select = select i1 %cond, i32 42000, i32 ptrtoint (ptr addrspace(1) @gv to i32)
%op = sdiv i32 %select, 42
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
index df77e7de43bf6..07d2fb4e9cbe6 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
@@ -7624,42 +7624,42 @@ define amdgpu_kernel void @sdiv_i64_oddk_denom(ptr addrspace(1) %out, i64 %x) {
;
; GFX6-LABEL: sdiv_i64_oddk_denom:
; GFX6: ; %bb.0:
-; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; GFX6-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x9
; GFX6-NEXT: v_mov_b32_e32 v2, 0xfd81e19
; GFX6-NEXT: v_mov_b32_e32 v0, 0x6ca94220
-; GFX6-NEXT: s_mov_b32 s7, 0xf000
-; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: v_mul_hi_u32 v3, s2, v2
-; GFX6-NEXT: v_mul_hi_u32 v4, s3, v2
-; GFX6-NEXT: s_mov_b32 s5, s1
-; GFX6-NEXT: v_mul_hi_u32 v1, s2, v0
-; GFX6-NEXT: s_mul_i32 s1, s3, 0xfd81e19
-; GFX6-NEXT: v_add_i32_e32 v3, vcc, s1, v3
-; GFX6-NEXT: s_mov_b32 s4, s0
-; GFX6-NEXT: s_mul_i32 s0, s2, 0x6ca94220
+; GFX6-NEXT: v_mul_hi_u32 v3, s6, v2
+; GFX6-NEXT: v_mul_hi_u32 v4, s7, v2
+; GFX6-NEXT: s_mov_b32 s1, s5
+; GFX6-NEXT: v_mul_hi_u32 v1, s6, v0
+; GFX6-NEXT: s_mul_i32 s5, s7, 0xfd81e19
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, s5, v3
+; GFX6-NEXT: s_mov_b32 s0, s4
+; GFX6-NEXT: s_mul_i32 s4, s6, 0x6ca94220
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc
-; GFX6-NEXT: v_add_i32_e32 v3, vcc, s0, v3
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, s4, v3
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v4, v1
-; GFX6-NEXT: v_addc_u32_e64 v3, s[0:1], 0, 0, vcc
-; GFX6-NEXT: s_ashr_i32 s1, s3, 31
-; GFX6-NEXT: v_mul_hi_u32 v0, s3, v0
-; GFX6-NEXT: v_mul_hi_u32 v2, s1, v2
-; GFX6-NEXT: s_mul_i32 s0, s3, 0x6ca94220
-; GFX6-NEXT: v_add_i32_e32 v1, vcc, s0, v1
-; GFX6-NEXT: s_mul_i32 s0, s1, 0x6ca94220
+; GFX6-NEXT: v_addc_u32_e64 v3, s[4:5], 0, 0, vcc
+; GFX6-NEXT: s_ashr_i32 s5, s7, 31
+; GFX6-NEXT: v_mul_hi_u32 v0, s7, v0
+; GFX6-NEXT: v_mul_hi_u32 v2, s5, v2
+; GFX6-NEXT: s_mul_i32 s4, s7, 0x6ca94220
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, s4, v1
+; GFX6-NEXT: s_mul_i32 s4, s5, 0x6ca94220
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v0, v3, vcc
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, s0, v2
-; GFX6-NEXT: s_mul_i32 s1, s1, 0xfd81e19
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, s1, v0
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, s1, v1
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, s4, v2
+; GFX6-NEXT: s_mul_i32 s4, s5, 0xfd81e19
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, s4, v0
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, s4, v1
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v3, v2, vcc
-; GFX6-NEXT: v_ashr_i64 v[2:3], v[0:1], 19
-; GFX6-NEXT: v_lshrrev_b32_e32 v0, 31, v1
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, v2, v0
-; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc
-; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NEXT: v_ashr_i64 v[0:1], v[0:1], 19
+; GFX6-NEXT: v_mov_b32_e32 v2, s5
+; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s5, v0
+; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX6-NEXT: s_endpgm
;
; GFX9-LABEL: sdiv_i64_oddk_denom:
@@ -7682,18 +7682,17 @@ define amdgpu_kernel void @sdiv_i64_oddk_denom(ptr addrspace(1) %out, i64 %x) {
; GFX9-NEXT: s_mul_hi_u32 s5, s3, 0x6ca94220
; GFX9-NEXT: s_add_u32 s2, s6, s2
; GFX9-NEXT: s_addc_u32 s4, s5, s4
-; GFX9-NEXT: s_ashr_i32 s3, s3, 31
-; GFX9-NEXT: s_mul_i32 s5, s3, 0x6ca94220
-; GFX9-NEXT: s_mul_hi_u32 s6, s3, 0xfd81e19
-; GFX9-NEXT: s_add_i32 s5, s6, s5
-; GFX9-NEXT: s_mul_i32 s3, s3, 0xfd81e19
-; GFX9-NEXT: s_add_i32 s5, s5, s3
-; GFX9-NEXT: s_add_u32 s2, s2, s3
-; GFX9-NEXT: s_addc_u32 s3, s4, s5
-; GFX9-NEXT: s_ashr_i64 s[4:5], s[2:3], 19
-; GFX9-NEXT: s_lshr_b32 s2, s3, 31
-; GFX9-NEXT: s_add_u32 s2, s4, s2
-; GFX9-NEXT: s_addc_u32 s3, s5, 0
+; GFX9-NEXT: s_ashr_i32 s5, s3, 31
+; GFX9-NEXT: s_mul_i32 s3, s5, 0x6ca94220
+; GFX9-NEXT: s_mul_hi_u32 s6, s5, 0xfd81e19
+; GFX9-NEXT: s_add_i32 s3, s6, s3
+; GFX9-NEXT: s_mul_i32 s6, s5, 0xfd81e19
+; GFX9-NEXT: s_add_i32 s3, s3, s6
+; GFX9-NEXT: s_add_u32 s2, s2, s6
+; GFX9-NEXT: s_addc_u32 s3, s4, s3
+; GFX9-NEXT: s_ashr_i64 s[2:3], s[2:3], 19
+; GFX9-NEXT: s_sub_u32 s2, s2, s5
+; GFX9-NEXT: s_subb_u32 s3, s3, s5
; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
@@ -8846,14 +8845,14 @@ define amdgpu_kernel void @srem_i64_oddk_denom(ptr addrspace(1) %out, i64 %x) {
; GFX6-NEXT: s_mul_i32 s1, s4, 0x6ca94220
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v0, v3, vcc
; GFX6-NEXT: v_add_i32_e32 v0, vcc, s1, v2
-; GFX6-NEXT: s_mul_i32 s4, s4, 0xfd81e19
-; GFX6-NEXT: v_add_i32_e32 v2, vcc, s4, v0
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, s4, v1
+; GFX6-NEXT: s_mul_i32 s1, s4, 0xfd81e19
+; GFX6-NEXT: v_add_i32_e32 v2, vcc, s1, v0
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, s1, v1
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v3, v2, vcc
-; GFX6-NEXT: v_ashr_i64 v[2:3], v[0:1], 19
-; GFX6-NEXT: v_lshrrev_b32_e32 v0, 31, v1
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, v2, v0
-; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc
+; GFX6-NEXT: v_ashr_i64 v[0:1], v[0:1], 19
+; GFX6-NEXT: v_mov_b32_e32 v2, s4
+; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s4, v0
+; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
; GFX6-NEXT: s_mov_b32 s4, 0x12d8fb
; GFX6-NEXT: v_mul_lo_u32 v1, v1, s4
; GFX6-NEXT: v_mul_hi_u32 v2, v0, s4
@@ -8890,14 +8889,13 @@ define amdgpu_kernel void @srem_i64_oddk_denom(ptr addrspace(1) %out, i64 %x) {
; GFX9-NEXT: s_mul_i32 s7, s6, 0x6ca94220
; GFX9-NEXT: s_mul_hi_u32 s8, s6, 0xfd81e19
; GFX9-NEXT: s_add_i32 s7, s8, s7
-; GFX9-NEXT: s_mul_i32 s6, s6, 0xfd81e19
-; GFX9-NEXT: s_add_i32 s7, s7, s6
-; GFX9-NEXT: s_add_u32 s4, s4, s6
+; GFX9-NEXT: s_mul_i32 s8, s6, 0xfd81e19
+; GFX9-NEXT: s_add_i32 s7, s7, s8
+; GFX9-NEXT: s_add_u32 s4, s4, s8
; GFX9-NEXT: s_addc_u32 s5, s5, s7
-; GFX9-NEXT: s_ashr_i64 s[6:7], s[4:5], 19
-; GFX9-NEXT: s_lshr_b32 s4, s5, 31
-; GFX9-NEXT: s_add_u32 s4, s6, s4
-; GFX9-NEXT: s_addc_u32 s5, s7, 0
+; GFX9-NEXT: s_ashr_i64 s[4:5], s[4:5], 19
+; GFX9-NEXT: s_sub_u32 s4, s4, s6
+; GFX9-NEXT: s_subb_u32 s5, s5, s6
; GFX9-NEXT: s_mul_i32 s5, s5, 0x12d8fb
; GFX9-NEXT: s_mul_hi_u32 s6, s4, 0x12d8fb
; GFX9-NEXT: s_add_i32 s6, s6, s5
@@ -9918,14 +9916,14 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x
}
define <2 x i32> @v_sdiv_i32_exact(<2 x i32> %num) {
-; CHECK-LABEL: @v_sdiv_i32_exact(
-; CHECK: %1 = extractelement <2 x i32> %num, i64 0
-; CHECK-NEXT: %2 = sdiv exact i32 %1, 4096
-; CHECK-NEXT: %3 = insertelement <2 x i32> poison, i32 %2, i64 0
-; CHECK-NEXT: %4 = extractelement <2 x i32> %num, i64 1
-; CHECK-NEXT: %5 = sdiv exact i32 %4, 1024
-; CHECK-NEXT: %6 = insertelement <2 x i32> %3, i32 %5, i64 1
-; CHECK-NEXT: ret <2 x i32> %6
+; CHECK-LABEL: @v_sdiv_i32_exact(
+; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[NUM:%.*]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = sdiv exact i32 [[TMP1]], 4096
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> poison, i32 [[TMP2]], i64 0
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[NUM]], i64 1
+; CHECK-NEXT: [[TMP5:%.*]] = sdiv exact i32 [[TMP4]], 1024
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP5]], i64 1
+; CHECK-NEXT: ret <2 x i32> [[TMP6]]
;
; GFX6-LABEL: v_sdiv_i32_exact:
; GFX6: ; %bb.0:
@@ -9940,19 +9938,19 @@ define <2 x i32> @v_sdiv_i32_exact(<2 x i32> %num) {
; GFX9-NEXT: v_ashrrev_i32_e32 v0, 12, v0
; GFX9-NEXT: v_ashrrev_i32_e32 v1, 10, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
- %result = sdiv exact <2 x i32> %num, <i32 4096, i32 1024>
- ret <2 x i32> %result
+ %result = sdiv exact <2 x i32> %num, <i32 4096, i32 1024>
+ ret <2 x i32> %result
}
define <2 x i64> @v_sdiv_i64_exact(<2 x i64> %num) {
-; CHECK-LABEL: @v_sdiv_i64_exact(
-; CHECK: %1 = extractelement <2 x i64> %num, i64 0
-; CHECK-NEXT: %2 = sdiv exact i64 %1, 4096
-; CHECK-NEXT: %3 = insertelement <2 x i64> poison, i64 %2, i64 0
-; CHECK-NEXT: %4 = extractelement <2 x i64> %num, i64 1
-; CHECK-NEXT: %5 = sdiv exact i64 %4, 1024
-; CHECK-NEXT: %6 = insertelement <2 x i64> %3, i64 %5, i64 1
-; CHECK-NEXT: ret <2 x i64> %6
+; CHECK-LABEL: @v_sdiv_i64_exact(
+; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i64> [[NUM:%.*]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = sdiv exact i64 [[TMP1]], 4096
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> poison, i64 [[TMP2]], i64 0
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[NUM]], i64 1
+; CHECK-NEXT: [[TMP5:%.*]] = sdiv exact i64 [[TMP4]], 1024
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[TMP5]], i64 1
+; CHECK-NEXT: ret <2 x i64> [[TMP6]]
;
; GFX6-LABEL: v_sdiv_i64_exact:
; GFX6: ; %bb.0:
@@ -9967,19 +9965,19 @@ define <2 x i64> @v_sdiv_i64_exact(<2 x i64> %num) {
; GFX9-NEXT: v_ashrrev_i64 v[0:1], 12, v[0:1]
; GFX9-NEXT: v_ashrrev_i64 v[2:3], 10, v[2:3]
; GFX9-NEXT: s_setpc_b64 s[30:31]
- %result = sdiv exact <2 x i64> %num, <i64 4096, i64 1024>
- ret <2 x i64> %result
+ %result = sdiv exact <2 x i64> %num, <i64 4096, i64 1024>
+ ret <2 x i64> %result
}
define <2 x i32> @v_udiv_i32_exact(<2 x i32> %num) {
-; CHECK-LABEL: @v_udiv_i32_exact(
-; CHECK: %1 = extractelement <2 x i32> %num, i64 0
-; CHECK-NEXT: %2 = udiv exact i32 %1, 4096
-; CHECK-NEXT: %3 = insertelement <2 x i32> poison, i32 %2, i64 0
-; CHECK-NEXT: %4 = extractelement <2 x i32> %num, i64 1
-; CHECK-NEXT: %5 = udiv exact i32 %4, 1024
-; CHECK-NEXT: %6 = insertelement <2 x i32> %3, i32 %5, i64 1
-; CHECK-NEXT: ret <2 x i32> %6
+; CHECK-LABEL: @v_udiv_i32_exact(
+; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[NUM:%.*]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = udiv exact i32 [[TMP1]], 4096
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> poison, i32 [[TMP2]], i64 0
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[NUM]], i64 1
+; CHECK-NEXT: [[TMP5:%.*]] = udiv exact i32 [[TMP4]], 1024
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP5]], i64 1
+; CHECK-NEXT: ret <2 x i32> [[TMP6]]
;
; GFX6-LABEL: v_udiv_i32_exact:
; GFX6: ; %bb.0:
@@ -9994,19 +9992,19 @@ define <2 x i32> @v_udiv_i32_exact(<2 x i32> %num) {
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 12, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 10, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
- %result = udiv exact <2 x i32> %num, <i32 4096, i32 1024>
- ret <2 x i32> %result
+ %result = udiv exact <2 x i32> %num, <i32 4096, i32 1024>
+ ret <2 x i32> %result
}
define <2 x i64> @v_udiv_i64_exact(<2 x i64> %num) {
-; CHECK-LABEL: @v_udiv_i64_exact(
-; CHECK: %1 = extractelement <2 x i64> %num, i64 0
-; CHECK-NEXT: %2 = udiv exact i64 %1, 4096
-; CHECK-NEXT: %3 = insertelement <2 x i64> poison, i64 %2, i64 0
-; CHECK-NEXT: %4 = extractelement <2 x i64> %num, i64 1
-; CHECK-NEXT: %5 = udiv exact i64 %4, 1024
-; CHECK-NEXT: %6 = insertelement <2 x i64> %3, i64 %5, i64 1
-; CHECK-NEXT: ret <2 x i64> %6
+; CHECK-LABEL: @v_udiv_i64_exact(
+; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i64> [[NUM:%.*]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = udiv exact i64 [[TMP1]], 4096
+; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> poison, i64 [[TMP2]], i64 0
+; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[NUM]], i64 1
+; CHECK-NEXT: [[TMP5:%.*]] = udiv exact i64 [[TMP4]], 1024
+; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[TMP5]], i64 1
+; CHECK-NEXT: ret <2 x i64> [[TMP6]]
;
; GFX6-LABEL: v_udiv_i64_exact:
; GFX6: ; %bb.0:
@@ -10021,8 +10019,8 @@ define <2 x i64> @v_udiv_i64_exact(<2 x i64> %num) {
; GFX9-NEXT: v_lshrrev_b64 v[0:1], 12, v[0:1]
; GFX9-NEXT: v_lshrrev_b64 v[2:3], 10, v[2:3]
; GFX9-NEXT: s_setpc_b64 s[30:31]
- %result = udiv exact <2 x i64> %num, <i64 4096, i64 1024>
- ret <2 x i64> %result
+ %result = udiv exact <2 x i64> %num, <i64 4096, i64 1024>
+ ret <2 x i64> %result
}
define i64 @udiv_i64_gt_smax(i8 %size) {
@@ -10074,6 +10072,11 @@ define i64 @udiv_i64_gt_smax(i8 %size) {
; GFX9-NEXT: v_alignbit_b32 v0, v1, v0, 3
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 3, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: @udiv_i64_gt_smax(
+; CHECK-NEXT: [[ESIZE:%.*]] = sext i8 [[SIZE:%.*]] to i64
+; CHECK-NEXT: [[MINUS:%.*]] = sub nuw nsw i64 -1, [[ESIZE]]
+; CHECK-NEXT: [[DIV:%.*]] = udiv i64 [[MINUS]], 10
+; CHECK-NEXT: ret i64 [[DIV]]
%esize = sext i8 %size to i64
%minus = sub nuw nsw i64 -1, %esize
%div = udiv i64 %minus, 10
@@ -10114,6 +10117,27 @@ define i64 @udiv_i64_9divbits(i8 %size) {
; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v2, vcc
; GFX9-NEXT: v_and_b32_e32 v0, 0x1ff, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: @udiv_i64_9divbits(
+; CHECK-NEXT: [[ZEXTEND:%.*]] = zext i8 [[SIZE:%.*]] to i64
+; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[ZEXTEND]] to i32
+; CHECK-NEXT: [[TMP2:%.*]] = add i32 1, [[TMP1]]
+; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i32
+; CHECK-NEXT: [[TMP5:%.*]] = uitofp i32 [[TMP4]] to float
+; CHECK-NEXT: [[TMP6:%.*]] = call float @llvm.amdgcn.rcp.f32(float 1.000000e+01)
+; CHECK-NEXT: [[TMP7:%.*]] = fmul float [[TMP5]], [[TMP6]]
+; CHECK-NEXT: [[TMP8:%.*]] = call float @llvm.trunc.f32(float [[TMP7]])
+; CHECK-NEXT: [[TMP9:%.*]] = fneg float [[TMP8]]
+; CHECK-NEXT: [[TMP10:%.*]] = call float @llvm.amdgcn.fmad.ftz.f32(float [[TMP9]], float 1.000000e+01, float [[TMP5]])
+; CHECK-NEXT: [[TMP11:%.*]] = fptoui float [[TMP8]] to i32
+; CHECK-NEXT: [[TMP12:%.*]] = call float @llvm.fabs.f32(float [[TMP10]])
+; CHECK-NEXT: [[TMP13:%.*]] = call float @llvm.fabs.f32(float 1.000000e+01)
+; CHECK-NEXT: [[TMP14:%.*]] = fcmp oge float [[TMP12]], [[TMP13]]
+; CHECK-NEXT: [[TMP15:%.*]] = select i1 [[TMP14]], i32 1, i32 0
+; CHECK-NEXT: [[TMP16:%.*]] = add i32 [[TMP11]], [[TMP15]]
+; CHECK-NEXT: [[TMP17:%.*]] = and i32 [[TMP16]], 511
+; CHECK-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
+; CHECK-NEXT: ret i64 [[TMP18]]
%zextend = zext i8 %size to i64
%num = add nuw nsw i64 1, %zextend
%div = udiv i64 %num, 10
@@ -10130,6 +10154,9 @@ define <2 x i64> @srem_zero_zero() {
; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
+; CHECK-LABEL: @srem_zero_zero(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: ret <2 x i64> poison
entry:
%B = srem <2 x i64> zeroinitializer, zeroinitializer
ret <2 x i64> %B
diff --git a/llvm/test/CodeGen/AMDGPU/div-rem-by-constant-64.ll b/llvm/test/CodeGen/AMDGPU/div-rem-by-constant-64.ll
index 95385b7cb14bc..7b52eff588f7c 100644
--- a/llvm/test/CodeGen/AMDGPU/div-rem-by-constant-64.ll
+++ b/llvm/test/CodeGen/AMDGPU/div-rem-by-constant-64.ll
@@ -25,9 +25,8 @@ define noundef i64 @srem64_3(i64 noundef %i) {
; GFX9-NEXT: v_mul_lo_u32 v5, v4, s7
; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v4, s6, v[2:3]
; GFX9-NEXT: v_add3_u32 v3, v6, v3, v5
-; GFX9-NEXT: v_lshrrev_b32_e32 v4, 31, v3
-; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
-; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v3, vcc
+; GFX9-NEXT: v_sub_co_u32_e32 v2, vcc, v2, v4
+; GFX9-NEXT: v_subb_co_u32_e32 v4, vcc, v3, v4, vcc
; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v2, 3, 0
; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v4, 3, v[3:4]
; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v2
@@ -47,21 +46,22 @@ define noundef i64 @srem64_3(i64 noundef %i) {
; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v0, s3, v[4:5]
; GFX942-NEXT: v_mov_b32_e32 v4, v5
; GFX942-NEXT: v_mov_b32_e32 v5, v3
-; GFX942-NEXT: v_lshl_add_u64 v[4:5], v[2:3], 0, v[4:5]
-; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v1, s3, v[4:5]
-; GFX942-NEXT: v_ashrrev_i32_e32 v2, 31, v1
-; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v2, s2, v[4:5]
-; GFX942-NEXT: v_mul_lo_u32 v6, v2, s3
-; GFX942-NEXT: v_mul_lo_u32 v2, v2, s2
-; GFX942-NEXT: v_add3_u32 v5, v2, v5, v6
-; GFX942-NEXT: v_lshrrev_b32_e32 v2, 31, v5
-; GFX942-NEXT: v_lshl_add_u64 v[2:3], v[4:5], 0, v[2:3]
-; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v2, 3, 0
-; GFX942-NEXT: v_mov_b32_e32 v2, v5
-; GFX942-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v3, 3, v[2:3]
-; GFX942-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v4
+; GFX942-NEXT: v_lshl_add_u64 v[2:3], v[2:3], 0, v[4:5]
+; GFX942-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v1, s3, v[2:3]
+; GFX942-NEXT: v_ashrrev_i32_e32 v4, 31, v1
+; GFX942-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v4, s2, v[2:3]
+; GFX942-NEXT: v_mul_lo_u32 v5, v4, s3
+; GFX942-NEXT: v_mul_lo_u32 v6, v4, s2
+; GFX942-NEXT: v_add3_u32 v3, v6, v3, v5
+; GFX942-NEXT: v_sub_co_u32_e32 v2, vcc, v2, v4
; GFX942-NEXT: s_nop 1
-; GFX942-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v2, vcc
+; GFX942-NEXT: v_subb_co_u32_e32 v5, vcc, v3, v4, vcc
+; GFX942-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v2, 3, 0
+; GFX942-NEXT: v_mov_b32_e32 v4, v3
+; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v5, 3, v[4:5]
+; GFX942-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v2
+; GFX942-NEXT: s_nop 1
+; GFX942-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v4, vcc
; GFX942-NEXT: s_setpc_b64 s[30:31]
;
; GFX1030-LABEL: srem64_3:
@@ -73,16 +73,15 @@ define noundef i64 @srem64_3(i64 noundef %i) {
; GFX1030-NEXT: v_mov_b32_e32 v2, v4
; GFX1030-NEXT: v_ashrrev_i32_e32 v4, 31, v1
; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, 0x55555555, v0, v[2:3]
+; GFX1030-NEXT: v_mul_lo_u32 v6, 0x55555556, v4
; GFX1030-NEXT: v_add_co_u32 v2, s4, v5, v3
; GFX1030-NEXT: v_add_co_ci_u32_e64 v3, null, 0, 0, s4
; GFX1030-NEXT: v_mul_lo_u32 v5, 0x55555555, v4
; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, 0x55555555, v1, v[2:3]
; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, 0x55555556, v4, v[2:3]
-; GFX1030-NEXT: v_mul_lo_u32 v4, 0x55555556, v4
-; GFX1030-NEXT: v_add3_u32 v3, v4, v3, v5
-; GFX1030-NEXT: v_lshrrev_b32_e32 v4, 31, v3
-; GFX1030-NEXT: v_add_co_u32 v2, vcc_lo, v2, v4
-; GFX1030-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v3, vcc_lo
+; GFX1030-NEXT: v_add3_u32 v3, v6, v3, v5
+; GFX1030-NEXT: v_sub_co_u32 v2, vcc_lo, v2, v4
+; GFX1030-NEXT: v_sub_co_ci_u32_e64 v4, null, v3, v4, vcc_lo
; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, v2, 3, 0
; GFX1030-NEXT: v_mad_u64_u32 v[3:4], null, v4, 3, v[3:4]
; GFX1030-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v2
@@ -112,9 +111,8 @@ define noundef i64 @srem64_6(i64 noundef %i) {
; GFX9-NEXT: v_mul_lo_u32 v5, v4, s7
; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v4, s6, v[2:3]
; GFX9-NEXT: v_add3_u32 v3, v6, v3, v5
-; GFX9-NEXT: v_lshrrev_b32_e32 v4, 31, v3
-; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
-; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v3, vcc
+; GFX9-NEXT: v_sub_co_u32_e32 v2, vcc, v2, v4
+; GFX9-NEXT: v_subb_co_u32_e32 v4, vcc, v3, v4, vcc
; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v2, 3, 0
; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v4, 3, v[3:4]
; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v2
@@ -134,21 +132,22 @@ define noundef i64 @srem64_6(i64 noundef %i) {
; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v0, s3, v[4:5]
; GFX942-NEXT: v_mov_b32_e32 v4, v5
; GFX942-NEXT: v_mov_b32_e32 v5, v3
-; GFX942-NEXT: v_lshl_add_u64 v[4:5], v[2:3], 0, v[4:5]
-; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v1, s3, v[4:5]
-; GFX942-NEXT: v_ashrrev_i32_e32 v2, 31, v1
-; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v2, s2, v[4:5]
-; GFX942-NEXT: v_mul_lo_u32 v6, v2, s3
-; GFX942-NEXT: v_mul_lo_u32 v2, v2, s2
-; GFX942-NEXT: v_add3_u32 v5, v2, v5, v6
-; GFX942-NEXT: v_lshrrev_b32_e32 v2, 31, v5
-; GFX942-NEXT: v_lshl_add_u64 v[2:3], v[4:5], 0, v[2:3]
-; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v2, 3, 0
-; GFX942-NEXT: v_mov_b32_e32 v2, v5
-; GFX942-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v3, 3, v[2:3]
-; GFX942-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v4
+; GFX942-NEXT: v_lshl_add_u64 v[2:3], v[2:3], 0, v[4:5]
+; GFX942-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v1, s3, v[2:3]
+; GFX942-NEXT: v_ashrrev_i32_e32 v4, 31, v1
+; GFX942-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v4, s2, v[2:3]
+; GFX942-NEXT: v_mul_lo_u32 v5, v4, s3
+; GFX942-NEXT: v_mul_lo_u32 v6, v4, s2
+; GFX942-NEXT: v_add3_u32 v3, v6, v3, v5
+; GFX942-NEXT: v_sub_co_u32_e32 v2, vcc, v2, v4
; GFX942-NEXT: s_nop 1
-; GFX942-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v2, vcc
+; GFX942-NEXT: v_subb_co_u32_e32 v5, vcc, v3, v4, vcc
+; GFX942-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v2, 3, 0
+; GFX942-NEXT: v_mov_b32_e32 v4, v3
+; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v5, 3, v[4:5]
+; GFX942-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v2
+; GFX942-NEXT: s_nop 1
+; GFX942-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v4, vcc
; GFX942-NEXT: s_setpc_b64 s[30:31]
;
; GFX1030-LABEL: srem64_6:
@@ -160,16 +159,15 @@ define noundef i64 @srem64_6(i64 noundef %i) {
; GFX1030-NEXT: v_mov_b32_e32 v2, v4
; GFX1030-NEXT: v_ashrrev_i32_e32 v4, 31, v1
; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, 0x55555555, v0, v[2:3]
+; GFX1030-NEXT: v_mul_lo_u32 v6, 0x55555556, v4
; GFX1030-NEXT: v_add_co_u32 v2, s4, v5, v3
; GFX1030-NEXT: v_add_co_ci_u32_e64 v3, null, 0, 0, s4
; GFX1030-NEXT: v_mul_lo_u32 v5, 0x55555555, v4
; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, 0x55555555, v1, v[2:3]
; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, 0x55555556, v4, v[2:3]
-; GFX1030-NEXT: v_mul_lo_u32 v4, 0x55555556, v4
-; GFX1030-NEXT: v_add3_u32 v3, v4, v3, v5
-; GFX1030-NEXT: v_lshrrev_b32_e32 v4, 31, v3
-; GFX1030-NEXT: v_add_co_u32 v2, vcc_lo, v2, v4
-; GFX1030-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v3, vcc_lo
+; GFX1030-NEXT: v_add3_u32 v3, v6, v3, v5
+; GFX1030-NEXT: v_sub_co_u32 v2, vcc_lo, v2, v4
+; GFX1030-NEXT: v_sub_co_ci_u32_e64 v4, null, v3, v4, vcc_lo
; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, v2, 3, 0
; GFX1030-NEXT: v_mad_u64_u32 v[3:4], null, v4, 3, v[3:4]
; GFX1030-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v2
@@ -331,17 +329,16 @@ define noundef i64 @sdiv64_3(i64 noundef %i) {
; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v1, s6, v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v2, v4
; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v0, s7, v[2:3]
-; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v1
-; GFX9-NEXT: v_mul_lo_u32 v4, v0, s7
+; GFX9-NEXT: v_ashrrev_i32_e32 v4, 31, v1
+; GFX9-NEXT: v_mul_lo_u32 v6, v4, s6
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v5, v3
; GFX9-NEXT: v_addc_co_u32_e64 v3, s[4:5], 0, 0, vcc
; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v1, s7, v[2:3]
-; GFX9-NEXT: v_mul_lo_u32 v5, v0, s6
-; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, s6, v[2:3]
-; GFX9-NEXT: v_add3_u32 v1, v5, v1, v4
-; GFX9-NEXT: v_lshrrev_b32_e32 v2, 31, v1
-; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
-; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-NEXT: v_mul_lo_u32 v5, v4, s7
+; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v4, s6, v[2:3]
+; GFX9-NEXT: v_add3_u32 v1, v6, v1, v5
+; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v4
+; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v4, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: sdiv64_3:
@@ -357,15 +354,16 @@ define noundef i64 @sdiv64_3(i64 noundef %i) {
; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v0, s3, v[4:5]
; GFX942-NEXT: v_mov_b32_e32 v4, v5
; GFX942-NEXT: v_mov_b32_e32 v5, v3
-; GFX942-NEXT: v_lshl_add_u64 v[4:5], v[2:3], 0, v[4:5]
-; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v1, s3, v[4:5]
-; GFX942-NEXT: v_ashrrev_i32_e32 v2, 31, v1
-; GFX942-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, s2, v[4:5]
-; GFX942-NEXT: v_mul_lo_u32 v4, v2, s3
-; GFX942-NEXT: v_mul_lo_u32 v2, v2, s2
-; GFX942-NEXT: v_add3_u32 v1, v2, v1, v4
-; GFX942-NEXT: v_lshrrev_b32_e32 v2, 31, v1
-; GFX942-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, v[2:3]
+; GFX942-NEXT: v_lshl_add_u64 v[2:3], v[2:3], 0, v[4:5]
+; GFX942-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v1, s3, v[2:3]
+; GFX942-NEXT: v_ashrrev_i32_e32 v4, 31, v1
+; GFX942-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v4, s2, v[2:3]
+; GFX942-NEXT: v_mul_lo_u32 v2, v4, s3
+; GFX942-NEXT: v_mul_lo_u32 v3, v4, s2
+; GFX942-NEXT: v_add3_u32 v1, v3, v1, v2
+; GFX942-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v4
+; GFX942-NEXT: s_nop 1
+; GFX942-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v4, vcc
; GFX942-NEXT: s_setpc_b64 s[30:31]
;
; GFX1030-LABEL: sdiv64_3:
@@ -375,18 +373,17 @@ define noundef i64 @sdiv64_3(i64 noundef %i) {
; GFX1030-NEXT: v_mov_b32_e32 v3, 0
; GFX1030-NEXT: v_mad_u64_u32 v[4:5], null, 0x55555556, v1, v[2:3]
; GFX1030-NEXT: v_mov_b32_e32 v2, v4
+; GFX1030-NEXT: v_ashrrev_i32_e32 v4, 31, v1
; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, 0x55555555, v0, v[2:3]
-; GFX1030-NEXT: v_ashrrev_i32_e32 v0, 31, v1
-; GFX1030-NEXT: v_mul_lo_u32 v4, 0x55555555, v0
; GFX1030-NEXT: v_add_co_u32 v2, s4, v5, v3
; GFX1030-NEXT: v_add_co_ci_u32_e64 v3, null, 0, 0, s4
-; GFX1030-NEXT: v_mul_lo_u32 v5, 0x55555556, v0
+; GFX1030-NEXT: v_mul_lo_u32 v5, 0x55555555, v4
; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, 0x55555555, v1, v[2:3]
-; GFX1030-NEXT: v_mad_u64_u32 v[0:1], null, 0x55555556, v0, v[2:3]
-; GFX1030-NEXT: v_add3_u32 v1, v5, v1, v4
-; GFX1030-NEXT: v_lshrrev_b32_e32 v2, 31, v1
-; GFX1030-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
-; GFX1030-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX1030-NEXT: v_mad_u64_u32 v[0:1], null, 0x55555556, v4, v[2:3]
+; GFX1030-NEXT: v_mul_lo_u32 v2, 0x55555556, v4
+; GFX1030-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v4
+; GFX1030-NEXT: v_add3_u32 v1, v2, v1, v5
+; GFX1030-NEXT: v_sub_co_ci_u32_e64 v1, null, v1, v4, vcc_lo
; GFX1030-NEXT: s_setpc_b64 s[30:31]
entry:
%div = sdiv i64 %i, 3
@@ -404,17 +401,16 @@ define noundef i64 @sdiv64_6(i64 noundef %i) {
; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v1, s6, v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v2, v4
; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v0, s7, v[2:3]
-; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v1
-; GFX9-NEXT: v_mul_lo_u32 v4, v0, s7
+; GFX9-NEXT: v_ashrrev_i32_e32 v4, 31, v1
+; GFX9-NEXT: v_mul_lo_u32 v6, v4, s6
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v5, v3
; GFX9-NEXT: v_addc_co_u32_e64 v3, s[4:5], 0, 0, vcc
; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v1, s7, v[2:3]
-; GFX9-NEXT: v_mul_lo_u32 v5, v0, s6
-; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, s6, v[2:3]
-; GFX9-NEXT: v_add3_u32 v1, v5, v1, v4
-; GFX9-NEXT: v_lshrrev_b32_e32 v2, 31, v1
-; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
-; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
+; GFX9-NEXT: v_mul_lo_u32 v5, v4, s7
+; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v4, s6, v[2:3]
+; GFX9-NEXT: v_add3_u32 v1, v6, v1, v5
+; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v4
+; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v4, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX942-LABEL: sdiv64_6:
@@ -430,15 +426,16 @@ define noundef i64 @sdiv64_6(i64 noundef %i) {
; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v0, s3, v[4:5]
; GFX942-NEXT: v_mov_b32_e32 v4, v5
; GFX942-NEXT: v_mov_b32_e32 v5, v3
-; GFX942-NEXT: v_lshl_add_u64 v[4:5], v[2:3], 0, v[4:5]
-; GFX942-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v1, s3, v[4:5]
-; GFX942-NEXT: v_ashrrev_i32_e32 v2, 31, v1
-; GFX942-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, s2, v[4:5]
-; GFX942-NEXT: v_mul_lo_u32 v4, v2, s3
-; GFX942-NEXT: v_mul_lo_u32 v2, v2, s2
-; GFX942-NEXT: v_add3_u32 v1, v2, v1, v4
-; GFX942-NEXT: v_lshrrev_b32_e32 v2, 31, v1
-; GFX942-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, v[2:3]
+; GFX942-NEXT: v_lshl_add_u64 v[2:3], v[2:3], 0, v[4:5]
+; GFX942-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v1, s3, v[2:3]
+; GFX942-NEXT: v_ashrrev_i32_e32 v4, 31, v1
+; GFX942-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v4, s2, v[2:3]
+; GFX942-NEXT: v_mul_lo_u32 v2, v4, s3
+; GFX942-NEXT: v_mul_lo_u32 v3, v4, s2
+; GFX942-NEXT: v_add3_u32 v1, v3, v1, v2
+; GFX942-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v4
+; GFX942-NEXT: s_nop 1
+; GFX942-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v4, vcc
; GFX942-NEXT: s_setpc_b64 s[30:31]
;
; GFX1030-LABEL: sdiv64_6:
@@ -448,18 +445,17 @@ define noundef i64 @sdiv64_6(i64 noundef %i) {
; GFX1030-NEXT: v_mov_b32_e32 v3, 0
; GFX1030-NEXT: v_mad_u64_u32 v[4:5], null, 0x55555556, v1, v[2:3]
; GFX1030-NEXT: v_mov_b32_e32 v2, v4
+; GFX1030-NEXT: v_ashrrev_i32_e32 v4, 31, v1
; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, 0x55555555, v0, v[2:3]
-; GFX1030-NEXT: v_ashrrev_i32_e32 v0, 31, v1
-; GFX1030-NEXT: v_mul_lo_u32 v4, 0x55555555, v0
; GFX1030-NEXT: v_add_co_u32 v2, s4, v5, v3
; GFX1030-NEXT: v_add_co_ci_u32_e64 v3, null, 0, 0, s4
-; GFX1030-NEXT: v_mul_lo_u32 v5, 0x55555556, v0
+; GFX1030-NEXT: v_mul_lo_u32 v5, 0x55555555, v4
; GFX1030-NEXT: v_mad_u64_u32 v[2:3], null, 0x55555555, v1, v[2:3]
-; GFX1030-NEXT: v_mad_u64_u32 v[0:1], null, 0x55555556, v0, v[2:3]
-; GFX1030-NEXT: v_add3_u32 v1, v5, v1, v4
-; GFX1030-NEXT: v_lshrrev_b32_e32 v2, 31, v1
-; GFX1030-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
-; GFX1030-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX1030-NEXT: v_mad_u64_u32 v[0:1], null, 0x55555556, v4, v[2:3]
+; GFX1030-NEXT: v_mul_lo_u32 v2, 0x55555556, v4
+; GFX1030-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v4
+; GFX1030-NEXT: v_add3_u32 v1, v2, v1, v5
+; GFX1030-NEXT: v_sub_co_ci_u32_e64 v1, null, v1, v4, vcc_lo
; GFX1030-NEXT: s_setpc_b64 s[30:31]
entry:
%div = sdiv i64 %i, 3
diff --git a/llvm/test/CodeGen/AMDGPU/sdiv.ll b/llvm/test/CodeGen/AMDGPU/sdiv.ll
index 441509ba01f64..4394819e3a9f5 100644
--- a/llvm/test/CodeGen/AMDGPU/sdiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/sdiv.ll
@@ -2200,22 +2200,22 @@ define amdgpu_kernel void @scalarize_mulhs_4xi32(ptr addrspace(1) nocapture read
; GCN-NEXT: s_mov_b32 s4, s2
; GCN-NEXT: s_mov_b32 s5, s3
; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: v_ashrrev_i32_e32 v4, 31, v0
; GCN-NEXT: v_mul_hi_i32 v0, v0, s0
+; GCN-NEXT: v_ashrrev_i32_e32 v5, 31, v1
; GCN-NEXT: v_mul_hi_i32 v1, v1, s0
+; GCN-NEXT: v_ashrrev_i32_e32 v6, 31, v2
; GCN-NEXT: v_mul_hi_i32 v2, v2, s0
+; GCN-NEXT: v_ashrrev_i32_e32 v7, 31, v3
; GCN-NEXT: v_mul_hi_i32 v3, v3, s0
-; GCN-NEXT: v_lshrrev_b32_e32 v4, 31, v0
; GCN-NEXT: v_ashrrev_i32_e32 v0, 12, v0
-; GCN-NEXT: v_lshrrev_b32_e32 v5, 31, v1
; GCN-NEXT: v_ashrrev_i32_e32 v1, 12, v1
-; GCN-NEXT: v_lshrrev_b32_e32 v6, 31, v2
; GCN-NEXT: v_ashrrev_i32_e32 v2, 12, v2
-; GCN-NEXT: v_lshrrev_b32_e32 v7, 31, v3
; GCN-NEXT: v_ashrrev_i32_e32 v3, 12, v3
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4
-; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v5
-; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v6
-; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v7
+; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
+; GCN-NEXT: v_sub_i32_e32 v1, vcc, v1, v5
+; GCN-NEXT: v_sub_i32_e32 v2, vcc, v2, v6
+; GCN-NEXT: v_sub_i32_e32 v3, vcc, v3, v7
; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; GCN-NEXT: s_endpgm
;
@@ -2232,22 +2232,22 @@ define amdgpu_kernel void @scalarize_mulhs_4xi32(ptr addrspace(1) nocapture read
; TONGA-NEXT: s_mov_b32 s4, s2
; TONGA-NEXT: s_mov_b32 s5, s3
; TONGA-NEXT: s_waitcnt vmcnt(0)
+; TONGA-NEXT: v_ashrrev_i32_e32 v4, 31, v0
; TONGA-NEXT: v_mul_hi_i32 v0, v0, s0
+; TONGA-NEXT: v_ashrrev_i32_e32 v5, 31, v1
; TONGA-NEXT: v_mul_hi_i32 v1, v1, s0
+; TONGA-NEXT: v_ashrrev_i32_e32 v6, 31, v2
; TONGA-NEXT: v_mul_hi_i32 v2, v2, s0
+; TONGA-NEXT: v_ashrrev_i32_e32 v7, 31, v3
; TONGA-NEXT: v_mul_hi_i32 v3, v3, s0
-; TONGA-NEXT: v_lshrrev_b32_e32 v4, 31, v0
; TONGA-NEXT: v_ashrrev_i32_e32 v0, 12, v0
-; TONGA-NEXT: v_lshrrev_b32_e32 v5, 31, v1
; TONGA-NEXT: v_ashrrev_i32_e32 v1, 12, v1
-; TONGA-NEXT: v_lshrrev_b32_e32 v6, 31, v2
; TONGA-NEXT: v_ashrrev_i32_e32 v2, 12, v2
-; TONGA-NEXT: v_lshrrev_b32_e32 v7, 31, v3
; TONGA-NEXT: v_ashrrev_i32_e32 v3, 12, v3
-; TONGA-NEXT: v_add_u32_e32 v0, vcc, v0, v4
-; TONGA-NEXT: v_add_u32_e32 v1, vcc, v1, v5
-; TONGA-NEXT: v_add_u32_e32 v2, vcc, v2, v6
-; TONGA-NEXT: v_add_u32_e32 v3, vcc, v3, v7
+; TONGA-NEXT: v_sub_u32_e32 v0, vcc, v0, v4
+; TONGA-NEXT: v_sub_u32_e32 v1, vcc, v1, v5
+; TONGA-NEXT: v_sub_u32_e32 v2, vcc, v2, v6
+; TONGA-NEXT: v_sub_u32_e32 v3, vcc, v3, v7
; TONGA-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; TONGA-NEXT: s_endpgm
;
@@ -2264,22 +2264,22 @@ define amdgpu_kernel void @scalarize_mulhs_4xi32(ptr addrspace(1) nocapture read
; GFX9-NEXT: s_mov_b32 s4, s2
; GFX9-NEXT: s_mov_b32 s5, s3
; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_ashrrev_i32_e32 v4, 31, v0
; GFX9-NEXT: v_mul_hi_i32 v0, v0, s0
+; GFX9-NEXT: v_ashrrev_i32_e32 v5, 31, v1
; GFX9-NEXT: v_mul_hi_i32 v1, v1, s0
+; GFX9-NEXT: v_ashrrev_i32_e32 v6, 31, v2
; GFX9-NEXT: v_mul_hi_i32 v2, v2, s0
+; GFX9-NEXT: v_ashrrev_i32_e32 v7, 31, v3
; GFX9-NEXT: v_mul_hi_i32 v3, v3, s0
-; GFX9-NEXT: v_lshrrev_b32_e32 v4, 31, v0
; GFX9-NEXT: v_ashrrev_i32_e32 v0, 12, v0
-; GFX9-NEXT: v_lshrrev_b32_e32 v5, 31, v1
; GFX9-NEXT: v_ashrrev_i32_e32 v1, 12, v1
-; GFX9-NEXT: v_lshrrev_b32_e32 v6, 31, v2
; GFX9-NEXT: v_ashrrev_i32_e32 v2, 12, v2
-; GFX9-NEXT: v_lshrrev_b32_e32 v7, 31, v3
; GFX9-NEXT: v_ashrrev_i32_e32 v3, 12, v3
-; GFX9-NEXT: v_add_u32_e32 v0, v0, v4
-; GFX9-NEXT: v_add_u32_e32 v1, v1, v5
-; GFX9-NEXT: v_add_u32_e32 v2, v2, v6
-; GFX9-NEXT: v_add_u32_e32 v3, v3, v7
+; GFX9-NEXT: v_sub_u32_e32 v0, v0, v4
+; GFX9-NEXT: v_sub_u32_e32 v1, v1, v5
+; GFX9-NEXT: v_sub_u32_e32 v2, v2, v6
+; GFX9-NEXT: v_sub_u32_e32 v3, v3, v7
; GFX9-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; GFX9-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/srem-seteq-illegal-types.ll b/llvm/test/CodeGen/AMDGPU/srem-seteq-illegal-types.ll
index 2efe27df2d10d..701d5aee1082f 100644
--- a/llvm/test/CodeGen/AMDGPU/srem-seteq-illegal-types.ll
+++ b/llvm/test/CodeGen/AMDGPU/srem-seteq-illegal-types.ll
@@ -23,10 +23,10 @@ define i1 @test_srem_even(i4 %X) nounwind {
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_bfe_i32 v1, v0, 0, 4
+; CHECK-NEXT: v_lshrrev_b32_e32 v2, 3, v1
; CHECK-NEXT: v_mul_i32_i24_e32 v1, 3, v1
-; CHECK-NEXT: v_lshrrev_b32_e32 v2, 4, v1
-; CHECK-NEXT: v_bfe_u32 v1, v1, 7, 1
-; CHECK-NEXT: v_add_i32_e32 v1, vcc, v2, v1
+; CHECK-NEXT: v_lshrrev_b32_e32 v1, 4, v1
+; CHECK-NEXT: v_sub_i32_e32 v1, vcc, v1, v2
; CHECK-NEXT: v_and_b32_e32 v1, 15, v1
; CHECK-NEXT: v_mul_u32_u24_e32 v1, 6, v1
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
@@ -65,19 +65,19 @@ define <3 x i1> @test_srem_vec(<3 x i31> %X) nounwind {
; CHECK-NEXT: v_bfe_i32 v4, v1, 0, 31
; CHECK-NEXT: v_bfe_i32 v5, v0, 0, 31
; CHECK-NEXT: s_mov_b32 s4, 0x38e38e39
+; CHECK-NEXT: v_bfe_i32 v6, v0, 30, 1
+; CHECK-NEXT: v_bfe_i32 v7, v1, 30, 1
; CHECK-NEXT: s_mov_b32 s5, 0xc71c71c7
; CHECK-NEXT: s_mov_b32 s6, 0x7ffffffd
; CHECK-NEXT: v_mul_hi_i32 v5, v5, s4
; CHECK-NEXT: v_mul_hi_i32 v4, v4, s4
; CHECK-NEXT: v_mul_hi_i32 v3, v3, s5
-; CHECK-NEXT: v_lshrrev_b32_e32 v6, 31, v5
; CHECK-NEXT: v_lshrrev_b32_e32 v5, 1, v5
-; CHECK-NEXT: v_lshrrev_b32_e32 v7, 31, v4
; CHECK-NEXT: v_lshrrev_b32_e32 v4, 1, v4
; CHECK-NEXT: v_lshrrev_b32_e32 v8, 31, v3
; CHECK-NEXT: v_lshrrev_b32_e32 v3, 1, v3
-; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6
-; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v7
+; CHECK-NEXT: v_sub_i32_e32 v5, vcc, v5, v6
+; CHECK-NEXT: v_sub_i32_e32 v4, vcc, v4, v7
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v8
; CHECK-NEXT: v_mul_lo_u32 v5, v5, 9
; CHECK-NEXT: v_mul_lo_u32 v4, v4, 9
@@ -88,12 +88,12 @@ define <3 x i1> @test_srem_vec(<3 x i31> %X) nounwind {
; CHECK-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2
; CHECK-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
; CHECK-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
+; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 3, v2
+; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 3, v0
; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, s6, v1
; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 3, v2
-; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; CHECK-NEXT: s_setpc_b64 s[30:31]
%srem = srem <3 x i31> %X, <i31 9, i31 9, i31 -9>
%cmp = icmp ne <3 x i31> %srem, <i31 3, i31 -3, i31 3>
diff --git a/llvm/test/CodeGen/AMDGPU/srem.ll b/llvm/test/CodeGen/AMDGPU/srem.ll
index 089c0b2d46578..76a386a7e56bd 100644
--- a/llvm/test/CodeGen/AMDGPU/srem.ll
+++ b/llvm/test/CodeGen/AMDGPU/srem.ll
@@ -14,10 +14,10 @@ define amdgpu_kernel void @srem_i16_7(ptr addrspace(1) %out, ptr addrspace(1) %i
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_readfirstlane_b32 s2, v1
; GCN-NEXT: s_sext_i32_i16 s2, s2
+; GCN-NEXT: s_ashr_i32 s3, s2, 15
; GCN-NEXT: s_mulk_i32 s2, 0x4925
-; GCN-NEXT: s_lshr_b32 s3, s2, 31
; GCN-NEXT: s_ashr_i32 s2, s2, 17
-; GCN-NEXT: s_add_i32 s2, s2, s3
+; GCN-NEXT: s_sub_i32 s2, s2, s3
; GCN-NEXT: s_mul_i32 s2, s2, 7
; GCN-NEXT: v_subrev_u32_e32 v1, s2, v1
; GCN-NEXT: global_store_short v0, v1, s[0:1]
@@ -34,16 +34,16 @@ define amdgpu_kernel void @srem_i16_7(ptr addrspace(1) %out, ptr addrspace(1) %i
; TAHITI-NEXT: s_mov_b32 s8, s2
; TAHITI-NEXT: s_mov_b32 s9, s3
; TAHITI-NEXT: buffer_load_sshort v0, off, s[8:11], 0
+; TAHITI-NEXT: s_movk_i32 s2, 0x4925
; TAHITI-NEXT: s_mov_b32 s4, s0
; TAHITI-NEXT: s_mov_b32 s5, s1
; TAHITI-NEXT: s_waitcnt vmcnt(0)
-; TAHITI-NEXT: v_readfirstlane_b32 s0, v0
-; TAHITI-NEXT: s_mulk_i32 s0, 0x4925
-; TAHITI-NEXT: s_lshr_b32 s1, s0, 31
-; TAHITI-NEXT: s_ashr_i32 s0, s0, 17
-; TAHITI-NEXT: s_add_i32 s0, s0, s1
-; TAHITI-NEXT: s_mul_i32 s0, s0, 7
-; TAHITI-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0
+; TAHITI-NEXT: v_mul_lo_u32 v1, v0, s2
+; TAHITI-NEXT: v_lshrrev_b32_e32 v2, 15, v0
+; TAHITI-NEXT: v_ashrrev_i32_e32 v1, 17, v1
+; TAHITI-NEXT: v_sub_i32_e32 v1, vcc, v1, v2
+; TAHITI-NEXT: v_mul_lo_u32 v1, v1, 7
+; TAHITI-NEXT: v_subrev_i32_e32 v0, vcc, v1, v0
; TAHITI-NEXT: buffer_store_short v0, off, s[4:7], 0
; TAHITI-NEXT: s_endpgm
;
@@ -59,10 +59,10 @@ define amdgpu_kernel void @srem_i16_7(ptr addrspace(1) %out, ptr addrspace(1) %i
; TONGA-NEXT: s_waitcnt vmcnt(0)
; TONGA-NEXT: v_readfirstlane_b32 s0, v2
; TONGA-NEXT: s_sext_i32_i16 s0, s0
+; TONGA-NEXT: s_ashr_i32 s1, s0, 15
; TONGA-NEXT: s_mulk_i32 s0, 0x4925
-; TONGA-NEXT: s_lshr_b32 s1, s0, 31
; TONGA-NEXT: s_ashr_i32 s0, s0, 17
-; TONGA-NEXT: s_add_i32 s0, s0, s1
+; TONGA-NEXT: s_sub_i32 s0, s0, s1
; TONGA-NEXT: s_mul_i32 s0, s0, 7
; TONGA-NEXT: v_subrev_u32_e32 v2, vcc, s0, v2
; TONGA-NEXT: flat_store_short v[0:1], v2
@@ -85,10 +85,10 @@ define amdgpu_kernel void @srem_i16_7(ptr addrspace(1) %out, ptr addrspace(1) %i
; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
; EG-NEXT: MULLO_INT * T0.Y, PV.W, literal.x,
; EG-NEXT: 18725(2.623931e-41), 0(0.000000e+00)
-; EG-NEXT: ASHR T0.W, PS, literal.x,
-; EG-NEXT: LSHR * T1.W, PS, literal.y,
-; EG-NEXT: 17(2.382207e-44), 31(4.344025e-44)
-; EG-NEXT: ADD_INT * T0.W, PV.W, PS,
+; EG-NEXT: ASHR T1.W, PS, literal.x,
+; EG-NEXT: LSHR * T0.W, T0.W, literal.y,
+; EG-NEXT: 17(2.382207e-44), 15(2.101948e-44)
+; EG-NEXT: SUB_INT * T0.W, PV.W, PS,
; EG-NEXT: MULLO_INT * T0.Y, PV.W, literal.x,
; EG-NEXT: 7(9.809089e-45), 0(0.000000e+00)
; EG-NEXT: AND_INT T0.W, KC0[2].Y, literal.x,
diff --git a/llvm/test/CodeGen/AMDGPU/trunc-combine.ll b/llvm/test/CodeGen/AMDGPU/trunc-combine.ll
index 0fd79048301cc..2cc764a5e0ec9 100644
--- a/llvm/test/CodeGen/AMDGPU/trunc-combine.ll
+++ b/llvm/test/CodeGen/AMDGPU/trunc-combine.ll
@@ -345,10 +345,10 @@ define <2 x i16> @vector_trunc_high_bits_undef_sdiv_lhs_alignbit_regression(i32
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_mov_b32 s4, 0x38e38e39
-; SI-NEXT: v_mul_hi_i32 v0, v0, s4
-; SI-NEXT: v_lshrrev_b32_e32 v1, 31, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 2, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, v0, v1
+; SI-NEXT: v_mul_hi_i32 v1, v0, s4
+; SI-NEXT: v_ashrrev_i32_e32 v0, 31, v0
+; SI-NEXT: v_lshrrev_b32_e32 v1, 2, v1
+; SI-NEXT: v_sub_i32_e32 v0, vcc, v1, v0
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; SI-NEXT: s_setpc_b64 s[30:31]
;
@@ -356,10 +356,10 @@ define <2 x i16> @vector_trunc_high_bits_undef_sdiv_lhs_alignbit_regression(i32
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_mov_b32 s4, 0x38e38e39
-; VI-NEXT: v_mul_hi_i32 v0, v0, s4
-; VI-NEXT: v_lshrrev_b32_e32 v1, 31, v0
-; VI-NEXT: v_ashrrev_i32_e32 v0, 2, v0
-; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v1
+; VI-NEXT: v_mul_hi_i32 v1, v0, s4
+; VI-NEXT: v_ashrrev_i32_e32 v0, 31, v0
+; VI-NEXT: v_ashrrev_i32_e32 v1, 2, v1
+; VI-NEXT: v_sub_u32_e32 v0, vcc, v1, v0
; VI-NEXT: s_setpc_b64 s[30:31]
%undef.hi.elt = insertelement <2 x i32> poison, i32 %arg0, i32 0
%lshr = sdiv <2 x i32> %undef.hi.elt, splat (i32 18)
@@ -373,9 +373,9 @@ define <2 x i16> @vector_trunc_high_bits_undef_srem_lhs_alignbit_regression(i32
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_mov_b32 s4, 0x38e38e39
; SI-NEXT: v_mul_hi_i32 v1, v0, s4
-; SI-NEXT: v_lshrrev_b32_e32 v2, 31, v1
+; SI-NEXT: v_ashrrev_i32_e32 v2, 31, v0
; SI-NEXT: v_lshrrev_b32_e32 v1, 2, v1
-; SI-NEXT: v_add_i32_e32 v1, vcc, v1, v2
+; SI-NEXT: v_sub_i32_e32 v1, vcc, v1, v2
; SI-NEXT: v_mul_lo_u32 v1, v1, 18
; SI-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -386,9 +386,9 @@ define <2 x i16> @vector_trunc_high_bits_undef_srem_lhs_alignbit_regression(i32
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_mov_b32 s4, 0x38e38e39
; VI-NEXT: v_mul_hi_i32 v1, v0, s4
-; VI-NEXT: v_lshrrev_b32_e32 v2, 31, v1
+; VI-NEXT: v_ashrrev_i32_e32 v2, 31, v0
; VI-NEXT: v_ashrrev_i32_e32 v1, 2, v1
-; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v2
+; VI-NEXT: v_sub_u32_e32 v1, vcc, v1, v2
; VI-NEXT: v_mul_lo_u32 v1, v1, 18
; VI-NEXT: v_sub_u32_e32 v0, vcc, v0, v1
; VI-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/ARM/srem-seteq-illegal-types.ll b/llvm/test/CodeGen/ARM/srem-seteq-illegal-types.ll
index 973362462f735..9a7bac62064cf 100644
--- a/llvm/test/CodeGen/ARM/srem-seteq-illegal-types.ll
+++ b/llvm/test/CodeGen/ARM/srem-seteq-illegal-types.ll
@@ -116,9 +116,9 @@ define i1 @test_srem_even(i4 %X) nounwind {
; ARM5: @ %bb.0:
; ARM5-NEXT: lsl r1, r0, #28
; ARM5-NEXT: asr r1, r1, #28
-; ARM5-NEXT: add r1, r1, r1, lsl #1
-; ARM5-NEXT: lsr r2, r1, #4
-; ARM5-NEXT: add r1, r2, r1, lsr #31
+; ARM5-NEXT: add r2, r1, r1, lsl #1
+; ARM5-NEXT: lsr r2, r2, #4
+; ARM5-NEXT: sub r1, r2, r1, lsr #3
; ARM5-NEXT: add r1, r1, r1, lsl #1
; ARM5-NEXT: sub r0, r0, r1, lsl #1
; ARM5-NEXT: and r0, r0, #15
@@ -131,9 +131,9 @@ define i1 @test_srem_even(i4 %X) nounwind {
; ARM6: @ %bb.0:
; ARM6-NEXT: lsl r1, r0, #28
; ARM6-NEXT: asr r1, r1, #28
-; ARM6-NEXT: add r1, r1, r1, lsl #1
-; ARM6-NEXT: lsr r2, r1, #4
-; ARM6-NEXT: add r1, r2, r1, lsr #31
+; ARM6-NEXT: add r2, r1, r1, lsl #1
+; ARM6-NEXT: lsr r2, r2, #4
+; ARM6-NEXT: sub r1, r2, r1, lsr #3
; ARM6-NEXT: add r1, r1, r1, lsl #1
; ARM6-NEXT: sub r0, r0, r1, lsl #1
; ARM6-NEXT: and r0, r0, #15
@@ -145,9 +145,9 @@ define i1 @test_srem_even(i4 %X) nounwind {
; ARM7-LABEL: test_srem_even:
; ARM7: @ %bb.0:
; ARM7-NEXT: sbfx r1, r0, #0, #4
-; ARM7-NEXT: add r1, r1, r1, lsl #1
-; ARM7-NEXT: lsr r2, r1, #4
-; ARM7-NEXT: add r1, r2, r1, lsr #31
+; ARM7-NEXT: add r2, r1, r1, lsl #1
+; ARM7-NEXT: lsr r2, r2, #4
+; ARM7-NEXT: sub r1, r2, r1, lsr #3
; ARM7-NEXT: add r1, r1, r1, lsl #1
; ARM7-NEXT: sub r0, r0, r1, lsl #1
; ARM7-NEXT: and r0, r0, #15
@@ -159,9 +159,9 @@ define i1 @test_srem_even(i4 %X) nounwind {
; ARM8-LABEL: test_srem_even:
; ARM8: @ %bb.0:
; ARM8-NEXT: sbfx r1, r0, #0, #4
-; ARM8-NEXT: add r1, r1, r1, lsl #1
-; ARM8-NEXT: lsr r2, r1, #4
-; ARM8-NEXT: add r1, r2, r1, lsr #31
+; ARM8-NEXT: add r2, r1, r1, lsl #1
+; ARM8-NEXT: lsr r2, r2, #4
+; ARM8-NEXT: sub r1, r2, r1, lsr #3
; ARM8-NEXT: add r1, r1, r1, lsl #1
; ARM8-NEXT: sub r0, r0, r1, lsl #1
; ARM8-NEXT: and r0, r0, #15
@@ -173,9 +173,9 @@ define i1 @test_srem_even(i4 %X) nounwind {
; NEON7-LABEL: test_srem_even:
; NEON7: @ %bb.0:
; NEON7-NEXT: sbfx r1, r0, #0, #4
-; NEON7-NEXT: add r1, r1, r1, lsl #1
-; NEON7-NEXT: lsr r2, r1, #4
-; NEON7-NEXT: add r1, r2, r1, lsr #31
+; NEON7-NEXT: add r2, r1, r1, lsl #1
+; NEON7-NEXT: lsr r2, r2, #4
+; NEON7-NEXT: sub r1, r2, r1, lsr #3
; NEON7-NEXT: add r1, r1, r1, lsl #1
; NEON7-NEXT: sub r0, r0, r1, lsl #1
; NEON7-NEXT: and r0, r0, #15
@@ -187,9 +187,9 @@ define i1 @test_srem_even(i4 %X) nounwind {
; NEON8-LABEL: test_srem_even:
; NEON8: @ %bb.0:
; NEON8-NEXT: sbfx r1, r0, #0, #4
-; NEON8-NEXT: add r1, r1, r1, lsl #1
-; NEON8-NEXT: lsr r2, r1, #4
-; NEON8-NEXT: add r1, r2, r1, lsr #31
+; NEON8-NEXT: add r2, r1, r1, lsl #1
+; NEON8-NEXT: lsr r2, r2, #4
+; NEON8-NEXT: sub r1, r2, r1, lsr #3
; NEON8-NEXT: add r1, r1, r1, lsl #1
; NEON8-NEXT: sub r0, r0, r1, lsl #1
; NEON8-NEXT: and r0, r0, #15
diff --git a/llvm/test/CodeGen/Mips/mips64muldiv.ll b/llvm/test/CodeGen/Mips/mips64muldiv.ll
index 89dd524269491..c338c6b5b3366 100644
--- a/llvm/test/CodeGen/Mips/mips64muldiv.ll
+++ b/llvm/test/CodeGen/Mips/mips64muldiv.ll
@@ -32,8 +32,8 @@ entry:
; ACC: mfhi $[[T1:[0-9]+]]
; GPR: dmuh $[[T1:[0-9]+]], $4, $[[T0]]
-; ALL: dsrl $2, $[[T1]], 63
-; ALL: daddu $2, $[[T1]], $2
+; ALL: dsra $2, $4, 63
+; ALL: dsubu $2, $[[T1]], $2
%div = sdiv i64 %a, 3
ret i64 %div
}
diff --git a/llvm/test/CodeGen/Mips/srem-seteq-illegal-types.ll b/llvm/test/CodeGen/Mips/srem-seteq-illegal-types.ll
index f4c78fb0fe160..1653f3b2823a4 100644
--- a/llvm/test/CodeGen/Mips/srem-seteq-illegal-types.ll
+++ b/llvm/test/CodeGen/Mips/srem-seteq-illegal-types.ll
@@ -44,12 +44,12 @@ define i1 @test_srem_even(i4 %X) nounwind {
; MIPSEL-LABEL: test_srem_even:
; MIPSEL: # %bb.0:
; MIPSEL-NEXT: sll $1, $4, 28
-; MIPSEL-NEXT: sra $1, $1, 28
-; MIPSEL-NEXT: sll $2, $1, 1
-; MIPSEL-NEXT: addu $1, $2, $1
-; MIPSEL-NEXT: srl $2, $1, 31
-; MIPSEL-NEXT: srl $1, $1, 4
-; MIPSEL-NEXT: addu $1, $1, $2
+; MIPSEL-NEXT: sra $2, $1, 28
+; MIPSEL-NEXT: sll $3, $2, 1
+; MIPSEL-NEXT: addu $2, $3, $2
+; MIPSEL-NEXT: srl $2, $2, 4
+; MIPSEL-NEXT: sra $1, $1, 31
+; MIPSEL-NEXT: subu $1, $2, $1
; MIPSEL-NEXT: addiu $2, $zero, 1
; MIPSEL-NEXT: sll $3, $1, 1
; MIPSEL-NEXT: sll $1, $1, 2
@@ -64,19 +64,19 @@ define i1 @test_srem_even(i4 %X) nounwind {
; MIPS64EL: # %bb.0:
; MIPS64EL-NEXT: sll $1, $4, 0
; MIPS64EL-NEXT: sll $2, $1, 28
-; MIPS64EL-NEXT: sra $2, $2, 28
+; MIPS64EL-NEXT: sra $3, $2, 28
+; MIPS64EL-NEXT: sll $4, $3, 1
+; MIPS64EL-NEXT: addu $3, $4, $3
+; MIPS64EL-NEXT: addiu $4, $zero, 1
+; MIPS64EL-NEXT: srl $3, $3, 4
+; MIPS64EL-NEXT: sra $2, $2, 31
+; MIPS64EL-NEXT: subu $2, $3, $2
; MIPS64EL-NEXT: sll $3, $2, 1
-; MIPS64EL-NEXT: addu $2, $3, $2
-; MIPS64EL-NEXT: addiu $3, $zero, 1
-; MIPS64EL-NEXT: srl $4, $2, 31
-; MIPS64EL-NEXT: srl $2, $2, 4
-; MIPS64EL-NEXT: addu $2, $2, $4
-; MIPS64EL-NEXT: sll $4, $2, 1
; MIPS64EL-NEXT: sll $2, $2, 2
-; MIPS64EL-NEXT: addu $2, $2, $4
+; MIPS64EL-NEXT: addu $2, $2, $3
; MIPS64EL-NEXT: subu $1, $1, $2
; MIPS64EL-NEXT: andi $1, $1, 15
-; MIPS64EL-NEXT: xor $1, $1, $3
+; MIPS64EL-NEXT: xor $1, $1, $4
; MIPS64EL-NEXT: jr $ra
; MIPS64EL-NEXT: sltiu $2, $1, 1
%srem = srem i4 %X, 6
diff --git a/llvm/test/CodeGen/PowerPC/machine-pre.ll b/llvm/test/CodeGen/PowerPC/machine-pre.ll
index 1c8e029c5a31e..a19c270b9564b 100644
--- a/llvm/test/CodeGen/PowerPC/machine-pre.ll
+++ b/llvm/test/CodeGen/PowerPC/machine-pre.ll
@@ -92,8 +92,8 @@ define dso_local signext i32 @foo(i32 signext %x, i32 signext %y) nounwind {
; CHECK-P9-NEXT: nop
; CHECK-P9-NEXT: mr r30, r3
; CHECK-P9-NEXT: mulhw r3, r28, r27
-; CHECK-P9-NEXT: srwi r4, r3, 31
-; CHECK-P9-NEXT: add r3, r3, r4
+; CHECK-P9-NEXT: srawi r4, r28, 31
+; CHECK-P9-NEXT: sub r3, r3, r4
; CHECK-P9-NEXT: slwi r4, r3, 1
; CHECK-P9-NEXT: add r3, r3, r4
; CHECK-P9-NEXT: sub r3, r28, r3
diff --git a/llvm/test/CodeGen/PowerPC/srem-lkk.ll b/llvm/test/CodeGen/PowerPC/srem-lkk.ll
index 0a93255781e09..f6f808ebcc692 100644
--- a/llvm/test/CodeGen/PowerPC/srem-lkk.ll
+++ b/llvm/test/CodeGen/PowerPC/srem-lkk.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu -mcpu=ppc64 < %s | FileCheck --check-prefix=CHECK %s
-; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu -mcpu=ppc < %s | FileCheck --check-prefix=CHECK %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu -mcpu=ppc64 < %s | FileCheck --check-prefixes=CHECK,CHECK-64 %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu -mcpu=ppc < %s | FileCheck --check-prefixes=CHECK,CHECK-32 %s
define i32 @fold_srem_positive_odd(i32 %x) {
; CHECK-LABEL: fold_srem_positive_odd:
@@ -21,17 +21,29 @@ define i32 @fold_srem_positive_odd(i32 %x) {
define i32 @fold_srem_positive_even(i32 %x) {
-; CHECK-LABEL: fold_srem_positive_even:
-; CHECK: # %bb.0:
-; CHECK-NEXT: lis 4, 15827
-; CHECK-NEXT: ori 4, 4, 36849
-; CHECK-NEXT: mulhw 4, 3, 4
-; CHECK-NEXT: srwi 5, 4, 31
-; CHECK-NEXT: srawi 4, 4, 8
-; CHECK-NEXT: add 4, 4, 5
-; CHECK-NEXT: mulli 4, 4, 1060
-; CHECK-NEXT: sub 3, 3, 4
-; CHECK-NEXT: blr
+; CHECK-64-LABEL: fold_srem_positive_even:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: lis 4, 15827
+; CHECK-64-NEXT: srawi 5, 3, 31
+; CHECK-64-NEXT: ori 4, 4, 36849
+; CHECK-64-NEXT: mulhw 4, 3, 4
+; CHECK-64-NEXT: srawi 4, 4, 8
+; CHECK-64-NEXT: sub 4, 4, 5
+; CHECK-64-NEXT: mulli 4, 4, 1060
+; CHECK-64-NEXT: sub 3, 3, 4
+; CHECK-64-NEXT: blr
+;
+; CHECK-32-LABEL: fold_srem_positive_even:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: lis 4, 15827
+; CHECK-32-NEXT: ori 4, 4, 36849
+; CHECK-32-NEXT: mulhw 4, 3, 4
+; CHECK-32-NEXT: srawi 4, 4, 8
+; CHECK-32-NEXT: srawi 5, 3, 31
+; CHECK-32-NEXT: sub 4, 4, 5
+; CHECK-32-NEXT: mulli 4, 4, 1060
+; CHECK-32-NEXT: sub 3, 3, 4
+; CHECK-32-NEXT: blr
%1 = srem i32 %x, 1060
ret i32 %1
}
diff --git a/llvm/test/CodeGen/PowerPC/srem-seteq-illegal-types.ll b/llvm/test/CodeGen/PowerPC/srem-seteq-illegal-types.ll
index 18b07b2aa5cec..1b8045f0e1772 100644
--- a/llvm/test/CodeGen/PowerPC/srem-seteq-illegal-types.ll
+++ b/llvm/test/CodeGen/PowerPC/srem-seteq-illegal-types.ll
@@ -45,10 +45,10 @@ define i1 @test_srem_even(i4 %X) nounwind {
; PPC: # %bb.0:
; PPC-NEXT: slwi 4, 3, 28
; PPC-NEXT: srawi 4, 4, 28
+; PPC-NEXT: srwi 5, 4, 3
; PPC-NEXT: mulli 4, 4, 3
-; PPC-NEXT: srwi 5, 4, 31
; PPC-NEXT: srwi 4, 4, 4
-; PPC-NEXT: add 4, 4, 5
+; PPC-NEXT: sub 4, 4, 5
; PPC-NEXT: mulli 4, 4, 6
; PPC-NEXT: sub 3, 3, 4
; PPC-NEXT: clrlwi 3, 3, 28
@@ -64,10 +64,10 @@ define i1 @test_srem_even(i4 %X) nounwind {
; PPC64LE-NEXT: slwi 4, 3, 28
; PPC64LE-NEXT: srawi 4, 4, 28
; PPC64LE-NEXT: slwi 5, 4, 1
-; PPC64LE-NEXT: add 4, 4, 5
-; PPC64LE-NEXT: srwi 5, 4, 31
-; PPC64LE-NEXT: srwi 4, 4, 4
-; PPC64LE-NEXT: add 4, 4, 5
+; PPC64LE-NEXT: add 5, 4, 5
+; PPC64LE-NEXT: srwi 4, 4, 3
+; PPC64LE-NEXT: srwi 5, 5, 4
+; PPC64LE-NEXT: sub 4, 5, 4
; PPC64LE-NEXT: mulli 4, 4, 6
; PPC64LE-NEXT: sub 3, 3, 4
; PPC64LE-NEXT: li 4, 1
@@ -182,32 +182,32 @@ define <3 x i1> @test_srem_vec(<3 x i33> %X) nounwind {
;
; PPC64LE-LABEL: test_srem_vec:
; PPC64LE: # %bb.0:
-; PPC64LE-NEXT: lis 6, 1820
+; PPC64LE-NEXT: lis 8, 1820
; PPC64LE-NEXT: sldi 3, 3, 31
; PPC64LE-NEXT: sldi 4, 4, 31
; PPC64LE-NEXT: sldi 5, 5, 31
-; PPC64LE-NEXT: ori 6, 6, 29127
-; PPC64LE-NEXT: sradi 3, 3, 31
-; PPC64LE-NEXT: sradi 4, 4, 31
+; PPC64LE-NEXT: ori 8, 8, 29127
+; PPC64LE-NEXT: sradi 7, 3, 31
+; PPC64LE-NEXT: sradi 3, 3, 63
+; PPC64LE-NEXT: sradi 6, 4, 31
+; PPC64LE-NEXT: sradi 4, 4, 63
; PPC64LE-NEXT: sradi 5, 5, 31
-; PPC64LE-NEXT: rldic 6, 6, 34, 3
-; PPC64LE-NEXT: oris 6, 6, 29127
-; PPC64LE-NEXT: ori 7, 6, 7282
-; PPC64LE-NEXT: mulhd 8, 3, 7
-; PPC64LE-NEXT: rldicl 9, 8, 1, 63
-; PPC64LE-NEXT: add 8, 8, 9
-; PPC64LE-NEXT: sldi 9, 8, 3
-; PPC64LE-NEXT: add 8, 8, 9
-; PPC64LE-NEXT: sub 3, 3, 8
+; PPC64LE-NEXT: rldic 8, 8, 34, 3
+; PPC64LE-NEXT: oris 8, 8, 29127
+; PPC64LE-NEXT: ori 9, 8, 7282
+; PPC64LE-NEXT: mulhd 10, 7, 9
+; PPC64LE-NEXT: sub 3, 10, 3
+; PPC64LE-NEXT: sldi 10, 3, 3
+; PPC64LE-NEXT: add 3, 3, 10
+; PPC64LE-NEXT: sub 3, 7, 3
; PPC64LE-NEXT: mtfprd 0, 3
-; PPC64LE-NEXT: mulhd 3, 4, 7
-; PPC64LE-NEXT: rldicl 7, 3, 1, 63
-; PPC64LE-NEXT: add 3, 3, 7
-; PPC64LE-NEXT: sldi 7, 3, 3
-; PPC64LE-NEXT: add 3, 3, 7
-; PPC64LE-NEXT: sub 3, 4, 3
+; PPC64LE-NEXT: mulhd 3, 6, 9
+; PPC64LE-NEXT: sub 3, 3, 4
+; PPC64LE-NEXT: sldi 4, 3, 3
+; PPC64LE-NEXT: add 3, 3, 4
+; PPC64LE-NEXT: sub 3, 6, 3
; PPC64LE-NEXT: mtfprd 1, 3
-; PPC64LE-NEXT: ori 3, 6, 7281
+; PPC64LE-NEXT: ori 3, 8, 7281
; PPC64LE-NEXT: mulhd 3, 5, 3
; PPC64LE-NEXT: sub 3, 3, 5
; PPC64LE-NEXT: rldicl 4, 3, 1, 63
@@ -230,16 +230,16 @@ define <3 x i1> @test_srem_vec(<3 x i33> %X) nounwind {
; PPC64LE-NEXT: addi 3, 3, .LCPI3_0 at toc@l
; PPC64LE-NEXT: xxswapd 37, 0
; PPC64LE-NEXT: lxvd2x 0, 0, 3
-; PPC64LE-NEXT: xxland 34, 34, 0
; PPC64LE-NEXT: xxland 35, 35, 0
-; PPC64LE-NEXT: vcmpequd 2, 2, 4
+; PPC64LE-NEXT: xxland 34, 34, 0
+; PPC64LE-NEXT: vcmpequd 3, 3, 4
+; PPC64LE-NEXT: vcmpequd 2, 2, 5
+; PPC64LE-NEXT: xxlnor 35, 35, 35
; PPC64LE-NEXT: xxlnor 0, 34, 34
-; PPC64LE-NEXT: vcmpequd 2, 3, 5
-; PPC64LE-NEXT: xxlnor 34, 34, 34
; PPC64LE-NEXT: mffprwz 4, 0
; PPC64LE-NEXT: xxswapd 1, 0
+; PPC64LE-NEXT: xxswapd 2, 35
; PPC64LE-NEXT: mffprwz 3, 1
-; PPC64LE-NEXT: xxswapd 2, 34
; PPC64LE-NEXT: mffprwz 5, 2
; PPC64LE-NEXT: blr
%srem = srem <3 x i33> %X, <i33 9, i33 9, i33 -9>
diff --git a/llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll b/llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll
index df55b92997765..a8a7b3cf5ae93 100644
--- a/llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll
+++ b/llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll
@@ -34,19 +34,19 @@ define <4 x i16> @fold_srem_vec_1(<4 x i16> %x) {
; P9LE-NEXT: srwi r5, r4, 31
; P9LE-NEXT: srawi r4, r4, 6
; P9LE-NEXT: add r4, r4, r5
+; P9LE-NEXT: lis r5, 21399
; P9LE-NEXT: mulli r4, r4, -124
+; P9LE-NEXT: ori r5, r5, 33437
; P9LE-NEXT: sub r3, r3, r4
-; P9LE-NEXT: lis r4, 21399
; P9LE-NEXT: mtvsrd v4, r3
; P9LE-NEXT: li r3, 4
-; P9LE-NEXT: ori r4, r4, 33437
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: vmrghh v3, v4, v3
; P9LE-NEXT: extsh r3, r3
-; P9LE-NEXT: mulhw r4, r3, r4
-; P9LE-NEXT: srwi r5, r4, 31
-; P9LE-NEXT: srawi r4, r4, 5
-; P9LE-NEXT: add r4, r4, r5
+; P9LE-NEXT: mulhw r5, r3, r5
+; P9LE-NEXT: srawi r4, r3, 31
+; P9LE-NEXT: srawi r5, r5, 5
+; P9LE-NEXT: sub r4, r5, r4
; P9LE-NEXT: mulli r4, r4, 98
; P9LE-NEXT: sub r3, r3, r4
; P9LE-NEXT: lis r4, -16728
@@ -107,18 +107,18 @@ define <4 x i16> @fold_srem_vec_1(<4 x i16> %x) {
; P9BE-NEXT: srwi r5, r4, 31
; P9BE-NEXT: srawi r4, r4, 8
; P9BE-NEXT: add r4, r4, r5
+; P9BE-NEXT: lis r5, 21399
; P9BE-NEXT: mulli r4, r4, -1003
+; P9BE-NEXT: ori r5, r5, 33437
; P9BE-NEXT: sub r3, r3, r4
-; P9BE-NEXT: lis r4, 21399
; P9BE-NEXT: mtfprwz f1, r3
; P9BE-NEXT: li r3, 4
-; P9BE-NEXT: ori r4, r4, 33437
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: extsh r3, r3
-; P9BE-NEXT: mulhw r4, r3, r4
-; P9BE-NEXT: srwi r5, r4, 31
-; P9BE-NEXT: srawi r4, r4, 5
-; P9BE-NEXT: add r4, r4, r5
+; P9BE-NEXT: mulhw r5, r3, r5
+; P9BE-NEXT: srawi r4, r3, 31
+; P9BE-NEXT: srawi r5, r5, 5
+; P9BE-NEXT: sub r4, r5, r4
; P9BE-NEXT: mulli r4, r4, 98
; P9BE-NEXT: sub r3, r3, r4
; P9BE-NEXT: mtfprwz f3, r3
@@ -129,113 +129,113 @@ define <4 x i16> @fold_srem_vec_1(<4 x i16> %x) {
; P8LE-LABEL: fold_srem_vec_1:
; P8LE: # %bb.0:
; P8LE-NEXT: xxswapd vs0, v2
-; P8LE-NEXT: lis r4, 21399
-; P8LE-NEXT: lis r5, -16728
-; P8LE-NEXT: lis r6, -21386
+; P8LE-NEXT: lis r8, -16728
+; P8LE-NEXT: lis r4, -21386
+; P8LE-NEXT: lis r9, 21399
+; P8LE-NEXT: lis r5, 31710
; P8LE-NEXT: mffprd r3, f0
-; P8LE-NEXT: ori r4, r4, 33437
-; P8LE-NEXT: ori r5, r5, 63249
-; P8LE-NEXT: ori r6, r6, 37253
-; P8LE-NEXT: rldicl r7, r3, 32, 48
-; P8LE-NEXT: rldicl r8, r3, 16, 48
-; P8LE-NEXT: clrldi r9, r3, 48
-; P8LE-NEXT: rldicl r3, r3, 48, 48
-; P8LE-NEXT: extsh r7, r7
-; P8LE-NEXT: extsh r8, r8
-; P8LE-NEXT: extsh r9, r9
+; P8LE-NEXT: ori r8, r8, 63249
+; P8LE-NEXT: ori r4, r4, 37253
+; P8LE-NEXT: ori r9, r9, 33437
+; P8LE-NEXT: ori r5, r5, 63421
+; P8LE-NEXT: rldicl r10, r3, 16, 48
+; P8LE-NEXT: clrldi r6, r3, 48
+; P8LE-NEXT: rldicl r7, r3, 48, 48
+; P8LE-NEXT: rldicl r3, r3, 32, 48
+; P8LE-NEXT: extsh r10, r10
+; P8LE-NEXT: extsh r6, r6
; P8LE-NEXT: extsh r3, r3
-; P8LE-NEXT: mulhw r4, r7, r4
-; P8LE-NEXT: mulhw r5, r8, r5
-; P8LE-NEXT: mulhw r6, r9, r6
-; P8LE-NEXT: srwi r10, r4, 31
-; P8LE-NEXT: srawi r4, r4, 5
-; P8LE-NEXT: add r6, r6, r9
-; P8LE-NEXT: add r4, r4, r10
-; P8LE-NEXT: srwi r10, r5, 31
-; P8LE-NEXT: srawi r5, r5, 8
-; P8LE-NEXT: mulli r4, r4, 98
-; P8LE-NEXT: add r5, r5, r10
-; P8LE-NEXT: srwi r10, r6, 31
-; P8LE-NEXT: srawi r6, r6, 6
-; P8LE-NEXT: add r6, r6, r10
-; P8LE-NEXT: mulli r5, r5, -1003
-; P8LE-NEXT: sub r4, r7, r4
-; P8LE-NEXT: mtvsrd v2, r4
-; P8LE-NEXT: mulli r4, r6, 95
-; P8LE-NEXT: sub r5, r8, r5
-; P8LE-NEXT: mtvsrd v3, r5
-; P8LE-NEXT: sub r4, r9, r4
-; P8LE-NEXT: mtvsrd v4, r4
-; P8LE-NEXT: lis r4, 31710
-; P8LE-NEXT: ori r4, r4, 63421
-; P8LE-NEXT: mulhw r4, r3, r4
-; P8LE-NEXT: sub r4, r4, r3
-; P8LE-NEXT: srwi r5, r4, 31
+; P8LE-NEXT: extsh r7, r7
+; P8LE-NEXT: mulhw r8, r10, r8
+; P8LE-NEXT: mulhw r4, r6, r4
+; P8LE-NEXT: mulhw r9, r3, r9
+; P8LE-NEXT: mulhw r5, r7, r5
+; P8LE-NEXT: srwi r11, r8, 31
+; P8LE-NEXT: srawi r8, r8, 8
+; P8LE-NEXT: add r4, r4, r6
+; P8LE-NEXT: srawi r9, r9, 5
+; P8LE-NEXT: sub r5, r5, r7
+; P8LE-NEXT: add r8, r8, r11
+; P8LE-NEXT: srawi r11, r3, 31
+; P8LE-NEXT: sub r9, r9, r11
+; P8LE-NEXT: srwi r11, r4, 31
; P8LE-NEXT: srawi r4, r4, 6
-; P8LE-NEXT: add r4, r4, r5
-; P8LE-NEXT: mulli r4, r4, -124
+; P8LE-NEXT: mulli r8, r8, -1003
+; P8LE-NEXT: add r4, r4, r11
+; P8LE-NEXT: srwi r11, r5, 31
+; P8LE-NEXT: srawi r5, r5, 6
+; P8LE-NEXT: add r5, r5, r11
+; P8LE-NEXT: mulli r4, r4, 95
+; P8LE-NEXT: sub r8, r10, r8
+; P8LE-NEXT: mulli r5, r5, -124
+; P8LE-NEXT: mtvsrd v2, r8
+; P8LE-NEXT: sub r4, r6, r4
+; P8LE-NEXT: sub r5, r7, r5
+; P8LE-NEXT: mtvsrd v3, r4
+; P8LE-NEXT: mulli r4, r9, 98
+; P8LE-NEXT: mtvsrd v4, r5
; P8LE-NEXT: sub r3, r3, r4
-; P8LE-NEXT: vmrghh v2, v3, v2
-; P8LE-NEXT: mtvsrd v3, r3
-; P8LE-NEXT: vmrghh v3, v3, v4
+; P8LE-NEXT: vmrghh v3, v4, v3
+; P8LE-NEXT: mtvsrd v4, r3
+; P8LE-NEXT: vmrghh v2, v2, v4
; P8LE-NEXT: xxmrglw v2, v2, v3
; P8LE-NEXT: blr
;
; P8BE-LABEL: fold_srem_vec_1:
; P8BE: # %bb.0:
; P8BE-NEXT: mfvsrd r3, v2
-; P8BE-NEXT: addis r6, r2, .LCPI0_0 at toc@ha
-; P8BE-NEXT: lis r4, -16728
-; P8BE-NEXT: lis r5, 21399
-; P8BE-NEXT: lis r7, 31710
-; P8BE-NEXT: addi r6, r6, .LCPI0_0 at toc@l
-; P8BE-NEXT: ori r4, r4, 63249
-; P8BE-NEXT: ori r5, r5, 33437
-; P8BE-NEXT: ori r7, r7, 63421
-; P8BE-NEXT: lxvw4x v2, 0, r6
-; P8BE-NEXT: clrldi r6, r3, 48
-; P8BE-NEXT: rldicl r8, r3, 48, 48
-; P8BE-NEXT: rldicl r9, r3, 32, 48
-; P8BE-NEXT: rldicl r3, r3, 16, 48
+; P8BE-NEXT: lis r8, -16728
+; P8BE-NEXT: lis r4, 31710
+; P8BE-NEXT: lis r9, 21399
+; P8BE-NEXT: lis r5, -21386
+; P8BE-NEXT: ori r8, r8, 63249
+; P8BE-NEXT: ori r4, r4, 63421
+; P8BE-NEXT: ori r9, r9, 33437
+; P8BE-NEXT: ori r5, r5, 37253
+; P8BE-NEXT: clrldi r10, r3, 48
+; P8BE-NEXT: rldicl r6, r3, 32, 48
+; P8BE-NEXT: rldicl r7, r3, 16, 48
+; P8BE-NEXT: rldicl r3, r3, 48, 48
+; P8BE-NEXT: extsh r10, r10
; P8BE-NEXT: extsh r6, r6
-; P8BE-NEXT: extsh r8, r8
-; P8BE-NEXT: extsh r9, r9
; P8BE-NEXT: extsh r3, r3
+; P8BE-NEXT: extsh r7, r7
+; P8BE-NEXT: mulhw r8, r10, r8
; P8BE-NEXT: mulhw r4, r6, r4
-; P8BE-NEXT: mulhw r5, r8, r5
-; P8BE-NEXT: mulhw r7, r9, r7
-; P8BE-NEXT: srwi r10, r4, 31
-; P8BE-NEXT: srawi r4, r4, 8
-; P8BE-NEXT: sub r7, r7, r9
-; P8BE-NEXT: add r4, r4, r10
-; P8BE-NEXT: srwi r10, r5, 31
-; P8BE-NEXT: srawi r5, r5, 5
-; P8BE-NEXT: mulli r4, r4, -1003
-; P8BE-NEXT: add r5, r5, r10
-; P8BE-NEXT: srwi r10, r7, 31
-; P8BE-NEXT: srawi r7, r7, 6
-; P8BE-NEXT: add r7, r7, r10
-; P8BE-NEXT: mulli r5, r5, 98
-; P8BE-NEXT: sub r4, r6, r4
-; P8BE-NEXT: mtvsrwz v3, r4
-; P8BE-NEXT: mulli r4, r7, -124
-; P8BE-NEXT: sub r5, r8, r5
-; P8BE-NEXT: mtvsrwz v4, r5
-; P8BE-NEXT: sub r4, r9, r4
-; P8BE-NEXT: mtvsrwz v5, r4
-; P8BE-NEXT: lis r4, -21386
-; P8BE-NEXT: ori r4, r4, 37253
-; P8BE-NEXT: mulhw r4, r3, r4
-; P8BE-NEXT: add r4, r4, r3
-; P8BE-NEXT: srwi r5, r4, 31
+; P8BE-NEXT: mulhw r9, r3, r9
+; P8BE-NEXT: mulhw r5, r7, r5
+; P8BE-NEXT: srwi r11, r8, 31
+; P8BE-NEXT: srawi r8, r8, 8
+; P8BE-NEXT: sub r4, r4, r6
+; P8BE-NEXT: srawi r9, r9, 5
+; P8BE-NEXT: add r5, r5, r7
+; P8BE-NEXT: add r8, r8, r11
+; P8BE-NEXT: srawi r11, r3, 31
+; P8BE-NEXT: sub r9, r9, r11
+; P8BE-NEXT: srwi r11, r4, 31
; P8BE-NEXT: srawi r4, r4, 6
-; P8BE-NEXT: add r4, r4, r5
-; P8BE-NEXT: mulli r4, r4, 95
+; P8BE-NEXT: mulli r8, r8, -1003
+; P8BE-NEXT: add r4, r4, r11
+; P8BE-NEXT: srwi r11, r5, 31
+; P8BE-NEXT: srawi r5, r5, 6
+; P8BE-NEXT: add r5, r5, r11
+; P8BE-NEXT: mulli r4, r4, -124
+; P8BE-NEXT: addis r11, r2, .LCPI0_0 at toc@ha
+; P8BE-NEXT: sub r8, r10, r8
+; P8BE-NEXT: mulli r5, r5, 95
+; P8BE-NEXT: addi r11, r11, .LCPI0_0 at toc@l
+; P8BE-NEXT: mtvsrwz v3, r8
+; P8BE-NEXT: lxvw4x v2, 0, r11
+; P8BE-NEXT: sub r4, r6, r4
+; P8BE-NEXT: sub r5, r7, r5
+; P8BE-NEXT: mtvsrwz v4, r4
+; P8BE-NEXT: mulli r4, r9, 98
+; P8BE-NEXT: mtvsrwz v5, r5
; P8BE-NEXT: sub r3, r3, r4
-; P8BE-NEXT: vperm v3, v4, v3, v2
-; P8BE-NEXT: mtvsrwz v4, r3
-; P8BE-NEXT: vperm v2, v4, v5, v2
-; P8BE-NEXT: xxmrghw v2, v2, v3
+; P8BE-NEXT: vperm v4, v5, v4, v2
+; P8BE-NEXT: mtvsrwz v5, r3
+; P8BE-NEXT: vperm v2, v5, v3, v2
+; P8BE-NEXT: xxmrghw v2, v4, v2
; P8BE-NEXT: blr
%1 = srem <4 x i16> %x, <i16 95, i16 -124, i16 98, i16 -1003>
ret <4 x i16> %1
@@ -923,18 +923,18 @@ define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) {
; P9LE-NEXT: srwi r5, r4, 31
; P9LE-NEXT: srawi r4, r4, 4
; P9LE-NEXT: add r4, r4, r5
+; P9LE-NEXT: lis r5, 24749
; P9LE-NEXT: mulli r4, r4, 23
+; P9LE-NEXT: ori r5, r5, 47143
; P9LE-NEXT: sub r3, r3, r4
-; P9LE-NEXT: lis r4, 24749
; P9LE-NEXT: mtvsrd v4, r3
; P9LE-NEXT: li r3, 6
-; P9LE-NEXT: ori r4, r4, 47143
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r3, r3
-; P9LE-NEXT: mulhw r4, r3, r4
-; P9LE-NEXT: srwi r5, r4, 31
-; P9LE-NEXT: srawi r4, r4, 11
-; P9LE-NEXT: add r4, r4, r5
+; P9LE-NEXT: mulhw r5, r3, r5
+; P9LE-NEXT: srawi r4, r3, 31
+; P9LE-NEXT: srawi r5, r5, 11
+; P9LE-NEXT: sub r4, r5, r4
; P9LE-NEXT: mulli r4, r4, 5423
; P9LE-NEXT: sub r3, r3, r4
; P9LE-NEXT: mtvsrd v2, r3
@@ -954,18 +954,18 @@ define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) {
; P9BE-NEXT: srwi r5, r4, 31
; P9BE-NEXT: srawi r4, r4, 4
; P9BE-NEXT: add r4, r4, r5
+; P9BE-NEXT: lis r5, 24749
; P9BE-NEXT: mulli r4, r4, 23
+; P9BE-NEXT: ori r5, r5, 47143
; P9BE-NEXT: sub r3, r3, r4
-; P9BE-NEXT: lis r4, 24749
; P9BE-NEXT: mtfprwz f0, r3
; P9BE-NEXT: li r3, 6
-; P9BE-NEXT: ori r4, r4, 47143
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: extsh r3, r3
-; P9BE-NEXT: mulhw r4, r3, r4
-; P9BE-NEXT: srwi r5, r4, 31
-; P9BE-NEXT: srawi r4, r4, 11
-; P9BE-NEXT: add r4, r4, r5
+; P9BE-NEXT: mulhw r5, r3, r5
+; P9BE-NEXT: srawi r4, r3, 31
+; P9BE-NEXT: srawi r5, r5, 11
+; P9BE-NEXT: sub r4, r5, r4
; P9BE-NEXT: mulli r4, r4, 5423
; P9BE-NEXT: sub r3, r3, r4
; P9BE-NEXT: lis r4, -14230
@@ -995,47 +995,47 @@ define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) {
; P8LE-LABEL: dont_fold_srem_one:
; P8LE: # %bb.0:
; P8LE-NEXT: xxswapd vs0, v2
+; P8LE-NEXT: lis r4, -14230
; P8LE-NEXT: lis r8, 24749
-; P8LE-NEXT: lis r4, -19946
-; P8LE-NEXT: lis r5, -14230
+; P8LE-NEXT: lis r5, -19946
; P8LE-NEXT: mffprd r3, f0
+; P8LE-NEXT: ori r4, r4, 30865
; P8LE-NEXT: ori r8, r8, 47143
-; P8LE-NEXT: ori r4, r4, 17097
-; P8LE-NEXT: ori r5, r5, 30865
-; P8LE-NEXT: rldicl r6, r3, 32, 48
-; P8LE-NEXT: rldicl r7, r3, 48, 48
+; P8LE-NEXT: ori r5, r5, 17097
+; P8LE-NEXT: rldicl r6, r3, 48, 48
+; P8LE-NEXT: rldicl r7, r3, 32, 48
; P8LE-NEXT: rldicl r3, r3, 16, 48
-; P8LE-NEXT: extsh r3, r3
; P8LE-NEXT: extsh r6, r6
+; P8LE-NEXT: extsh r3, r3
; P8LE-NEXT: extsh r7, r7
-; P8LE-NEXT: mulhw r8, r3, r8
; P8LE-NEXT: mulhw r4, r6, r4
+; P8LE-NEXT: mulhw r8, r3, r8
+; P8LE-NEXT: srawi r9, r3, 31
; P8LE-NEXT: mulhw r5, r7, r5
-; P8LE-NEXT: srwi r9, r8, 31
-; P8LE-NEXT: srawi r8, r8, 11
; P8LE-NEXT: add r4, r4, r6
+; P8LE-NEXT: srawi r8, r8, 11
; P8LE-NEXT: add r5, r5, r7
-; P8LE-NEXT: add r8, r8, r9
+; P8LE-NEXT: sub r8, r8, r9
; P8LE-NEXT: srwi r9, r4, 31
-; P8LE-NEXT: srawi r4, r4, 4
-; P8LE-NEXT: mulli r8, r8, 5423
+; P8LE-NEXT: srawi r4, r4, 9
; P8LE-NEXT: add r4, r4, r9
; P8LE-NEXT: srwi r9, r5, 31
-; P8LE-NEXT: srawi r5, r5, 9
+; P8LE-NEXT: srawi r5, r5, 4
+; P8LE-NEXT: mulli r4, r4, 654
; P8LE-NEXT: add r5, r5, r9
-; P8LE-NEXT: sub r3, r3, r8
-; P8LE-NEXT: mtvsrd v2, r3
-; P8LE-NEXT: mulli r3, r4, 23
-; P8LE-NEXT: mulli r4, r5, 654
-; P8LE-NEXT: sub r3, r6, r3
-; P8LE-NEXT: sub r4, r7, r4
-; P8LE-NEXT: mtvsrd v3, r3
-; P8LE-NEXT: li r3, 0
-; P8LE-NEXT: mtvsrd v4, r3
-; P8LE-NEXT: vmrghh v2, v2, v3
+; P8LE-NEXT: li r9, 0
+; P8LE-NEXT: mulli r5, r5, 23
+; P8LE-NEXT: mtvsrd v2, r9
+; P8LE-NEXT: sub r4, r6, r4
; P8LE-NEXT: mtvsrd v3, r4
+; P8LE-NEXT: mulli r4, r8, 5423
+; P8LE-NEXT: sub r5, r7, r5
+; P8LE-NEXT: mtvsrd v4, r5
+; P8LE-NEXT: sub r3, r3, r4
+; P8LE-NEXT: vmrghh v2, v3, v2
+; P8LE-NEXT: mtvsrd v3, r3
; P8LE-NEXT: vmrghh v3, v3, v4
-; P8LE-NEXT: xxmrglw v2, v2, v3
+; P8LE-NEXT: xxmrglw v2, v3, v2
; P8LE-NEXT: blr
;
; P8BE-LABEL: dont_fold_srem_one:
@@ -1056,11 +1056,11 @@ define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) {
; P8BE-NEXT: mulhw r4, r6, r4
; P8BE-NEXT: mulhw r8, r3, r8
; P8BE-NEXT: mulhw r5, r7, r5
+; P8BE-NEXT: srawi r9, r3, 31
; P8BE-NEXT: add r4, r4, r6
-; P8BE-NEXT: srwi r9, r8, 31
; P8BE-NEXT: srawi r8, r8, 11
; P8BE-NEXT: add r5, r5, r7
-; P8BE-NEXT: add r8, r8, r9
+; P8BE-NEXT: sub r8, r8, r9
; P8BE-NEXT: srwi r9, r4, 31
; P8BE-NEXT: srawi r4, r4, 4
; P8BE-NEXT: add r4, r4, r9
@@ -1103,18 +1103,18 @@ define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) {
; P9LE-NEXT: srwi r5, r4, 31
; P9LE-NEXT: srawi r4, r4, 4
; P9LE-NEXT: add r4, r4, r5
+; P9LE-NEXT: lis r5, 24749
; P9LE-NEXT: mulli r4, r4, 23
+; P9LE-NEXT: ori r5, r5, 47143
; P9LE-NEXT: sub r3, r3, r4
-; P9LE-NEXT: lis r4, 24749
; P9LE-NEXT: mtvsrd v3, r3
; P9LE-NEXT: li r3, 6
-; P9LE-NEXT: ori r4, r4, 47143
; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r3, r3
-; P9LE-NEXT: mulhw r4, r3, r4
-; P9LE-NEXT: srwi r5, r4, 31
-; P9LE-NEXT: srawi r4, r4, 11
-; P9LE-NEXT: add r4, r4, r5
+; P9LE-NEXT: mulhw r5, r3, r5
+; P9LE-NEXT: srawi r4, r3, 31
+; P9LE-NEXT: srawi r5, r5, 11
+; P9LE-NEXT: sub r4, r5, r4
; P9LE-NEXT: mulli r4, r4, 5423
; P9LE-NEXT: sub r3, r3, r4
; P9LE-NEXT: mtvsrd v4, r3
@@ -1145,18 +1145,18 @@ define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) {
; P9BE-NEXT: srwi r5, r4, 31
; P9BE-NEXT: srawi r4, r4, 4
; P9BE-NEXT: add r4, r4, r5
+; P9BE-NEXT: lis r5, 24749
; P9BE-NEXT: mulli r4, r4, 23
+; P9BE-NEXT: ori r5, r5, 47143
; P9BE-NEXT: sub r3, r3, r4
-; P9BE-NEXT: lis r4, 24749
; P9BE-NEXT: mtfprwz f0, r3
; P9BE-NEXT: li r3, 6
-; P9BE-NEXT: ori r4, r4, 47143
; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: extsh r3, r3
-; P9BE-NEXT: mulhw r4, r3, r4
-; P9BE-NEXT: srwi r5, r4, 31
-; P9BE-NEXT: srawi r4, r4, 11
-; P9BE-NEXT: add r4, r4, r5
+; P9BE-NEXT: mulhw r5, r3, r5
+; P9BE-NEXT: srawi r4, r3, 31
+; P9BE-NEXT: srawi r5, r5, 11
+; P9BE-NEXT: sub r4, r5, r4
; P9BE-NEXT: mulli r4, r4, 5423
; P9BE-NEXT: sub r3, r3, r4
; P9BE-NEXT: mtfprwz f1, r3
@@ -1181,41 +1181,41 @@ define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) {
; P8LE-LABEL: dont_fold_urem_i16_smax:
; P8LE: # %bb.0:
; P8LE-NEXT: xxswapd vs0, v2
-; P8LE-NEXT: lis r4, -19946
-; P8LE-NEXT: lis r6, 24749
-; P8LE-NEXT: li r8, 0
+; P8LE-NEXT: li r3, 0
+; P8LE-NEXT: mtvsrd v2, r3
; P8LE-NEXT: mffprd r3, f0
-; P8LE-NEXT: ori r4, r4, 17097
-; P8LE-NEXT: ori r6, r6, 47143
-; P8LE-NEXT: mtvsrd v2, r8
-; P8LE-NEXT: rldicl r5, r3, 32, 48
-; P8LE-NEXT: rldicl r7, r3, 16, 48
-; P8LE-NEXT: rldicl r3, r3, 48, 48
-; P8LE-NEXT: extsh r5, r5
-; P8LE-NEXT: extsh r7, r7
-; P8LE-NEXT: extsh r3, r3
-; P8LE-NEXT: mulhw r4, r5, r4
-; P8LE-NEXT: mulhw r6, r7, r6
-; P8LE-NEXT: add r4, r4, r5
-; P8LE-NEXT: srwi r8, r6, 31
-; P8LE-NEXT: srawi r6, r6, 11
-; P8LE-NEXT: add r6, r6, r8
-; P8LE-NEXT: srwi r8, r4, 31
-; P8LE-NEXT: srawi r4, r4, 4
-; P8LE-NEXT: add r4, r4, r8
-; P8LE-NEXT: mulli r6, r6, 5423
-; P8LE-NEXT: mulli r4, r4, 23
-; P8LE-NEXT: sub r6, r7, r6
-; P8LE-NEXT: sub r4, r5, r4
-; P8LE-NEXT: srawi r5, r3, 15
-; P8LE-NEXT: mtvsrd v3, r6
+; P8LE-NEXT: rldicl r4, r3, 48, 48
+; P8LE-NEXT: extsh r4, r4
+; P8LE-NEXT: srawi r5, r4, 15
; P8LE-NEXT: addze r5, r5
-; P8LE-NEXT: mtvsrd v4, r4
-; P8LE-NEXT: slwi r4, r5, 15
+; P8LE-NEXT: slwi r5, r5, 15
+; P8LE-NEXT: sub r4, r4, r5
+; P8LE-NEXT: lis r5, -19946
+; P8LE-NEXT: mtvsrd v3, r4
+; P8LE-NEXT: rldicl r4, r3, 32, 48
+; P8LE-NEXT: ori r5, r5, 17097
+; P8LE-NEXT: rldicl r3, r3, 16, 48
+; P8LE-NEXT: extsh r4, r4
+; P8LE-NEXT: extsh r3, r3
+; P8LE-NEXT: mulhw r5, r4, r5
+; P8LE-NEXT: add r5, r5, r4
+; P8LE-NEXT: srwi r6, r5, 31
+; P8LE-NEXT: srawi r5, r5, 4
+; P8LE-NEXT: add r5, r5, r6
+; P8LE-NEXT: mulli r5, r5, 23
+; P8LE-NEXT: sub r4, r4, r5
+; P8LE-NEXT: srawi r5, r3, 31
+; P8LE-NEXT: vmrghh v2, v3, v2
+; P8LE-NEXT: mtvsrd v3, r4
+; P8LE-NEXT: lis r4, 24749
+; P8LE-NEXT: ori r4, r4, 47143
+; P8LE-NEXT: mulhw r4, r3, r4
+; P8LE-NEXT: srawi r4, r4, 11
+; P8LE-NEXT: sub r4, r4, r5
+; P8LE-NEXT: mulli r4, r4, 5423
; P8LE-NEXT: sub r3, r3, r4
-; P8LE-NEXT: vmrghh v3, v3, v4
; P8LE-NEXT: mtvsrd v4, r3
-; P8LE-NEXT: vmrghh v2, v4, v2
+; P8LE-NEXT: vmrghh v3, v4, v3
; P8LE-NEXT: xxmrglw v2, v3, v2
; P8LE-NEXT: blr
;
@@ -1234,10 +1234,10 @@ define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) {
; P8BE-NEXT: extsh r3, r3
; P8BE-NEXT: mulhw r4, r5, r4
; P8BE-NEXT: mulhw r6, r7, r6
+; P8BE-NEXT: srawi r8, r7, 31
; P8BE-NEXT: add r4, r4, r5
-; P8BE-NEXT: srwi r8, r6, 31
; P8BE-NEXT: srawi r6, r6, 11
-; P8BE-NEXT: add r6, r6, r8
+; P8BE-NEXT: sub r6, r6, r8
; P8BE-NEXT: srwi r8, r4, 31
; P8BE-NEXT: srawi r4, r4, 4
; P8BE-NEXT: add r4, r4, r8
@@ -1269,42 +1269,42 @@ define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) {
define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) {
; P9LE-LABEL: dont_fold_srem_i64:
; P9LE: # %bb.0:
-; P9LE-NEXT: lis r4, 12374
-; P9LE-NEXT: mfvsrd r3, v3
-; P9LE-NEXT: ori r4, r4, 56339
-; P9LE-NEXT: rldic r4, r4, 33, 1
-; P9LE-NEXT: oris r4, r4, 58853
-; P9LE-NEXT: ori r4, r4, 6055
+; P9LE-NEXT: lis r4, 5698
+; P9LE-NEXT: mfvsrld r3, v3
+; P9LE-NEXT: ori r4, r4, 51289
+; P9LE-NEXT: rldic r4, r4, 35, 0
+; P9LE-NEXT: oris r4, r4, 22795
+; P9LE-NEXT: ori r4, r4, 8549
; P9LE-NEXT: mulhd r4, r3, r4
+; P9LE-NEXT: add r4, r4, r3
; P9LE-NEXT: rldicl r5, r4, 1, 63
-; P9LE-NEXT: sradi r4, r4, 11
+; P9LE-NEXT: sradi r4, r4, 4
; P9LE-NEXT: add r4, r4, r5
-; P9LE-NEXT: lis r5, 5698
-; P9LE-NEXT: mulli r4, r4, 5423
-; P9LE-NEXT: ori r5, r5, 51289
-; P9LE-NEXT: rldic r5, r5, 35, 0
-; P9LE-NEXT: oris r5, r5, 22795
+; P9LE-NEXT: lis r5, 12374
+; P9LE-NEXT: ori r5, r5, 56339
+; P9LE-NEXT: mulli r4, r4, 23
+; P9LE-NEXT: rldic r5, r5, 33, 1
+; P9LE-NEXT: oris r5, r5, 58853
; P9LE-NEXT: sub r3, r3, r4
-; P9LE-NEXT: mfvsrld r4, v3
-; P9LE-NEXT: ori r5, r5, 8549
+; P9LE-NEXT: mfvsrd r4, v3
+; P9LE-NEXT: ori r5, r5, 6055
+; P9LE-NEXT: sradi r6, r4, 63
; P9LE-NEXT: mulhd r5, r4, r5
-; P9LE-NEXT: add r5, r5, r4
-; P9LE-NEXT: rldicl r6, r5, 1, 63
-; P9LE-NEXT: sradi r5, r5, 4
-; P9LE-NEXT: add r5, r5, r6
-; P9LE-NEXT: mulli r5, r5, 23
+; P9LE-NEXT: sradi r5, r5, 11
+; P9LE-NEXT: sub r5, r5, r6
+; P9LE-NEXT: mulli r5, r5, 5423
; P9LE-NEXT: sub r4, r4, r5
-; P9LE-NEXT: mtvsrdd v3, r3, r4
+; P9LE-NEXT: mtvsrdd v3, r4, r3
; P9LE-NEXT: lis r4, 3206
; P9LE-NEXT: mfvsrd r3, v2
; P9LE-NEXT: ori r4, r4, 42889
+; P9LE-NEXT: sradi r5, r3, 63
; P9LE-NEXT: rldic r4, r4, 35, 1
; P9LE-NEXT: oris r4, r4, 1603
; P9LE-NEXT: ori r4, r4, 21445
; P9LE-NEXT: mulhd r4, r3, r4
-; P9LE-NEXT: rldicl r5, r4, 1, 63
; P9LE-NEXT: sradi r4, r4, 8
-; P9LE-NEXT: add r4, r4, r5
+; P9LE-NEXT: sub r4, r4, r5
; P9LE-NEXT: mulli r4, r4, 654
; P9LE-NEXT: sub r3, r3, r4
; P9LE-NEXT: li r4, 0
@@ -1313,42 +1313,42 @@ define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) {
;
; P9BE-LABEL: dont_fold_srem_i64:
; P9BE: # %bb.0:
-; P9BE-NEXT: lis r4, 12374
-; P9BE-NEXT: mfvsrld r3, v3
-; P9BE-NEXT: ori r4, r4, 56339
-; P9BE-NEXT: rldic r4, r4, 33, 1
-; P9BE-NEXT: oris r4, r4, 58853
-; P9BE-NEXT: ori r4, r4, 6055
+; P9BE-NEXT: lis r4, 5698
+; P9BE-NEXT: mfvsrd r3, v3
+; P9BE-NEXT: ori r4, r4, 51289
+; P9BE-NEXT: rldic r4, r4, 35, 0
+; P9BE-NEXT: oris r4, r4, 22795
+; P9BE-NEXT: ori r4, r4, 8549
; P9BE-NEXT: mulhd r4, r3, r4
+; P9BE-NEXT: add r4, r4, r3
; P9BE-NEXT: rldicl r5, r4, 1, 63
-; P9BE-NEXT: sradi r4, r4, 11
+; P9BE-NEXT: sradi r4, r4, 4
; P9BE-NEXT: add r4, r4, r5
-; P9BE-NEXT: lis r5, 5698
-; P9BE-NEXT: ori r5, r5, 51289
-; P9BE-NEXT: mulli r4, r4, 5423
-; P9BE-NEXT: rldic r5, r5, 35, 0
-; P9BE-NEXT: oris r5, r5, 22795
+; P9BE-NEXT: lis r5, 12374
+; P9BE-NEXT: mulli r4, r4, 23
+; P9BE-NEXT: ori r5, r5, 56339
+; P9BE-NEXT: rldic r5, r5, 33, 1
+; P9BE-NEXT: oris r5, r5, 58853
; P9BE-NEXT: sub r3, r3, r4
-; P9BE-NEXT: mfvsrd r4, v3
-; P9BE-NEXT: ori r5, r5, 8549
+; P9BE-NEXT: mfvsrld r4, v3
+; P9BE-NEXT: ori r5, r5, 6055
; P9BE-NEXT: mulhd r5, r4, r5
-; P9BE-NEXT: add r5, r5, r4
-; P9BE-NEXT: rldicl r6, r5, 1, 63
-; P9BE-NEXT: sradi r5, r5, 4
-; P9BE-NEXT: add r5, r5, r6
-; P9BE-NEXT: mulli r5, r5, 23
+; P9BE-NEXT: sradi r6, r4, 63
+; P9BE-NEXT: sradi r5, r5, 11
+; P9BE-NEXT: sub r5, r5, r6
+; P9BE-NEXT: mulli r5, r5, 5423
; P9BE-NEXT: sub r4, r4, r5
-; P9BE-NEXT: mtvsrdd v3, r4, r3
+; P9BE-NEXT: mtvsrdd v3, r3, r4
; P9BE-NEXT: lis r4, 3206
; P9BE-NEXT: mfvsrld r3, v2
; P9BE-NEXT: ori r4, r4, 42889
+; P9BE-NEXT: sradi r5, r3, 63
; P9BE-NEXT: rldic r4, r4, 35, 1
; P9BE-NEXT: oris r4, r4, 1603
; P9BE-NEXT: ori r4, r4, 21445
; P9BE-NEXT: mulhd r4, r3, r4
-; P9BE-NEXT: rldicl r5, r4, 1, 63
; P9BE-NEXT: sradi r4, r4, 8
-; P9BE-NEXT: add r4, r4, r5
+; P9BE-NEXT: sub r4, r4, r5
; P9BE-NEXT: mulli r4, r4, 654
; P9BE-NEXT: sub r3, r3, r4
; P9BE-NEXT: mtvsrdd v2, 0, r3
@@ -1369,6 +1369,7 @@ define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) {
; P8LE-NEXT: rldic r4, r4, 33, 1
; P8LE-NEXT: rldic r3, r3, 35, 0
; P8LE-NEXT: rldic r5, r5, 35, 1
+; P8LE-NEXT: sradi r9, r7, 63
; P8LE-NEXT: oris r4, r4, 58853
; P8LE-NEXT: oris r3, r3, 22795
; P8LE-NEXT: oris r5, r5, 1603
@@ -1378,13 +1379,12 @@ define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) {
; P8LE-NEXT: mulhd r4, r7, r4
; P8LE-NEXT: mulhd r3, r6, r3
; P8LE-NEXT: mulhd r5, r8, r5
-; P8LE-NEXT: rldicl r9, r4, 1, 63
; P8LE-NEXT: sradi r4, r4, 11
; P8LE-NEXT: add r3, r3, r6
-; P8LE-NEXT: add r4, r4, r9
-; P8LE-NEXT: rldicl r9, r5, 1, 63
; P8LE-NEXT: sradi r5, r5, 8
-; P8LE-NEXT: add r5, r5, r9
+; P8LE-NEXT: sub r4, r4, r9
+; P8LE-NEXT: sradi r9, r8, 63
+; P8LE-NEXT: sub r5, r5, r9
; P8LE-NEXT: rldicl r9, r3, 1, 63
; P8LE-NEXT: sradi r3, r3, 4
; P8LE-NEXT: mulli r4, r4, 5423
@@ -1422,19 +1422,19 @@ define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) {
; P8BE-NEXT: oris r4, r4, 58853
; P8BE-NEXT: oris r3, r3, 22795
; P8BE-NEXT: oris r5, r5, 1603
+; P8BE-NEXT: sradi r9, r7, 63
; P8BE-NEXT: ori r4, r4, 6055
; P8BE-NEXT: ori r3, r3, 8549
; P8BE-NEXT: ori r5, r5, 21445
; P8BE-NEXT: mulhd r4, r7, r4
; P8BE-NEXT: mulhd r3, r6, r3
; P8BE-NEXT: mulhd r5, r8, r5
-; P8BE-NEXT: rldicl r9, r4, 1, 63
; P8BE-NEXT: sradi r4, r4, 11
; P8BE-NEXT: add r3, r3, r6
-; P8BE-NEXT: add r4, r4, r9
-; P8BE-NEXT: rldicl r9, r5, 1, 63
; P8BE-NEXT: sradi r5, r5, 8
-; P8BE-NEXT: add r5, r5, r9
+; P8BE-NEXT: sub r4, r4, r9
+; P8BE-NEXT: sradi r9, r8, 63
+; P8BE-NEXT: sub r5, r5, r9
; P8BE-NEXT: rldicl r9, r3, 1, 63
; P8BE-NEXT: sradi r3, r3, 4
; P8BE-NEXT: mulli r4, r4, 5423
diff --git a/llvm/test/CodeGen/RISCV/div-by-constant.ll b/llvm/test/CodeGen/RISCV/div-by-constant.ll
index 1aa0cd053f3ed..81072baf8c026 100644
--- a/llvm/test/CodeGen/RISCV/div-by-constant.ll
+++ b/llvm/test/CodeGen/RISCV/div-by-constant.ll
@@ -331,20 +331,20 @@ define i32 @sdiv_constant_no_srai(i32 %a) nounwind {
; RV32: # %bb.0:
; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1366
-; RV32-NEXT: mulh a0, a0, a1
-; RV32-NEXT: srli a1, a0, 31
-; RV32-NEXT: add a0, a0, a1
+; RV32-NEXT: mulh a1, a0, a1
+; RV32-NEXT: srai a0, a0, 31
+; RV32-NEXT: sub a0, a1, a0
; RV32-NEXT: ret
;
; RV64-LABEL: sdiv_constant_no_srai:
; RV64: # %bb.0:
-; RV64-NEXT: sext.w a0, a0
-; RV64-NEXT: lui a1, 349525
-; RV64-NEXT: addi a1, a1, 1366
-; RV64-NEXT: mul a0, a0, a1
-; RV64-NEXT: srli a1, a0, 63
-; RV64-NEXT: srli a0, a0, 32
-; RV64-NEXT: addw a0, a0, a1
+; RV64-NEXT: sext.w a1, a0
+; RV64-NEXT: lui a2, 349525
+; RV64-NEXT: addi a2, a2, 1366
+; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: srli a1, a1, 32
+; RV64-NEXT: sraiw a0, a0, 31
+; RV64-NEXT: subw a0, a1, a0
; RV64-NEXT: ret
%1 = sdiv i32 %a, 3
ret i32 %1
@@ -356,21 +356,21 @@ define i32 @sdiv_constant_srai(i32 %a) nounwind {
; RV32: # %bb.0:
; RV32-NEXT: lui a1, 419430
; RV32-NEXT: addi a1, a1, 1639
-; RV32-NEXT: mulh a0, a0, a1
-; RV32-NEXT: srli a1, a0, 31
-; RV32-NEXT: srai a0, a0, 1
-; RV32-NEXT: add a0, a0, a1
+; RV32-NEXT: mulh a1, a0, a1
+; RV32-NEXT: srai a1, a1, 1
+; RV32-NEXT: srai a0, a0, 31
+; RV32-NEXT: sub a0, a1, a0
; RV32-NEXT: ret
;
; RV64-LABEL: sdiv_constant_srai:
; RV64: # %bb.0:
-; RV64-NEXT: sext.w a0, a0
-; RV64-NEXT: lui a1, 419430
-; RV64-NEXT: addi a1, a1, 1639
-; RV64-NEXT: mul a0, a0, a1
-; RV64-NEXT: srli a1, a0, 63
-; RV64-NEXT: srai a0, a0, 33
-; RV64-NEXT: add a0, a0, a1
+; RV64-NEXT: sext.w a1, a0
+; RV64-NEXT: lui a2, 419430
+; RV64-NEXT: addi a2, a2, 1639
+; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: srai a1, a1, 33
+; RV64-NEXT: sraiw a0, a0, 31
+; RV64-NEXT: sub a0, a1, a0
; RV64-NEXT: ret
%1 = sdiv i32 %a, 5
ret i32 %1
@@ -450,9 +450,9 @@ define i64 @sdiv64_constant_no_srai(i64 %a) nounwind {
; RV64: # %bb.0:
; RV64-NEXT: lui a1, %hi(.LCPI12_0)
; RV64-NEXT: ld a1, %lo(.LCPI12_0)(a1)
-; RV64-NEXT: mulh a0, a0, a1
-; RV64-NEXT: srli a1, a0, 63
-; RV64-NEXT: add a0, a0, a1
+; RV64-NEXT: mulh a1, a0, a1
+; RV64-NEXT: srai a0, a0, 63
+; RV64-NEXT: sub a0, a1, a0
; RV64-NEXT: ret
%1 = sdiv i64 %a, 3
ret i64 %1
@@ -474,10 +474,10 @@ define i64 @sdiv64_constant_srai(i64 %a) nounwind {
; RV64: # %bb.0:
; RV64-NEXT: lui a1, %hi(.LCPI13_0)
; RV64-NEXT: ld a1, %lo(.LCPI13_0)(a1)
-; RV64-NEXT: mulh a0, a0, a1
-; RV64-NEXT: srli a1, a0, 63
-; RV64-NEXT: srai a0, a0, 1
-; RV64-NEXT: add a0, a0, a1
+; RV64-NEXT: mulh a1, a0, a1
+; RV64-NEXT: srai a1, a1, 1
+; RV64-NEXT: srai a0, a0, 63
+; RV64-NEXT: sub a0, a1, a0
; RV64-NEXT: ret
%1 = sdiv i64 %a, 5
ret i64 %1
@@ -544,42 +544,42 @@ define i8 @sdiv8_constant_no_srai(i8 %a) nounwind {
; RV32IM: # %bb.0:
; RV32IM-NEXT: slli a0, a0, 24
; RV32IM-NEXT: li a1, 86
-; RV32IM-NEXT: srai a0, a0, 24
-; RV32IM-NEXT: mul a0, a0, a1
-; RV32IM-NEXT: srli a1, a0, 31
-; RV32IM-NEXT: srli a0, a0, 8
-; RV32IM-NEXT: add a0, a0, a1
+; RV32IM-NEXT: srai a2, a0, 24
+; RV32IM-NEXT: mul a1, a2, a1
+; RV32IM-NEXT: srli a1, a1, 8
+; RV32IM-NEXT: srai a0, a0, 31
+; RV32IM-NEXT: sub a0, a1, a0
; RV32IM-NEXT: ret
;
; RV32IMZB-LABEL: sdiv8_constant_no_srai:
; RV32IMZB: # %bb.0:
; RV32IMZB-NEXT: sext.b a0, a0
; RV32IMZB-NEXT: li a1, 86
-; RV32IMZB-NEXT: mul a0, a0, a1
-; RV32IMZB-NEXT: srli a1, a0, 31
-; RV32IMZB-NEXT: srli a0, a0, 8
-; RV32IMZB-NEXT: add a0, a0, a1
+; RV32IMZB-NEXT: mul a1, a0, a1
+; RV32IMZB-NEXT: srli a1, a1, 8
+; RV32IMZB-NEXT: srai a0, a0, 7
+; RV32IMZB-NEXT: sub a0, a1, a0
; RV32IMZB-NEXT: ret
;
; RV64IM-LABEL: sdiv8_constant_no_srai:
; RV64IM: # %bb.0:
; RV64IM-NEXT: slli a0, a0, 56
; RV64IM-NEXT: li a1, 86
-; RV64IM-NEXT: srai a0, a0, 56
-; RV64IM-NEXT: mul a0, a0, a1
-; RV64IM-NEXT: srli a1, a0, 63
-; RV64IM-NEXT: srli a0, a0, 8
-; RV64IM-NEXT: add a0, a0, a1
+; RV64IM-NEXT: srai a2, a0, 56
+; RV64IM-NEXT: mul a1, a2, a1
+; RV64IM-NEXT: srli a1, a1, 8
+; RV64IM-NEXT: srai a0, a0, 63
+; RV64IM-NEXT: sub a0, a1, a0
; RV64IM-NEXT: ret
;
; RV64IMZB-LABEL: sdiv8_constant_no_srai:
; RV64IMZB: # %bb.0:
; RV64IMZB-NEXT: sext.b a0, a0
; RV64IMZB-NEXT: li a1, 86
-; RV64IMZB-NEXT: mul a0, a0, a1
-; RV64IMZB-NEXT: srli a1, a0, 63
-; RV64IMZB-NEXT: srli a0, a0, 8
-; RV64IMZB-NEXT: add a0, a0, a1
+; RV64IMZB-NEXT: mul a1, a0, a1
+; RV64IMZB-NEXT: srli a1, a1, 8
+; RV64IMZB-NEXT: srai a0, a0, 7
+; RV64IMZB-NEXT: sub a0, a1, a0
; RV64IMZB-NEXT: ret
%1 = sdiv i8 %a, 3
ret i8 %1
@@ -590,42 +590,42 @@ define i8 @sdiv8_constant_srai(i8 %a) nounwind {
; RV32IM: # %bb.0:
; RV32IM-NEXT: slli a0, a0, 24
; RV32IM-NEXT: li a1, 103
-; RV32IM-NEXT: srai a0, a0, 24
-; RV32IM-NEXT: mul a0, a0, a1
-; RV32IM-NEXT: srli a1, a0, 31
-; RV32IM-NEXT: srai a0, a0, 9
-; RV32IM-NEXT: add a0, a0, a1
+; RV32IM-NEXT: srai a2, a0, 24
+; RV32IM-NEXT: mul a1, a2, a1
+; RV32IM-NEXT: srai a1, a1, 9
+; RV32IM-NEXT: srai a0, a0, 31
+; RV32IM-NEXT: sub a0, a1, a0
; RV32IM-NEXT: ret
;
; RV32IMZB-LABEL: sdiv8_constant_srai:
; RV32IMZB: # %bb.0:
; RV32IMZB-NEXT: sext.b a0, a0
; RV32IMZB-NEXT: li a1, 103
-; RV32IMZB-NEXT: mul a0, a0, a1
-; RV32IMZB-NEXT: srli a1, a0, 31
-; RV32IMZB-NEXT: srai a0, a0, 9
-; RV32IMZB-NEXT: add a0, a0, a1
+; RV32IMZB-NEXT: mul a1, a0, a1
+; RV32IMZB-NEXT: srai a1, a1, 9
+; RV32IMZB-NEXT: srai a0, a0, 7
+; RV32IMZB-NEXT: sub a0, a1, a0
; RV32IMZB-NEXT: ret
;
; RV64IM-LABEL: sdiv8_constant_srai:
; RV64IM: # %bb.0:
; RV64IM-NEXT: slli a0, a0, 56
; RV64IM-NEXT: li a1, 103
-; RV64IM-NEXT: srai a0, a0, 56
-; RV64IM-NEXT: mul a0, a0, a1
-; RV64IM-NEXT: srli a1, a0, 63
-; RV64IM-NEXT: srai a0, a0, 9
-; RV64IM-NEXT: add a0, a0, a1
+; RV64IM-NEXT: srai a2, a0, 56
+; RV64IM-NEXT: mul a1, a2, a1
+; RV64IM-NEXT: srai a1, a1, 9
+; RV64IM-NEXT: srai a0, a0, 63
+; RV64IM-NEXT: sub a0, a1, a0
; RV64IM-NEXT: ret
;
; RV64IMZB-LABEL: sdiv8_constant_srai:
; RV64IMZB: # %bb.0:
; RV64IMZB-NEXT: sext.b a0, a0
; RV64IMZB-NEXT: li a1, 103
-; RV64IMZB-NEXT: mul a0, a0, a1
-; RV64IMZB-NEXT: srli a1, a0, 63
-; RV64IMZB-NEXT: srai a0, a0, 9
-; RV64IMZB-NEXT: add a0, a0, a1
+; RV64IMZB-NEXT: mul a1, a0, a1
+; RV64IMZB-NEXT: srai a1, a1, 9
+; RV64IMZB-NEXT: srai a0, a0, 7
+; RV64IMZB-NEXT: sub a0, a1, a0
; RV64IMZB-NEXT: ret
%1 = sdiv i8 %a, 5
ret i8 %1
@@ -752,12 +752,12 @@ define i16 @sdiv16_constant_no_srai(i16 %a) nounwind {
; RV32IM: # %bb.0:
; RV32IM-NEXT: slli a0, a0, 16
; RV32IM-NEXT: lui a1, 5
-; RV32IM-NEXT: srai a0, a0, 16
+; RV32IM-NEXT: srai a2, a0, 16
; RV32IM-NEXT: addi a1, a1, 1366
-; RV32IM-NEXT: mul a0, a0, a1
-; RV32IM-NEXT: srli a1, a0, 31
-; RV32IM-NEXT: srli a0, a0, 16
-; RV32IM-NEXT: add a0, a0, a1
+; RV32IM-NEXT: mul a1, a2, a1
+; RV32IM-NEXT: srli a1, a1, 16
+; RV32IM-NEXT: srai a0, a0, 31
+; RV32IM-NEXT: sub a0, a1, a0
; RV32IM-NEXT: ret
;
; RV32IMZB-LABEL: sdiv16_constant_no_srai:
@@ -765,22 +765,22 @@ define i16 @sdiv16_constant_no_srai(i16 %a) nounwind {
; RV32IMZB-NEXT: sext.h a0, a0
; RV32IMZB-NEXT: lui a1, 5
; RV32IMZB-NEXT: addi a1, a1, 1366
-; RV32IMZB-NEXT: mul a0, a0, a1
-; RV32IMZB-NEXT: srli a1, a0, 31
-; RV32IMZB-NEXT: srli a0, a0, 16
-; RV32IMZB-NEXT: add a0, a0, a1
+; RV32IMZB-NEXT: mul a1, a0, a1
+; RV32IMZB-NEXT: srli a1, a1, 16
+; RV32IMZB-NEXT: srai a0, a0, 15
+; RV32IMZB-NEXT: sub a0, a1, a0
; RV32IMZB-NEXT: ret
;
; RV64IM-LABEL: sdiv16_constant_no_srai:
; RV64IM: # %bb.0:
; RV64IM-NEXT: slli a0, a0, 48
; RV64IM-NEXT: lui a1, 5
-; RV64IM-NEXT: srai a0, a0, 48
+; RV64IM-NEXT: srai a2, a0, 48
; RV64IM-NEXT: addi a1, a1, 1366
-; RV64IM-NEXT: mul a0, a0, a1
-; RV64IM-NEXT: srli a1, a0, 63
-; RV64IM-NEXT: srli a0, a0, 16
-; RV64IM-NEXT: add a0, a0, a1
+; RV64IM-NEXT: mul a1, a2, a1
+; RV64IM-NEXT: srli a1, a1, 16
+; RV64IM-NEXT: srai a0, a0, 63
+; RV64IM-NEXT: sub a0, a1, a0
; RV64IM-NEXT: ret
;
; RV64IMZB-LABEL: sdiv16_constant_no_srai:
@@ -788,10 +788,10 @@ define i16 @sdiv16_constant_no_srai(i16 %a) nounwind {
; RV64IMZB-NEXT: sext.h a0, a0
; RV64IMZB-NEXT: lui a1, 5
; RV64IMZB-NEXT: addi a1, a1, 1366
-; RV64IMZB-NEXT: mul a0, a0, a1
-; RV64IMZB-NEXT: srli a1, a0, 63
-; RV64IMZB-NEXT: srli a0, a0, 16
-; RV64IMZB-NEXT: add a0, a0, a1
+; RV64IMZB-NEXT: mul a1, a0, a1
+; RV64IMZB-NEXT: srli a1, a1, 16
+; RV64IMZB-NEXT: srai a0, a0, 15
+; RV64IMZB-NEXT: sub a0, a1, a0
; RV64IMZB-NEXT: ret
%1 = sdiv i16 %a, 3
ret i16 %1
@@ -802,12 +802,12 @@ define i16 @sdiv16_constant_srai(i16 %a) nounwind {
; RV32IM: # %bb.0:
; RV32IM-NEXT: slli a0, a0, 16
; RV32IM-NEXT: lui a1, 6
-; RV32IM-NEXT: srai a0, a0, 16
+; RV32IM-NEXT: srai a2, a0, 16
; RV32IM-NEXT: addi a1, a1, 1639
-; RV32IM-NEXT: mul a0, a0, a1
-; RV32IM-NEXT: srli a1, a0, 31
-; RV32IM-NEXT: srai a0, a0, 17
-; RV32IM-NEXT: add a0, a0, a1
+; RV32IM-NEXT: mul a1, a2, a1
+; RV32IM-NEXT: srai a1, a1, 17
+; RV32IM-NEXT: srai a0, a0, 31
+; RV32IM-NEXT: sub a0, a1, a0
; RV32IM-NEXT: ret
;
; RV32IMZB-LABEL: sdiv16_constant_srai:
@@ -815,22 +815,22 @@ define i16 @sdiv16_constant_srai(i16 %a) nounwind {
; RV32IMZB-NEXT: sext.h a0, a0
; RV32IMZB-NEXT: lui a1, 6
; RV32IMZB-NEXT: addi a1, a1, 1639
-; RV32IMZB-NEXT: mul a0, a0, a1
-; RV32IMZB-NEXT: srli a1, a0, 31
-; RV32IMZB-NEXT: srai a0, a0, 17
-; RV32IMZB-NEXT: add a0, a0, a1
+; RV32IMZB-NEXT: mul a1, a0, a1
+; RV32IMZB-NEXT: srai a1, a1, 17
+; RV32IMZB-NEXT: srai a0, a0, 15
+; RV32IMZB-NEXT: sub a0, a1, a0
; RV32IMZB-NEXT: ret
;
; RV64IM-LABEL: sdiv16_constant_srai:
; RV64IM: # %bb.0:
; RV64IM-NEXT: slli a0, a0, 48
; RV64IM-NEXT: lui a1, 6
-; RV64IM-NEXT: srai a0, a0, 48
+; RV64IM-NEXT: srai a2, a0, 48
; RV64IM-NEXT: addi a1, a1, 1639
-; RV64IM-NEXT: mul a0, a0, a1
-; RV64IM-NEXT: srli a1, a0, 63
-; RV64IM-NEXT: srai a0, a0, 17
-; RV64IM-NEXT: add a0, a0, a1
+; RV64IM-NEXT: mul a1, a2, a1
+; RV64IM-NEXT: srai a1, a1, 17
+; RV64IM-NEXT: srai a0, a0, 63
+; RV64IM-NEXT: sub a0, a1, a0
; RV64IM-NEXT: ret
;
; RV64IMZB-LABEL: sdiv16_constant_srai:
@@ -838,10 +838,10 @@ define i16 @sdiv16_constant_srai(i16 %a) nounwind {
; RV64IMZB-NEXT: sext.h a0, a0
; RV64IMZB-NEXT: lui a1, 6
; RV64IMZB-NEXT: addi a1, a1, 1639
-; RV64IMZB-NEXT: mul a0, a0, a1
-; RV64IMZB-NEXT: srli a1, a0, 63
-; RV64IMZB-NEXT: srai a0, a0, 17
-; RV64IMZB-NEXT: add a0, a0, a1
+; RV64IMZB-NEXT: mul a1, a0, a1
+; RV64IMZB-NEXT: srai a1, a1, 17
+; RV64IMZB-NEXT: srai a0, a0, 15
+; RV64IMZB-NEXT: sub a0, a1, a0
; RV64IMZB-NEXT: ret
%1 = sdiv i16 %a, 5
ret i16 %1
diff --git a/llvm/test/CodeGen/RISCV/div.ll b/llvm/test/CodeGen/RISCV/div.ll
index b160a532770db..1f1e798c73e01 100644
--- a/llvm/test/CodeGen/RISCV/div.ll
+++ b/llvm/test/CodeGen/RISCV/div.ll
@@ -617,10 +617,10 @@ define i32 @sdiv_constant(i32 %a) nounwind {
; RV32IM: # %bb.0:
; RV32IM-NEXT: lui a1, 419430
; RV32IM-NEXT: addi a1, a1, 1639
-; RV32IM-NEXT: mulh a0, a0, a1
-; RV32IM-NEXT: srli a1, a0, 31
-; RV32IM-NEXT: srai a0, a0, 1
-; RV32IM-NEXT: add a0, a0, a1
+; RV32IM-NEXT: mulh a1, a0, a1
+; RV32IM-NEXT: srai a1, a1, 1
+; RV32IM-NEXT: srai a0, a0, 31
+; RV32IM-NEXT: sub a0, a1, a0
; RV32IM-NEXT: ret
;
; RV64I-LABEL: sdiv_constant:
@@ -636,13 +636,13 @@ define i32 @sdiv_constant(i32 %a) nounwind {
;
; RV64IM-LABEL: sdiv_constant:
; RV64IM: # %bb.0:
-; RV64IM-NEXT: sext.w a0, a0
-; RV64IM-NEXT: lui a1, 419430
-; RV64IM-NEXT: addi a1, a1, 1639
-; RV64IM-NEXT: mul a0, a0, a1
-; RV64IM-NEXT: srli a1, a0, 63
-; RV64IM-NEXT: srai a0, a0, 33
-; RV64IM-NEXT: add a0, a0, a1
+; RV64IM-NEXT: sext.w a1, a0
+; RV64IM-NEXT: lui a2, 419430
+; RV64IM-NEXT: addi a2, a2, 1639
+; RV64IM-NEXT: mul a1, a1, a2
+; RV64IM-NEXT: srai a1, a1, 33
+; RV64IM-NEXT: sraiw a0, a0, 31
+; RV64IM-NEXT: sub a0, a1, a0
; RV64IM-NEXT: ret
%1 = sdiv i32 %a, 5
ret i32 %1
@@ -816,10 +816,10 @@ define i64 @sdiv64_constant(i64 %a) nounwind {
; RV64IM: # %bb.0:
; RV64IM-NEXT: lui a1, %hi(.LCPI21_0)
; RV64IM-NEXT: ld a1, %lo(.LCPI21_0)(a1)
-; RV64IM-NEXT: mulh a0, a0, a1
-; RV64IM-NEXT: srli a1, a0, 63
-; RV64IM-NEXT: srai a0, a0, 1
-; RV64IM-NEXT: add a0, a0, a1
+; RV64IM-NEXT: mulh a1, a0, a1
+; RV64IM-NEXT: srai a1, a1, 1
+; RV64IM-NEXT: srai a0, a0, 63
+; RV64IM-NEXT: sub a0, a1, a0
; RV64IM-NEXT: ret
%1 = sdiv i64 %a, 5
ret i64 %1
@@ -978,11 +978,11 @@ define i8 @sdiv8_constant(i8 %a) nounwind {
; RV32IM: # %bb.0:
; RV32IM-NEXT: slli a0, a0, 24
; RV32IM-NEXT: li a1, 103
-; RV32IM-NEXT: srai a0, a0, 24
-; RV32IM-NEXT: mul a0, a0, a1
-; RV32IM-NEXT: srli a1, a0, 31
-; RV32IM-NEXT: srai a0, a0, 9
-; RV32IM-NEXT: add a0, a0, a1
+; RV32IM-NEXT: srai a2, a0, 24
+; RV32IM-NEXT: mul a1, a2, a1
+; RV32IM-NEXT: srai a1, a1, 9
+; RV32IM-NEXT: srai a0, a0, 31
+; RV32IM-NEXT: sub a0, a1, a0
; RV32IM-NEXT: ret
;
; RV64I-LABEL: sdiv8_constant:
@@ -1001,11 +1001,11 @@ define i8 @sdiv8_constant(i8 %a) nounwind {
; RV64IM: # %bb.0:
; RV64IM-NEXT: slli a0, a0, 56
; RV64IM-NEXT: li a1, 103
-; RV64IM-NEXT: srai a0, a0, 56
-; RV64IM-NEXT: mul a0, a0, a1
-; RV64IM-NEXT: srli a1, a0, 63
-; RV64IM-NEXT: srai a0, a0, 9
-; RV64IM-NEXT: add a0, a0, a1
+; RV64IM-NEXT: srai a2, a0, 56
+; RV64IM-NEXT: mul a1, a2, a1
+; RV64IM-NEXT: srai a1, a1, 9
+; RV64IM-NEXT: srai a0, a0, 63
+; RV64IM-NEXT: sub a0, a1, a0
; RV64IM-NEXT: ret
%1 = sdiv i8 %a, 5
ret i8 %1
@@ -1164,12 +1164,12 @@ define i16 @sdiv16_constant(i16 %a) nounwind {
; RV32IM: # %bb.0:
; RV32IM-NEXT: slli a0, a0, 16
; RV32IM-NEXT: lui a1, 6
-; RV32IM-NEXT: srai a0, a0, 16
+; RV32IM-NEXT: srai a2, a0, 16
; RV32IM-NEXT: addi a1, a1, 1639
-; RV32IM-NEXT: mul a0, a0, a1
-; RV32IM-NEXT: srli a1, a0, 31
-; RV32IM-NEXT: srai a0, a0, 17
-; RV32IM-NEXT: add a0, a0, a1
+; RV32IM-NEXT: mul a1, a2, a1
+; RV32IM-NEXT: srai a1, a1, 17
+; RV32IM-NEXT: srai a0, a0, 31
+; RV32IM-NEXT: sub a0, a1, a0
; RV32IM-NEXT: ret
;
; RV64I-LABEL: sdiv16_constant:
@@ -1188,12 +1188,12 @@ define i16 @sdiv16_constant(i16 %a) nounwind {
; RV64IM: # %bb.0:
; RV64IM-NEXT: slli a0, a0, 48
; RV64IM-NEXT: lui a1, 6
-; RV64IM-NEXT: srai a0, a0, 48
+; RV64IM-NEXT: srai a2, a0, 48
; RV64IM-NEXT: addi a1, a1, 1639
-; RV64IM-NEXT: mul a0, a0, a1
-; RV64IM-NEXT: srli a1, a0, 63
-; RV64IM-NEXT: srai a0, a0, 17
-; RV64IM-NEXT: add a0, a0, a1
+; RV64IM-NEXT: mul a1, a2, a1
+; RV64IM-NEXT: srai a1, a1, 17
+; RV64IM-NEXT: srai a0, a0, 63
+; RV64IM-NEXT: sub a0, a1, a0
; RV64IM-NEXT: ret
%1 = sdiv i16 %a, 5
ret i16 %1
diff --git a/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
index 1474c73dacfc8..7a3c03b4009b6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
@@ -814,9 +814,9 @@ define i32 @extractelt_sdiv_nxv4i32_splat(<vscale x 4 x i32> %x) {
; RV32M-NEXT: vmv.x.s a0, v8
; RV32M-NEXT: lui a1, 349525
; RV32M-NEXT: addi a1, a1, 1366
-; RV32M-NEXT: mulh a0, a0, a1
-; RV32M-NEXT: srli a1, a0, 31
-; RV32M-NEXT: add a0, a0, a1
+; RV32M-NEXT: mulh a1, a0, a1
+; RV32M-NEXT: srai a0, a0, 31
+; RV32M-NEXT: sub a0, a1, a0
; RV32M-NEXT: ret
%bo = sdiv <vscale x 4 x i32> %x, splat (i32 3)
%ext = extractelement <vscale x 4 x i32> %bo, i32 0
@@ -841,9 +841,9 @@ define i32 @extractelt_udiv_nxv4i32_splat(<vscale x 4 x i32> %x) {
; RV32M-NEXT: vmv.x.s a0, v8
; RV32M-NEXT: lui a1, 349525
; RV32M-NEXT: addi a1, a1, 1366
-; RV32M-NEXT: mulh a0, a0, a1
-; RV32M-NEXT: srli a1, a0, 31
-; RV32M-NEXT: add a0, a0, a1
+; RV32M-NEXT: mulh a1, a0, a1
+; RV32M-NEXT: srai a0, a0, 31
+; RV32M-NEXT: sub a0, a1, a0
; RV32M-NEXT: ret
%bo = sdiv <vscale x 4 x i32> %x, splat (i32 3)
%ext = extractelement <vscale x 4 x i32> %bo, i32 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
index 22bb7bf317241..ab5781138003c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
@@ -798,10 +798,10 @@ define i32 @extractelt_sdiv_nxv4i32_splat(<vscale x 4 x i32> %x) {
; RV64M-NEXT: vmv.x.s a0, v8
; RV64M-NEXT: lui a1, 349525
; RV64M-NEXT: addi a1, a1, 1366
-; RV64M-NEXT: mul a0, a0, a1
-; RV64M-NEXT: srli a1, a0, 63
-; RV64M-NEXT: srli a0, a0, 32
-; RV64M-NEXT: addw a0, a0, a1
+; RV64M-NEXT: mul a1, a0, a1
+; RV64M-NEXT: srli a1, a1, 32
+; RV64M-NEXT: srli a0, a0, 31
+; RV64M-NEXT: subw a0, a1, a0
; RV64M-NEXT: ret
%bo = sdiv <vscale x 4 x i32> %x, splat (i32 3)
%ext = extractelement <vscale x 4 x i32> %bo, i32 0
@@ -826,10 +826,10 @@ define i32 @extractelt_udiv_nxv4i32_splat(<vscale x 4 x i32> %x) {
; RV64M-NEXT: vmv.x.s a0, v8
; RV64M-NEXT: lui a1, 349525
; RV64M-NEXT: addi a1, a1, 1366
-; RV64M-NEXT: mul a0, a0, a1
-; RV64M-NEXT: srli a1, a0, 63
-; RV64M-NEXT: srli a0, a0, 32
-; RV64M-NEXT: addw a0, a0, a1
+; RV64M-NEXT: mul a1, a0, a1
+; RV64M-NEXT: srli a1, a1, 32
+; RV64M-NEXT: srli a0, a0, 31
+; RV64M-NEXT: subw a0, a1, a0
; RV64M-NEXT: ret
%bo = sdiv <vscale x 4 x i32> %x, splat (i32 3)
%ext = extractelement <vscale x 4 x i32> %bo, i32 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
index 9580d6caf08c3..7ad9764ee528d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
@@ -97,7 +97,6 @@ define float @extractelt_v4f32(<4 x float> %a) nounwind {
; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
-;
%b = extractelement <4 x float> %a, i32 2
ret float %b
}
@@ -108,7 +107,6 @@ define double @extractelt_v2f64(<2 x double> %a) nounwind {
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
-;
%b = extractelement <2 x double> %a, i32 0
ret double %b
}
@@ -120,7 +118,6 @@ define i8 @extractelt_v32i8(<32 x i8> %a) nounwind {
; CHECK-NEXT: vslidedown.vi v8, v8, 7
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
-;
%b = extractelement <32 x i8> %a, i32 7
ret i8 %b
}
@@ -132,7 +129,6 @@ define i16 @extractelt_v16i16(<16 x i16> %a) nounwind {
; CHECK-NEXT: vslidedown.vi v8, v8, 7
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
-;
%b = extractelement <16 x i16> %a, i32 7
ret i16 %b
}
@@ -144,7 +140,6 @@ define i32 @extractelt_v8i32(<8 x i32> %a) nounwind {
; CHECK-NEXT: vslidedown.vi v8, v8, 6
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
-;
%b = extractelement <8 x i32> %a, i32 6
ret i32 %b
}
@@ -166,7 +161,6 @@ define i64 @extractelt_v4i64(<4 x i64> %a) nounwind {
; RV64-NEXT: vslidedown.vi v8, v8, 3
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
-;
%b = extractelement <4 x i64> %a, i32 3
ret i64 %b
}
@@ -179,7 +173,6 @@ define bfloat @extractelt_v16bf16(<16 x bfloat> %a) nounwind {
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: fmv.h.x fa0, a0
; CHECK-NEXT: ret
-;
%b = extractelement <16 x bfloat> %a, i32 7
ret bfloat %b
}
@@ -199,7 +192,6 @@ define half @extractelt_v16f16(<16 x half> %a) nounwind {
; ZVFHMIN-NEXT: vmv.x.s a0, v8
; ZVFHMIN-NEXT: fmv.h.x fa0, a0
; ZVFHMIN-NEXT: ret
-;
%b = extractelement <16 x half> %a, i32 7
ret half %b
}
@@ -211,7 +203,6 @@ define float @extractelt_v8f32(<8 x float> %a) nounwind {
; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
-;
%b = extractelement <8 x float> %a, i32 2
ret float %b
}
@@ -222,7 +213,6 @@ define double @extractelt_v4f64(<4 x double> %a) nounwind {
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
-;
%b = extractelement <4 x double> %a, i32 0
ret double %b
}
@@ -247,7 +237,6 @@ define i64 @extractelt_v3i64(<3 x i64> %a) nounwind {
; RV64-NEXT: vslidedown.vi v8, v8, 2
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
-;
%b = extractelement <3 x i64> %a, i32 2
ret i64 %b
}
@@ -289,7 +278,6 @@ define i32 @extractelt_v32i32(<32 x i32> %a) nounwind {
; RV64-NEXT: ld s0, 240(sp) # 8-byte Folded Reload
; RV64-NEXT: addi sp, sp, 256
; RV64-NEXT: ret
-;
%b = extractelement <32 x i32> %a, i32 31
ret i32 %b
}
@@ -331,7 +319,6 @@ define i32 @extractelt_v64i32(<64 x i32> %a) nounwind {
; RV64-NEXT: ld s0, 240(sp) # 8-byte Folded Reload
; RV64-NEXT: addi sp, sp, 256
; RV64-NEXT: ret
-;
%b = extractelement <64 x i32> %a, i32 63
ret i32 %b
}
@@ -343,7 +330,6 @@ define i8 @extractelt_v16i8_idx(<16 x i8> %a, i32 zeroext %idx) nounwind {
; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
-;
%b = extractelement <16 x i8> %a, i32 %idx
ret i8 %b
}
@@ -355,7 +341,6 @@ define i16 @extractelt_v8i16_idx(<8 x i16> %a, i32 zeroext %idx) nounwind {
; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
-;
%b = extractelement <8 x i16> %a, i32 %idx
ret i16 %b
}
@@ -368,7 +353,6 @@ define i32 @extractelt_v4i32_idx(<4 x i32> %a, i32 zeroext %idx) nounwind {
; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
-;
%b = add <4 x i32> %a, %a
%c = extractelement <4 x i32> %b, i32 %idx
ret i32 %c
@@ -394,7 +378,6 @@ define i64 @extractelt_v2i64_idx(<2 x i64> %a, i32 zeroext %idx) nounwind {
; RV64-NEXT: vslidedown.vx v8, v8, a0
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
-;
%b = add <2 x i64> %a, %a
%c = extractelement <2 x i64> %b, i32 %idx
ret i64 %c
@@ -413,7 +396,6 @@ define bfloat @extractelt_v8bf16_idx(<8 x bfloat> %a, i32 zeroext %idx) nounwind
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: fmv.h.x fa0, a0
; CHECK-NEXT: ret
-;
%b = fadd <8 x bfloat> %a, %a
%c = extractelement <8 x bfloat> %b, i32 %idx
ret bfloat %c
@@ -440,7 +422,6 @@ define half @extractelt_v8f16_idx(<8 x half> %a, i32 zeroext %idx) nounwind {
; ZVFHMIN-NEXT: vmv.x.s a0, v8
; ZVFHMIN-NEXT: fmv.h.x fa0, a0
; ZVFHMIN-NEXT: ret
-;
%b = fadd <8 x half> %a, %a
%c = extractelement <8 x half> %b, i32 %idx
ret half %c
@@ -454,7 +435,6 @@ define float @extractelt_v4f32_idx(<4 x float> %a, i32 zeroext %idx) nounwind {
; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
-;
%b = fadd <4 x float> %a, %a
%c = extractelement <4 x float> %b, i32 %idx
ret float %c
@@ -468,7 +448,6 @@ define double @extractelt_v2f64_idx(<2 x double> %a, i32 zeroext %idx) nounwind
; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
-;
%b = fadd <2 x double> %a, %a
%c = extractelement <2 x double> %b, i32 %idx
ret double %c
@@ -481,7 +460,6 @@ define i8 @extractelt_v32i8_idx(<32 x i8> %a, i32 zeroext %idx) nounwind {
; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
-;
%b = extractelement <32 x i8> %a, i32 %idx
ret i8 %b
}
@@ -493,7 +471,6 @@ define i16 @extractelt_v16i16_idx(<16 x i16> %a, i32 zeroext %idx) nounwind {
; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
-;
%b = extractelement <16 x i16> %a, i32 %idx
ret i16 %b
}
@@ -506,7 +483,6 @@ define i32 @extractelt_v8i32_idx(<8 x i32> %a, i32 zeroext %idx) nounwind {
; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
-;
%b = add <8 x i32> %a, %a
%c = extractelement <8 x i32> %b, i32 %idx
ret i32 %c
@@ -532,7 +508,6 @@ define i64 @extractelt_v4i64_idx(<4 x i64> %a, i32 zeroext %idx) nounwind {
; RV64-NEXT: vslidedown.vx v8, v8, a0
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
-;
%b = add <4 x i64> %a, %a
%c = extractelement <4 x i64> %b, i32 %idx
ret i64 %c
@@ -551,7 +526,6 @@ define bfloat @extractelt_v16bf16_idx(<16 x bfloat> %a, i32 zeroext %idx) nounwi
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: fmv.h.x fa0, a0
; CHECK-NEXT: ret
-;
%b = fadd <16 x bfloat> %a, %a
%c = extractelement <16 x bfloat> %b, i32 %idx
ret bfloat %c
@@ -578,7 +552,6 @@ define half @extractelt_v16f16_idx(<16 x half> %a, i32 zeroext %idx) nounwind {
; ZVFHMIN-NEXT: vmv.x.s a0, v8
; ZVFHMIN-NEXT: fmv.h.x fa0, a0
; ZVFHMIN-NEXT: ret
-;
%b = fadd <16 x half> %a, %a
%c = extractelement <16 x half> %b, i32 %idx
ret half %c
@@ -592,7 +565,6 @@ define float @extractelt_v8f32_idx(<8 x float> %a, i32 zeroext %idx) nounwind {
; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
-;
%b = fadd <8 x float> %a, %a
%c = extractelement <8 x float> %b, i32 %idx
ret float %c
@@ -606,7 +578,6 @@ define double @extractelt_v4f64_idx(<4 x double> %a, i32 zeroext %idx) nounwind
; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
-;
%b = fadd <4 x double> %a, %a
%c = extractelement <4 x double> %b, i32 %idx
ret double %c
@@ -637,7 +608,6 @@ define i64 @extractelt_v3i64_idx(<3 x i64> %a, i32 zeroext %idx) nounwind {
; RV64-NEXT: vslidedown.vx v8, v8, a0
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
-;
%b = add <3 x i64> %a, %a
%c = extractelement <3 x i64> %b, i32 %idx
ret i64 %c
@@ -743,7 +713,6 @@ define i32 @extractelt_v32i32_idx(ptr %x, i32 zeroext %idx) nounwind {
; RV64M-NEXT: ld s0, 240(sp) # 8-byte Folded Reload
; RV64M-NEXT: addi sp, sp, 256
; RV64M-NEXT: ret
-;
%a = load <32 x i32>, ptr %x
%b = add <32 x i32> %a, %a
%c = extractelement <32 x i32> %b, i32 %idx
@@ -800,7 +769,6 @@ define i32 @extractelt_v64i32_idx(<64 x i32> %a, i32 zeroext %idx) nounwind {
; RV64-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
; RV64-NEXT: addi sp, sp, 384
; RV64-NEXT: ret
-;
%b = add <64 x i32> %a, %a
%c = extractelement <64 x i32> %b, i32 %idx
ret i32 %c
@@ -813,7 +781,6 @@ define void @store_extractelt_v16i8(<16 x i8> %a, ptr %p) nounwind {
; CHECK-NEXT: vslidedown.vi v8, v8, 7
; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
-;
%b = extractelement <16 x i8> %a, i32 7
store i8 %b, ptr %p
ret void
@@ -826,7 +793,6 @@ define void @store_extractelt_v8i16(<8 x i16> %a, ptr %p) nounwind {
; CHECK-NEXT: vslidedown.vi v8, v8, 7
; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
-;
%b = extractelement <8 x i16> %a, i32 7
store i16 %b, ptr %p
ret void
@@ -839,7 +805,6 @@ define void @store_extractelt_v4i32(<4 x i32> %a, ptr %p) nounwind {
; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret
-;
%b = extractelement <4 x i32> %a, i32 2
store i32 %b, ptr %p
ret void
@@ -865,7 +830,6 @@ define void @store_extractelt_v2i64(<2 x i64> %a, ptr %p) nounwind {
; RV64-NEXT: vslidedown.vi v8, v8, 1
; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: ret
-;
%b = extractelement <2 x i64> %a, i64 1
store i64 %b, ptr %p
ret void
@@ -878,7 +842,6 @@ define void @store_extractelt_v2f64(<2 x double> %a, ptr %p) nounwind {
; CHECK-NEXT: vslidedown.vi v8, v8, 1
; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: ret
-;
%b = extractelement <2 x double> %a, i64 1
store double %b, ptr %p
ret void
@@ -900,7 +863,6 @@ define i32 @extractelt_add_v4i32(<4 x i32> %x) {
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: addiw a0, a0, 13
; RV64-NEXT: ret
-;
%bo = add <4 x i32> %x, <i32 11, i32 12, i32 13, i32 14>
%ext = extractelement <4 x i32> %bo, i32 2
ret i32 %ext
@@ -924,7 +886,6 @@ define i32 @extractelt_sub_v4i32(<4 x i32> %x) {
; RV64-NEXT: li a1, 13
; RV64-NEXT: subw a0, a1, a0
; RV64-NEXT: ret
-;
%bo = sub <4 x i32> <i32 11, i32 12, i32 13, i32 14>, %x
%ext = extractelement <4 x i32> %bo, i32 2
ret i32 %ext
@@ -966,7 +927,6 @@ define i32 @extractelt_mul_v4i32(<4 x i32> %x) {
; RV64M-NEXT: li a1, 13
; RV64M-NEXT: mulw a0, a0, a1
; RV64M-NEXT: ret
-;
%bo = mul <4 x i32> %x, <i32 11, i32 12, i32 13, i32 14>
%ext = extractelement <4 x i32> %bo, i32 2
ret i32 %ext
@@ -1004,9 +964,9 @@ define i32 @extractelt_sdiv_v4i32(<4 x i32> %x) {
; RV32M-NEXT: vmv.x.s a1, v8
; RV32M-NEXT: addi a0, a0, -945
; RV32M-NEXT: mulh a0, a1, a0
-; RV32M-NEXT: srli a1, a0, 31
; RV32M-NEXT: srai a0, a0, 2
-; RV32M-NEXT: add a0, a0, a1
+; RV32M-NEXT: srai a1, a1, 31
+; RV32M-NEXT: sub a0, a0, a1
; RV32M-NEXT: ret
;
; RV64NOM-LABEL: extractelt_sdiv_v4i32:
@@ -1040,11 +1000,10 @@ define i32 @extractelt_sdiv_v4i32(<4 x i32> %x) {
; RV64M-NEXT: vmv.x.s a1, v8
; RV64M-NEXT: addi a0, a0, -945
; RV64M-NEXT: mul a0, a1, a0
-; RV64M-NEXT: srli a1, a0, 63
; RV64M-NEXT: srai a0, a0, 34
-; RV64M-NEXT: add a0, a0, a1
+; RV64M-NEXT: srai a1, a1, 31
+; RV64M-NEXT: sub a0, a0, a1
; RV64M-NEXT: ret
-;
%bo = sdiv <4 x i32> %x, <i32 11, i32 12, i32 13, i32 14>
%ext = extractelement <4 x i32> %bo, i32 2
ret i32 %ext
@@ -1099,7 +1058,6 @@ define i32 @extractelt_udiv_v4i32(<4 x i32> %x) {
; RV64M-NEXT: mulhu a0, a1, a0
; RV64M-NEXT: srli a0, a0, 34
; RV64M-NEXT: ret
-;
%bo = udiv <4 x i32> %x, <i32 11, i32 12, i32 13, i32 14>
%ext = extractelement <4 x i32> %bo, i32 2
ret i32 %ext
@@ -1115,7 +1073,6 @@ define float @extractelt_fadd_v4f32(<4 x float> %x) {
; CHECK-NEXT: fmv.w.x fa4, a0
; CHECK-NEXT: fadd.s fa0, fa5, fa4
; CHECK-NEXT: ret
-;
%bo = fadd <4 x float> %x, <float 11.0, float 12.0, float 13.0, float 14.0>
%ext = extractelement <4 x float> %bo, i32 2
ret float %ext
@@ -1131,7 +1088,6 @@ define float @extractelt_fsub_v4f32(<4 x float> %x) {
; CHECK-NEXT: fmv.w.x fa4, a0
; CHECK-NEXT: fsub.s fa0, fa4, fa5
; CHECK-NEXT: ret
-;
%bo = fsub <4 x float> <float 11.0, float 12.0, float 13.0, float 14.0>, %x
%ext = extractelement <4 x float> %bo, i32 2
ret float %ext
@@ -1147,7 +1103,6 @@ define float @extractelt_fmul_v4f32(<4 x float> %x) {
; CHECK-NEXT: fmv.w.x fa4, a0
; CHECK-NEXT: fmul.s fa0, fa5, fa4
; CHECK-NEXT: ret
-;
%bo = fmul <4 x float> %x, <float 11.0, float 12.0, float 13.0, float 14.0>
%ext = extractelement <4 x float> %bo, i32 2
ret float %ext
@@ -1163,7 +1118,6 @@ define float @extractelt_fdiv_v4f32(<4 x float> %x) {
; CHECK-NEXT: fmv.w.x fa4, a0
; CHECK-NEXT: fdiv.s fa0, fa5, fa4
; CHECK-NEXT: ret
-;
%bo = fdiv <4 x float> %x, <float 11.0, float 12.0, float 13.0, float 14.0>
%ext = extractelement <4 x float> %bo, i32 2
ret float %ext
@@ -1176,7 +1130,6 @@ define i32 @extractelt_v16i32_idx7_exact_vlen(<16 x i32> %a) nounwind vscale_ran
; CHECK-NEXT: vslidedown.vi v8, v9, 3
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
-;
%b = extractelement <16 x i32> %a, i32 7
ret i32 %b
}
@@ -1188,7 +1141,6 @@ define i32 @extractelt_v16i32_idx15_exact_vlen(<16 x i32> %a) nounwind vscale_ra
; CHECK-NEXT: vslidedown.vi v8, v11, 3
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
-;
%b = extractelement <16 x i32> %a, i32 15
ret i32 %b
}
diff --git a/llvm/test/CodeGen/RISCV/srem-lkk.ll b/llvm/test/CodeGen/RISCV/srem-lkk.ll
index 54a8f8625bbe0..5d00098a21da0 100644
--- a/llvm/test/CodeGen/RISCV/srem-lkk.ll
+++ b/llvm/test/CodeGen/RISCV/srem-lkk.ll
@@ -68,11 +68,11 @@ define i32 @fold_srem_positive_even(i32 %x) nounwind {
; RV32IM-LABEL: fold_srem_positive_even:
; RV32IM: # %bb.0:
; RV32IM-NEXT: lui a1, 253241
+; RV32IM-NEXT: srai a2, a0, 31
; RV32IM-NEXT: addi a1, a1, -15
; RV32IM-NEXT: mulh a1, a0, a1
-; RV32IM-NEXT: srli a2, a1, 31
; RV32IM-NEXT: srai a1, a1, 8
-; RV32IM-NEXT: add a1, a1, a2
+; RV32IM-NEXT: sub a1, a1, a2
; RV32IM-NEXT: li a2, 1060
; RV32IM-NEXT: mul a1, a1, a2
; RV32IM-NEXT: sub a0, a0, a1
@@ -95,9 +95,9 @@ define i32 @fold_srem_positive_even(i32 %x) nounwind {
; RV64IM-NEXT: lui a2, 253241
; RV64IM-NEXT: addi a2, a2, -15
; RV64IM-NEXT: mul a1, a1, a2
-; RV64IM-NEXT: srli a2, a1, 63
+; RV64IM-NEXT: sraiw a2, a0, 31
; RV64IM-NEXT: srai a1, a1, 40
-; RV64IM-NEXT: add a1, a1, a2
+; RV64IM-NEXT: sub a1, a1, a2
; RV64IM-NEXT: li a2, 1060
; RV64IM-NEXT: mul a1, a1, a2
; RV64IM-NEXT: subw a0, a0, a1
@@ -416,10 +416,10 @@ define i64 @dont_fold_srem_i64(i64 %x) nounwind {
; RV64IM: # %bb.0:
; RV64IM-NEXT: lui a1, %hi(.LCPI8_0)
; RV64IM-NEXT: ld a1, %lo(.LCPI8_0)(a1)
+; RV64IM-NEXT: srai a2, a0, 63
; RV64IM-NEXT: mulh a1, a0, a1
-; RV64IM-NEXT: srli a2, a1, 63
; RV64IM-NEXT: srai a1, a1, 5
-; RV64IM-NEXT: add a1, a1, a2
+; RV64IM-NEXT: sub a1, a1, a2
; RV64IM-NEXT: li a2, 98
; RV64IM-NEXT: mul a1, a1, a2
; RV64IM-NEXT: sub a0, a0, a1
diff --git a/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll b/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
index 06bbe5209df35..c96f8fb3ee619 100644
--- a/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
+++ b/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
@@ -165,13 +165,13 @@ define i1 @test_srem_even(i4 %X) nounwind {
; RV32M-NEXT: slli a1, a0, 28
; RV32M-NEXT: srai a1, a1, 28
; RV32M-NEXT: slli a2, a1, 1
+; RV32M-NEXT: add a2, a2, a1
+; RV32M-NEXT: srli a1, a1, 3
+; RV32M-NEXT: srli a2, a2, 4
+; RV32M-NEXT: sub a2, a2, a1
+; RV32M-NEXT: slli a1, a2, 1
+; RV32M-NEXT: slli a2, a2, 2
; RV32M-NEXT: add a1, a2, a1
-; RV32M-NEXT: srli a2, a1, 31
-; RV32M-NEXT: srli a1, a1, 4
-; RV32M-NEXT: add a1, a1, a2
-; RV32M-NEXT: slli a2, a1, 1
-; RV32M-NEXT: slli a1, a1, 2
-; RV32M-NEXT: add a1, a1, a2
; RV32M-NEXT: sub a0, a0, a1
; RV32M-NEXT: andi a0, a0, 15
; RV32M-NEXT: addi a0, a0, -1
@@ -183,13 +183,13 @@ define i1 @test_srem_even(i4 %X) nounwind {
; RV64M-NEXT: slli a1, a0, 60
; RV64M-NEXT: srai a1, a1, 60
; RV64M-NEXT: slli a2, a1, 1
+; RV64M-NEXT: add a2, a2, a1
+; RV64M-NEXT: srli a1, a1, 3
+; RV64M-NEXT: srli a2, a2, 4
+; RV64M-NEXT: sub a2, a2, a1
+; RV64M-NEXT: slli a1, a2, 1
+; RV64M-NEXT: slli a2, a2, 2
; RV64M-NEXT: add a1, a2, a1
-; RV64M-NEXT: srli a2, a1, 63
-; RV64M-NEXT: srli a1, a1, 4
-; RV64M-NEXT: add a1, a1, a2
-; RV64M-NEXT: slli a2, a1, 1
-; RV64M-NEXT: slli a1, a1, 2
-; RV64M-NEXT: add a1, a1, a2
; RV64M-NEXT: sub a0, a0, a1
; RV64M-NEXT: andi a0, a0, 15
; RV64M-NEXT: addi a0, a0, -1
@@ -201,13 +201,13 @@ define i1 @test_srem_even(i4 %X) nounwind {
; RV32MV-NEXT: slli a1, a0, 28
; RV32MV-NEXT: srai a1, a1, 28
; RV32MV-NEXT: slli a2, a1, 1
+; RV32MV-NEXT: add a2, a2, a1
+; RV32MV-NEXT: srli a1, a1, 3
+; RV32MV-NEXT: srli a2, a2, 4
+; RV32MV-NEXT: sub a2, a2, a1
+; RV32MV-NEXT: slli a1, a2, 1
+; RV32MV-NEXT: slli a2, a2, 2
; RV32MV-NEXT: add a1, a2, a1
-; RV32MV-NEXT: srli a2, a1, 31
-; RV32MV-NEXT: srli a1, a1, 4
-; RV32MV-NEXT: add a1, a1, a2
-; RV32MV-NEXT: slli a2, a1, 1
-; RV32MV-NEXT: slli a1, a1, 2
-; RV32MV-NEXT: add a1, a1, a2
; RV32MV-NEXT: sub a0, a0, a1
; RV32MV-NEXT: andi a0, a0, 15
; RV32MV-NEXT: addi a0, a0, -1
@@ -219,13 +219,13 @@ define i1 @test_srem_even(i4 %X) nounwind {
; RV64MV-NEXT: slli a1, a0, 60
; RV64MV-NEXT: srai a1, a1, 60
; RV64MV-NEXT: slli a2, a1, 1
+; RV64MV-NEXT: add a2, a2, a1
+; RV64MV-NEXT: srli a1, a1, 3
+; RV64MV-NEXT: srli a2, a2, 4
+; RV64MV-NEXT: sub a2, a2, a1
+; RV64MV-NEXT: slli a1, a2, 1
+; RV64MV-NEXT: slli a2, a2, 2
; RV64MV-NEXT: add a1, a2, a1
-; RV64MV-NEXT: srli a2, a1, 63
-; RV64MV-NEXT: srli a1, a1, 4
-; RV64MV-NEXT: add a1, a1, a2
-; RV64MV-NEXT: slli a2, a1, 1
-; RV64MV-NEXT: slli a1, a1, 2
-; RV64MV-NEXT: add a1, a1, a2
; RV64MV-NEXT: sub a0, a0, a1
; RV64MV-NEXT: andi a0, a0, 15
; RV64MV-NEXT: addi a0, a0, -1
@@ -611,65 +611,65 @@ define void @test_srem_vec(ptr %X) nounwind {
; RV64M-NEXT: lwu a2, 8(a0)
; RV64M-NEXT: lbu a3, 12(a0)
; RV64M-NEXT: lui a4, %hi(.LCPI3_0)
-; RV64M-NEXT: lui a5, 699051
-; RV64M-NEXT: addi a5, a5, -1365
-; RV64M-NEXT: slli a6, a5, 32
-; RV64M-NEXT: add a5, a5, a6
-; RV64M-NEXT: srli a6, a1, 2
-; RV64M-NEXT: slli a7, a2, 62
-; RV64M-NEXT: or a6, a7, a6
-; RV64M-NEXT: lui a7, %hi(.LCPI3_1)
-; RV64M-NEXT: slli a3, a3, 32
-; RV64M-NEXT: or a2, a2, a3
-; RV64M-NEXT: lui a3, %hi(.LCPI3_2)
+; RV64M-NEXT: lui a5, %hi(.LCPI3_1)
+; RV64M-NEXT: lui a6, 699051
+; RV64M-NEXT: addi a6, a6, -1365
+; RV64M-NEXT: slli a7, a6, 32
+; RV64M-NEXT: add a6, a6, a7
+; RV64M-NEXT: slli a7, a1, 31
+; RV64M-NEXT: srai a7, a7, 31
+; RV64M-NEXT: mul a6, a7, a6
+; RV64M-NEXT: lui a7, %hi(.LCPI3_2)
; RV64M-NEXT: ld a4, %lo(.LCPI3_0)(a4)
-; RV64M-NEXT: ld a7, %lo(.LCPI3_1)(a7)
-; RV64M-NEXT: ld a3, %lo(.LCPI3_2)(a3)
-; RV64M-NEXT: slli a1, a1, 31
+; RV64M-NEXT: ld a5, %lo(.LCPI3_1)(a5)
+; RV64M-NEXT: ld a7, %lo(.LCPI3_2)(a7)
+; RV64M-NEXT: srli a1, a1, 2
+; RV64M-NEXT: slli a3, a3, 32
+; RV64M-NEXT: or a3, a2, a3
+; RV64M-NEXT: slli a2, a2, 62
+; RV64M-NEXT: or a1, a2, a1
+; RV64M-NEXT: srai a2, a2, 63
; RV64M-NEXT: srai a1, a1, 31
-; RV64M-NEXT: srai a6, a6, 31
-; RV64M-NEXT: slli a2, a2, 29
-; RV64M-NEXT: mul a1, a1, a5
-; RV64M-NEXT: srai a2, a2, 31
-; RV64M-NEXT: mulh a5, a6, a7
-; RV64M-NEXT: add a1, a1, a3
-; RV64M-NEXT: mulh a4, a2, a4
-; RV64M-NEXT: srli a7, a5, 63
+; RV64M-NEXT: slli a3, a3, 29
+; RV64M-NEXT: srai a3, a3, 31
+; RV64M-NEXT: mulh a5, a1, a5
+; RV64M-NEXT: add a6, a6, a7
+; RV64M-NEXT: mulh a4, a3, a4
; RV64M-NEXT: srai a5, a5, 1
-; RV64M-NEXT: add a5, a5, a7
-; RV64M-NEXT: slli a7, a1, 63
-; RV64M-NEXT: srli a1, a1, 1
-; RV64M-NEXT: or a1, a1, a7
-; RV64M-NEXT: srli a7, a4, 63
+; RV64M-NEXT: sub a5, a5, a2
+; RV64M-NEXT: slli a2, a6, 63
+; RV64M-NEXT: srli a6, a6, 1
+; RV64M-NEXT: or a2, a6, a2
+; RV64M-NEXT: srli a6, a4, 63
; RV64M-NEXT: srai a4, a4, 1
-; RV64M-NEXT: add a4, a4, a7
-; RV64M-NEXT: sltu a1, a3, a1
-; RV64M-NEXT: add a6, a6, a5
+; RV64M-NEXT: add a4, a4, a6
+; RV64M-NEXT: add a1, a1, a5
; RV64M-NEXT: slli a5, a5, 3
-; RV64M-NEXT: add a2, a2, a4
-; RV64M-NEXT: slli a4, a4, 2
-; RV64M-NEXT: sub a3, a6, a5
-; RV64M-NEXT: neg a1, a1
-; RV64M-NEXT: add a2, a2, a4
-; RV64M-NEXT: addi a3, a3, -1
-; RV64M-NEXT: slli a1, a1, 31
+; RV64M-NEXT: sltu a2, a7, a2
+; RV64M-NEXT: slli a6, a4, 2
+; RV64M-NEXT: add a3, a3, a4
+; RV64M-NEXT: sub a1, a1, a5
+; RV64M-NEXT: neg a2, a2
+; RV64M-NEXT: add a3, a3, a6
+; RV64M-NEXT: addi a1, a1, -1
+; RV64M-NEXT: slli a2, a2, 31
+; RV64M-NEXT: addi a3, a3, -2
+; RV64M-NEXT: seqz a1, a1
+; RV64M-NEXT: srli a2, a2, 31
; RV64M-NEXT: seqz a3, a3
-; RV64M-NEXT: addi a2, a2, -2
-; RV64M-NEXT: srli a1, a1, 31
-; RV64M-NEXT: seqz a2, a2
+; RV64M-NEXT: addi a1, a1, -1
; RV64M-NEXT: addi a3, a3, -1
-; RV64M-NEXT: addi a2, a2, -1
-; RV64M-NEXT: slli a4, a3, 33
-; RV64M-NEXT: slli a3, a3, 31
+; RV64M-NEXT: slli a4, a1, 33
+; RV64M-NEXT: slli a1, a1, 31
+; RV64M-NEXT: or a2, a2, a4
+; RV64M-NEXT: slli a4, a3, 2
+; RV64M-NEXT: srli a1, a1, 62
+; RV64M-NEXT: slli a3, a3, 29
; RV64M-NEXT: or a1, a1, a4
-; RV64M-NEXT: slli a4, a2, 2
-; RV64M-NEXT: srli a3, a3, 62
-; RV64M-NEXT: slli a2, a2, 29
-; RV64M-NEXT: or a3, a3, a4
-; RV64M-NEXT: srli a2, a2, 61
-; RV64M-NEXT: sd a1, 0(a0)
-; RV64M-NEXT: sw a3, 8(a0)
-; RV64M-NEXT: sb a2, 12(a0)
+; RV64M-NEXT: srli a3, a3, 61
+; RV64M-NEXT: sd a2, 0(a0)
+; RV64M-NEXT: sw a1, 8(a0)
+; RV64M-NEXT: sb a3, 12(a0)
; RV64M-NEXT: ret
;
; RV32MV-LABEL: test_srem_vec:
@@ -792,58 +792,58 @@ define void @test_srem_vec(ptr %X) nounwind {
;
; RV64MV-LABEL: test_srem_vec:
; RV64MV: # %bb.0:
-; RV64MV-NEXT: ld a1, 0(a0)
-; RV64MV-NEXT: lwu a2, 8(a0)
+; RV64MV-NEXT: ld a2, 0(a0)
+; RV64MV-NEXT: lwu a1, 8(a0)
; RV64MV-NEXT: lbu a3, 12(a0)
; RV64MV-NEXT: lui a4, %hi(.LCPI3_0)
-; RV64MV-NEXT: lui a5, %hi(.LCPI3_1)
-; RV64MV-NEXT: lui a6, %hi(.LCPI3_2)
-; RV64MV-NEXT: lui a7, 32
-; RV64MV-NEXT: ld a4, %lo(.LCPI3_0)(a4)
-; RV64MV-NEXT: ld a5, %lo(.LCPI3_1)(a5)
-; RV64MV-NEXT: ld a6, %lo(.LCPI3_2)(a6)
-; RV64MV-NEXT: addi a7, a7, 256
+; RV64MV-NEXT: lui a5, %hi(.LCPI3_2)
+; RV64MV-NEXT: lui a6, 32
+; RV64MV-NEXT: ld a5, %lo(.LCPI3_2)(a5)
+; RV64MV-NEXT: addi a6, a6, 256
; RV64MV-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; RV64MV-NEXT: vmv.s.x v10, a7
+; RV64MV-NEXT: vmv.s.x v10, a6
+; RV64MV-NEXT: slli a6, a2, 31
+; RV64MV-NEXT: srai a7, a6, 31
+; RV64MV-NEXT: srai a6, a6, 63
+; RV64MV-NEXT: mulh a5, a7, a5
+; RV64MV-NEXT: sub a5, a5, a6
+; RV64MV-NEXT: lui a6, %hi(.LCPI3_1)
+; RV64MV-NEXT: ld a4, %lo(.LCPI3_0)(a4)
+; RV64MV-NEXT: ld a6, %lo(.LCPI3_1)(a6)
+; RV64MV-NEXT: srli a2, a2, 2
; RV64MV-NEXT: slli a3, a3, 32
-; RV64MV-NEXT: srli a7, a1, 2
-; RV64MV-NEXT: or a3, a2, a3
-; RV64MV-NEXT: slli a2, a2, 62
-; RV64MV-NEXT: slli a1, a1, 31
-; RV64MV-NEXT: or a2, a2, a7
-; RV64MV-NEXT: srai a1, a1, 31
-; RV64MV-NEXT: slli a3, a3, 29
+; RV64MV-NEXT: or a3, a1, a3
+; RV64MV-NEXT: slli a1, a1, 62
+; RV64MV-NEXT: or a2, a1, a2
+; RV64MV-NEXT: srai a1, a1, 63
; RV64MV-NEXT: srai a2, a2, 31
-; RV64MV-NEXT: mulh a5, a1, a5
+; RV64MV-NEXT: slli a3, a3, 29
; RV64MV-NEXT: srai a3, a3, 31
-; RV64MV-NEXT: mulh a4, a2, a4
-; RV64MV-NEXT: srli a7, a5, 63
-; RV64MV-NEXT: add a5, a5, a7
-; RV64MV-NEXT: srli a7, a4, 63
-; RV64MV-NEXT: srai a4, a4, 1
-; RV64MV-NEXT: mulh a6, a3, a6
-; RV64MV-NEXT: add a4, a4, a7
-; RV64MV-NEXT: slli a7, a5, 1
-; RV64MV-NEXT: slli a5, a5, 2
-; RV64MV-NEXT: add a5, a5, a7
-; RV64MV-NEXT: srli a7, a6, 63
+; RV64MV-NEXT: mulh a6, a2, a6
+; RV64MV-NEXT: mulh a4, a3, a4
; RV64MV-NEXT: srai a6, a6, 1
-; RV64MV-NEXT: add a6, a6, a7
-; RV64MV-NEXT: add a2, a2, a4
-; RV64MV-NEXT: slli a4, a4, 3
-; RV64MV-NEXT: sub a2, a2, a4
-; RV64MV-NEXT: sub a1, a1, a5
-; RV64MV-NEXT: li a4, -1
-; RV64MV-NEXT: srli a4, a4, 31
+; RV64MV-NEXT: sub a1, a6, a1
+; RV64MV-NEXT: slli a6, a5, 1
+; RV64MV-NEXT: slli a5, a5, 2
+; RV64MV-NEXT: add a5, a5, a6
+; RV64MV-NEXT: srli a6, a4, 63
+; RV64MV-NEXT: srai a4, a4, 1
+; RV64MV-NEXT: add a4, a4, a6
+; RV64MV-NEXT: li a6, -1
+; RV64MV-NEXT: srli a6, a6, 31
; RV64MV-NEXT: vsext.vf8 v8, v10
-; RV64MV-NEXT: add a3, a3, a6
-; RV64MV-NEXT: slli a6, a6, 2
-; RV64MV-NEXT: vmv.v.x v10, a1
-; RV64MV-NEXT: add a3, a3, a6
+; RV64MV-NEXT: add a2, a2, a1
+; RV64MV-NEXT: slli a1, a1, 3
+; RV64MV-NEXT: sub a5, a7, a5
+; RV64MV-NEXT: slli a7, a4, 2
+; RV64MV-NEXT: add a3, a3, a4
+; RV64MV-NEXT: sub a2, a2, a1
+; RV64MV-NEXT: vmv.v.x v10, a5
+; RV64MV-NEXT: add a3, a3, a7
; RV64MV-NEXT: vslide1down.vx v10, v10, a2
; RV64MV-NEXT: vslide1down.vx v10, v10, a3
; RV64MV-NEXT: vslidedown.vi v10, v10, 1
-; RV64MV-NEXT: vand.vx v10, v10, a4
+; RV64MV-NEXT: vand.vx v10, v10, a6
; RV64MV-NEXT: vmsne.vv v0, v10, v8
; RV64MV-NEXT: vmv.v.i v8, 0
; RV64MV-NEXT: vmerge.vim v8, v8, -1, v0
@@ -852,7 +852,7 @@ define void @test_srem_vec(ptr %X) nounwind {
; RV64MV-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64MV-NEXT: vslidedown.vi v8, v8, 1
; RV64MV-NEXT: vmv.x.s a2, v10
-; RV64MV-NEXT: and a1, a1, a4
+; RV64MV-NEXT: and a1, a1, a6
; RV64MV-NEXT: vmv.x.s a3, v8
; RV64MV-NEXT: slli a4, a2, 31
; RV64MV-NEXT: slli a5, a3, 33
diff --git a/llvm/test/CodeGen/RISCV/srem-vector-lkk.ll b/llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
index 7548885f8405b..1d8457d919b6c 100644
--- a/llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
+++ b/llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
@@ -59,40 +59,40 @@ define <4 x i16> @fold_srem_vec_1(<4 x i16> %x) nounwind {
; RV32IM-NEXT: lh a1, 12(a1)
; RV32IM-NEXT: lui a5, 706409
; RV32IM-NEXT: lui a6, 507375
-; RV32IM-NEXT: lui a7, 342392
-; RV32IM-NEXT: lui t0, 780943
+; RV32IM-NEXT: lui a7, 780943
+; RV32IM-NEXT: lui t0, 342392
; RV32IM-NEXT: addi a5, a5, 389
; RV32IM-NEXT: addi a6, a6, 1981
-; RV32IM-NEXT: addi a7, a7, 669
-; RV32IM-NEXT: addi t0, t0, 1809
+; RV32IM-NEXT: addi a7, a7, 1809
+; RV32IM-NEXT: addi t0, t0, 669
; RV32IM-NEXT: mulh a5, a3, a5
; RV32IM-NEXT: mulh a6, a2, a6
-; RV32IM-NEXT: mulh a7, a4, a7
-; RV32IM-NEXT: mulh t0, a1, t0
-; RV32IM-NEXT: add a5, a5, a3
-; RV32IM-NEXT: sub a6, a6, a2
+; RV32IM-NEXT: mulh a7, a1, a7
+; RV32IM-NEXT: mulh t0, a4, t0
; RV32IM-NEXT: srli t1, a7, 31
-; RV32IM-NEXT: srli a7, a7, 5
+; RV32IM-NEXT: srli a7, a7, 8
; RV32IM-NEXT: add a7, a7, t1
-; RV32IM-NEXT: srli t1, t0, 31
-; RV32IM-NEXT: srli t0, t0, 8
-; RV32IM-NEXT: add t0, t0, t1
+; RV32IM-NEXT: srai t1, a4, 31
+; RV32IM-NEXT: add a5, a5, a3
+; RV32IM-NEXT: sub a6, a6, a2
+; RV32IM-NEXT: srli t0, t0, 5
+; RV32IM-NEXT: sub t0, t0, t1
; RV32IM-NEXT: srli t1, a5, 31
; RV32IM-NEXT: srli a5, a5, 6
; RV32IM-NEXT: add a5, a5, t1
; RV32IM-NEXT: srli t1, a6, 31
; RV32IM-NEXT: srli a6, a6, 6
; RV32IM-NEXT: add a6, a6, t1
-; RV32IM-NEXT: li t1, 98
-; RV32IM-NEXT: mul a7, a7, t1
; RV32IM-NEXT: li t1, -1003
+; RV32IM-NEXT: mul a7, a7, t1
+; RV32IM-NEXT: li t1, 98
; RV32IM-NEXT: mul t0, t0, t1
; RV32IM-NEXT: li t1, 95
; RV32IM-NEXT: mul a5, a5, t1
; RV32IM-NEXT: li t1, -124
; RV32IM-NEXT: mul a6, a6, t1
-; RV32IM-NEXT: sub a4, a4, a7
-; RV32IM-NEXT: sub a1, a1, t0
+; RV32IM-NEXT: sub a1, a1, a7
+; RV32IM-NEXT: sub a4, a4, t0
; RV32IM-NEXT: sub a3, a3, a5
; RV32IM-NEXT: sub a2, a2, a6
; RV32IM-NEXT: sh a3, 0(a0)
@@ -153,38 +153,38 @@ define <4 x i16> @fold_srem_vec_1(<4 x i16> %x) nounwind {
; RV64IM-NEXT: lui a6, %hi(.LCPI0_1)
; RV64IM-NEXT: lui a7, %hi(.LCPI0_2)
; RV64IM-NEXT: lui t0, %hi(.LCPI0_3)
+; RV64IM-NEXT: ld a7, %lo(.LCPI0_2)(a7)
; RV64IM-NEXT: ld a5, %lo(.LCPI0_0)(a5)
; RV64IM-NEXT: ld a6, %lo(.LCPI0_1)(a6)
-; RV64IM-NEXT: ld a7, %lo(.LCPI0_2)(a7)
; RV64IM-NEXT: ld t0, %lo(.LCPI0_3)(t0)
+; RV64IM-NEXT: mulh a7, a1, a7
+; RV64IM-NEXT: srli t1, a7, 63
+; RV64IM-NEXT: srli a7, a7, 7
+; RV64IM-NEXT: add a7, a7, t1
+; RV64IM-NEXT: srai t1, a4, 63
; RV64IM-NEXT: mulh a5, a3, a5
; RV64IM-NEXT: mulh a6, a2, a6
-; RV64IM-NEXT: mulh a7, a4, a7
-; RV64IM-NEXT: mulh t0, a1, t0
+; RV64IM-NEXT: mulh t0, a4, t0
; RV64IM-NEXT: add a5, a5, a3
; RV64IM-NEXT: sub a6, a6, a2
-; RV64IM-NEXT: srli t1, a7, 63
-; RV64IM-NEXT: srli a7, a7, 5
-; RV64IM-NEXT: add a7, a7, t1
-; RV64IM-NEXT: srli t1, t0, 63
-; RV64IM-NEXT: srli t0, t0, 7
-; RV64IM-NEXT: add t0, t0, t1
+; RV64IM-NEXT: srli t0, t0, 5
+; RV64IM-NEXT: sub t0, t0, t1
; RV64IM-NEXT: srli t1, a5, 63
; RV64IM-NEXT: srli a5, a5, 6
; RV64IM-NEXT: add a5, a5, t1
; RV64IM-NEXT: srli t1, a6, 63
; RV64IM-NEXT: srli a6, a6, 6
; RV64IM-NEXT: add a6, a6, t1
-; RV64IM-NEXT: li t1, 98
-; RV64IM-NEXT: mul a7, a7, t1
; RV64IM-NEXT: li t1, -1003
+; RV64IM-NEXT: mul a7, a7, t1
+; RV64IM-NEXT: li t1, 98
; RV64IM-NEXT: mul t0, t0, t1
; RV64IM-NEXT: li t1, 95
; RV64IM-NEXT: mul a5, a5, t1
; RV64IM-NEXT: li t1, -124
; RV64IM-NEXT: mul a6, a6, t1
-; RV64IM-NEXT: sub a4, a4, a7
-; RV64IM-NEXT: sub a1, a1, t0
+; RV64IM-NEXT: sub a1, a1, a7
+; RV64IM-NEXT: sub a4, a4, t0
; RV64IM-NEXT: sub a3, a3, a5
; RV64IM-NEXT: sub a2, a2, a6
; RV64IM-NEXT: sh a3, 0(a0)
@@ -815,11 +815,11 @@ define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) nounwind {
; RV32IM-NEXT: mulh a4, a2, a4
; RV32IM-NEXT: mulh a5, a3, a5
; RV32IM-NEXT: mulh a6, a1, a6
+; RV32IM-NEXT: srai a7, a1, 31
; RV32IM-NEXT: add a4, a4, a2
; RV32IM-NEXT: add a5, a5, a3
-; RV32IM-NEXT: srli a7, a6, 31
; RV32IM-NEXT: srli a6, a6, 11
-; RV32IM-NEXT: add a6, a6, a7
+; RV32IM-NEXT: sub a6, a6, a7
; RV32IM-NEXT: srli a7, a4, 31
; RV32IM-NEXT: srli a4, a4, 9
; RV32IM-NEXT: add a4, a4, a7
@@ -886,19 +886,19 @@ define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) nounwind {
; RV64IM-NEXT: lui a4, %hi(.LCPI4_0)
; RV64IM-NEXT: lui a5, %hi(.LCPI4_1)
; RV64IM-NEXT: lui a6, %hi(.LCPI4_2)
-; RV64IM-NEXT: ld a4, %lo(.LCPI4_0)(a4)
; RV64IM-NEXT: ld a5, %lo(.LCPI4_1)(a5)
+; RV64IM-NEXT: ld a4, %lo(.LCPI4_0)(a4)
; RV64IM-NEXT: ld a6, %lo(.LCPI4_2)(a6)
-; RV64IM-NEXT: mulh a4, a3, a4
+; RV64IM-NEXT: srai a7, a2, 63
; RV64IM-NEXT: mulh a5, a2, a5
+; RV64IM-NEXT: srli a5, a5, 8
+; RV64IM-NEXT: sub a5, a5, a7
+; RV64IM-NEXT: srai a7, a1, 63
+; RV64IM-NEXT: mulh a4, a3, a4
; RV64IM-NEXT: mulh a6, a1, a6
; RV64IM-NEXT: add a4, a4, a3
-; RV64IM-NEXT: srli a7, a5, 63
-; RV64IM-NEXT: srli a5, a5, 8
-; RV64IM-NEXT: add a5, a5, a7
-; RV64IM-NEXT: srli a7, a6, 63
; RV64IM-NEXT: srli a6, a6, 11
-; RV64IM-NEXT: add a6, a6, a7
+; RV64IM-NEXT: sub a6, a6, a7
; RV64IM-NEXT: srli a7, a4, 63
; RV64IM-NEXT: srli a4, a4, 4
; RV64IM-NEXT: add a4, a4, a7
@@ -971,9 +971,9 @@ define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) nounwind {
; RV32IM-NEXT: addi a5, a5, -2009
; RV32IM-NEXT: mulh a4, a3, a4
; RV32IM-NEXT: mulh a5, a1, a5
-; RV32IM-NEXT: srli a7, a5, 31
+; RV32IM-NEXT: srai a7, a1, 31
; RV32IM-NEXT: srli a5, a5, 11
-; RV32IM-NEXT: add a5, a5, a7
+; RV32IM-NEXT: sub a5, a5, a7
; RV32IM-NEXT: srli a7, a2, 17
; RV32IM-NEXT: add a4, a4, a3
; RV32IM-NEXT: add a7, a2, a7
@@ -1038,16 +1038,16 @@ define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) nounwind {
; RV64IM-NEXT: lh a1, 24(a1)
; RV64IM-NEXT: lui a4, %hi(.LCPI5_0)
; RV64IM-NEXT: lui a5, %hi(.LCPI5_1)
-; RV64IM-NEXT: ld a5, %lo(.LCPI5_1)(a5)
; RV64IM-NEXT: lui a6, 8
; RV64IM-NEXT: ld a4, %lo(.LCPI5_0)(a4)
+; RV64IM-NEXT: ld a5, %lo(.LCPI5_1)(a5)
; RV64IM-NEXT: srli a7, a2, 49
-; RV64IM-NEXT: mulh a5, a1, a5
; RV64IM-NEXT: add a7, a2, a7
; RV64IM-NEXT: and a6, a7, a6
-; RV64IM-NEXT: srli a7, a5, 63
+; RV64IM-NEXT: srai a7, a1, 63
+; RV64IM-NEXT: mulh a5, a1, a5
; RV64IM-NEXT: srli a5, a5, 11
-; RV64IM-NEXT: add a5, a5, a7
+; RV64IM-NEXT: sub a5, a5, a7
; RV64IM-NEXT: mulh a4, a3, a4
; RV64IM-NEXT: add a4, a4, a3
; RV64IM-NEXT: sub a2, a2, a6
@@ -1256,19 +1256,19 @@ define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) nounwind {
; RV64IM-NEXT: lui a4, %hi(.LCPI6_0)
; RV64IM-NEXT: lui a5, %hi(.LCPI6_1)
; RV64IM-NEXT: lui a6, %hi(.LCPI6_2)
-; RV64IM-NEXT: ld a4, %lo(.LCPI6_0)(a4)
; RV64IM-NEXT: ld a5, %lo(.LCPI6_1)(a5)
+; RV64IM-NEXT: ld a4, %lo(.LCPI6_0)(a4)
; RV64IM-NEXT: ld a6, %lo(.LCPI6_2)(a6)
-; RV64IM-NEXT: mulh a4, a3, a4
+; RV64IM-NEXT: srai a7, a2, 63
; RV64IM-NEXT: mulh a5, a2, a5
+; RV64IM-NEXT: srai a5, a5, 8
+; RV64IM-NEXT: sub a5, a5, a7
+; RV64IM-NEXT: srai a7, a1, 63
+; RV64IM-NEXT: mulh a4, a3, a4
; RV64IM-NEXT: mulh a6, a1, a6
; RV64IM-NEXT: add a4, a4, a3
-; RV64IM-NEXT: srli a7, a5, 63
-; RV64IM-NEXT: srai a5, a5, 8
-; RV64IM-NEXT: add a5, a5, a7
-; RV64IM-NEXT: srli a7, a6, 63
; RV64IM-NEXT: srai a6, a6, 11
-; RV64IM-NEXT: add a6, a6, a7
+; RV64IM-NEXT: sub a6, a6, a7
; RV64IM-NEXT: srli a7, a4, 63
; RV64IM-NEXT: srai a4, a4, 4
; RV64IM-NEXT: add a4, a4, a7
diff --git a/llvm/test/CodeGen/SPARC/predictable-select.ll b/llvm/test/CodeGen/SPARC/predictable-select.ll
index cf200a121d0f1..137c853790a84 100644
--- a/llvm/test/CodeGen/SPARC/predictable-select.ll
+++ b/llvm/test/CodeGen/SPARC/predictable-select.ll
@@ -20,11 +20,11 @@ define i32 @cdiv(i32 %cond, i32 %num) #0 {
; SPARC-NEXT: .LBB0_2: ! %select.true.sink
; SPARC-NEXT: sethi 1398101, %o1
; SPARC-NEXT: or %o1, 342, %o1
-; SPARC-NEXT: smul %o0, %o1, %o0
-; SPARC-NEXT: rd %y, %o0
-; SPARC-NEXT: srl %o0, 31, %o1
+; SPARC-NEXT: smul %o0, %o1, %o1
+; SPARC-NEXT: rd %y, %o1
+; SPARC-NEXT: sra %o0, 31, %o0
; SPARC-NEXT: retl
-; SPARC-NEXT: add %o0, %o1, %o0
+; SPARC-NEXT: sub %o1, %o0, %o0
;
; SPARC64-LABEL: cdiv:
; SPARC64: ! %bb.0: ! %entry
@@ -35,14 +35,14 @@ define i32 @cdiv(i32 %cond, i32 %num) #0 {
; SPARC64-NEXT: retl
; SPARC64-NEXT: nop
; SPARC64-NEXT: .LBB0_2: ! %select.true.sink
-; SPARC64-NEXT: sra %o0, 0, %o0
-; SPARC64-NEXT: sethi 1398101, %o1
-; SPARC64-NEXT: or %o1, 342, %o1
-; SPARC64-NEXT: mulx %o0, %o1, %o0
-; SPARC64-NEXT: srlx %o0, 63, %o1
-; SPARC64-NEXT: srlx %o0, 32, %o0
+; SPARC64-NEXT: sra %o0, 0, %o1
+; SPARC64-NEXT: sethi 1398101, %o2
+; SPARC64-NEXT: or %o2, 342, %o2
+; SPARC64-NEXT: mulx %o1, %o2, %o1
+; SPARC64-NEXT: srlx %o1, 32, %o1
+; SPARC64-NEXT: sra %o0, 31, %o0
; SPARC64-NEXT: retl
-; SPARC64-NEXT: add %o0, %o1, %o0
+; SPARC64-NEXT: sub %o1, %o0, %o0
;
; SPARC-NO-PREDICTOR-LABEL: cdiv:
; SPARC-NO-PREDICTOR: ! %bb.0: ! %entry
@@ -50,8 +50,8 @@ define i32 @cdiv(i32 %cond, i32 %num) #0 {
; SPARC-NO-PREDICTOR-NEXT: or %o2, 342, %o2
; SPARC-NO-PREDICTOR-NEXT: smul %o1, %o2, %o2
; SPARC-NO-PREDICTOR-NEXT: rd %y, %o2
-; SPARC-NO-PREDICTOR-NEXT: srl %o2, 31, %o3
-; SPARC-NO-PREDICTOR-NEXT: add %o2, %o3, %o2
+; SPARC-NO-PREDICTOR-NEXT: sra %o1, 31, %o3
+; SPARC-NO-PREDICTOR-NEXT: sub %o2, %o3, %o2
; SPARC-NO-PREDICTOR-NEXT: cmp %o0, 0
; SPARC-NO-PREDICTOR-NEXT: move %icc, %o2, %o1
; SPARC-NO-PREDICTOR-NEXT: retl
@@ -63,9 +63,9 @@ define i32 @cdiv(i32 %cond, i32 %num) #0 {
; SPARC64-NO-PREDICTOR-NEXT: sethi 1398101, %o3
; SPARC64-NO-PREDICTOR-NEXT: or %o3, 342, %o3
; SPARC64-NO-PREDICTOR-NEXT: mulx %o2, %o3, %o2
-; SPARC64-NO-PREDICTOR-NEXT: srlx %o2, 63, %o3
; SPARC64-NO-PREDICTOR-NEXT: srlx %o2, 32, %o2
-; SPARC64-NO-PREDICTOR-NEXT: add %o2, %o3, %o2
+; SPARC64-NO-PREDICTOR-NEXT: sra %o1, 31, %o3
+; SPARC64-NO-PREDICTOR-NEXT: sub %o2, %o3, %o2
; SPARC64-NO-PREDICTOR-NEXT: cmp %o0, 0
; SPARC64-NO-PREDICTOR-NEXT: move %icc, %o2, %o1
; SPARC64-NO-PREDICTOR-NEXT: retl
diff --git a/llvm/test/CodeGen/SystemZ/int-div-06.ll b/llvm/test/CodeGen/SystemZ/int-div-06.ll
index 9de717857d7d9..55a9292da4fb9 100644
--- a/llvm/test/CodeGen/SystemZ/int-div-06.ll
+++ b/llvm/test/CodeGen/SystemZ/int-div-06.ll
@@ -6,10 +6,11 @@
define i32 @f1(i32 %a) {
; CHECK-LABEL: f1:
; CHECK: lgfr [[REG:%r[0-5]]], %r2
+; CHECK: sra %r2, 31
; CHECK: msgfi [[REG]], 502748801
-; CHECK-DAG: srlg [[RES1:%r[0-5]]], [[REG]], 63
-; CHECK-DAG: srag %r2, [[REG]], 46
-; CHECK: ar %r2, [[RES1]]
+; CHECK: srag [[REG]], [[REG]], 46
+; CHECK: sr [[REG]], %r2
+; CHECK: lr %r2, [[REG]]
; CHECK: br %r14
%b = sdiv i32 %a, 139968
ret i32 %b
@@ -31,13 +32,13 @@ define i64 @f3(i64 %dummy, i64 %a) {
; CHECK-LABEL: f3:
; CHECK-DAG: llihf [[CONST:%r[0-5]]], 1005497601
; CHECK-DAG: oilf [[CONST]], 4251762321
-; CHECK-DAG: srag [[REG:%r[0-5]]], %r3, 63
-; CHECK-DAG: ngr [[REG]], [[CONST]]
+; CHECK-DAG: srag [[SIGN:%r[0-5]]], %r3, 63
+; CHECK-DAG: lgr [[TMP:%r[0-5]]], [[SIGN]]
+; CHECK-DAG: ngr [[TMP]], [[CONST]]
; CHECK-DAG: mlgr %r2, [[CONST]]
-; CHECK: sgr %r2, [[REG]]
-; CHECK: srlg [[RES1:%r[0-5]]], %r2, 63
+; CHECK: sgr %r2, [[TMP]]
; CHECK: srag %r2, %r2, 15
-; CHECK: agr %r2, [[RES1]]
+; CHECK: sgr %r2, [[SIGN]]
; CHECK: br %r14
%b = sdiv i64 %a, 139968
ret i64 %b
diff --git a/llvm/test/CodeGen/Thumb/srem-seteq-illegal-types.ll b/llvm/test/CodeGen/Thumb/srem-seteq-illegal-types.ll
index 00eed6483cc12..032259f6d7c9f 100644
--- a/llvm/test/CodeGen/Thumb/srem-seteq-illegal-types.ll
+++ b/llvm/test/CodeGen/Thumb/srem-seteq-illegal-types.ll
@@ -37,9 +37,9 @@ define i1 @test_srem_even(i4 %X) nounwind {
; CHECK-NEXT: asrs r1, r1, #28
; CHECK-NEXT: movs r2, #3
; CHECK-NEXT: muls r2, r1, r2
-; CHECK-NEXT: lsrs r1, r2, #31
; CHECK-NEXT: lsrs r2, r2, #4
-; CHECK-NEXT: adds r1, r2, r1
+; CHECK-NEXT: lsrs r1, r1, #3
+; CHECK-NEXT: subs r1, r2, r1
; CHECK-NEXT: movs r2, #6
; CHECK-NEXT: muls r2, r1, r2
; CHECK-NEXT: subs r0, r0, r2
diff --git a/llvm/test/CodeGen/Thumb2/srem-seteq-illegal-types.ll b/llvm/test/CodeGen/Thumb2/srem-seteq-illegal-types.ll
index 304605d1e9be2..5bdb8d90e7a10 100644
--- a/llvm/test/CodeGen/Thumb2/srem-seteq-illegal-types.ll
+++ b/llvm/test/CodeGen/Thumb2/srem-seteq-illegal-types.ll
@@ -26,9 +26,9 @@ define i1 @test_srem_even(i4 %X) nounwind {
; CHECK-LABEL: test_srem_even:
; CHECK: @ %bb.0:
; CHECK-NEXT: sbfx r1, r0, #0, #4
-; CHECK-NEXT: add.w r1, r1, r1, lsl #1
-; CHECK-NEXT: lsrs r2, r1, #4
-; CHECK-NEXT: add.w r1, r2, r1, lsr #31
+; CHECK-NEXT: add.w r2, r1, r1, lsl #1
+; CHECK-NEXT: lsrs r2, r2, #4
+; CHECK-NEXT: sub.w r1, r2, r1, lsr #3
; CHECK-NEXT: add.w r1, r1, r1, lsl #1
; CHECK-NEXT: sub.w r0, r0, r1, lsl #1
; CHECK-NEXT: and r0, r0, #15
diff --git a/llvm/test/CodeGen/VE/Scalar/div.ll b/llvm/test/CodeGen/VE/Scalar/div.ll
index 64caf8a835468..9ecb9bf9932a5 100644
--- a/llvm/test/CodeGen/VE/Scalar/div.ll
+++ b/llvm/test/CodeGen/VE/Scalar/div.ll
@@ -150,10 +150,10 @@ define signext i32 @divi32ri(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: divi32ri:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 1431655766
-; CHECK-NEXT: muls.l %s0, %s0, %s1
-; CHECK-NEXT: srl %s1, %s0, 63
-; CHECK-NEXT: srl %s0, %s0, 32
-; CHECK-NEXT: adds.w.sx %s0, %s0, %s1
+; CHECK-NEXT: muls.l %s1, %s0, %s1
+; CHECK-NEXT: srl %s1, %s1, 32
+; CHECK-NEXT: sra.w.sx %s0, %s0, 31
+; CHECK-NEXT: subs.w.sx %s0, %s1, %s0
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%r = sdiv i32 %a, 3
diff --git a/llvm/test/CodeGen/VE/Scalar/rem.ll b/llvm/test/CodeGen/VE/Scalar/rem.ll
index 9911405c6a68d..f69cbb2dd3eaf 100644
--- a/llvm/test/CodeGen/VE/Scalar/rem.ll
+++ b/llvm/test/CodeGen/VE/Scalar/rem.ll
@@ -167,9 +167,9 @@ define signext i32 @remi32ri(i32 signext %a) {
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 1431655766
; CHECK-NEXT: muls.l %s1, %s0, %s1
-; CHECK-NEXT: srl %s2, %s1, 63
; CHECK-NEXT: srl %s1, %s1, 32
-; CHECK-NEXT: adds.w.sx %s1, %s1, %s2
+; CHECK-NEXT: sra.w.sx %s2, %s0, 31
+; CHECK-NEXT: subs.w.sx %s1, %s1, %s2
; CHECK-NEXT: muls.w.sx %s1, 3, %s1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
diff --git a/llvm/test/CodeGen/X86/bypass-slow-division-32.ll b/llvm/test/CodeGen/X86/bypass-slow-division-32.ll
index fe4201d9a2f73..768dae3ab528f 100644
--- a/llvm/test/CodeGen/X86/bypass-slow-division-32.ll
+++ b/llvm/test/CodeGen/X86/bypass-slow-division-32.ll
@@ -108,7 +108,7 @@ define i32 @Test_use_div_and_idiv(i32 %a, i32 %b) nounwind {
; CHECK-NEXT: movzbl %cl, %eax
; CHECK-NEXT: divb %bl
; CHECK-NEXT: movzbl %al, %eax
-; CHECK-NEXT: .LBB3_6:
+; CHECK-NEXT: .LBB3_6: # %.split.split
; CHECK-NEXT: addl %eax, %esi
; CHECK-NEXT: movl %esi, %eax
; CHECK-NEXT: popl %esi
@@ -133,12 +133,14 @@ define i32 @Test_use_div_imm_imm() nounwind {
define i32 @Test_use_div_reg_imm(i32 %a) nounwind {
; CHECK-LABEL: Test_use_div_reg_imm:
; CHECK: # %bb.0:
-; CHECK-NEXT: movl $1041204193, %eax # imm = 0x3E0F83E1
-; CHECK-NEXT: imull {{[0-9]+}}(%esp)
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT: movl $1041204193, %edx # imm = 0x3E0F83E1
+; CHECK-NEXT: movl %ecx, %eax
+; CHECK-NEXT: imull %edx
; CHECK-NEXT: movl %edx, %eax
-; CHECK-NEXT: shrl $31, %eax
-; CHECK-NEXT: sarl $3, %edx
-; CHECK-NEXT: addl %edx, %eax
+; CHECK-NEXT: sarl $3, %eax
+; CHECK-NEXT: sarl $31, %ecx
+; CHECK-NEXT: subl %ecx, %eax
; CHECK-NEXT: retl
%resultdiv = sdiv i32 %a, 33
ret i32 %resultdiv
@@ -151,10 +153,10 @@ define i32 @Test_use_rem_reg_imm(i32 %a) nounwind {
; CHECK-NEXT: movl $1041204193, %edx # imm = 0x3E0F83E1
; CHECK-NEXT: movl %ecx, %eax
; CHECK-NEXT: imull %edx
-; CHECK-NEXT: movl %edx, %eax
-; CHECK-NEXT: shrl $31, %eax
; CHECK-NEXT: sarl $3, %edx
-; CHECK-NEXT: addl %eax, %edx
+; CHECK-NEXT: movl %ecx, %eax
+; CHECK-NEXT: sarl $31, %eax
+; CHECK-NEXT: subl %eax, %edx
; CHECK-NEXT: movl %edx, %eax
; CHECK-NEXT: shll $5, %eax
; CHECK-NEXT: addl %edx, %eax
@@ -172,15 +174,15 @@ define i32 @Test_use_divrem_reg_imm(i32 %a) nounwind {
; CHECK-NEXT: movl $1041204193, %edx # imm = 0x3E0F83E1
; CHECK-NEXT: movl %ecx, %eax
; CHECK-NEXT: imull %edx
-; CHECK-NEXT: movl %edx, %eax
-; CHECK-NEXT: shrl $31, %eax
; CHECK-NEXT: sarl $3, %edx
+; CHECK-NEXT: movl %ecx, %eax
+; CHECK-NEXT: sarl $31, %eax
+; CHECK-NEXT: subl %eax, %edx
+; CHECK-NEXT: movl %edx, %eax
+; CHECK-NEXT: shll $5, %eax
; CHECK-NEXT: addl %edx, %eax
-; CHECK-NEXT: movl %eax, %edx
-; CHECK-NEXT: shll $5, %edx
-; CHECK-NEXT: addl %eax, %edx
-; CHECK-NEXT: subl %edx, %ecx
-; CHECK-NEXT: addl %eax, %ecx
+; CHECK-NEXT: subl %eax, %ecx
+; CHECK-NEXT: addl %edx, %ecx
; CHECK-NEXT: movl %ecx, %eax
; CHECK-NEXT: retl
%resultdiv = sdiv i32 %a, 33
diff --git a/llvm/test/CodeGen/X86/divide-by-constant.ll b/llvm/test/CodeGen/X86/divide-by-constant.ll
index e0bff50e2e2dd..eb6468edc5502 100644
--- a/llvm/test/CodeGen/X86/divide-by-constant.ll
+++ b/llvm/test/CodeGen/X86/divide-by-constant.ll
@@ -67,22 +67,20 @@ entry:
define signext i16 @test4(i16 signext %x) nounwind {
; X86-LABEL: test4:
; X86: # %bb.0: # %entry
-; X86-NEXT: movswl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: imull $1986, %eax, %eax # imm = 0x7C2
-; X86-NEXT: movl %eax, %ecx
-; X86-NEXT: shrl $31, %ecx
+; X86-NEXT: movswl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: imull $1986, %ecx, %eax # imm = 0x7C2
+; X86-NEXT: sarl $15, %ecx
; X86-NEXT: shrl $16, %eax
-; X86-NEXT: addl %ecx, %eax
+; X86-NEXT: subl %ecx, %eax
; X86-NEXT: # kill: def $ax killed $ax killed $eax
; X86-NEXT: retl
;
; X64-LABEL: test4:
; X64: # %bb.0: # %entry
; X64-NEXT: imull $1986, %edi, %eax # imm = 0x7C2
-; X64-NEXT: movl %eax, %ecx
-; X64-NEXT: shrl $31, %ecx
+; X64-NEXT: sarl $15, %edi
; X64-NEXT: shrl $16, %eax
-; X64-NEXT: addl %ecx, %eax
+; X64-NEXT: subl %edi, %eax
; X64-NEXT: # kill: def $ax killed $ax killed $eax
; X64-NEXT: retq
entry:
@@ -113,22 +111,20 @@ define i32 @test5(i32 %A) nounwind {
define signext i16 @test6(i16 signext %x) nounwind {
; X86-LABEL: test6:
; X86: # %bb.0: # %entry
-; X86-NEXT: movswl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: imull $26215, %eax, %eax # imm = 0x6667
-; X86-NEXT: movl %eax, %ecx
-; X86-NEXT: shrl $31, %ecx
+; X86-NEXT: movswl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: imull $26215, %ecx, %eax # imm = 0x6667
+; X86-NEXT: sarl $15, %ecx
; X86-NEXT: sarl $18, %eax
-; X86-NEXT: addl %ecx, %eax
+; X86-NEXT: subl %ecx, %eax
; X86-NEXT: # kill: def $ax killed $ax killed $eax
; X86-NEXT: retl
;
; X64-LABEL: test6:
; X64: # %bb.0: # %entry
; X64-NEXT: imull $26215, %edi, %eax # imm = 0x6667
-; X64-NEXT: movl %eax, %ecx
-; X64-NEXT: shrl $31, %ecx
+; X64-NEXT: sarl $15, %edi
; X64-NEXT: sarl $18, %eax
-; X64-NEXT: addl %ecx, %eax
+; X64-NEXT: subl %edi, %eax
; X64-NEXT: # kill: def $ax killed $ax killed $eax
; X64-NEXT: retq
entry:
@@ -463,9 +459,10 @@ define { i64, i32 } @PR38622_signed(i64) nounwind {
; X64-NEXT: movq %rdi, %rax
; X64-NEXT: imulq %rcx
; X64-NEXT: movq %rdx, %rax
-; X64-NEXT: shrq $63, %rax
-; X64-NEXT: sarq $28, %rdx
-; X64-NEXT: addq %rdx, %rax
+; X64-NEXT: sarq $28, %rax
+; X64-NEXT: movq %rdi, %rcx
+; X64-NEXT: sarq $63, %rcx
+; X64-NEXT: subq %rcx, %rax
; X64-NEXT: imull $-294967296, %eax, %ecx # imm = 0xEE6B2800
; X64-NEXT: subl %ecx, %edi
; X64-NEXT: movl %edi, %edx
diff --git a/llvm/test/CodeGen/X86/freeze-binary.ll b/llvm/test/CodeGen/X86/freeze-binary.ll
index 7201ca47d8588..6f185dc2d42b0 100644
--- a/llvm/test/CodeGen/X86/freeze-binary.ll
+++ b/llvm/test/CodeGen/X86/freeze-binary.ll
@@ -999,30 +999,34 @@ define i32 @freeze_ucmp(i32 %a0) nounwind {
define void @pr59676_frozen(ptr %dst, i32 %x.orig) {
; X86-LABEL: pr59676_frozen:
; X86: # %bb.0:
-; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: pushl %esi
+; X86-NEXT: .cfi_def_cfa_offset 8
+; X86-NEXT: .cfi_offset %esi, -8
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: imull %eax, %eax
-; X86-NEXT: imull $84, %eax, %eax
+; X86-NEXT: imull $84, %eax, %ecx
; X86-NEXT: movl $818089009, %edx # imm = 0x30C30C31
+; X86-NEXT: movl %ecx, %eax
; X86-NEXT: imull %edx
-; X86-NEXT: movl %edx, %eax
-; X86-NEXT: shrl $31, %eax
; X86-NEXT: sarl $3, %edx
-; X86-NEXT: addl %eax, %edx
-; X86-NEXT: movl %edx, (%ecx)
+; X86-NEXT: sarl $31, %ecx
+; X86-NEXT: subl %ecx, %edx
+; X86-NEXT: movl %edx, (%esi)
+; X86-NEXT: popl %esi
+; X86-NEXT: .cfi_def_cfa_offset 4
; X86-NEXT: retl
;
; X64-LABEL: pr59676_frozen:
; X64: # %bb.0:
; X64-NEXT: imull %esi, %esi
; X64-NEXT: imull $84, %esi, %eax
-; X64-NEXT: cltq
-; X64-NEXT: imulq $818089009, %rax, %rax # imm = 0x30C30C31
-; X64-NEXT: movq %rax, %rcx
-; X64-NEXT: shrq $63, %rcx
-; X64-NEXT: sarq $35, %rax
-; X64-NEXT: addl %ecx, %eax
-; X64-NEXT: movl %eax, (%rdi)
+; X64-NEXT: movslq %eax, %rcx
+; X64-NEXT: sarl $31, %eax
+; X64-NEXT: imulq $818089009, %rcx, %rcx # imm = 0x30C30C31
+; X64-NEXT: sarq $35, %rcx
+; X64-NEXT: subl %eax, %ecx
+; X64-NEXT: movl %ecx, (%rdi)
; X64-NEXT: retq
%x = freeze i32 %x.orig
%mul = mul i32 %x, 42
@@ -1037,30 +1041,34 @@ define void @pr59676_frozen(ptr %dst, i32 %x.orig) {
define void @pr59676_nsw_frozen(ptr %dst, i32 %x.orig) {
; X86-LABEL: pr59676_nsw_frozen:
; X86: # %bb.0:
-; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: pushl %esi
+; X86-NEXT: .cfi_def_cfa_offset 8
+; X86-NEXT: .cfi_offset %esi, -8
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: imull %eax, %eax
-; X86-NEXT: imull $84, %eax, %eax
+; X86-NEXT: imull $84, %eax, %ecx
; X86-NEXT: movl $818089009, %edx # imm = 0x30C30C31
+; X86-NEXT: movl %ecx, %eax
; X86-NEXT: imull %edx
-; X86-NEXT: movl %edx, %eax
-; X86-NEXT: shrl $31, %eax
; X86-NEXT: sarl $3, %edx
-; X86-NEXT: addl %eax, %edx
-; X86-NEXT: movl %edx, (%ecx)
+; X86-NEXT: sarl $31, %ecx
+; X86-NEXT: subl %ecx, %edx
+; X86-NEXT: movl %edx, (%esi)
+; X86-NEXT: popl %esi
+; X86-NEXT: .cfi_def_cfa_offset 4
; X86-NEXT: retl
;
; X64-LABEL: pr59676_nsw_frozen:
; X64: # %bb.0:
; X64-NEXT: imull %esi, %esi
; X64-NEXT: imull $84, %esi, %eax
-; X64-NEXT: cltq
-; X64-NEXT: imulq $818089009, %rax, %rax # imm = 0x30C30C31
-; X64-NEXT: movq %rax, %rcx
-; X64-NEXT: shrq $63, %rcx
-; X64-NEXT: sarq $35, %rax
-; X64-NEXT: addl %ecx, %eax
-; X64-NEXT: movl %eax, (%rdi)
+; X64-NEXT: movslq %eax, %rcx
+; X64-NEXT: sarl $31, %eax
+; X64-NEXT: imulq $818089009, %rcx, %rcx # imm = 0x30C30C31
+; X64-NEXT: sarq $35, %rcx
+; X64-NEXT: subl %eax, %ecx
+; X64-NEXT: movl %ecx, (%rdi)
; X64-NEXT: retq
%x = freeze i32 %x.orig
%mul = mul nsw i32 %x, 42
@@ -1075,30 +1083,34 @@ define void @pr59676_nsw_frozen(ptr %dst, i32 %x.orig) {
define void @pr59676_nsw(ptr %dst, i32 %x) {
; X86-LABEL: pr59676_nsw:
; X86: # %bb.0:
+; X86-NEXT: pushl %esi
+; X86-NEXT: .cfi_def_cfa_offset 8
+; X86-NEXT: .cfi_offset %esi, -8
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: imull %eax, %eax
-; X86-NEXT: imull $84, %eax, %eax
+; X86-NEXT: imull $84, %eax, %ecx
; X86-NEXT: movl $818089009, %edx # imm = 0x30C30C31
+; X86-NEXT: movl %ecx, %eax
; X86-NEXT: imull %edx
-; X86-NEXT: movl %edx, %eax
-; X86-NEXT: shrl $31, %eax
; X86-NEXT: sarl $3, %edx
-; X86-NEXT: addl %eax, %edx
-; X86-NEXT: movl %edx, (%ecx)
+; X86-NEXT: sarl $31, %ecx
+; X86-NEXT: subl %ecx, %edx
+; X86-NEXT: movl %edx, (%esi)
+; X86-NEXT: popl %esi
+; X86-NEXT: .cfi_def_cfa_offset 4
; X86-NEXT: retl
;
; X64-LABEL: pr59676_nsw:
; X64: # %bb.0:
; X64-NEXT: imull %esi, %esi
; X64-NEXT: imull $84, %esi, %eax
-; X64-NEXT: cltq
-; X64-NEXT: imulq $818089009, %rax, %rax # imm = 0x30C30C31
-; X64-NEXT: movq %rax, %rcx
-; X64-NEXT: shrq $63, %rcx
-; X64-NEXT: sarq $35, %rax
-; X64-NEXT: addl %ecx, %eax
-; X64-NEXT: movl %eax, (%rdi)
+; X64-NEXT: movslq %eax, %rcx
+; X64-NEXT: sarl $31, %eax
+; X64-NEXT: imulq $818089009, %rcx, %rcx # imm = 0x30C30C31
+; X64-NEXT: sarq $35, %rcx
+; X64-NEXT: subl %eax, %ecx
+; X64-NEXT: movl %ecx, (%rdi)
; X64-NEXT: retq
%mul = mul nsw i32 %x, 42
%shl = shl i32 %x, 1
diff --git a/llvm/test/CodeGen/X86/load-scalar-as-vector.ll b/llvm/test/CodeGen/X86/load-scalar-as-vector.ll
index d2359ced3e19d..80af3fd5b4023 100644
--- a/llvm/test/CodeGen/X86/load-scalar-as-vector.ll
+++ b/llvm/test/CodeGen/X86/load-scalar-as-vector.ll
@@ -415,12 +415,12 @@ define <4 x i32> @srem_op1_constant(ptr %p) nounwind {
; SSE-LABEL: srem_op1_constant:
; SSE: # %bb.0:
; SSE-NEXT: movslq (%rdi), %rax
-; SSE-NEXT: imulq $818089009, %rax, %rcx # imm = 0x30C30C31
-; SSE-NEXT: movq %rcx, %rdx
-; SSE-NEXT: shrq $63, %rdx
-; SSE-NEXT: sarq $35, %rcx
-; SSE-NEXT: addl %edx, %ecx
-; SSE-NEXT: imull $42, %ecx, %ecx
+; SSE-NEXT: movl %eax, %ecx
+; SSE-NEXT: sarl $31, %ecx
+; SSE-NEXT: imulq $818089009, %rax, %rdx # imm = 0x30C30C31
+; SSE-NEXT: sarq $35, %rdx
+; SSE-NEXT: subl %ecx, %edx
+; SSE-NEXT: imull $42, %edx, %ecx
; SSE-NEXT: subl %ecx, %eax
; SSE-NEXT: movd %eax, %xmm0
; SSE-NEXT: retq
@@ -428,12 +428,12 @@ define <4 x i32> @srem_op1_constant(ptr %p) nounwind {
; AVX-LABEL: srem_op1_constant:
; AVX: # %bb.0:
; AVX-NEXT: movslq (%rdi), %rax
-; AVX-NEXT: imulq $818089009, %rax, %rcx # imm = 0x30C30C31
-; AVX-NEXT: movq %rcx, %rdx
-; AVX-NEXT: shrq $63, %rdx
-; AVX-NEXT: sarq $35, %rcx
-; AVX-NEXT: addl %edx, %ecx
-; AVX-NEXT: imull $42, %ecx, %ecx
+; AVX-NEXT: movl %eax, %ecx
+; AVX-NEXT: sarl $31, %ecx
+; AVX-NEXT: imulq $818089009, %rax, %rdx # imm = 0x30C30C31
+; AVX-NEXT: sarq $35, %rdx
+; AVX-NEXT: subl %ecx, %edx
+; AVX-NEXT: imull $42, %edx, %ecx
; AVX-NEXT: subl %ecx, %eax
; AVX-NEXT: vmovd %eax, %xmm0
; AVX-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/pr14088.ll b/llvm/test/CodeGen/X86/pr14088.ll
index 83bf13280f94a..9d414c6b0b714 100644
--- a/llvm/test/CodeGen/X86/pr14088.ll
+++ b/llvm/test/CodeGen/X86/pr14088.ll
@@ -18,20 +18,19 @@ define i32 @f(i1 %foo, ptr %tm_year2, ptr %bar, i16 %zed, i32 %zed2) {
; CHECK-NEXT: jne .LBB0_2
; CHECK-NEXT: # %bb.1: # %if.end
; CHECK-NEXT: movslq %r8d, %rax
+; CHECK-NEXT: sarl $31, %r8d
; CHECK-NEXT: imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
-; CHECK-NEXT: movq %rcx, %rdi
-; CHECK-NEXT: shrq $63, %rdi
; CHECK-NEXT: sarq $37, %rcx
-; CHECK-NEXT: addl %edi, %ecx
+; CHECK-NEXT: subl %r8d, %ecx
; CHECK-NEXT: imull $100, %ecx, %ecx
; CHECK-NEXT: subl %ecx, %eax
; CHECK-NEXT: movw %ax, (%rsi)
+; CHECK-NEXT: movswl %ax, %ecx
+; CHECK-NEXT: sarl $15, %ecx
; CHECK-NEXT: movswq %ax, %rax
; CHECK-NEXT: imulq $1717986919, %rax, %rax # imm = 0x66666667
-; CHECK-NEXT: movq %rax, %rcx
-; CHECK-NEXT: shrq $63, %rcx
; CHECK-NEXT: shrq $34, %rax
-; CHECK-NEXT: addl %ecx, %eax
+; CHECK-NEXT: subl %ecx, %eax
; CHECK-NEXT: movb %al, (%rdx)
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: .LBB0_2: # %return
diff --git a/llvm/test/CodeGen/X86/pr34080-2.ll b/llvm/test/CodeGen/X86/pr34080-2.ll
index 279373a7aab3f..71c572a8b57e2 100644
--- a/llvm/test/CodeGen/X86/pr34080-2.ll
+++ b/llvm/test/CodeGen/X86/pr34080-2.ll
@@ -13,10 +13,10 @@ define void @computeJD(ptr) nounwind {
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: andl $-8, %esp
; CHECK-NEXT: subl $40, %esp
-; CHECK-NEXT: movl 8(%ebp), %ebx
-; CHECK-NEXT: movl 8(%ebx), %esi
+; CHECK-NEXT: movl 8(%ebp), %ecx
+; CHECK-NEXT: movl 8(%ecx), %esi
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: cmpl $3, 12(%ebx)
+; CHECK-NEXT: cmpl $3, 12(%ecx)
; CHECK-NEXT: setl %al
; CHECK-NEXT: subl %eax, %esi
; CHECK-NEXT: movl $-1374389535, %ecx # imm = 0xAE147AE1
@@ -27,25 +27,26 @@ define void @computeJD(ptr) nounwind {
; CHECK-NEXT: shrl $31, %eax
; CHECK-NEXT: sarl $5, %ecx
; CHECK-NEXT: addl %eax, %ecx
+; CHECK-NEXT: movl %esi, %ebx
+; CHECK-NEXT: sarl $31, %ebx
; CHECK-NEXT: movl $1374389535, %edx # imm = 0x51EB851F
; CHECK-NEXT: movl %esi, %eax
; CHECK-NEXT: imull %edx
; CHECK-NEXT: movl %edx, %edi
-; CHECK-NEXT: movl %edx, %eax
-; CHECK-NEXT: shrl $31, %eax
; CHECK-NEXT: sarl $7, %edi
-; CHECK-NEXT: addl %eax, %edi
-; CHECK-NEXT: imull $36525, %esi, %eax # imm = 0x8EAD
-; CHECK-NEXT: addl $172251900, %eax # imm = 0xA445AFC
+; CHECK-NEXT: subl %ebx, %edi
+; CHECK-NEXT: imull $36525, %esi, %esi # imm = 0x8EAD
+; CHECK-NEXT: addl $172251900, %esi # imm = 0xA445AFC
+; CHECK-NEXT: movl %esi, %eax
; CHECK-NEXT: movl $1374389535, %edx # imm = 0x51EB851F
; CHECK-NEXT: imull %edx
-; CHECK-NEXT: movl %edx, %eax
-; CHECK-NEXT: shrl $31, %eax
+; CHECK-NEXT: sarl $31, %esi
; CHECK-NEXT: sarl $5, %edx
-; CHECK-NEXT: addl %eax, %edx
-; CHECK-NEXT: addl 16(%ebx), %ecx
+; CHECK-NEXT: subl %esi, %edx
+; CHECK-NEXT: movl 8(%ebp), %esi
+; CHECK-NEXT: addl 16(%esi), %ecx
; CHECK-NEXT: addl %edi, %ecx
-; CHECK-NEXT: leal 257(%ecx,%edx), %eax
+; CHECK-NEXT: leal 257(%edx,%ecx), %eax
; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp)
; CHECK-NEXT: fildl {{[0-9]+}}(%esp)
; CHECK-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}}
@@ -57,11 +58,11 @@ define void @computeJD(ptr) nounwind {
; CHECK-NEXT: fldcw {{[0-9]+}}(%esp)
; CHECK-NEXT: fistpll {{[0-9]+}}(%esp)
; CHECK-NEXT: fldcw {{[0-9]+}}(%esp)
-; CHECK-NEXT: movb $1, 36(%ebx)
-; CHECK-NEXT: imull $3600000, 20(%ebx), %ecx # imm = 0x36EE80
-; CHECK-NEXT: imull $60000, 24(%ebx), %eax # imm = 0xEA60
+; CHECK-NEXT: movb $1, 36(%esi)
+; CHECK-NEXT: imull $3600000, 20(%esi), %ecx # imm = 0x36EE80
+; CHECK-NEXT: imull $60000, 24(%esi), %eax # imm = 0xEA60
; CHECK-NEXT: addl %ecx, %eax
-; CHECK-NEXT: fldl 28(%ebx)
+; CHECK-NEXT: fldl 28(%esi)
; CHECK-NEXT: fmuls {{\.?LCPI[0-9]+_[0-9]+}}
; CHECK-NEXT: fnstcw {{[0-9]+}}(%esp)
; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
@@ -76,8 +77,8 @@ define void @computeJD(ptr) nounwind {
; CHECK-NEXT: adcl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: addl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: adcl {{[0-9]+}}(%esp), %ecx
-; CHECK-NEXT: movl %eax, (%ebx)
-; CHECK-NEXT: movl %ecx, 4(%ebx)
+; CHECK-NEXT: movl %eax, (%esi)
+; CHECK-NEXT: movl %ecx, 4(%esi)
; CHECK-NEXT: leal -12(%ebp), %esp
; CHECK-NEXT: popl %esi
; CHECK-NEXT: popl %edi
diff --git a/llvm/test/CodeGen/X86/pr44812.ll b/llvm/test/CodeGen/X86/pr44812.ll
index 7c4dc67dc9c0e..707fd7f0222d3 100644
--- a/llvm/test/CodeGen/X86/pr44812.ll
+++ b/llvm/test/CodeGen/X86/pr44812.ll
@@ -4,18 +4,25 @@
define <2 x i32> @foo(<2 x i32> %tmp) {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: pushl %esi
+; CHECK-NEXT: .cfi_def_cfa_offset 8
+; CHECK-NEXT: .cfi_offset %esi, -8
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: leal 7(%eax), %ecx
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: cmovnsl %eax, %ecx
; CHECK-NEXT: sarl $3, %ecx
-; CHECK-NEXT: movl $1717986919, %eax # imm = 0x66666667
-; CHECK-NEXT: imull {{[0-9]+}}(%esp)
+; CHECK-NEXT: movl $1717986919, %edx # imm = 0x66666667
+; CHECK-NEXT: movl %esi, %eax
+; CHECK-NEXT: imull %edx
; CHECK-NEXT: movl %edx, %eax
-; CHECK-NEXT: shrl $31, %eax
-; CHECK-NEXT: sarl $2, %edx
-; CHECK-NEXT: addl %edx, %eax
+; CHECK-NEXT: sarl $2, %eax
+; CHECK-NEXT: sarl $31, %esi
+; CHECK-NEXT: subl %esi, %eax
; CHECK-NEXT: movl %ecx, %edx
+; CHECK-NEXT: popl %esi
+; CHECK-NEXT: .cfi_def_cfa_offset 4
; CHECK-NEXT: retl
entry:
%tmp1 = sdiv <2 x i32> %tmp, <i32 10, i32 8>
diff --git a/llvm/test/CodeGen/X86/shrink-wrap-chkstk-x86_64.ll b/llvm/test/CodeGen/X86/shrink-wrap-chkstk-x86_64.ll
index 0793c33d2e8eb..6ea0879ed1a8f 100644
--- a/llvm/test/CodeGen/X86/shrink-wrap-chkstk-x86_64.ll
+++ b/llvm/test/CodeGen/X86/shrink-wrap-chkstk-x86_64.ll
@@ -13,12 +13,12 @@ define void @fn1() nounwind uwtable {
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: jne .LBB0_2
; CHECK-NEXT: # %bb.1: # %select.true.sink
-; CHECK-NEXT: cltq
-; CHECK-NEXT: imulq $715827883, %rax, %rax # imm = 0x2AAAAAAB
-; CHECK-NEXT: movq %rax, %rcx
-; CHECK-NEXT: shrq $63, %rcx
-; CHECK-NEXT: shrq $32, %rax
-; CHECK-NEXT: addl %ecx, %eax
+; CHECK-NEXT: movslq %eax, %rcx
+; CHECK-NEXT: sarl $31, %eax
+; CHECK-NEXT: imulq $715827883, %rcx, %rcx # imm = 0x2AAAAAAB
+; CHECK-NEXT: shrq $32, %rcx
+; CHECK-NEXT: subl %eax, %ecx
+; CHECK-NEXT: movl %ecx, %eax
; CHECK-NEXT: .LBB0_2: # %select.end
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: movl $4128, %eax # imm = 0x1020
diff --git a/llvm/test/CodeGen/X86/srem-lkk.ll b/llvm/test/CodeGen/X86/srem-lkk.ll
index ae30ae4463a93..31dc58f126964 100644
--- a/llvm/test/CodeGen/X86/srem-lkk.ll
+++ b/llvm/test/CodeGen/X86/srem-lkk.ll
@@ -25,11 +25,10 @@ define i32 @fold_srem_positive_even(i32 %x) {
; CHECK-LABEL: fold_srem_positive_even:
; CHECK: # %bb.0:
; CHECK-NEXT: movslq %edi, %rax
+; CHECK-NEXT: sarl $31, %edi
; CHECK-NEXT: imulq $1037275121, %rax, %rcx # imm = 0x3DD38FF1
-; CHECK-NEXT: movq %rcx, %rdx
-; CHECK-NEXT: shrq $63, %rdx
; CHECK-NEXT: sarq $40, %rcx
-; CHECK-NEXT: addl %edx, %ecx
+; CHECK-NEXT: subl %edi, %ecx
; CHECK-NEXT: imull $1060, %ecx, %ecx # imm = 0x424
; CHECK-NEXT: subl %ecx, %eax
; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
@@ -146,10 +145,10 @@ define i64 @dont_fold_srem_i64(i64 %x) {
; CHECK-NEXT: movabsq $6023426636313322977, %rcx # imm = 0x5397829CBC14E5E1
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: imulq %rcx
-; CHECK-NEXT: movq %rdx, %rax
-; CHECK-NEXT: shrq $63, %rax
; CHECK-NEXT: sarq $5, %rdx
-; CHECK-NEXT: addq %rax, %rdx
+; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: sarq $63, %rax
+; CHECK-NEXT: subq %rax, %rdx
; CHECK-NEXT: imulq $98, %rdx, %rax
; CHECK-NEXT: subq %rax, %rdi
; CHECK-NEXT: movq %rdi, %rax
diff --git a/llvm/test/CodeGen/X86/srem-seteq-illegal-types.ll b/llvm/test/CodeGen/X86/srem-seteq-illegal-types.ll
index 650b562e6cb5c..f10c3fd840798 100644
--- a/llvm/test/CodeGen/X86/srem-seteq-illegal-types.ll
+++ b/llvm/test/CodeGen/X86/srem-seteq-illegal-types.ll
@@ -36,13 +36,12 @@ define i1 @test_srem_even(i4 %X) nounwind {
; X86-NEXT: movl %eax, %ecx
; X86-NEXT: shlb $4, %cl
; X86-NEXT: sarb $4, %cl
-; X86-NEXT: movzbl %cl, %ecx
-; X86-NEXT: leal (%ecx,%ecx,2), %ecx
-; X86-NEXT: movl %ecx, %edx
-; X86-NEXT: shrb $7, %dl
-; X86-NEXT: shrb $4, %cl
-; X86-NEXT: addb %dl, %cl
-; X86-NEXT: movzbl %cl, %ecx
+; X86-NEXT: movzbl %cl, %edx
+; X86-NEXT: shrb $3, %cl
+; X86-NEXT: leal (%edx,%edx,2), %edx
+; X86-NEXT: shrb $4, %dl
+; X86-NEXT: subb %cl, %dl
+; X86-NEXT: movzbl %dl, %ecx
; X86-NEXT: addl %ecx, %ecx
; X86-NEXT: leal (%ecx,%ecx,2), %ecx
; X86-NEXT: subb %cl, %al
@@ -57,12 +56,11 @@ define i1 @test_srem_even(i4 %X) nounwind {
; X64-NEXT: shlb $4, %al
; X64-NEXT: sarb $4, %al
; X64-NEXT: movzbl %al, %eax
-; X64-NEXT: leal (%rax,%rax,2), %eax
-; X64-NEXT: movl %eax, %ecx
-; X64-NEXT: shrb $7, %cl
-; X64-NEXT: shrb $4, %al
-; X64-NEXT: addb %cl, %al
-; X64-NEXT: movzbl %al, %eax
+; X64-NEXT: leal (%rax,%rax,2), %ecx
+; X64-NEXT: shrb $4, %cl
+; X64-NEXT: shrb $3, %al
+; X64-NEXT: subb %al, %cl
+; X64-NEXT: movzbl %cl, %eax
; X64-NEXT: addl %eax, %eax
; X64-NEXT: leal (%rax,%rax,2), %eax
; X64-NEXT: subb %al, %dil
@@ -167,54 +165,54 @@ define <3 x i1> @test_srem_vec(<3 x i33> %X) nounwind {
;
; SSE2-LABEL: test_srem_vec:
; SSE2: # %bb.0:
-; SSE2-NEXT: movq %rdx, %rcx
-; SSE2-NEXT: shlq $31, %rcx
-; SSE2-NEXT: sarq $31, %rcx
+; SSE2-NEXT: movq %rdx, %r9
; SSE2-NEXT: shlq $31, %rdi
-; SSE2-NEXT: sarq $31, %rdi
+; SSE2-NEXT: movq %rdi, %rcx
+; SSE2-NEXT: sarq $31, %rcx
; SSE2-NEXT: shlq $31, %rsi
-; SSE2-NEXT: sarq $31, %rsi
-; SSE2-NEXT: movabsq $2049638230412172402, %r8 # imm = 0x1C71C71C71C71C72
-; SSE2-NEXT: movq %rsi, %rax
-; SSE2-NEXT: imulq %r8
-; SSE2-NEXT: movq %rdx, %rax
-; SSE2-NEXT: shrq $63, %rax
-; SSE2-NEXT: addq %rdx, %rax
-; SSE2-NEXT: leaq (%rax,%rax,8), %rax
-; SSE2-NEXT: subq %rax, %rsi
-; SSE2-NEXT: movq %rsi, %xmm1
-; SSE2-NEXT: movq %rdi, %rax
-; SSE2-NEXT: imulq %r8
-; SSE2-NEXT: movq %rdx, %rax
-; SSE2-NEXT: shrq $63, %rax
-; SSE2-NEXT: addq %rdx, %rax
-; SSE2-NEXT: leaq (%rax,%rax,8), %rax
-; SSE2-NEXT: subq %rax, %rdi
-; SSE2-NEXT: movq %rdi, %xmm0
-; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
-; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [8589934591,8589934591]
-; SSE2-NEXT: pand %xmm1, %xmm0
+; SSE2-NEXT: movq %rsi, %r8
+; SSE2-NEXT: sarq $31, %r8
+; SSE2-NEXT: shlq $31, %r9
+; SSE2-NEXT: sarq $31, %r9
; SSE2-NEXT: movabsq $2049638230412172401, %rdx # imm = 0x1C71C71C71C71C71
-; SSE2-NEXT: movq %rcx, %rax
+; SSE2-NEXT: movq %r9, %rax
; SSE2-NEXT: imulq %rdx
-; SSE2-NEXT: subq %rcx, %rdx
+; SSE2-NEXT: subq %r9, %rdx
; SSE2-NEXT: movq %rdx, %rax
; SSE2-NEXT: shrq $63, %rax
; SSE2-NEXT: sarq $3, %rdx
; SSE2-NEXT: addq %rax, %rdx
; SSE2-NEXT: leaq (%rdx,%rdx,8), %rax
-; SSE2-NEXT: addq %rcx, %rax
-; SSE2-NEXT: movq %rax, %xmm2
-; SSE2-NEXT: pand %xmm1, %xmm2
+; SSE2-NEXT: addq %r9, %rax
+; SSE2-NEXT: movq %rax, %xmm0
+; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [8589934591,8589934591]
+; SSE2-NEXT: pand %xmm1, %xmm0
+; SSE2-NEXT: movabsq $2049638230412172402, %r9 # imm = 0x1C71C71C71C71C72
+; SSE2-NEXT: movq %r8, %rax
+; SSE2-NEXT: imulq %r9
+; SSE2-NEXT: sarq $63, %rsi
+; SSE2-NEXT: subq %rsi, %rdx
+; SSE2-NEXT: leaq (%rdx,%rdx,8), %rax
+; SSE2-NEXT: subq %rax, %r8
+; SSE2-NEXT: movq %r8, %xmm2
+; SSE2-NEXT: movq %rcx, %rax
+; SSE2-NEXT: imulq %r9
+; SSE2-NEXT: sarq $63, %rdi
+; SSE2-NEXT: subq %rdi, %rdx
+; SSE2-NEXT: leaq (%rdx,%rdx,8), %rax
+; SSE2-NEXT: subq %rax, %rcx
+; SSE2-NEXT: movq %rcx, %xmm3
+; SSE2-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm2[0]
+; SSE2-NEXT: pand %xmm1, %xmm3
+; SSE2-NEXT: pcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
; SSE2-NEXT: pcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; SSE2-NEXT: pcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
-; SSE2-NEXT: movdqa %xmm0, %xmm1
-; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,3],xmm2[1,2]
-; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[0,3]
-; SSE2-NEXT: andps %xmm1, %xmm0
-; SSE2-NEXT: pcmpeqd %xmm1, %xmm1
-; SSE2-NEXT: pxor %xmm0, %xmm1
-; SSE2-NEXT: movdqa %xmm1, -{{[0-9]+}}(%rsp)
+; SSE2-NEXT: movdqa %xmm3, %xmm1
+; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,3],xmm0[1,2]
+; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,2],xmm0[0,3]
+; SSE2-NEXT: andps %xmm1, %xmm3
+; SSE2-NEXT: pcmpeqd %xmm0, %xmm0
+; SSE2-NEXT: pxor %xmm3, %xmm0
+; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
@@ -226,26 +224,26 @@ define <3 x i1> @test_srem_vec(<3 x i33> %X) nounwind {
; SSE41-NEXT: shlq $31, %rcx
; SSE41-NEXT: sarq $31, %rcx
; SSE41-NEXT: shlq $31, %rdi
-; SSE41-NEXT: sarq $31, %rdi
+; SSE41-NEXT: movq %rdi, %r8
+; SSE41-NEXT: sarq $31, %r8
; SSE41-NEXT: shlq $31, %rsi
-; SSE41-NEXT: sarq $31, %rsi
-; SSE41-NEXT: movabsq $2049638230412172402, %r8 # imm = 0x1C71C71C71C71C72
-; SSE41-NEXT: movq %rsi, %rax
-; SSE41-NEXT: imulq %r8
-; SSE41-NEXT: movq %rdx, %rax
-; SSE41-NEXT: shrq $63, %rax
-; SSE41-NEXT: addq %rdx, %rax
-; SSE41-NEXT: leaq (%rax,%rax,8), %rax
-; SSE41-NEXT: subq %rax, %rsi
-; SSE41-NEXT: movq %rsi, %xmm1
-; SSE41-NEXT: movq %rdi, %rax
-; SSE41-NEXT: imulq %r8
-; SSE41-NEXT: movq %rdx, %rax
-; SSE41-NEXT: shrq $63, %rax
-; SSE41-NEXT: addq %rdx, %rax
-; SSE41-NEXT: leaq (%rax,%rax,8), %rax
-; SSE41-NEXT: subq %rax, %rdi
-; SSE41-NEXT: movq %rdi, %xmm0
+; SSE41-NEXT: movq %rsi, %r9
+; SSE41-NEXT: sarq $31, %r9
+; SSE41-NEXT: movabsq $2049638230412172402, %r10 # imm = 0x1C71C71C71C71C72
+; SSE41-NEXT: movq %r9, %rax
+; SSE41-NEXT: imulq %r10
+; SSE41-NEXT: sarq $63, %rsi
+; SSE41-NEXT: subq %rsi, %rdx
+; SSE41-NEXT: leaq (%rdx,%rdx,8), %rax
+; SSE41-NEXT: subq %rax, %r9
+; SSE41-NEXT: movq %r9, %xmm1
+; SSE41-NEXT: movq %r8, %rax
+; SSE41-NEXT: imulq %r10
+; SSE41-NEXT: sarq $63, %rdi
+; SSE41-NEXT: subq %rdi, %rdx
+; SSE41-NEXT: leaq (%rdx,%rdx,8), %rax
+; SSE41-NEXT: subq %rax, %r8
+; SSE41-NEXT: movq %r8, %xmm0
; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE41-NEXT: pmovsxbd {{.*#+}} xmm1 = [4294967295,1,4294967295,1]
; SSE41-NEXT: pand %xmm1, %xmm0
@@ -261,16 +259,16 @@ define <3 x i1> @test_srem_vec(<3 x i33> %X) nounwind {
; SSE41-NEXT: addq %rcx, %rax
; SSE41-NEXT: movq %rax, %xmm2
; SSE41-NEXT: pand %xmm1, %xmm2
-; SSE41-NEXT: pcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; SSE41-NEXT: pcmpeqd %xmm1, %xmm1
-; SSE41-NEXT: pxor %xmm1, %xmm0
; SSE41-NEXT: movl $3, %eax
-; SSE41-NEXT: movq %rax, %xmm3
-; SSE41-NEXT: pcmpeqq %xmm2, %xmm3
-; SSE41-NEXT: pxor %xmm1, %xmm3
+; SSE41-NEXT: movq %rax, %xmm1
+; SSE41-NEXT: pcmpeqq %xmm2, %xmm1
+; SSE41-NEXT: pcmpeqd %xmm2, %xmm2
+; SSE41-NEXT: pxor %xmm2, %xmm1
+; SSE41-NEXT: pcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE41-NEXT: pxor %xmm2, %xmm0
; SSE41-NEXT: movd %xmm0, %eax
; SSE41-NEXT: pextrb $8, %xmm0, %edx
-; SSE41-NEXT: pextrb $0, %xmm3, %ecx
+; SSE41-NEXT: pextrb $0, %xmm1, %ecx
; SSE41-NEXT: # kill: def $al killed $al killed $eax
; SSE41-NEXT: # kill: def $dl killed $dl killed $edx
; SSE41-NEXT: # kill: def $cl killed $cl killed $ecx
@@ -282,26 +280,26 @@ define <3 x i1> @test_srem_vec(<3 x i33> %X) nounwind {
; AVX1-NEXT: shlq $31, %rcx
; AVX1-NEXT: sarq $31, %rcx
; AVX1-NEXT: shlq $31, %rdi
-; AVX1-NEXT: sarq $31, %rdi
+; AVX1-NEXT: movq %rdi, %r8
+; AVX1-NEXT: sarq $31, %r8
; AVX1-NEXT: shlq $31, %rsi
-; AVX1-NEXT: sarq $31, %rsi
-; AVX1-NEXT: movabsq $2049638230412172402, %r8 # imm = 0x1C71C71C71C71C72
-; AVX1-NEXT: movq %rsi, %rax
-; AVX1-NEXT: imulq %r8
-; AVX1-NEXT: movq %rdx, %rax
-; AVX1-NEXT: shrq $63, %rax
-; AVX1-NEXT: addq %rdx, %rax
-; AVX1-NEXT: leaq (%rax,%rax,8), %rax
-; AVX1-NEXT: subq %rax, %rsi
-; AVX1-NEXT: vmovq %rsi, %xmm0
-; AVX1-NEXT: movq %rdi, %rax
-; AVX1-NEXT: imulq %r8
-; AVX1-NEXT: movq %rdx, %rax
-; AVX1-NEXT: shrq $63, %rax
-; AVX1-NEXT: addq %rdx, %rax
-; AVX1-NEXT: leaq (%rax,%rax,8), %rax
-; AVX1-NEXT: subq %rax, %rdi
-; AVX1-NEXT: vmovq %rdi, %xmm1
+; AVX1-NEXT: movq %rsi, %r9
+; AVX1-NEXT: sarq $31, %r9
+; AVX1-NEXT: movabsq $2049638230412172402, %r10 # imm = 0x1C71C71C71C71C72
+; AVX1-NEXT: movq %r9, %rax
+; AVX1-NEXT: imulq %r10
+; AVX1-NEXT: sarq $63, %rsi
+; AVX1-NEXT: subq %rsi, %rdx
+; AVX1-NEXT: leaq (%rdx,%rdx,8), %rax
+; AVX1-NEXT: subq %rax, %r9
+; AVX1-NEXT: vmovq %r9, %xmm0
+; AVX1-NEXT: movq %r8, %rax
+; AVX1-NEXT: imulq %r10
+; AVX1-NEXT: sarq $63, %rdi
+; AVX1-NEXT: subq %rdi, %rdx
+; AVX1-NEXT: leaq (%rdx,%rdx,8), %rax
+; AVX1-NEXT: subq %rax, %r8
+; AVX1-NEXT: vmovq %r8, %xmm1
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
; AVX1-NEXT: movabsq $2049638230412172401, %rdx # imm = 0x1C71C71C71C71C71
; AVX1-NEXT: movq %rcx, %rax
@@ -339,26 +337,26 @@ define <3 x i1> @test_srem_vec(<3 x i33> %X) nounwind {
; AVX2-NEXT: shlq $31, %rcx
; AVX2-NEXT: sarq $31, %rcx
; AVX2-NEXT: shlq $31, %rdi
-; AVX2-NEXT: sarq $31, %rdi
+; AVX2-NEXT: movq %rdi, %r8
+; AVX2-NEXT: sarq $31, %r8
; AVX2-NEXT: shlq $31, %rsi
-; AVX2-NEXT: sarq $31, %rsi
-; AVX2-NEXT: movabsq $2049638230412172402, %r8 # imm = 0x1C71C71C71C71C72
-; AVX2-NEXT: movq %rsi, %rax
-; AVX2-NEXT: imulq %r8
-; AVX2-NEXT: movq %rdx, %rax
-; AVX2-NEXT: shrq $63, %rax
-; AVX2-NEXT: addq %rdx, %rax
-; AVX2-NEXT: leaq (%rax,%rax,8), %rax
-; AVX2-NEXT: subq %rax, %rsi
-; AVX2-NEXT: vmovq %rsi, %xmm0
-; AVX2-NEXT: movq %rdi, %rax
-; AVX2-NEXT: imulq %r8
-; AVX2-NEXT: movq %rdx, %rax
-; AVX2-NEXT: shrq $63, %rax
-; AVX2-NEXT: addq %rdx, %rax
-; AVX2-NEXT: leaq (%rax,%rax,8), %rax
-; AVX2-NEXT: subq %rax, %rdi
-; AVX2-NEXT: vmovq %rdi, %xmm1
+; AVX2-NEXT: movq %rsi, %r9
+; AVX2-NEXT: sarq $31, %r9
+; AVX2-NEXT: movabsq $2049638230412172402, %r10 # imm = 0x1C71C71C71C71C72
+; AVX2-NEXT: movq %r9, %rax
+; AVX2-NEXT: imulq %r10
+; AVX2-NEXT: sarq $63, %rsi
+; AVX2-NEXT: subq %rsi, %rdx
+; AVX2-NEXT: leaq (%rdx,%rdx,8), %rax
+; AVX2-NEXT: subq %rax, %r9
+; AVX2-NEXT: vmovq %r9, %xmm0
+; AVX2-NEXT: movq %r8, %rax
+; AVX2-NEXT: imulq %r10
+; AVX2-NEXT: sarq $63, %rdi
+; AVX2-NEXT: subq %rdi, %rdx
+; AVX2-NEXT: leaq (%rdx,%rdx,8), %rax
+; AVX2-NEXT: subq %rax, %r8
+; AVX2-NEXT: vmovq %r8, %xmm1
; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
; AVX2-NEXT: movabsq $2049638230412172401, %rdx # imm = 0x1C71C71C71C71C71
; AVX2-NEXT: movq %rcx, %rax
@@ -394,26 +392,26 @@ define <3 x i1> @test_srem_vec(<3 x i33> %X) nounwind {
; AVX512VL-NEXT: shlq $31, %rcx
; AVX512VL-NEXT: sarq $31, %rcx
; AVX512VL-NEXT: shlq $31, %rdi
-; AVX512VL-NEXT: sarq $31, %rdi
+; AVX512VL-NEXT: movq %rdi, %r8
+; AVX512VL-NEXT: sarq $31, %r8
; AVX512VL-NEXT: shlq $31, %rsi
-; AVX512VL-NEXT: sarq $31, %rsi
-; AVX512VL-NEXT: movabsq $2049638230412172402, %r8 # imm = 0x1C71C71C71C71C72
-; AVX512VL-NEXT: movq %rsi, %rax
-; AVX512VL-NEXT: imulq %r8
-; AVX512VL-NEXT: movq %rdx, %rax
-; AVX512VL-NEXT: shrq $63, %rax
-; AVX512VL-NEXT: addq %rdx, %rax
-; AVX512VL-NEXT: leaq (%rax,%rax,8), %rax
-; AVX512VL-NEXT: subq %rax, %rsi
-; AVX512VL-NEXT: vmovq %rsi, %xmm0
-; AVX512VL-NEXT: movq %rdi, %rax
-; AVX512VL-NEXT: imulq %r8
-; AVX512VL-NEXT: movq %rdx, %rax
-; AVX512VL-NEXT: shrq $63, %rax
-; AVX512VL-NEXT: addq %rdx, %rax
-; AVX512VL-NEXT: leaq (%rax,%rax,8), %rax
-; AVX512VL-NEXT: subq %rax, %rdi
-; AVX512VL-NEXT: vmovq %rdi, %xmm1
+; AVX512VL-NEXT: movq %rsi, %r9
+; AVX512VL-NEXT: sarq $31, %r9
+; AVX512VL-NEXT: movabsq $2049638230412172402, %r10 # imm = 0x1C71C71C71C71C72
+; AVX512VL-NEXT: movq %r9, %rax
+; AVX512VL-NEXT: imulq %r10
+; AVX512VL-NEXT: sarq $63, %rsi
+; AVX512VL-NEXT: subq %rsi, %rdx
+; AVX512VL-NEXT: leaq (%rdx,%rdx,8), %rax
+; AVX512VL-NEXT: subq %rax, %r9
+; AVX512VL-NEXT: vmovq %r9, %xmm0
+; AVX512VL-NEXT: movq %r8, %rax
+; AVX512VL-NEXT: imulq %r10
+; AVX512VL-NEXT: sarq $63, %rdi
+; AVX512VL-NEXT: subq %rdi, %rdx
+; AVX512VL-NEXT: leaq (%rdx,%rdx,8), %rax
+; AVX512VL-NEXT: subq %rax, %r8
+; AVX512VL-NEXT: vmovq %r8, %xmm1
; AVX512VL-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
; AVX512VL-NEXT: movabsq $2049638230412172401, %rdx # imm = 0x1C71C71C71C71C71
; AVX512VL-NEXT: movq %rcx, %rax
diff --git a/llvm/test/CodeGen/X86/srem-vector-lkk.ll b/llvm/test/CodeGen/X86/srem-vector-lkk.ll
index f9de4e18857c9..d94686eaf8cf3 100644
--- a/llvm/test/CodeGen/X86/srem-vector-lkk.ll
+++ b/llvm/test/CodeGen/X86/srem-vector-lkk.ll
@@ -422,10 +422,10 @@ define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) {
; SSE2-NEXT: movabsq $6966426675817289639, %rdx # imm = 0x60ADB826E5E517A7
; SSE2-NEXT: movq %rcx, %rax
; SSE2-NEXT: imulq %rdx
-; SSE2-NEXT: movq %rdx, %rax
-; SSE2-NEXT: shrq $63, %rax
; SSE2-NEXT: sarq $11, %rdx
-; SSE2-NEXT: addq %rax, %rdx
+; SSE2-NEXT: movq %rcx, %rax
+; SSE2-NEXT: sarq $63, %rax
+; SSE2-NEXT: subq %rax, %rdx
; SSE2-NEXT: imulq $5423, %rdx, %rax # imm = 0x152F
; SSE2-NEXT: subq %rax, %rcx
; SSE2-NEXT: movq %rcx, %xmm2
@@ -435,10 +435,10 @@ define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) {
; SSE2-NEXT: movabsq $7220743857598845893, %rdx # imm = 0x64353C48064353C5
; SSE2-NEXT: movq %rcx, %rax
; SSE2-NEXT: imulq %rdx
-; SSE2-NEXT: movq %rdx, %rax
-; SSE2-NEXT: shrq $63, %rax
; SSE2-NEXT: sarq $8, %rdx
-; SSE2-NEXT: addq %rax, %rdx
+; SSE2-NEXT: movq %rcx, %rax
+; SSE2-NEXT: sarq $63, %rax
+; SSE2-NEXT: subq %rax, %rdx
; SSE2-NEXT: imulq $654, %rdx, %rax # imm = 0x28E
; SSE2-NEXT: subq %rax, %rcx
; SSE2-NEXT: movq %rcx, %xmm0
@@ -466,10 +466,10 @@ define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) {
; SSE4-NEXT: movabsq $6966426675817289639, %rdx # imm = 0x60ADB826E5E517A7
; SSE4-NEXT: movq %rcx, %rax
; SSE4-NEXT: imulq %rdx
-; SSE4-NEXT: movq %rdx, %rax
-; SSE4-NEXT: shrq $63, %rax
; SSE4-NEXT: sarq $11, %rdx
-; SSE4-NEXT: addq %rax, %rdx
+; SSE4-NEXT: movq %rcx, %rax
+; SSE4-NEXT: sarq $63, %rax
+; SSE4-NEXT: subq %rax, %rdx
; SSE4-NEXT: imulq $5423, %rdx, %rax # imm = 0x152F
; SSE4-NEXT: subq %rax, %rcx
; SSE4-NEXT: movq %rcx, %xmm2
@@ -478,10 +478,10 @@ define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) {
; SSE4-NEXT: movabsq $7220743857598845893, %rdx # imm = 0x64353C48064353C5
; SSE4-NEXT: movq %rcx, %rax
; SSE4-NEXT: imulq %rdx
-; SSE4-NEXT: movq %rdx, %rax
-; SSE4-NEXT: shrq $63, %rax
; SSE4-NEXT: sarq $8, %rdx
-; SSE4-NEXT: addq %rax, %rdx
+; SSE4-NEXT: movq %rcx, %rax
+; SSE4-NEXT: sarq $63, %rax
+; SSE4-NEXT: subq %rax, %rdx
; SSE4-NEXT: imulq $654, %rdx, %rax # imm = 0x28E
; SSE4-NEXT: subq %rax, %rcx
; SSE4-NEXT: movq %rcx, %xmm0
@@ -509,10 +509,10 @@ define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) {
; AVX1-NEXT: movabsq $6966426675817289639, %rdx # imm = 0x60ADB826E5E517A7
; AVX1-NEXT: movq %rcx, %rax
; AVX1-NEXT: imulq %rdx
-; AVX1-NEXT: movq %rdx, %rax
-; AVX1-NEXT: shrq $63, %rax
; AVX1-NEXT: sarq $11, %rdx
-; AVX1-NEXT: addq %rax, %rdx
+; AVX1-NEXT: movq %rcx, %rax
+; AVX1-NEXT: sarq $63, %rax
+; AVX1-NEXT: subq %rax, %rdx
; AVX1-NEXT: imulq $5423, %rdx, %rax # imm = 0x152F
; AVX1-NEXT: subq %rax, %rcx
; AVX1-NEXT: vmovq %rcx, %xmm1
@@ -521,10 +521,10 @@ define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) {
; AVX1-NEXT: movabsq $7220743857598845893, %rdx # imm = 0x64353C48064353C5
; AVX1-NEXT: movq %rcx, %rax
; AVX1-NEXT: imulq %rdx
-; AVX1-NEXT: movq %rdx, %rax
-; AVX1-NEXT: shrq $63, %rax
; AVX1-NEXT: sarq $8, %rdx
-; AVX1-NEXT: addq %rax, %rdx
+; AVX1-NEXT: movq %rcx, %rax
+; AVX1-NEXT: sarq $63, %rax
+; AVX1-NEXT: subq %rax, %rdx
; AVX1-NEXT: imulq $654, %rdx, %rax # imm = 0x28E
; AVX1-NEXT: subq %rax, %rcx
; AVX1-NEXT: vmovq %rcx, %xmm0
@@ -553,10 +553,10 @@ define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) {
; AVX2-NEXT: movabsq $6966426675817289639, %rdx # imm = 0x60ADB826E5E517A7
; AVX2-NEXT: movq %rcx, %rax
; AVX2-NEXT: imulq %rdx
-; AVX2-NEXT: movq %rdx, %rax
-; AVX2-NEXT: shrq $63, %rax
; AVX2-NEXT: sarq $11, %rdx
-; AVX2-NEXT: addq %rax, %rdx
+; AVX2-NEXT: movq %rcx, %rax
+; AVX2-NEXT: sarq $63, %rax
+; AVX2-NEXT: subq %rax, %rdx
; AVX2-NEXT: imulq $5423, %rdx, %rax # imm = 0x152F
; AVX2-NEXT: subq %rax, %rcx
; AVX2-NEXT: vmovq %rcx, %xmm1
@@ -565,10 +565,10 @@ define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) {
; AVX2-NEXT: movabsq $7220743857598845893, %rdx # imm = 0x64353C48064353C5
; AVX2-NEXT: movq %rcx, %rax
; AVX2-NEXT: imulq %rdx
-; AVX2-NEXT: movq %rdx, %rax
-; AVX2-NEXT: shrq $63, %rax
; AVX2-NEXT: sarq $8, %rdx
-; AVX2-NEXT: addq %rax, %rdx
+; AVX2-NEXT: movq %rcx, %rax
+; AVX2-NEXT: sarq $63, %rax
+; AVX2-NEXT: subq %rax, %rdx
; AVX2-NEXT: imulq $654, %rdx, %rax # imm = 0x28E
; AVX2-NEXT: subq %rax, %rcx
; AVX2-NEXT: vmovq %rcx, %xmm0
@@ -597,10 +597,10 @@ define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) {
; AVX512-NEXT: movabsq $6966426675817289639, %rdx # imm = 0x60ADB826E5E517A7
; AVX512-NEXT: movq %rcx, %rax
; AVX512-NEXT: imulq %rdx
-; AVX512-NEXT: movq %rdx, %rax
-; AVX512-NEXT: shrq $63, %rax
; AVX512-NEXT: sarq $11, %rdx
-; AVX512-NEXT: addq %rax, %rdx
+; AVX512-NEXT: movq %rcx, %rax
+; AVX512-NEXT: sarq $63, %rax
+; AVX512-NEXT: subq %rax, %rdx
; AVX512-NEXT: imulq $5423, %rdx, %rax # imm = 0x152F
; AVX512-NEXT: subq %rax, %rcx
; AVX512-NEXT: vmovq %rcx, %xmm2
@@ -609,10 +609,10 @@ define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) {
; AVX512-NEXT: movabsq $7220743857598845893, %rdx # imm = 0x64353C48064353C5
; AVX512-NEXT: movq %rcx, %rax
; AVX512-NEXT: imulq %rdx
-; AVX512-NEXT: movq %rdx, %rax
-; AVX512-NEXT: shrq $63, %rax
; AVX512-NEXT: sarq $8, %rdx
-; AVX512-NEXT: addq %rax, %rdx
+; AVX512-NEXT: movq %rcx, %rax
+; AVX512-NEXT: sarq $63, %rax
+; AVX512-NEXT: subq %rax, %rdx
; AVX512-NEXT: imulq $654, %rdx, %rax # imm = 0x28E
; AVX512-NEXT: subq %rax, %rcx
; AVX512-NEXT: vmovq %rcx, %xmm1
diff --git a/llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll b/llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll
index 3117865184ecc..add07742c4a8d 100644
--- a/llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll
+++ b/llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll
@@ -12,21 +12,21 @@
define <2 x i64> @test_div7_2i64(<2 x i64> %a) nounwind {
; SSE2-LABEL: test_div7_2i64:
; SSE2: # %bb.0:
-; SSE2-NEXT: movq %xmm0, %rax
-; SSE2-NEXT: movabsq $5270498306774157605, %rcx # imm = 0x4924924924924925
-; SSE2-NEXT: imulq %rcx
-; SSE2-NEXT: movq %rdx, %rax
-; SSE2-NEXT: shrq $63, %rax
+; SSE2-NEXT: movq %xmm0, %rcx
+; SSE2-NEXT: movabsq $5270498306774157605, %rsi # imm = 0x4924924924924925
+; SSE2-NEXT: movq %rcx, %rax
+; SSE2-NEXT: imulq %rsi
; SSE2-NEXT: sarq %rdx
-; SSE2-NEXT: addq %rax, %rdx
+; SSE2-NEXT: sarq $63, %rcx
+; SSE2-NEXT: subq %rcx, %rdx
; SSE2-NEXT: movq %rdx, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
-; SSE2-NEXT: movq %xmm0, %rax
-; SSE2-NEXT: imulq %rcx
-; SSE2-NEXT: movq %rdx, %rax
-; SSE2-NEXT: shrq $63, %rax
+; SSE2-NEXT: movq %xmm0, %rcx
+; SSE2-NEXT: movq %rcx, %rax
+; SSE2-NEXT: imulq %rsi
; SSE2-NEXT: sarq %rdx
-; SSE2-NEXT: addq %rax, %rdx
+; SSE2-NEXT: sarq $63, %rcx
+; SSE2-NEXT: subq %rcx, %rdx
; SSE2-NEXT: movq %rdx, %xmm0
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; SSE2-NEXT: movdqa %xmm1, %xmm0
@@ -34,40 +34,40 @@ define <2 x i64> @test_div7_2i64(<2 x i64> %a) nounwind {
;
; SSE41-LABEL: test_div7_2i64:
; SSE41: # %bb.0:
-; SSE41-NEXT: pextrq $1, %xmm0, %rax
-; SSE41-NEXT: movabsq $5270498306774157605, %rcx # imm = 0x4924924924924925
-; SSE41-NEXT: imulq %rcx
-; SSE41-NEXT: movq %rdx, %rax
-; SSE41-NEXT: shrq $63, %rax
+; SSE41-NEXT: pextrq $1, %xmm0, %rcx
+; SSE41-NEXT: movabsq $5270498306774157605, %rsi # imm = 0x4924924924924925
+; SSE41-NEXT: movq %rcx, %rax
+; SSE41-NEXT: imulq %rsi
; SSE41-NEXT: sarq %rdx
-; SSE41-NEXT: addq %rax, %rdx
+; SSE41-NEXT: sarq $63, %rcx
+; SSE41-NEXT: subq %rcx, %rdx
; SSE41-NEXT: movq %rdx, %xmm1
-; SSE41-NEXT: movq %xmm0, %rax
-; SSE41-NEXT: imulq %rcx
-; SSE41-NEXT: movq %rdx, %rax
-; SSE41-NEXT: shrq $63, %rax
+; SSE41-NEXT: movq %xmm0, %rcx
+; SSE41-NEXT: movq %rcx, %rax
+; SSE41-NEXT: imulq %rsi
; SSE41-NEXT: sarq %rdx
-; SSE41-NEXT: addq %rax, %rdx
+; SSE41-NEXT: sarq $63, %rcx
+; SSE41-NEXT: subq %rcx, %rdx
; SSE41-NEXT: movq %rdx, %xmm0
; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE41-NEXT: retq
;
; AVX-LABEL: test_div7_2i64:
; AVX: # %bb.0:
-; AVX-NEXT: vpextrq $1, %xmm0, %rax
-; AVX-NEXT: movabsq $5270498306774157605, %rcx # imm = 0x4924924924924925
-; AVX-NEXT: imulq %rcx
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
+; AVX-NEXT: vpextrq $1, %xmm0, %rcx
+; AVX-NEXT: movabsq $5270498306774157605, %rsi # imm = 0x4924924924924925
+; AVX-NEXT: movq %rcx, %rax
+; AVX-NEXT: imulq %rsi
; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
+; AVX-NEXT: sarq $63, %rcx
+; AVX-NEXT: subq %rcx, %rdx
; AVX-NEXT: vmovq %rdx, %xmm1
-; AVX-NEXT: vmovq %xmm0, %rax
-; AVX-NEXT: imulq %rcx
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
+; AVX-NEXT: vmovq %xmm0, %rcx
+; AVX-NEXT: movq %rcx, %rax
+; AVX-NEXT: imulq %rsi
; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
+; AVX-NEXT: sarq $63, %rcx
+; AVX-NEXT: subq %rcx, %rdx
; AVX-NEXT: vmovq %rdx, %xmm0
; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX-NEXT: retq
@@ -360,10 +360,10 @@ define <2 x i64> @test_rem7_2i64(<2 x i64> %a) nounwind {
; SSE2-NEXT: movabsq $5270498306774157605, %rsi # imm = 0x4924924924924925
; SSE2-NEXT: movq %rcx, %rax
; SSE2-NEXT: imulq %rsi
-; SSE2-NEXT: movq %rdx, %rax
-; SSE2-NEXT: shrq $63, %rax
; SSE2-NEXT: sarq %rdx
-; SSE2-NEXT: addq %rax, %rdx
+; SSE2-NEXT: movq %rcx, %rax
+; SSE2-NEXT: sarq $63, %rax
+; SSE2-NEXT: subq %rax, %rdx
; SSE2-NEXT: leaq (,%rdx,8), %rax
; SSE2-NEXT: subq %rax, %rdx
; SSE2-NEXT: addq %rcx, %rdx
@@ -372,10 +372,10 @@ define <2 x i64> @test_rem7_2i64(<2 x i64> %a) nounwind {
; SSE2-NEXT: movq %xmm0, %rcx
; SSE2-NEXT: movq %rcx, %rax
; SSE2-NEXT: imulq %rsi
-; SSE2-NEXT: movq %rdx, %rax
-; SSE2-NEXT: shrq $63, %rax
; SSE2-NEXT: sarq %rdx
-; SSE2-NEXT: addq %rax, %rdx
+; SSE2-NEXT: movq %rcx, %rax
+; SSE2-NEXT: sarq $63, %rax
+; SSE2-NEXT: subq %rax, %rdx
; SSE2-NEXT: leaq (,%rdx,8), %rax
; SSE2-NEXT: subq %rax, %rdx
; SSE2-NEXT: addq %rcx, %rdx
@@ -390,10 +390,10 @@ define <2 x i64> @test_rem7_2i64(<2 x i64> %a) nounwind {
; SSE41-NEXT: movabsq $5270498306774157605, %rsi # imm = 0x4924924924924925
; SSE41-NEXT: movq %rcx, %rax
; SSE41-NEXT: imulq %rsi
-; SSE41-NEXT: movq %rdx, %rax
-; SSE41-NEXT: shrq $63, %rax
; SSE41-NEXT: sarq %rdx
-; SSE41-NEXT: addq %rax, %rdx
+; SSE41-NEXT: movq %rcx, %rax
+; SSE41-NEXT: sarq $63, %rax
+; SSE41-NEXT: subq %rax, %rdx
; SSE41-NEXT: leaq (,%rdx,8), %rax
; SSE41-NEXT: subq %rax, %rdx
; SSE41-NEXT: addq %rcx, %rdx
@@ -401,10 +401,10 @@ define <2 x i64> @test_rem7_2i64(<2 x i64> %a) nounwind {
; SSE41-NEXT: movq %xmm0, %rcx
; SSE41-NEXT: movq %rcx, %rax
; SSE41-NEXT: imulq %rsi
-; SSE41-NEXT: movq %rdx, %rax
-; SSE41-NEXT: shrq $63, %rax
; SSE41-NEXT: sarq %rdx
-; SSE41-NEXT: addq %rax, %rdx
+; SSE41-NEXT: movq %rcx, %rax
+; SSE41-NEXT: sarq $63, %rax
+; SSE41-NEXT: subq %rax, %rdx
; SSE41-NEXT: leaq (,%rdx,8), %rax
; SSE41-NEXT: subq %rax, %rdx
; SSE41-NEXT: addq %rcx, %rdx
@@ -418,10 +418,10 @@ define <2 x i64> @test_rem7_2i64(<2 x i64> %a) nounwind {
; AVX-NEXT: movabsq $5270498306774157605, %rsi # imm = 0x4924924924924925
; AVX-NEXT: movq %rcx, %rax
; AVX-NEXT: imulq %rsi
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
+; AVX-NEXT: movq %rcx, %rax
+; AVX-NEXT: sarq $63, %rax
+; AVX-NEXT: subq %rax, %rdx
; AVX-NEXT: leaq (,%rdx,8), %rax
; AVX-NEXT: subq %rax, %rdx
; AVX-NEXT: addq %rcx, %rdx
@@ -429,10 +429,10 @@ define <2 x i64> @test_rem7_2i64(<2 x i64> %a) nounwind {
; AVX-NEXT: vmovq %xmm0, %rcx
; AVX-NEXT: movq %rcx, %rax
; AVX-NEXT: imulq %rsi
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
+; AVX-NEXT: movq %rcx, %rax
+; AVX-NEXT: sarq $63, %rax
+; AVX-NEXT: subq %rax, %rdx
; AVX-NEXT: leaq (,%rdx,8), %rax
; AVX-NEXT: subq %rax, %rdx
; AVX-NEXT: addq %rcx, %rdx
diff --git a/llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll b/llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll
index fa5692aa9cef1..f169bc3bf3543 100644
--- a/llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll
+++ b/llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll
@@ -11,35 +11,35 @@ define <4 x i64> @test_div7_4i64(<4 x i64> %a) nounwind {
; AVX1-LABEL: test_div7_4i64:
; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
-; AVX1-NEXT: vpextrq $1, %xmm1, %rax
-; AVX1-NEXT: movabsq $5270498306774157605, %rcx # imm = 0x4924924924924925
-; AVX1-NEXT: imulq %rcx
-; AVX1-NEXT: movq %rdx, %rax
-; AVX1-NEXT: shrq $63, %rax
+; AVX1-NEXT: vpextrq $1, %xmm1, %rcx
+; AVX1-NEXT: movabsq $5270498306774157605, %rsi # imm = 0x4924924924924925
+; AVX1-NEXT: movq %rcx, %rax
+; AVX1-NEXT: imulq %rsi
; AVX1-NEXT: sarq %rdx
-; AVX1-NEXT: addq %rax, %rdx
+; AVX1-NEXT: sarq $63, %rcx
+; AVX1-NEXT: subq %rcx, %rdx
; AVX1-NEXT: vmovq %rdx, %xmm2
-; AVX1-NEXT: vmovq %xmm1, %rax
-; AVX1-NEXT: imulq %rcx
-; AVX1-NEXT: movq %rdx, %rax
-; AVX1-NEXT: shrq $63, %rax
+; AVX1-NEXT: vmovq %xmm1, %rcx
+; AVX1-NEXT: movq %rcx, %rax
+; AVX1-NEXT: imulq %rsi
; AVX1-NEXT: sarq %rdx
-; AVX1-NEXT: addq %rax, %rdx
+; AVX1-NEXT: sarq $63, %rcx
+; AVX1-NEXT: subq %rcx, %rdx
; AVX1-NEXT: vmovq %rdx, %xmm1
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
-; AVX1-NEXT: vpextrq $1, %xmm0, %rax
-; AVX1-NEXT: imulq %rcx
-; AVX1-NEXT: movq %rdx, %rax
-; AVX1-NEXT: shrq $63, %rax
+; AVX1-NEXT: vpextrq $1, %xmm0, %rcx
+; AVX1-NEXT: movq %rcx, %rax
+; AVX1-NEXT: imulq %rsi
; AVX1-NEXT: sarq %rdx
-; AVX1-NEXT: addq %rax, %rdx
+; AVX1-NEXT: sarq $63, %rcx
+; AVX1-NEXT: subq %rcx, %rdx
; AVX1-NEXT: vmovq %rdx, %xmm2
-; AVX1-NEXT: vmovq %xmm0, %rax
-; AVX1-NEXT: imulq %rcx
-; AVX1-NEXT: movq %rdx, %rax
-; AVX1-NEXT: shrq $63, %rax
+; AVX1-NEXT: vmovq %xmm0, %rcx
+; AVX1-NEXT: movq %rcx, %rax
+; AVX1-NEXT: imulq %rsi
; AVX1-NEXT: sarq %rdx
-; AVX1-NEXT: addq %rax, %rdx
+; AVX1-NEXT: sarq $63, %rcx
+; AVX1-NEXT: subq %rcx, %rdx
; AVX1-NEXT: vmovq %rdx, %xmm0
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
@@ -48,35 +48,35 @@ define <4 x i64> @test_div7_4i64(<4 x i64> %a) nounwind {
; AVX2-LABEL: test_div7_4i64:
; AVX2: # %bb.0:
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
-; AVX2-NEXT: vpextrq $1, %xmm1, %rax
-; AVX2-NEXT: movabsq $5270498306774157605, %rcx # imm = 0x4924924924924925
-; AVX2-NEXT: imulq %rcx
-; AVX2-NEXT: movq %rdx, %rax
-; AVX2-NEXT: shrq $63, %rax
+; AVX2-NEXT: vpextrq $1, %xmm1, %rcx
+; AVX2-NEXT: movabsq $5270498306774157605, %rsi # imm = 0x4924924924924925
+; AVX2-NEXT: movq %rcx, %rax
+; AVX2-NEXT: imulq %rsi
; AVX2-NEXT: sarq %rdx
-; AVX2-NEXT: addq %rax, %rdx
+; AVX2-NEXT: sarq $63, %rcx
+; AVX2-NEXT: subq %rcx, %rdx
; AVX2-NEXT: vmovq %rdx, %xmm2
-; AVX2-NEXT: vmovq %xmm1, %rax
-; AVX2-NEXT: imulq %rcx
-; AVX2-NEXT: movq %rdx, %rax
-; AVX2-NEXT: shrq $63, %rax
+; AVX2-NEXT: vmovq %xmm1, %rcx
+; AVX2-NEXT: movq %rcx, %rax
+; AVX2-NEXT: imulq %rsi
; AVX2-NEXT: sarq %rdx
-; AVX2-NEXT: addq %rax, %rdx
+; AVX2-NEXT: sarq $63, %rcx
+; AVX2-NEXT: subq %rcx, %rdx
; AVX2-NEXT: vmovq %rdx, %xmm1
; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
-; AVX2-NEXT: vpextrq $1, %xmm0, %rax
-; AVX2-NEXT: imulq %rcx
-; AVX2-NEXT: movq %rdx, %rax
-; AVX2-NEXT: shrq $63, %rax
+; AVX2-NEXT: vpextrq $1, %xmm0, %rcx
+; AVX2-NEXT: movq %rcx, %rax
+; AVX2-NEXT: imulq %rsi
; AVX2-NEXT: sarq %rdx
-; AVX2-NEXT: addq %rax, %rdx
+; AVX2-NEXT: sarq $63, %rcx
+; AVX2-NEXT: subq %rcx, %rdx
; AVX2-NEXT: vmovq %rdx, %xmm2
-; AVX2-NEXT: vmovq %xmm0, %rax
-; AVX2-NEXT: imulq %rcx
-; AVX2-NEXT: movq %rdx, %rax
-; AVX2-NEXT: shrq $63, %rax
+; AVX2-NEXT: vmovq %xmm0, %rcx
+; AVX2-NEXT: movq %rcx, %rax
+; AVX2-NEXT: imulq %rsi
; AVX2-NEXT: sarq %rdx
-; AVX2-NEXT: addq %rax, %rdx
+; AVX2-NEXT: sarq $63, %rcx
+; AVX2-NEXT: subq %rcx, %rdx
; AVX2-NEXT: vmovq %rdx, %xmm0
; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
@@ -343,10 +343,10 @@ define <4 x i64> @test_rem7_4i64(<4 x i64> %a) nounwind {
; AVX1-NEXT: movabsq $5270498306774157605, %rsi # imm = 0x4924924924924925
; AVX1-NEXT: movq %rcx, %rax
; AVX1-NEXT: imulq %rsi
-; AVX1-NEXT: movq %rdx, %rax
-; AVX1-NEXT: shrq $63, %rax
; AVX1-NEXT: sarq %rdx
-; AVX1-NEXT: addq %rax, %rdx
+; AVX1-NEXT: movq %rcx, %rax
+; AVX1-NEXT: sarq $63, %rax
+; AVX1-NEXT: subq %rax, %rdx
; AVX1-NEXT: leaq (,%rdx,8), %rax
; AVX1-NEXT: subq %rax, %rdx
; AVX1-NEXT: addq %rcx, %rdx
@@ -354,10 +354,10 @@ define <4 x i64> @test_rem7_4i64(<4 x i64> %a) nounwind {
; AVX1-NEXT: vmovq %xmm1, %rcx
; AVX1-NEXT: movq %rcx, %rax
; AVX1-NEXT: imulq %rsi
-; AVX1-NEXT: movq %rdx, %rax
-; AVX1-NEXT: shrq $63, %rax
; AVX1-NEXT: sarq %rdx
-; AVX1-NEXT: addq %rax, %rdx
+; AVX1-NEXT: movq %rcx, %rax
+; AVX1-NEXT: sarq $63, %rax
+; AVX1-NEXT: subq %rax, %rdx
; AVX1-NEXT: leaq (,%rdx,8), %rax
; AVX1-NEXT: subq %rax, %rdx
; AVX1-NEXT: addq %rcx, %rdx
@@ -366,10 +366,10 @@ define <4 x i64> @test_rem7_4i64(<4 x i64> %a) nounwind {
; AVX1-NEXT: vpextrq $1, %xmm0, %rcx
; AVX1-NEXT: movq %rcx, %rax
; AVX1-NEXT: imulq %rsi
-; AVX1-NEXT: movq %rdx, %rax
-; AVX1-NEXT: shrq $63, %rax
; AVX1-NEXT: sarq %rdx
-; AVX1-NEXT: addq %rax, %rdx
+; AVX1-NEXT: movq %rcx, %rax
+; AVX1-NEXT: sarq $63, %rax
+; AVX1-NEXT: subq %rax, %rdx
; AVX1-NEXT: leaq (,%rdx,8), %rax
; AVX1-NEXT: subq %rax, %rdx
; AVX1-NEXT: addq %rcx, %rdx
@@ -377,10 +377,10 @@ define <4 x i64> @test_rem7_4i64(<4 x i64> %a) nounwind {
; AVX1-NEXT: vmovq %xmm0, %rcx
; AVX1-NEXT: movq %rcx, %rax
; AVX1-NEXT: imulq %rsi
-; AVX1-NEXT: movq %rdx, %rax
-; AVX1-NEXT: shrq $63, %rax
; AVX1-NEXT: sarq %rdx
-; AVX1-NEXT: addq %rax, %rdx
+; AVX1-NEXT: movq %rcx, %rax
+; AVX1-NEXT: sarq $63, %rax
+; AVX1-NEXT: subq %rax, %rdx
; AVX1-NEXT: leaq (,%rdx,8), %rax
; AVX1-NEXT: subq %rax, %rdx
; AVX1-NEXT: addq %rcx, %rdx
@@ -396,10 +396,10 @@ define <4 x i64> @test_rem7_4i64(<4 x i64> %a) nounwind {
; AVX2-NEXT: movabsq $5270498306774157605, %rsi # imm = 0x4924924924924925
; AVX2-NEXT: movq %rcx, %rax
; AVX2-NEXT: imulq %rsi
-; AVX2-NEXT: movq %rdx, %rax
-; AVX2-NEXT: shrq $63, %rax
; AVX2-NEXT: sarq %rdx
-; AVX2-NEXT: addq %rax, %rdx
+; AVX2-NEXT: movq %rcx, %rax
+; AVX2-NEXT: sarq $63, %rax
+; AVX2-NEXT: subq %rax, %rdx
; AVX2-NEXT: leaq (,%rdx,8), %rax
; AVX2-NEXT: subq %rax, %rdx
; AVX2-NEXT: addq %rcx, %rdx
@@ -407,10 +407,10 @@ define <4 x i64> @test_rem7_4i64(<4 x i64> %a) nounwind {
; AVX2-NEXT: vmovq %xmm1, %rcx
; AVX2-NEXT: movq %rcx, %rax
; AVX2-NEXT: imulq %rsi
-; AVX2-NEXT: movq %rdx, %rax
-; AVX2-NEXT: shrq $63, %rax
; AVX2-NEXT: sarq %rdx
-; AVX2-NEXT: addq %rax, %rdx
+; AVX2-NEXT: movq %rcx, %rax
+; AVX2-NEXT: sarq $63, %rax
+; AVX2-NEXT: subq %rax, %rdx
; AVX2-NEXT: leaq (,%rdx,8), %rax
; AVX2-NEXT: subq %rax, %rdx
; AVX2-NEXT: addq %rcx, %rdx
@@ -419,10 +419,10 @@ define <4 x i64> @test_rem7_4i64(<4 x i64> %a) nounwind {
; AVX2-NEXT: vpextrq $1, %xmm0, %rcx
; AVX2-NEXT: movq %rcx, %rax
; AVX2-NEXT: imulq %rsi
-; AVX2-NEXT: movq %rdx, %rax
-; AVX2-NEXT: shrq $63, %rax
; AVX2-NEXT: sarq %rdx
-; AVX2-NEXT: addq %rax, %rdx
+; AVX2-NEXT: movq %rcx, %rax
+; AVX2-NEXT: sarq $63, %rax
+; AVX2-NEXT: subq %rax, %rdx
; AVX2-NEXT: leaq (,%rdx,8), %rax
; AVX2-NEXT: subq %rax, %rdx
; AVX2-NEXT: addq %rcx, %rdx
@@ -430,10 +430,10 @@ define <4 x i64> @test_rem7_4i64(<4 x i64> %a) nounwind {
; AVX2-NEXT: vmovq %xmm0, %rcx
; AVX2-NEXT: movq %rcx, %rax
; AVX2-NEXT: imulq %rsi
-; AVX2-NEXT: movq %rdx, %rax
-; AVX2-NEXT: shrq $63, %rax
; AVX2-NEXT: sarq %rdx
-; AVX2-NEXT: addq %rax, %rdx
+; AVX2-NEXT: movq %rcx, %rax
+; AVX2-NEXT: sarq $63, %rax
+; AVX2-NEXT: subq %rax, %rdx
; AVX2-NEXT: leaq (,%rdx,8), %rax
; AVX2-NEXT: subq %rax, %rdx
; AVX2-NEXT: addq %rcx, %rdx
diff --git a/llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll b/llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll
index b11756a5e3b4e..aadf341a954c2 100644
--- a/llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll
+++ b/llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll
@@ -10,68 +10,68 @@ define <8 x i64> @test_div7_8i64(<8 x i64> %a) nounwind {
; AVX-LABEL: test_div7_8i64:
; AVX: # %bb.0:
; AVX-NEXT: vextracti32x4 $3, %zmm0, %xmm1
-; AVX-NEXT: vpextrq $1, %xmm1, %rax
-; AVX-NEXT: movabsq $5270498306774157605, %rcx # imm = 0x4924924924924925
-; AVX-NEXT: imulq %rcx
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
+; AVX-NEXT: vpextrq $1, %xmm1, %rcx
+; AVX-NEXT: movabsq $5270498306774157605, %rsi # imm = 0x4924924924924925
+; AVX-NEXT: movq %rcx, %rax
+; AVX-NEXT: imulq %rsi
; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
+; AVX-NEXT: sarq $63, %rcx
+; AVX-NEXT: subq %rcx, %rdx
; AVX-NEXT: vmovq %rdx, %xmm2
-; AVX-NEXT: vmovq %xmm1, %rax
-; AVX-NEXT: imulq %rcx
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
+; AVX-NEXT: vmovq %xmm1, %rcx
+; AVX-NEXT: movq %rcx, %rax
+; AVX-NEXT: imulq %rsi
; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
+; AVX-NEXT: sarq $63, %rcx
+; AVX-NEXT: subq %rcx, %rdx
; AVX-NEXT: vmovq %rdx, %xmm1
; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX-NEXT: vextracti32x4 $2, %zmm0, %xmm2
-; AVX-NEXT: vpextrq $1, %xmm2, %rax
-; AVX-NEXT: imulq %rcx
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
+; AVX-NEXT: vpextrq $1, %xmm2, %rcx
+; AVX-NEXT: movq %rcx, %rax
+; AVX-NEXT: imulq %rsi
; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
+; AVX-NEXT: sarq $63, %rcx
+; AVX-NEXT: subq %rcx, %rdx
; AVX-NEXT: vmovq %rdx, %xmm3
-; AVX-NEXT: vmovq %xmm2, %rax
-; AVX-NEXT: imulq %rcx
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
+; AVX-NEXT: vmovq %xmm2, %rcx
+; AVX-NEXT: movq %rcx, %rax
+; AVX-NEXT: imulq %rsi
; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
+; AVX-NEXT: sarq $63, %rcx
+; AVX-NEXT: subq %rcx, %rdx
; AVX-NEXT: vmovq %rdx, %xmm2
; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
; AVX-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1
; AVX-NEXT: vextracti128 $1, %ymm0, %xmm2
-; AVX-NEXT: vpextrq $1, %xmm2, %rax
-; AVX-NEXT: imulq %rcx
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
+; AVX-NEXT: vpextrq $1, %xmm2, %rcx
+; AVX-NEXT: movq %rcx, %rax
+; AVX-NEXT: imulq %rsi
; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
+; AVX-NEXT: sarq $63, %rcx
+; AVX-NEXT: subq %rcx, %rdx
; AVX-NEXT: vmovq %rdx, %xmm3
-; AVX-NEXT: vmovq %xmm2, %rax
-; AVX-NEXT: imulq %rcx
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
+; AVX-NEXT: vmovq %xmm2, %rcx
+; AVX-NEXT: movq %rcx, %rax
+; AVX-NEXT: imulq %rsi
; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
+; AVX-NEXT: sarq $63, %rcx
+; AVX-NEXT: subq %rcx, %rdx
; AVX-NEXT: vmovq %rdx, %xmm2
; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
-; AVX-NEXT: vpextrq $1, %xmm0, %rax
-; AVX-NEXT: imulq %rcx
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
+; AVX-NEXT: vpextrq $1, %xmm0, %rcx
+; AVX-NEXT: movq %rcx, %rax
+; AVX-NEXT: imulq %rsi
; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
+; AVX-NEXT: sarq $63, %rcx
+; AVX-NEXT: subq %rcx, %rdx
; AVX-NEXT: vmovq %rdx, %xmm3
-; AVX-NEXT: vmovq %xmm0, %rax
-; AVX-NEXT: imulq %rcx
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
+; AVX-NEXT: vmovq %xmm0, %rcx
+; AVX-NEXT: movq %rcx, %rax
+; AVX-NEXT: imulq %rsi
; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
+; AVX-NEXT: sarq $63, %rcx
+; AVX-NEXT: subq %rcx, %rdx
; AVX-NEXT: vmovq %rdx, %xmm0
; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm3[0]
; AVX-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
@@ -282,10 +282,10 @@ define <8 x i64> @test_rem7_8i64(<8 x i64> %a) nounwind {
; AVX-NEXT: movabsq $5270498306774157605, %rsi # imm = 0x4924924924924925
; AVX-NEXT: movq %rcx, %rax
; AVX-NEXT: imulq %rsi
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
+; AVX-NEXT: movq %rcx, %rax
+; AVX-NEXT: sarq $63, %rax
+; AVX-NEXT: subq %rax, %rdx
; AVX-NEXT: leaq (,%rdx,8), %rax
; AVX-NEXT: subq %rax, %rdx
; AVX-NEXT: addq %rcx, %rdx
@@ -293,10 +293,10 @@ define <8 x i64> @test_rem7_8i64(<8 x i64> %a) nounwind {
; AVX-NEXT: vmovq %xmm1, %rcx
; AVX-NEXT: movq %rcx, %rax
; AVX-NEXT: imulq %rsi
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
+; AVX-NEXT: movq %rcx, %rax
+; AVX-NEXT: sarq $63, %rax
+; AVX-NEXT: subq %rax, %rdx
; AVX-NEXT: leaq (,%rdx,8), %rax
; AVX-NEXT: subq %rax, %rdx
; AVX-NEXT: addq %rcx, %rdx
@@ -306,10 +306,10 @@ define <8 x i64> @test_rem7_8i64(<8 x i64> %a) nounwind {
; AVX-NEXT: vpextrq $1, %xmm2, %rcx
; AVX-NEXT: movq %rcx, %rax
; AVX-NEXT: imulq %rsi
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
+; AVX-NEXT: movq %rcx, %rax
+; AVX-NEXT: sarq $63, %rax
+; AVX-NEXT: subq %rax, %rdx
; AVX-NEXT: leaq (,%rdx,8), %rax
; AVX-NEXT: subq %rax, %rdx
; AVX-NEXT: addq %rcx, %rdx
@@ -317,10 +317,10 @@ define <8 x i64> @test_rem7_8i64(<8 x i64> %a) nounwind {
; AVX-NEXT: vmovq %xmm2, %rcx
; AVX-NEXT: movq %rcx, %rax
; AVX-NEXT: imulq %rsi
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
+; AVX-NEXT: movq %rcx, %rax
+; AVX-NEXT: sarq $63, %rax
+; AVX-NEXT: subq %rax, %rdx
; AVX-NEXT: leaq (,%rdx,8), %rax
; AVX-NEXT: subq %rax, %rdx
; AVX-NEXT: addq %rcx, %rdx
@@ -331,10 +331,10 @@ define <8 x i64> @test_rem7_8i64(<8 x i64> %a) nounwind {
; AVX-NEXT: vpextrq $1, %xmm2, %rcx
; AVX-NEXT: movq %rcx, %rax
; AVX-NEXT: imulq %rsi
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
+; AVX-NEXT: movq %rcx, %rax
+; AVX-NEXT: sarq $63, %rax
+; AVX-NEXT: subq %rax, %rdx
; AVX-NEXT: leaq (,%rdx,8), %rax
; AVX-NEXT: subq %rax, %rdx
; AVX-NEXT: addq %rcx, %rdx
@@ -342,10 +342,10 @@ define <8 x i64> @test_rem7_8i64(<8 x i64> %a) nounwind {
; AVX-NEXT: vmovq %xmm2, %rcx
; AVX-NEXT: movq %rcx, %rax
; AVX-NEXT: imulq %rsi
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
+; AVX-NEXT: movq %rcx, %rax
+; AVX-NEXT: sarq $63, %rax
+; AVX-NEXT: subq %rax, %rdx
; AVX-NEXT: leaq (,%rdx,8), %rax
; AVX-NEXT: subq %rax, %rdx
; AVX-NEXT: addq %rcx, %rdx
@@ -354,10 +354,10 @@ define <8 x i64> @test_rem7_8i64(<8 x i64> %a) nounwind {
; AVX-NEXT: vpextrq $1, %xmm0, %rcx
; AVX-NEXT: movq %rcx, %rax
; AVX-NEXT: imulq %rsi
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
+; AVX-NEXT: movq %rcx, %rax
+; AVX-NEXT: sarq $63, %rax
+; AVX-NEXT: subq %rax, %rdx
; AVX-NEXT: leaq (,%rdx,8), %rax
; AVX-NEXT: subq %rax, %rdx
; AVX-NEXT: addq %rcx, %rdx
@@ -365,10 +365,10 @@ define <8 x i64> @test_rem7_8i64(<8 x i64> %a) nounwind {
; AVX-NEXT: vmovq %xmm0, %rcx
; AVX-NEXT: movq %rcx, %rax
; AVX-NEXT: imulq %rsi
-; AVX-NEXT: movq %rdx, %rax
-; AVX-NEXT: shrq $63, %rax
; AVX-NEXT: sarq %rdx
-; AVX-NEXT: addq %rax, %rdx
+; AVX-NEXT: movq %rcx, %rax
+; AVX-NEXT: sarq $63, %rax
+; AVX-NEXT: subq %rax, %rdx
; AVX-NEXT: leaq (,%rdx,8), %rax
; AVX-NEXT: subq %rax, %rdx
; AVX-NEXT: addq %rcx, %rdx
More information about the llvm-commits
mailing list