[llvm] [X86] Attempt to fold extract_vector_elt(logicop(x,y),i) -> extract_vector_elt(x,i) (PR #194581)
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Tue Apr 28 04:10:34 PDT 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-selectiondag
Author: Simon Pilgrim (RKSimon)
<details>
<summary>Changes</summary>
When extracting from logicops, we often don't need to extract the result if one of the element sources is identity (and(x,-1) -> x, or/xor(x,0) -> x etc.), so this patch uses SimplifyMultipleUseDemandedVectorElts to peek through to an underlying build_vector.
I had hoped to make this generic, but there's still a lot of yak shaving to deal with first, as usual - I've included the minimal x86-specific fixes:
* missing constant folding of (vXi1 logicop(bitcast(c1),bitcast(c2)))
* fold kshiftr(concat_vectors(x,y,z,w),c) -> concat_vectors(z,w,0,0)
Fixes #<!-- -->193700
---
Patch is 127.67 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/194581.diff
9 Files Affected:
- (modified) llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (+7)
- (modified) llvm/lib/Target/X86/X86ISelLowering.cpp (+26-3)
- (modified) llvm/test/CodeGen/X86/known-never-zero.ll (+2-2)
- (modified) llvm/test/CodeGen/X86/masked_store.ll (+68-138)
- (modified) llvm/test/CodeGen/X86/pr173924.ll (+19-20)
- (modified) llvm/test/CodeGen/X86/pr193700.ll (+22-92)
- (modified) llvm/test/CodeGen/X86/pr45563-2.ll (+107-109)
- (modified) llvm/test/CodeGen/X86/pr45833.ll (+97-101)
- (modified) llvm/test/CodeGen/X86/ucmp.ll (+819-822)
``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 407c42cdfe401..6ee1499e8e775 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -7767,6 +7767,13 @@ SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, const SDLoc &DL,
}
}
}
+ // Logic ops can be folded from raw integer bits - mainly for AVX512 masks.
+ if (ISD::isBitwiseLogicOp(Opcode) && isa<ConstantSDNode>(N1) &&
+ isa<ConstantSDNode>(N2)) {
+ if (SDValue Res = FoldConstantArithmetic(Opcode, DL, N1.getValueType(),
+ {N1, N2}, Flags))
+ return getBitcast(VT, Res);
+ }
}
// Fold (mul step_vector(C0), C1) to (step_vector(C0 * C1)).
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index c2d99a3d2b226..6b926b8131db5 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -47943,6 +47943,17 @@ static SDValue combineExtractVectorElt(SDNode *N, SelectionDAG &DAG,
return SDValue();
}
+ // Attempt to avoid multi-use src if we don't need anything from it.
+ // TODO: Generlize this and move to DAGCombine.
+ if (CIdx && ISD::isBitwiseLogicOp(InputVector.getOpcode())) {
+ unsigned Idx = CIdx->getZExtValue();
+ APInt DemandedElts = APInt::getOneBitSet(NumSrcElts, Idx);
+ if (SDValue NewVector = TLI.SimplifyMultipleUseDemandedVectorElts(
+ InputVector, DemandedElts, DAG))
+ if (NewVector.getOpcode() == ISD::BUILD_VECTOR)
+ return DAG.getNode(N->getOpcode(), dl, VT, NewVector, EltIdx);
+ }
+
// Detect mmx extraction of all bits as a i64. It works better as a bitcast.
if (VT == MVT::i64 && SrcVT == MVT::v1i64 &&
InputVector.getOpcode() == ISD::BITCAST &&
@@ -61966,10 +61977,10 @@ static SDValue combineKSHIFT(SDNode *N, SelectionDAG &DAG,
DAG.getConstant(NewCst, DL, SrcC->getValueType(0)));
}
- // Fold kshiftr(extract_subvector(X,C1),C2)
- // --> extract_subvector(kshiftr(X,C1+C2),0)
- // Fold kshiftr(kshiftr(X,C1),C2) --> kshiftr(X,C1+C2)
if (Opcode == X86ISD::KSHIFTR) {
+ // Fold kshiftr(extract_subvector(X,C1),C2)
+ // --> extract_subvector(kshiftr(X,C1+C2),0)
+ // Fold kshiftr(kshiftr(X,C1),C2) --> kshiftr(X,C1+C2)
if (Src.getOpcode() == ISD::EXTRACT_SUBVECTOR ||
Src.getOpcode() == X86ISD::KSHIFTR) {
SDValue Inner = Src.getOperand(0);
@@ -61982,6 +61993,18 @@ static SDValue combineKSHIFT(SDNode *N, SelectionDAG &DAG,
DAG.getVectorIdxConstant(0, DL));
}
}
+ // Fold kshiftr(concat_vectors(X,Y,Z,W),C)
+ // --> concat_vectors(Z,W,0,0) iff amount is whole subvector shift.
+ if (Src.getOpcode() == ISD::CONCAT_VECTORS &&
+ (Amt % Src.getOperand(0).getValueType().getVectorNumElements()) == 0) {
+ unsigned NumSubs = Src.getNumOperands();
+ EVT SubVT = Src.getOperand(0).getValueType();
+ unsigned Ofs = Amt / SubVT.getVectorNumElements();
+ SmallVector<SDValue, 4> SubOps(NumSubs, DAG.getConstant(0, DL, SubVT));
+ for (unsigned I = Ofs; I != NumSubs; ++I)
+ SubOps[I - Ofs] = Src.getOperand(I);
+ return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, SubOps);
+ }
}
// Fold kshift(logicop(X,C1),C2)
diff --git a/llvm/test/CodeGen/X86/known-never-zero.ll b/llvm/test/CodeGen/X86/known-never-zero.ll
index 5b3e60f9aa1e3..910f1375ed1ca 100644
--- a/llvm/test/CodeGen/X86/known-never-zero.ll
+++ b/llvm/test/CodeGen/X86/known-never-zero.ll
@@ -1624,7 +1624,7 @@ define i32 @udiv_known_nonzero_vec(<4 x i32> %xx, <4 x i32> %y, ptr %p) nounwind
; X64: # %bb.0:
; X64-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-NEXT: vpextrd $1, %xmm1, %ecx
-; X64-NEXT: vpextrd $1, %xmm0, %eax
+; X64-NEXT: movl $-1, %eax
; X64-NEXT: xorl %edx, %edx
; X64-NEXT: divl %ecx
; X64-NEXT: movl %eax, %ecx
@@ -1754,7 +1754,7 @@ define i32 @sdiv_known_nonzero_vec(<4 x i32> %xx, <4 x i32> %y, ptr %p) nounwind
; X64: # %bb.0:
; X64-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-NEXT: vpextrd $1, %xmm1, %ecx
-; X64-NEXT: vpextrd $1, %xmm0, %eax
+; X64-NEXT: movl $-1, %eax
; X64-NEXT: cltd
; X64-NEXT: idivl %ecx
; X64-NEXT: movl %eax, %ecx
diff --git a/llvm/test/CodeGen/X86/masked_store.ll b/llvm/test/CodeGen/X86/masked_store.ll
index 4db275d37cfaa..b647350543cf4 100644
--- a/llvm/test/CodeGen/X86/masked_store.ll
+++ b/llvm/test/CodeGen/X86/masked_store.ll
@@ -7051,10 +7051,10 @@ define void @store_v24i32_v24i32_stride6_vf4_only_even_numbered_elts(ptr %trigge
; AVX512VLBW-NEXT: vmovdqa64 (%rsi), %zmm0
; AVX512VLBW-NEXT: vmovdqa64 64(%rsi), %zmm1
; AVX512VLBW-NEXT: vpxor %xmm2, %xmm2, %xmm2
-; AVX512VLBW-NEXT: movw $21845, %ax ## imm = 0x5555
+; AVX512VLBW-NEXT: movl $5592405, %eax ## imm = 0x555555
; AVX512VLBW-NEXT: kmovd %eax, %k1
; AVX512VLBW-NEXT: vpcmpgtd (%rdi), %zmm2, %k1 {%k1}
-; AVX512VLBW-NEXT: movw $85, %ax
+; AVX512VLBW-NEXT: movl $85, %eax
; AVX512VLBW-NEXT: kmovd %eax, %k2
; AVX512VLBW-NEXT: vpcmpgtd 64(%rdi), %zmm2, %k2 {%k2}
; AVX512VLBW-NEXT: vmovdqu32 %zmm1, 64(%rdx) {%k2}
@@ -7070,10 +7070,10 @@ define void @store_v24i32_v24i32_stride6_vf4_only_even_numbered_elts(ptr %trigge
; X86-AVX512-NEXT: vmovdqa64 (%edx), %zmm0
; X86-AVX512-NEXT: vmovdqa64 64(%edx), %zmm1
; X86-AVX512-NEXT: vpxor %xmm2, %xmm2, %xmm2
-; X86-AVX512-NEXT: movw $21845, %dx ## imm = 0x5555
+; X86-AVX512-NEXT: movl $5592405, %edx ## imm = 0x555555
; X86-AVX512-NEXT: kmovd %edx, %k1
; X86-AVX512-NEXT: vpcmpgtd (%ecx), %zmm2, %k1 {%k1}
-; X86-AVX512-NEXT: movw $85, %dx
+; X86-AVX512-NEXT: movl $85, %edx
; X86-AVX512-NEXT: kmovd %edx, %k2
; X86-AVX512-NEXT: vpcmpgtd 64(%ecx), %zmm2, %k2 {%k2}
; X86-AVX512-NEXT: vmovdqu32 %zmm1, 64(%eax) {%k2}
@@ -7090,138 +7090,68 @@ define void @store_v24i32_v24i32_stride6_vf4_only_even_numbered_elts(ptr %trigge
; From https://reviews.llvm.org/rGf8d9097168b7#1165311
define void @undefshuffle(<8 x i1> %i0, ptr %src, ptr %dst) nounwind {
-; SSE2-LABEL: undefshuffle:
-; SSE2: ## %bb.0: ## %else
-; SSE2-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
-; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
-; SSE2-NEXT: movd %eax, %xmm0
-; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
-; SSE2-NEXT: pinsrw $1, %eax, %xmm0
-; SSE2-NEXT: pinsrw $2, -{{[0-9]+}}(%rsp), %xmm0
-; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
-; SSE2-NEXT: pinsrw $3, %eax, %xmm0
-; SSE2-NEXT: psllw $15, %xmm0
-; SSE2-NEXT: packsswb %xmm0, %xmm0
-; SSE2-NEXT: pmovmskb %xmm0, %eax
-; SSE2-NEXT: testb $1, %al
-; SSE2-NEXT: jne LBB39_1
-; SSE2-NEXT: ## %bb.2: ## %else23
-; SSE2-NEXT: testb $2, %al
-; SSE2-NEXT: jne LBB39_3
-; SSE2-NEXT: LBB39_4: ## %else25
-; SSE2-NEXT: testb $4, %al
-; SSE2-NEXT: jne LBB39_5
-; SSE2-NEXT: LBB39_6: ## %else27
-; SSE2-NEXT: testb $8, %al
-; SSE2-NEXT: jne LBB39_7
-; SSE2-NEXT: LBB39_8: ## %else29
-; SSE2-NEXT: testb $16, %al
-; SSE2-NEXT: jne LBB39_9
-; SSE2-NEXT: LBB39_10: ## %else31
-; SSE2-NEXT: testb $32, %al
-; SSE2-NEXT: jne LBB39_11
-; SSE2-NEXT: LBB39_12: ## %else33
-; SSE2-NEXT: testb $64, %al
-; SSE2-NEXT: jne LBB39_13
-; SSE2-NEXT: LBB39_14: ## %else35
-; SSE2-NEXT: testb $-128, %al
-; SSE2-NEXT: jne LBB39_15
-; SSE2-NEXT: LBB39_16: ## %else37
-; SSE2-NEXT: retq
-; SSE2-NEXT: LBB39_1: ## %cond.store
-; SSE2-NEXT: movl $0, (%rsi)
-; SSE2-NEXT: testb $2, %al
-; SSE2-NEXT: je LBB39_4
-; SSE2-NEXT: LBB39_3: ## %cond.store24
-; SSE2-NEXT: movl $0, 4(%rsi)
-; SSE2-NEXT: testb $4, %al
-; SSE2-NEXT: je LBB39_6
-; SSE2-NEXT: LBB39_5: ## %cond.store26
-; SSE2-NEXT: movl $0, 8(%rsi)
-; SSE2-NEXT: testb $8, %al
-; SSE2-NEXT: je LBB39_8
-; SSE2-NEXT: LBB39_7: ## %cond.store28
-; SSE2-NEXT: movl $0, 12(%rsi)
-; SSE2-NEXT: testb $16, %al
-; SSE2-NEXT: je LBB39_10
-; SSE2-NEXT: LBB39_9: ## %cond.store30
-; SSE2-NEXT: movl $0, 16(%rsi)
-; SSE2-NEXT: testb $32, %al
-; SSE2-NEXT: je LBB39_12
-; SSE2-NEXT: LBB39_11: ## %cond.store32
-; SSE2-NEXT: movl $0, 20(%rsi)
-; SSE2-NEXT: testb $64, %al
-; SSE2-NEXT: je LBB39_14
-; SSE2-NEXT: LBB39_13: ## %cond.store34
-; SSE2-NEXT: movl $0, 24(%rsi)
-; SSE2-NEXT: testb $-128, %al
-; SSE2-NEXT: je LBB39_16
-; SSE2-NEXT: LBB39_15: ## %cond.store36
-; SSE2-NEXT: movl $0, 28(%rsi)
-; SSE2-NEXT: retq
-;
-; SSE4-LABEL: undefshuffle:
-; SSE4: ## %bb.0: ## %else
-; SSE4-NEXT: psllw $15, %xmm0
-; SSE4-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; SSE4-NEXT: packsswb %xmm0, %xmm0
-; SSE4-NEXT: pmovmskb %xmm0, %eax
-; SSE4-NEXT: testb $1, %al
-; SSE4-NEXT: jne LBB39_1
-; SSE4-NEXT: ## %bb.2: ## %else23
-; SSE4-NEXT: testb $2, %al
-; SSE4-NEXT: jne LBB39_3
-; SSE4-NEXT: LBB39_4: ## %else25
-; SSE4-NEXT: testb $4, %al
-; SSE4-NEXT: jne LBB39_5
-; SSE4-NEXT: LBB39_6: ## %else27
-; SSE4-NEXT: testb $8, %al
-; SSE4-NEXT: jne LBB39_7
-; SSE4-NEXT: LBB39_8: ## %else29
-; SSE4-NEXT: testb $16, %al
-; SSE4-NEXT: jne LBB39_9
-; SSE4-NEXT: LBB39_10: ## %else31
-; SSE4-NEXT: testb $32, %al
-; SSE4-NEXT: jne LBB39_11
-; SSE4-NEXT: LBB39_12: ## %else33
-; SSE4-NEXT: testb $64, %al
-; SSE4-NEXT: jne LBB39_13
-; SSE4-NEXT: LBB39_14: ## %else35
-; SSE4-NEXT: testb $-128, %al
-; SSE4-NEXT: jne LBB39_15
-; SSE4-NEXT: LBB39_16: ## %else37
-; SSE4-NEXT: retq
-; SSE4-NEXT: LBB39_1: ## %cond.store
-; SSE4-NEXT: movl $0, (%rsi)
-; SSE4-NEXT: testb $2, %al
-; SSE4-NEXT: je LBB39_4
-; SSE4-NEXT: LBB39_3: ## %cond.store24
-; SSE4-NEXT: movl $0, 4(%rsi)
-; SSE4-NEXT: testb $4, %al
-; SSE4-NEXT: je LBB39_6
-; SSE4-NEXT: LBB39_5: ## %cond.store26
-; SSE4-NEXT: movl $0, 8(%rsi)
-; SSE4-NEXT: testb $8, %al
-; SSE4-NEXT: je LBB39_8
-; SSE4-NEXT: LBB39_7: ## %cond.store28
-; SSE4-NEXT: movl $0, 12(%rsi)
-; SSE4-NEXT: testb $16, %al
-; SSE4-NEXT: je LBB39_10
-; SSE4-NEXT: LBB39_9: ## %cond.store30
-; SSE4-NEXT: movl $0, 16(%rsi)
-; SSE4-NEXT: testb $32, %al
-; SSE4-NEXT: je LBB39_12
-; SSE4-NEXT: LBB39_11: ## %cond.store32
-; SSE4-NEXT: movl $0, 20(%rsi)
-; SSE4-NEXT: testb $64, %al
-; SSE4-NEXT: je LBB39_14
-; SSE4-NEXT: LBB39_13: ## %cond.store34
-; SSE4-NEXT: movl $0, 24(%rsi)
-; SSE4-NEXT: testb $-128, %al
-; SSE4-NEXT: je LBB39_16
-; SSE4-NEXT: LBB39_15: ## %cond.store36
-; SSE4-NEXT: movl $0, 28(%rsi)
-; SSE4-NEXT: retq
+; SSE-LABEL: undefshuffle:
+; SSE: ## %bb.0: ## %else
+; SSE-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
+; SSE-NEXT: psllw $15, %xmm0
+; SSE-NEXT: packsswb %xmm0, %xmm0
+; SSE-NEXT: pmovmskb %xmm0, %eax
+; SSE-NEXT: testb $1, %al
+; SSE-NEXT: jne LBB39_1
+; SSE-NEXT: ## %bb.2: ## %else23
+; SSE-NEXT: testb $2, %al
+; SSE-NEXT: jne LBB39_3
+; SSE-NEXT: LBB39_4: ## %else25
+; SSE-NEXT: testb $4, %al
+; SSE-NEXT: jne LBB39_5
+; SSE-NEXT: LBB39_6: ## %else27
+; SSE-NEXT: testb $8, %al
+; SSE-NEXT: jne LBB39_7
+; SSE-NEXT: LBB39_8: ## %else29
+; SSE-NEXT: testb $16, %al
+; SSE-NEXT: jne LBB39_9
+; SSE-NEXT: LBB39_10: ## %else31
+; SSE-NEXT: testb $32, %al
+; SSE-NEXT: jne LBB39_11
+; SSE-NEXT: LBB39_12: ## %else33
+; SSE-NEXT: testb $64, %al
+; SSE-NEXT: jne LBB39_13
+; SSE-NEXT: LBB39_14: ## %else35
+; SSE-NEXT: testb $-128, %al
+; SSE-NEXT: jne LBB39_15
+; SSE-NEXT: LBB39_16: ## %else37
+; SSE-NEXT: retq
+; SSE-NEXT: LBB39_1: ## %cond.store
+; SSE-NEXT: movl $0, (%rsi)
+; SSE-NEXT: testb $2, %al
+; SSE-NEXT: je LBB39_4
+; SSE-NEXT: LBB39_3: ## %cond.store24
+; SSE-NEXT: movl $0, 4(%rsi)
+; SSE-NEXT: testb $4, %al
+; SSE-NEXT: je LBB39_6
+; SSE-NEXT: LBB39_5: ## %cond.store26
+; SSE-NEXT: movl $0, 8(%rsi)
+; SSE-NEXT: testb $8, %al
+; SSE-NEXT: je LBB39_8
+; SSE-NEXT: LBB39_7: ## %cond.store28
+; SSE-NEXT: movl $0, 12(%rsi)
+; SSE-NEXT: testb $16, %al
+; SSE-NEXT: je LBB39_10
+; SSE-NEXT: LBB39_9: ## %cond.store30
+; SSE-NEXT: movl $0, 16(%rsi)
+; SSE-NEXT: testb $32, %al
+; SSE-NEXT: je LBB39_12
+; SSE-NEXT: LBB39_11: ## %cond.store32
+; SSE-NEXT: movl $0, 20(%rsi)
+; SSE-NEXT: testb $64, %al
+; SSE-NEXT: je LBB39_14
+; SSE-NEXT: LBB39_13: ## %cond.store34
+; SSE-NEXT: movl $0, 24(%rsi)
+; SSE-NEXT: testb $-128, %al
+; SSE-NEXT: je LBB39_16
+; SSE-NEXT: LBB39_15: ## %cond.store36
+; SSE-NEXT: movl $0, 28(%rsi)
+; SSE-NEXT: retq
;
; AVX1-LABEL: undefshuffle:
; AVX1: ## %bb.0:
@@ -7234,8 +7164,8 @@ define void @undefshuffle(<8 x i1> %i0, ptr %src, ptr %dst) nounwind {
;
; AVX2-LABEL: undefshuffle:
; AVX2: ## %bb.0:
-; AVX2-NEXT: ## kill: def $xmm0 killed $xmm0 def $ymm0
-; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,u,u,2,3,u,u,4,5,u,u,6,7,u,u],zero,zero,ymm0[u,u],zero,zero,ymm0[u,u],zero,zero,ymm0[u,u],zero,zero,ymm0[u,u]
+; AVX2-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
+; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX2-NEXT: vpslld $31, %ymm0, %ymm0
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vpmaskmovd %ymm1, %ymm0, (%rsi)
diff --git a/llvm/test/CodeGen/X86/pr173924.ll b/llvm/test/CodeGen/X86/pr173924.ll
index a25f62a0ab071..d86b82edb7249 100644
--- a/llvm/test/CodeGen/X86/pr173924.ll
+++ b/llvm/test/CodeGen/X86/pr173924.ll
@@ -6,29 +6,28 @@ define i256 @PR173924(<8 x i256> %a0) {
; CHECK-LABEL: PR173924:
; CHECK: # %bb.0:
; CHECK-NEXT: movq %rdi, %rax
-; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rdi
-; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rdx
-; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rcx
-; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %r8
-; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %r10
-; CHECK-NEXT: vmovd {{.*#+}} xmm0 = [1,0,0,0]
-; CHECK-NEXT: vpand {{[0-9]+}}(%rsp), %ymm0, %ymm0
-; CHECK-NEXT: vmovq %xmm0, %r11
+; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %ecx
+; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %edi
+; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %r8d
+; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %edx
+; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %r10d
+; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %r11d
+; CHECK-NEXT: andl $1, %r11d
+; CHECK-NEXT: andl $1, %r9d
+; CHECK-NEXT: addl %r11d, %r9d
; CHECK-NEXT: andl $1, %r10d
-; CHECK-NEXT: andl $1, %esi
-; CHECK-NEXT: addq %r10, %rsi
-; CHECK-NEXT: andl $1, %r8d
-; CHECK-NEXT: andl $1, %ecx
-; CHECK-NEXT: addq %r8, %rcx
-; CHECK-NEXT: addq %rsi, %rcx
; CHECK-NEXT: andl $1, %edx
-; CHECK-NEXT: addq %r11, %rdx
+; CHECK-NEXT: addl %r10d, %edx
+; CHECK-NEXT: addl %r9d, %edx
+; CHECK-NEXT: andl $1, %r8d
+; CHECK-NEXT: andl $1, %esi
+; CHECK-NEXT: addl %r8d, %esi
; CHECK-NEXT: andl $1, %edi
-; CHECK-NEXT: andl $1, %r9d
-; CHECK-NEXT: addq %rdi, %r9
-; CHECK-NEXT: addq %rdx, %r9
-; CHECK-NEXT: addq %rcx, %r9
-; CHECK-NEXT: vmovq %r9, %xmm0
+; CHECK-NEXT: andl $1, %ecx
+; CHECK-NEXT: addl %edi, %ecx
+; CHECK-NEXT: addl %esi, %ecx
+; CHECK-NEXT: addl %edx, %ecx
+; CHECK-NEXT: vmovd %ecx, %xmm0
; CHECK-NEXT: vmovdqu %ymm0, (%rax)
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/pr193700.ll b/llvm/test/CodeGen/X86/pr193700.ll
index 43aede5a795ee..6e62295766c98 100644
--- a/llvm/test/CodeGen/X86/pr193700.ll
+++ b/llvm/test/CodeGen/X86/pr193700.ll
@@ -1,57 +1,19 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64 | FileCheck %s --check-prefixes=CHECK,SSE,SSE2
-; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=CHECK,SSE,SSE42
-; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=CHECK,AVX,AVX2
-; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v2 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s
define i128 @hot_end_mask(ptr %token, i32 %end) {
-; SSE2-LABEL: hot_end_mask:
-; SSE2: # %bb.0:
-; SSE2-NEXT: # kill: def $esi killed $esi def $rsi
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = mem[2,3,2,3]
-; SSE2-NEXT: movl (%rdi), %eax
-; SSE2-NEXT: movq %xmm0, %rdx
-; SSE2-NEXT: shlq $32, %rsi
-; SSE2-NEXT: orq %rsi, %rax
-; SSE2-NEXT: movq %xmm0, 8(%rdi)
-; SSE2-NEXT: movq %rax, (%rdi)
-; SSE2-NEXT: retq
-;
-; SSE42-LABEL: hot_end_mask:
-; SSE42: # %bb.0:
-; SSE42-NEXT: # kill: def $esi killed $esi def $rsi
-; SSE42-NEXT: movdqa (%rdi), %xmm0
-; SSE42-NEXT: pextrq $1, %xmm0, %rdx
-; SSE42-NEXT: movd %xmm0, %eax
-; SSE42-NEXT: shlq $32, %rsi
-; SSE42-NEXT: pextrq $1, %xmm0, 8(%rdi)
-; SSE42-NEXT: orq %rsi, %rax
-; SSE42-NEXT: movq %rax, (%rdi)
-; SSE42-NEXT: retq
-;
-; AVX2-LABEL: hot_end_mask:
-; AVX2: # %bb.0:
-; AVX2-NEXT: vmovdqa (%rdi), %xmm0
-; AVX2-NEXT: vpextrq $1, %xmm0, %rdx
-; AVX2-NEXT: # kill: def $esi killed $esi def $rsi
-; AVX2-NEXT: vmovd %xmm0, %eax
-; AVX2-NEXT: shlq $32, %rsi
-; AVX2-NEXT: orq %rsi, %rax
-; AVX2-NEXT: vpextrq $1, %xmm0, 8(%rdi)
-; AVX2-NEXT: movq %rax, (%rdi)
-; AVX2-NEXT: retq
-;
-; AVX512-LABEL: hot_end_mask:
-; AVX512: # %bb.0:
-; AVX512-NEXT: # kill: def $esi killed $esi def $rsi
-; AVX512-NEXT: vmovdqa (%rdi), %xmm0
-; AVX512-NEXT: vpextrq $1, %xmm0, %rdx
-; AVX512-NEXT: vmovd %xmm0, %eax
-; AVX512-NEXT: shlq $32, %rsi
-; AVX512-NEXT: orq %rsi, %rax
-; AVX512-NEXT: vpextrq $1, %xmm0, 8(%rdi)
-; AVX512-NEXT: movq %rax, (%rdi)
-; AVX512-NEXT: retq
+; CHECK-LABEL: hot_end_mask:
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
+; CHECK-NEXT: movq 8(%rdi), %rdx
+; CHECK-NEXT: movl (%rdi), %eax
+; CHECK-NEXT: shlq $32, %rsi
+; CHECK-NEXT: orq %rsi, %rax
+; CHECK-NEXT: movq %rax, (%rdi)
+; CHECK-NEXT: retq
%load = load i128, ptr %token, align 16
%mask = and i128 %load, -18446744069414584321
%zext = zext i32 %end to i128
@@ -62,44 +24,15 @@ define i128 @hot_end_mask(ptr %token, i32 %end) {
}
define i128 @hot_start_mask(ptr %token, i32 %start) {
-; SSE2-LABEL: hot_start_mask:
-; SSE2: # %bb.0:
-; SSE2-NEXT: movdqa (%rdi), %xmm0
-; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; SSE2-NEXT: movq %xmm1, %rdx
-; SSE2-NEXT: movq %xmm0, %rcx
-; SSE2-NEXT: movl %esi, %eax
-; SSE2-NEXT: orq %rcx, %rax
-; SSE2-NEXT: movq %xmm1, 8(%rdi)
-; SSE2-NEXT: movq %rax, (%rdi)
-; SSE2-NEXT: retq
-;
-; SSE42-LABEL: hot_start_mask:
-; SSE42: # %bb.0:
-; SSE42-NEXT: movdqa (%rdi), %xmm0
-; SSE42-NEXT: pxor %xmm1, %xmm1
-; SSE42-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3,4,5,6,7]
-; SSE42-NEXT: movq %xmm1, %rcx
-; SSE42-NEXT: pextrq $1, %xmm0, %rdx
-; SSE42-NEXT: movl %esi, %eax
-; SSE42-NEXT: pextrq $1, %xmm0, 8(%rdi)
-; SSE42-NEXT: orq %rcx, %rax
-; SSE42-NEXT: movq %rax, (%rdi)
-; SSE42-NEXT: retq
-;
-; AVX-LABEL: hot_start_mask:
-; AVX: # %bb.0:
-; AVX-NEXT: vmovdqa (%rdi), %xmm0
-; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; AVX-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0],xmm0[1,2,3]
-; AVX-NEXT: vmovq %xmm1, %rcx
-; AVX-NEXT: vpextrq $1, %xmm0, %rdx
-; AVX-NEXT: movl %esi, %eax
-; AVX-NEXT: orq %rcx, %rax
-; AVX-NEXT: vpextrq $1, %xmm0, 8(%rdi)
-; AVX-NEXT: movq %rax, (%rdi)
-; AVX-NEXT: retq
+; CHECK-LABEL: hot_start_mask:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movq 8(%rdi), %rdx
+; CHECK-NEXT: movl 4(%rdi), %ecx
+; CHECK-NEXT: shlq $32, %rcx
+; CHECK-NEXT: movl %esi, %eax
+; CHECK-NEXT: orq %rcx, %rax
+; CHECK-NEXT: movq %rax, (%rdi)
+; CHECK-NEXT: retq
%load = load i128, ptr %token, align 16
%mask = and i128 %load, -4294967296
%zext = zext i32 %start to i128
@@ -107,6 +40,3 @@ define i128 @hot_start_mask(ptr...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/194581
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