[llvm] [llvm][RISCV] Promote VECREDUCE_FADD to f32 on zvfhmin and zvfbfmin (PR #194587)
Brandon Wu via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 28 03:50:05 PDT 2026
https://github.com/4vtomat updated https://github.com/llvm/llvm-project/pull/194587
>From 6020ba4f860e838797188b7b49061ab7e72d0a9c Mon Sep 17 00:00:00 2001
From: Brandon Wu <brandon.wu at sifive.com>
Date: Tue, 28 Apr 2026 17:29:22 +0800
Subject: [PATCH 1/3] pre commit test
---
.../RISCV/rvv/fixed-vectors-reduction-fp.ll | 5361 +++++++++++++++--
1 file changed, 4994 insertions(+), 367 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
index 1ccc52be36215..443aec860b83f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
@@ -1,247 +1,3530 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,RV32 %s
-; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,RV64 %s
+; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,ZVFH,RV32 %s
+; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,ZVFH,RV64 %s
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfhmin,+f,+d -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,ZVFHMIN,RV32,ZVFHMIN32 %s
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfhmin,+f,+d -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,ZVFHMIN,RV64,ZVFHMIN64 %s
define half @vreduce_fadd_v1f16(<1 x half> %v, half %s) {
-; CHECK-LABEL: vreduce_fadd_v1f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; CHECK-NEXT: vfmv.f.s fa5, v8
-; CHECK-NEXT: fadd.h fa0, fa0, fa5
-; CHECK-NEXT: ret
+; ZVFH-LABEL: vreduce_fadd_v1f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFH-NEXT: vfmv.f.s fa5, v8
+; ZVFH-NEXT: fadd.h fa0, fa0, fa5
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: vreduce_fadd_v1f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vmv.x.s a0, v8
+; ZVFHMIN-NEXT: fmv.h.x fa5, a0
+; ZVFHMIN-NEXT: fadd.h fa0, fa0, fa5
+; ZVFHMIN-NEXT: ret
%red = call reassoc half @llvm.vector.reduce.fadd.v1f16(half %s, <1 x half> %v)
ret half %red
}
define half @vreduce_ord_fadd_v1f16(<1 x half> %v, half %s) {
-; CHECK-LABEL: vreduce_ord_fadd_v1f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vfredosum.vs v8, v8, v9
-; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: vreduce_ord_fadd_v1f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; ZVFH-NEXT: vfmv.s.f v9, fa0
+; ZVFH-NEXT: vfredosum.vs v8, v8, v9
+; ZVFH-NEXT: vfmv.f.s fa0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: vreduce_ord_fadd_v1f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vmv.x.s a0, v8
+; ZVFHMIN-NEXT: fmv.h.x fa5, a0
+; ZVFHMIN-NEXT: fadd.h fa0, fa0, fa5
+; ZVFHMIN-NEXT: ret
%red = call half @llvm.vector.reduce.fadd.v1f16(half %s, <1 x half> %v)
ret half %red
}
define half @vreduce_fadd_v2f16(ptr %x, half %s) {
-; CHECK-LABEL: vreduce_fadd_v2f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vfredusum.vs v8, v8, v9
-; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: vreduce_fadd_v2f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vfmv.s.f v9, fa0
+; ZVFH-NEXT: vfredusum.vs v8, v8, v9
+; ZVFH-NEXT: vfmv.f.s fa0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: vreduce_fadd_v2f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a0)
+; ZVFHMIN-NEXT: vmv.x.s a0, v8
+; ZVFHMIN-NEXT: vslidedown.vi v8, v8, 1
+; ZVFHMIN-NEXT: fmv.h.x fa5, a0
+; ZVFHMIN-NEXT: vmv.x.s a0, v8
+; ZVFHMIN-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN-NEXT: fadd.h fa0, fa0, fa5
+; ZVFHMIN-NEXT: ret
%v = load <2 x half>, ptr %x
%red = call reassoc half @llvm.vector.reduce.fadd.v2f16(half %s, <2 x half> %v)
ret half %red
}
define half @vreduce_ord_fadd_v2f16(ptr %x, half %s) {
-; CHECK-LABEL: vreduce_ord_fadd_v2f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vfredosum.vs v8, v8, v9
-; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: vreduce_ord_fadd_v2f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vfmv.s.f v9, fa0
+; ZVFH-NEXT: vfredosum.vs v8, v8, v9
+; ZVFH-NEXT: vfmv.f.s fa0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: vreduce_ord_fadd_v2f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a0)
+; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 1
+; ZVFHMIN-NEXT: vmv.x.s a0, v8
+; ZVFHMIN-NEXT: fmv.h.x fa5, a0
+; ZVFHMIN-NEXT: vmv.x.s a0, v9
+; ZVFHMIN-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN-NEXT: fadd.h fa5, fa0, fa5
+; ZVFHMIN-NEXT: fadd.h fa0, fa5, fa4
+; ZVFHMIN-NEXT: ret
%v = load <2 x half>, ptr %x
%red = call half @llvm.vector.reduce.fadd.v2f16(half %s, <2 x half> %v)
ret half %red
}
define half @vreduce_fadd_v4f16(ptr %x, half %s) {
-; CHECK-LABEL: vreduce_fadd_v4f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vfredusum.vs v8, v8, v9
-; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: vreduce_fadd_v4f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vfmv.s.f v9, fa0
+; ZVFH-NEXT: vfredusum.vs v8, v8, v9
+; ZVFH-NEXT: vfmv.f.s fa0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: vreduce_fadd_v4f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a0)
+; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 3
+; ZVFHMIN-NEXT: vmv.x.s a0, v8
+; ZVFHMIN-NEXT: fmv.h.x fa5, a0
+; ZVFHMIN-NEXT: vmv.x.s a0, v9
+; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 2
+; ZVFHMIN-NEXT: vslidedown.vi v8, v8, 1
+; ZVFHMIN-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN-NEXT: vmv.x.s a0, v9
+; ZVFHMIN-NEXT: fmv.h.x fa3, a0
+; ZVFHMIN-NEXT: vmv.x.s a0, v8
+; ZVFHMIN-NEXT: fmv.h.x fa2, a0
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa2
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa3
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN-NEXT: fadd.h fa0, fa0, fa5
+; ZVFHMIN-NEXT: ret
%v = load <4 x half>, ptr %x
%red = call reassoc half @llvm.vector.reduce.fadd.v4f16(half %s, <4 x half> %v)
ret half %red
}
define half @vreduce_ord_fadd_v4f16(ptr %x, half %s) {
-; CHECK-LABEL: vreduce_ord_fadd_v4f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vfredosum.vs v8, v8, v9
-; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: vreduce_ord_fadd_v4f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vfmv.s.f v9, fa0
+; ZVFH-NEXT: vfredosum.vs v8, v8, v9
+; ZVFH-NEXT: vfmv.f.s fa0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: vreduce_ord_fadd_v4f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a0)
+; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 3
+; ZVFHMIN-NEXT: vmv.x.s a0, v8
+; ZVFHMIN-NEXT: fmv.h.x fa5, a0
+; ZVFHMIN-NEXT: vmv.x.s a0, v9
+; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 2
+; ZVFHMIN-NEXT: vslidedown.vi v8, v8, 1
+; ZVFHMIN-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN-NEXT: vmv.x.s a0, v9
+; ZVFHMIN-NEXT: fmv.h.x fa3, a0
+; ZVFHMIN-NEXT: vmv.x.s a0, v8
+; ZVFHMIN-NEXT: fmv.h.x fa2, a0
+; ZVFHMIN-NEXT: fadd.h fa5, fa0, fa5
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa2
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa3
+; ZVFHMIN-NEXT: fadd.h fa0, fa5, fa4
+; ZVFHMIN-NEXT: ret
%v = load <4 x half>, ptr %x
%red = call half @llvm.vector.reduce.fadd.v4f16(half %s, <4 x half> %v)
ret half %red
}
define half @vreduce_fadd_v7f16(ptr %x, half %s) {
-; CHECK-LABEL: vreduce_fadd_v7f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 7, e16, m1, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vfredusum.vs v8, v8, v9
-; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: vreduce_fadd_v7f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 7, e16, m1, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vfmv.s.f v9, fa0
+; ZVFH-NEXT: vfredusum.vs v8, v8, v9
+; ZVFH-NEXT: vfmv.f.s fa0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: vreduce_fadd_v7f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 7, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a0)
+; ZVFHMIN-NEXT: vmv.x.s a0, v8
+; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 1
+; ZVFHMIN-NEXT: fmv.h.x fa5, a0
+; ZVFHMIN-NEXT: vmv.x.s a0, v9
+; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 2
+; ZVFHMIN-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN-NEXT: vmv.x.s a0, v9
+; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 3
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN-NEXT: vmv.x.s a0, v9
+; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 4
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN-NEXT: vmv.x.s a0, v9
+; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 5
+; ZVFHMIN-NEXT: vslidedown.vi v8, v8, 6
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN-NEXT: vmv.x.s a0, v9
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN-NEXT: vmv.x.s a0, v8
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN-NEXT: fadd.h fa0, fa0, fa5
+; ZVFHMIN-NEXT: ret
%v = load <7 x half>, ptr %x
%red = call reassoc half @llvm.vector.reduce.fadd.v7f16(half %s, <7 x half> %v)
ret half %red
}
define half @vreduce_fadd_v8f16(ptr %x, half %s) {
-; CHECK-LABEL: vreduce_fadd_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vfredusum.vs v8, v8, v9
-; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: vreduce_fadd_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vfmv.s.f v9, fa0
+; ZVFH-NEXT: vfredusum.vs v8, v8, v9
+; ZVFH-NEXT: vfmv.f.s fa0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: vreduce_fadd_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a0)
+; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 7
+; ZVFHMIN-NEXT: vmv.x.s a0, v8
+; ZVFHMIN-NEXT: fmv.h.x fa5, a0
+; ZVFHMIN-NEXT: vmv.x.s a0, v9
+; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 6
+; ZVFHMIN-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN-NEXT: vmv.x.s a0, v9
+; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 5
+; ZVFHMIN-NEXT: fmv.h.x fa3, a0
+; ZVFHMIN-NEXT: vmv.x.s a0, v9
+; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 4
+; ZVFHMIN-NEXT: fmv.h.x fa2, a0
+; ZVFHMIN-NEXT: vmv.x.s a0, v9
+; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 3
+; ZVFHMIN-NEXT: fmv.h.x fa1, a0
+; ZVFHMIN-NEXT: vmv.x.s a0, v9
+; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 2
+; ZVFHMIN-NEXT: vslidedown.vi v8, v8, 1
+; ZVFHMIN-NEXT: fmv.h.x ft0, a0
+; ZVFHMIN-NEXT: vmv.x.s a0, v9
+; ZVFHMIN-NEXT: fmv.h.x ft1, a0
+; ZVFHMIN-NEXT: vmv.x.s a0, v8
+; ZVFHMIN-NEXT: fmv.h.x ft2, a0
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft2
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft1
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft0
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa1
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa2
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa3
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN-NEXT: fadd.h fa0, fa0, fa5
+; ZVFHMIN-NEXT: ret
%v = load <8 x half>, ptr %x
%red = call reassoc half @llvm.vector.reduce.fadd.v8f16(half %s, <8 x half> %v)
ret half %red
}
define half @vreduce_ord_fadd_v8f16(ptr %x, half %s) {
-; CHECK-LABEL: vreduce_ord_fadd_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vfredosum.vs v8, v8, v9
-; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: vreduce_ord_fadd_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vfmv.s.f v9, fa0
+; ZVFH-NEXT: vfredosum.vs v8, v8, v9
+; ZVFH-NEXT: vfmv.f.s fa0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: vreduce_ord_fadd_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a0)
+; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 7
+; ZVFHMIN-NEXT: vmv.x.s a0, v8
+; ZVFHMIN-NEXT: fmv.h.x fa5, a0
+; ZVFHMIN-NEXT: vmv.x.s a0, v9
+; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 6
+; ZVFHMIN-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN-NEXT: vmv.x.s a0, v9
+; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 5
+; ZVFHMIN-NEXT: fmv.h.x fa3, a0
+; ZVFHMIN-NEXT: vmv.x.s a0, v9
+; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 4
+; ZVFHMIN-NEXT: fmv.h.x fa2, a0
+; ZVFHMIN-NEXT: vmv.x.s a0, v9
+; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 3
+; ZVFHMIN-NEXT: fmv.h.x fa1, a0
+; ZVFHMIN-NEXT: vmv.x.s a0, v9
+; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 2
+; ZVFHMIN-NEXT: vslidedown.vi v8, v8, 1
+; ZVFHMIN-NEXT: fmv.h.x ft0, a0
+; ZVFHMIN-NEXT: vmv.x.s a0, v9
+; ZVFHMIN-NEXT: fmv.h.x ft1, a0
+; ZVFHMIN-NEXT: vmv.x.s a0, v8
+; ZVFHMIN-NEXT: fmv.h.x ft2, a0
+; ZVFHMIN-NEXT: fadd.h fa5, fa0, fa5
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft2
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft1
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft0
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa1
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa2
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa3
+; ZVFHMIN-NEXT: fadd.h fa0, fa5, fa4
+; ZVFHMIN-NEXT: ret
%v = load <8 x half>, ptr %x
%red = call half @llvm.vector.reduce.fadd.v8f16(half %s, <8 x half> %v)
ret half %red
}
define half @vreduce_fadd_v16f16(ptr %x, half %s) {
-; CHECK-LABEL: vreduce_fadd_v16f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vfmv.s.f v10, fa0
-; CHECK-NEXT: vfredusum.vs v8, v8, v10
-; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: vreduce_fadd_v16f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vfmv.s.f v10, fa0
+; ZVFH-NEXT: vfredusum.vs v8, v8, v10
+; ZVFH-NEXT: vfmv.f.s fa0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: vreduce_fadd_v16f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a0)
+; ZVFHMIN-NEXT: vslidedown.vi v10, v8, 15
+; ZVFHMIN-NEXT: vslidedown.vi v12, v8, 14
+; ZVFHMIN-NEXT: vslidedown.vi v14, v8, 13
+; ZVFHMIN-NEXT: vmv.x.s a0, v10
+; ZVFHMIN-NEXT: vslidedown.vi v10, v8, 12
+; ZVFHMIN-NEXT: vmv.x.s a1, v12
+; ZVFHMIN-NEXT: vslidedown.vi v12, v8, 11
+; ZVFHMIN-NEXT: vmv.x.s a2, v14
+; ZVFHMIN-NEXT: vslidedown.vi v14, v8, 10
+; ZVFHMIN-NEXT: vmv.x.s a3, v10
+; ZVFHMIN-NEXT: vslidedown.vi v10, v8, 9
+; ZVFHMIN-NEXT: vmv.x.s a4, v12
+; ZVFHMIN-NEXT: vslidedown.vi v12, v8, 8
+; ZVFHMIN-NEXT: vmv.x.s a5, v14
+; ZVFHMIN-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 7
+; ZVFHMIN-NEXT: vslidedown.vi v11, v8, 6
+; ZVFHMIN-NEXT: vmv.x.s a6, v10
+; ZVFHMIN-NEXT: vslidedown.vi v10, v8, 5
+; ZVFHMIN-NEXT: vslidedown.vi v13, v8, 4
+; ZVFHMIN-NEXT: vmv.x.s a7, v12
+; ZVFHMIN-NEXT: vslidedown.vi v12, v8, 3
+; ZVFHMIN-NEXT: vslidedown.vi v14, v8, 2
+; ZVFHMIN-NEXT: vmv.x.s t0, v8
+; ZVFHMIN-NEXT: vslidedown.vi v8, v8, 1
+; ZVFHMIN-NEXT: vmv.x.s t1, v9
+; ZVFHMIN-NEXT: vmv.x.s t2, v11
+; ZVFHMIN-NEXT: vmv.x.s t3, v10
+; ZVFHMIN-NEXT: fmv.h.x fa5, t0
+; ZVFHMIN-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN-NEXT: fmv.h.x fa3, a1
+; ZVFHMIN-NEXT: fmv.h.x fa2, a2
+; ZVFHMIN-NEXT: fmv.h.x fa1, a3
+; ZVFHMIN-NEXT: fmv.h.x ft0, a4
+; ZVFHMIN-NEXT: fmv.h.x ft1, a5
+; ZVFHMIN-NEXT: fmv.h.x ft2, a6
+; ZVFHMIN-NEXT: fmv.h.x ft3, a7
+; ZVFHMIN-NEXT: fmv.h.x ft4, t1
+; ZVFHMIN-NEXT: fmv.h.x ft5, t2
+; ZVFHMIN-NEXT: fmv.h.x ft6, t3
+; ZVFHMIN-NEXT: vmv.x.s a0, v13
+; ZVFHMIN-NEXT: fmv.h.x ft7, a0
+; ZVFHMIN-NEXT: vmv.x.s a0, v12
+; ZVFHMIN-NEXT: fmv.h.x fa6, a0
+; ZVFHMIN-NEXT: vmv.x.s a0, v14
+; ZVFHMIN-NEXT: fmv.h.x fa7, a0
+; ZVFHMIN-NEXT: vmv.x.s a0, v8
+; ZVFHMIN-NEXT: fmv.h.x ft8, a0
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft8
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa7
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa6
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft7
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft6
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft5
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft4
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft3
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft2
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft1
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft0
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa1
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa2
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa3
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN-NEXT: fadd.h fa0, fa0, fa5
+; ZVFHMIN-NEXT: ret
%v = load <16 x half>, ptr %x
%red = call reassoc half @llvm.vector.reduce.fadd.v16f16(half %s, <16 x half> %v)
ret half %red
}
define half @vreduce_ord_fadd_v16f16(ptr %x, half %s) {
-; CHECK-LABEL: vreduce_ord_fadd_v16f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vfmv.s.f v10, fa0
-; CHECK-NEXT: vfredosum.vs v8, v8, v10
-; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: vreduce_ord_fadd_v16f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vfmv.s.f v10, fa0
+; ZVFH-NEXT: vfredosum.vs v8, v8, v10
+; ZVFH-NEXT: vfmv.f.s fa0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: vreduce_ord_fadd_v16f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a0)
+; ZVFHMIN-NEXT: vslidedown.vi v10, v8, 15
+; ZVFHMIN-NEXT: vslidedown.vi v12, v8, 14
+; ZVFHMIN-NEXT: vslidedown.vi v14, v8, 13
+; ZVFHMIN-NEXT: vmv.x.s a0, v10
+; ZVFHMIN-NEXT: vslidedown.vi v10, v8, 12
+; ZVFHMIN-NEXT: vmv.x.s a1, v12
+; ZVFHMIN-NEXT: vslidedown.vi v12, v8, 11
+; ZVFHMIN-NEXT: vmv.x.s a2, v14
+; ZVFHMIN-NEXT: vslidedown.vi v14, v8, 10
+; ZVFHMIN-NEXT: vmv.x.s a3, v10
+; ZVFHMIN-NEXT: vslidedown.vi v10, v8, 9
+; ZVFHMIN-NEXT: vmv.x.s a4, v12
+; ZVFHMIN-NEXT: vslidedown.vi v12, v8, 8
+; ZVFHMIN-NEXT: vmv.x.s a5, v14
+; ZVFHMIN-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 7
+; ZVFHMIN-NEXT: vslidedown.vi v11, v8, 6
+; ZVFHMIN-NEXT: vmv.x.s a6, v10
+; ZVFHMIN-NEXT: vslidedown.vi v10, v8, 5
+; ZVFHMIN-NEXT: vslidedown.vi v13, v8, 4
+; ZVFHMIN-NEXT: vmv.x.s a7, v12
+; ZVFHMIN-NEXT: vslidedown.vi v12, v8, 3
+; ZVFHMIN-NEXT: vslidedown.vi v14, v8, 2
+; ZVFHMIN-NEXT: vmv.x.s t0, v8
+; ZVFHMIN-NEXT: vslidedown.vi v8, v8, 1
+; ZVFHMIN-NEXT: vmv.x.s t1, v9
+; ZVFHMIN-NEXT: vmv.x.s t2, v11
+; ZVFHMIN-NEXT: vmv.x.s t3, v10
+; ZVFHMIN-NEXT: fmv.h.x fa5, t0
+; ZVFHMIN-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN-NEXT: fmv.h.x fa3, a1
+; ZVFHMIN-NEXT: fmv.h.x fa2, a2
+; ZVFHMIN-NEXT: fmv.h.x fa1, a3
+; ZVFHMIN-NEXT: fmv.h.x ft0, a4
+; ZVFHMIN-NEXT: fmv.h.x ft1, a5
+; ZVFHMIN-NEXT: fmv.h.x ft2, a6
+; ZVFHMIN-NEXT: fmv.h.x ft3, a7
+; ZVFHMIN-NEXT: fmv.h.x ft4, t1
+; ZVFHMIN-NEXT: fmv.h.x ft5, t2
+; ZVFHMIN-NEXT: fmv.h.x ft6, t3
+; ZVFHMIN-NEXT: vmv.x.s a0, v13
+; ZVFHMIN-NEXT: fmv.h.x ft7, a0
+; ZVFHMIN-NEXT: vmv.x.s a0, v12
+; ZVFHMIN-NEXT: fmv.h.x fa6, a0
+; ZVFHMIN-NEXT: vmv.x.s a0, v14
+; ZVFHMIN-NEXT: fmv.h.x fa7, a0
+; ZVFHMIN-NEXT: vmv.x.s a0, v8
+; ZVFHMIN-NEXT: fmv.h.x ft8, a0
+; ZVFHMIN-NEXT: fadd.h fa5, fa0, fa5
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft8
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa7
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa6
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft7
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft6
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft5
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft4
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft3
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft2
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft1
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft0
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa1
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa2
+; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa3
+; ZVFHMIN-NEXT: fadd.h fa0, fa5, fa4
+; ZVFHMIN-NEXT: ret
%v = load <16 x half>, ptr %x
%red = call half @llvm.vector.reduce.fadd.v16f16(half %s, <16 x half> %v)
ret half %red
}
define half @vreduce_fadd_v32f16(ptr %x, half %s) {
-; CHECK-LABEL: vreduce_fadd_v32f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, 32
-; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vfmv.s.f v12, fa0
-; CHECK-NEXT: vfredusum.vs v8, v8, v12
-; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: vreduce_fadd_v32f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: li a1, 32
+; ZVFH-NEXT: vsetvli zero, a1, e16, m4, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vfmv.s.f v12, fa0
+; ZVFH-NEXT: vfredusum.vs v8, v8, v12
+; ZVFH-NEXT: vfmv.f.s fa0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN32-LABEL: vreduce_fadd_v32f16:
+; ZVFHMIN32: # %bb.0:
+; ZVFHMIN32-NEXT: addi sp, sp, -128
+; ZVFHMIN32-NEXT: .cfi_def_cfa_offset 128
+; ZVFHMIN32-NEXT: sw ra, 124(sp) # 4-byte Folded Spill
+; ZVFHMIN32-NEXT: sw s0, 120(sp) # 4-byte Folded Spill
+; ZVFHMIN32-NEXT: .cfi_offset ra, -4
+; ZVFHMIN32-NEXT: .cfi_offset s0, -8
+; ZVFHMIN32-NEXT: addi s0, sp, 128
+; ZVFHMIN32-NEXT: .cfi_def_cfa s0, 0
+; ZVFHMIN32-NEXT: andi sp, sp, -64
+; ZVFHMIN32-NEXT: li a1, 32
+; ZVFHMIN32-NEXT: vsetvli zero, a1, e16, m4, ta, ma
+; ZVFHMIN32-NEXT: vle16.v v8, (a0)
+; ZVFHMIN32-NEXT: mv a0, sp
+; ZVFHMIN32-NEXT: vse16.v v8, (a0)
+; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFHMIN32-NEXT: vslidedown.vi v16, v8, 15
+; ZVFHMIN32-NEXT: vslidedown.vi v18, v8, 14
+; ZVFHMIN32-NEXT: vslidedown.vi v20, v8, 13
+; ZVFHMIN32-NEXT: vslidedown.vi v10, v8, 12
+; ZVFHMIN32-NEXT: vslidedown.vi v12, v8, 11
+; ZVFHMIN32-NEXT: vslidedown.vi v14, v8, 10
+; ZVFHMIN32-NEXT: vslidedown.vi v22, v8, 9
+; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFHMIN32-NEXT: vslidedown.vi v11, v8, 7
+; ZVFHMIN32-NEXT: vslidedown.vi v13, v8, 6
+; ZVFHMIN32-NEXT: vslidedown.vi v15, v8, 5
+; ZVFHMIN32-NEXT: vslidedown.vi v17, v8, 4
+; ZVFHMIN32-NEXT: vslidedown.vi v19, v8, 3
+; ZVFHMIN32-NEXT: vslidedown.vi v21, v8, 2
+; ZVFHMIN32-NEXT: vmv.x.s a5, v8
+; ZVFHMIN32-NEXT: vslidedown.vi v23, v8, 1
+; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFHMIN32-NEXT: vslidedown.vi v8, v8, 8
+; ZVFHMIN32-NEXT: vmv.x.s a0, v16
+; ZVFHMIN32-NEXT: vmv.x.s a1, v18
+; ZVFHMIN32-NEXT: vmv.x.s a2, v20
+; ZVFHMIN32-NEXT: vmv.x.s a3, v22
+; ZVFHMIN32-NEXT: vmv.x.s a4, v8
+; ZVFHMIN32-NEXT: vmv.x.s a6, v11
+; ZVFHMIN32-NEXT: vmv.x.s a7, v13
+; ZVFHMIN32-NEXT: vmv.x.s t0, v15
+; ZVFHMIN32-NEXT: vmv.x.s t1, v17
+; ZVFHMIN32-NEXT: vmv.x.s t2, v19
+; ZVFHMIN32-NEXT: vmv.x.s t3, v21
+; ZVFHMIN32-NEXT: vmv.x.s t4, v23
+; ZVFHMIN32-NEXT: fmv.h.x fa5, a5
+; ZVFHMIN32-NEXT: fmv.h.x fa4, t4
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, t3
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, t2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, t1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, t0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a7
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a6
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a4
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v14
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v12
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v10
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: lh a0, 32(sp)
+; ZVFHMIN32-NEXT: lh a1, 34(sp)
+; ZVFHMIN32-NEXT: lh a2, 36(sp)
+; ZVFHMIN32-NEXT: lh a3, 38(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 40(sp)
+; ZVFHMIN32-NEXT: lh a1, 42(sp)
+; ZVFHMIN32-NEXT: lh a2, 44(sp)
+; ZVFHMIN32-NEXT: lh a3, 46(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 48(sp)
+; ZVFHMIN32-NEXT: lh a1, 50(sp)
+; ZVFHMIN32-NEXT: lh a2, 52(sp)
+; ZVFHMIN32-NEXT: lh a3, 54(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 56(sp)
+; ZVFHMIN32-NEXT: lh a1, 58(sp)
+; ZVFHMIN32-NEXT: lh a2, 60(sp)
+; ZVFHMIN32-NEXT: lh a3, 62(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fadd.h fa0, fa0, fa5
+; ZVFHMIN32-NEXT: addi sp, s0, -128
+; ZVFHMIN32-NEXT: .cfi_def_cfa sp, 128
+; ZVFHMIN32-NEXT: lw ra, 124(sp) # 4-byte Folded Reload
+; ZVFHMIN32-NEXT: lw s0, 120(sp) # 4-byte Folded Reload
+; ZVFHMIN32-NEXT: .cfi_restore ra
+; ZVFHMIN32-NEXT: .cfi_restore s0
+; ZVFHMIN32-NEXT: addi sp, sp, 128
+; ZVFHMIN32-NEXT: .cfi_def_cfa_offset 0
+; ZVFHMIN32-NEXT: ret
+;
+; ZVFHMIN64-LABEL: vreduce_fadd_v32f16:
+; ZVFHMIN64: # %bb.0:
+; ZVFHMIN64-NEXT: addi sp, sp, -128
+; ZVFHMIN64-NEXT: .cfi_def_cfa_offset 128
+; ZVFHMIN64-NEXT: sd ra, 120(sp) # 8-byte Folded Spill
+; ZVFHMIN64-NEXT: sd s0, 112(sp) # 8-byte Folded Spill
+; ZVFHMIN64-NEXT: .cfi_offset ra, -8
+; ZVFHMIN64-NEXT: .cfi_offset s0, -16
+; ZVFHMIN64-NEXT: addi s0, sp, 128
+; ZVFHMIN64-NEXT: .cfi_def_cfa s0, 0
+; ZVFHMIN64-NEXT: andi sp, sp, -64
+; ZVFHMIN64-NEXT: li a1, 32
+; ZVFHMIN64-NEXT: vsetvli zero, a1, e16, m4, ta, ma
+; ZVFHMIN64-NEXT: vle16.v v8, (a0)
+; ZVFHMIN64-NEXT: mv a0, sp
+; ZVFHMIN64-NEXT: vse16.v v8, (a0)
+; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFHMIN64-NEXT: vslidedown.vi v16, v8, 15
+; ZVFHMIN64-NEXT: vslidedown.vi v18, v8, 14
+; ZVFHMIN64-NEXT: vslidedown.vi v20, v8, 13
+; ZVFHMIN64-NEXT: vslidedown.vi v10, v8, 12
+; ZVFHMIN64-NEXT: vslidedown.vi v12, v8, 11
+; ZVFHMIN64-NEXT: vslidedown.vi v14, v8, 10
+; ZVFHMIN64-NEXT: vslidedown.vi v22, v8, 9
+; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFHMIN64-NEXT: vslidedown.vi v11, v8, 7
+; ZVFHMIN64-NEXT: vslidedown.vi v13, v8, 6
+; ZVFHMIN64-NEXT: vslidedown.vi v15, v8, 5
+; ZVFHMIN64-NEXT: vslidedown.vi v17, v8, 4
+; ZVFHMIN64-NEXT: vslidedown.vi v19, v8, 3
+; ZVFHMIN64-NEXT: vslidedown.vi v21, v8, 2
+; ZVFHMIN64-NEXT: vmv.x.s a5, v8
+; ZVFHMIN64-NEXT: vslidedown.vi v23, v8, 1
+; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFHMIN64-NEXT: vslidedown.vi v8, v8, 8
+; ZVFHMIN64-NEXT: vmv.x.s a0, v16
+; ZVFHMIN64-NEXT: vmv.x.s a1, v18
+; ZVFHMIN64-NEXT: vmv.x.s a2, v20
+; ZVFHMIN64-NEXT: vmv.x.s a3, v22
+; ZVFHMIN64-NEXT: vmv.x.s a4, v8
+; ZVFHMIN64-NEXT: vmv.x.s a6, v11
+; ZVFHMIN64-NEXT: vmv.x.s a7, v13
+; ZVFHMIN64-NEXT: vmv.x.s t0, v15
+; ZVFHMIN64-NEXT: vmv.x.s t1, v17
+; ZVFHMIN64-NEXT: vmv.x.s t2, v19
+; ZVFHMIN64-NEXT: vmv.x.s t3, v21
+; ZVFHMIN64-NEXT: vmv.x.s t4, v23
+; ZVFHMIN64-NEXT: fmv.h.x fa5, a5
+; ZVFHMIN64-NEXT: fmv.h.x fa4, t4
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, t3
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, t2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, t1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, t0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a7
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a6
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a4
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v14
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v12
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v10
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: lh a0, 32(sp)
+; ZVFHMIN64-NEXT: lh a1, 34(sp)
+; ZVFHMIN64-NEXT: lh a2, 36(sp)
+; ZVFHMIN64-NEXT: lh a3, 38(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 40(sp)
+; ZVFHMIN64-NEXT: lh a1, 42(sp)
+; ZVFHMIN64-NEXT: lh a2, 44(sp)
+; ZVFHMIN64-NEXT: lh a3, 46(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 48(sp)
+; ZVFHMIN64-NEXT: lh a1, 50(sp)
+; ZVFHMIN64-NEXT: lh a2, 52(sp)
+; ZVFHMIN64-NEXT: lh a3, 54(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 56(sp)
+; ZVFHMIN64-NEXT: lh a1, 58(sp)
+; ZVFHMIN64-NEXT: lh a2, 60(sp)
+; ZVFHMIN64-NEXT: lh a3, 62(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fadd.h fa0, fa0, fa5
+; ZVFHMIN64-NEXT: addi sp, s0, -128
+; ZVFHMIN64-NEXT: .cfi_def_cfa sp, 128
+; ZVFHMIN64-NEXT: ld ra, 120(sp) # 8-byte Folded Reload
+; ZVFHMIN64-NEXT: ld s0, 112(sp) # 8-byte Folded Reload
+; ZVFHMIN64-NEXT: .cfi_restore ra
+; ZVFHMIN64-NEXT: .cfi_restore s0
+; ZVFHMIN64-NEXT: addi sp, sp, 128
+; ZVFHMIN64-NEXT: .cfi_def_cfa_offset 0
+; ZVFHMIN64-NEXT: ret
%v = load <32 x half>, ptr %x
%red = call reassoc half @llvm.vector.reduce.fadd.v32f16(half %s, <32 x half> %v)
ret half %red
}
define half @vreduce_ord_fadd_v32f16(ptr %x, half %s) {
-; CHECK-LABEL: vreduce_ord_fadd_v32f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, 32
-; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vfmv.s.f v12, fa0
-; CHECK-NEXT: vfredosum.vs v8, v8, v12
-; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: vreduce_ord_fadd_v32f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: li a1, 32
+; ZVFH-NEXT: vsetvli zero, a1, e16, m4, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vfmv.s.f v12, fa0
+; ZVFH-NEXT: vfredosum.vs v8, v8, v12
+; ZVFH-NEXT: vfmv.f.s fa0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN32-LABEL: vreduce_ord_fadd_v32f16:
+; ZVFHMIN32: # %bb.0:
+; ZVFHMIN32-NEXT: addi sp, sp, -128
+; ZVFHMIN32-NEXT: .cfi_def_cfa_offset 128
+; ZVFHMIN32-NEXT: sw ra, 124(sp) # 4-byte Folded Spill
+; ZVFHMIN32-NEXT: sw s0, 120(sp) # 4-byte Folded Spill
+; ZVFHMIN32-NEXT: .cfi_offset ra, -4
+; ZVFHMIN32-NEXT: .cfi_offset s0, -8
+; ZVFHMIN32-NEXT: addi s0, sp, 128
+; ZVFHMIN32-NEXT: .cfi_def_cfa s0, 0
+; ZVFHMIN32-NEXT: andi sp, sp, -64
+; ZVFHMIN32-NEXT: li a1, 32
+; ZVFHMIN32-NEXT: vsetvli zero, a1, e16, m4, ta, ma
+; ZVFHMIN32-NEXT: vle16.v v8, (a0)
+; ZVFHMIN32-NEXT: mv a0, sp
+; ZVFHMIN32-NEXT: vse16.v v8, (a0)
+; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFHMIN32-NEXT: vslidedown.vi v16, v8, 15
+; ZVFHMIN32-NEXT: vslidedown.vi v18, v8, 14
+; ZVFHMIN32-NEXT: vslidedown.vi v20, v8, 13
+; ZVFHMIN32-NEXT: vslidedown.vi v10, v8, 12
+; ZVFHMIN32-NEXT: vslidedown.vi v12, v8, 11
+; ZVFHMIN32-NEXT: vslidedown.vi v14, v8, 10
+; ZVFHMIN32-NEXT: vslidedown.vi v22, v8, 9
+; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFHMIN32-NEXT: vslidedown.vi v11, v8, 7
+; ZVFHMIN32-NEXT: vslidedown.vi v13, v8, 6
+; ZVFHMIN32-NEXT: vslidedown.vi v15, v8, 5
+; ZVFHMIN32-NEXT: vslidedown.vi v17, v8, 4
+; ZVFHMIN32-NEXT: vslidedown.vi v19, v8, 3
+; ZVFHMIN32-NEXT: vslidedown.vi v21, v8, 2
+; ZVFHMIN32-NEXT: vslidedown.vi v23, v8, 1
+; ZVFHMIN32-NEXT: vmv.x.s a5, v8
+; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFHMIN32-NEXT: vslidedown.vi v8, v8, 8
+; ZVFHMIN32-NEXT: vmv.x.s a0, v16
+; ZVFHMIN32-NEXT: vmv.x.s a1, v18
+; ZVFHMIN32-NEXT: vmv.x.s a2, v20
+; ZVFHMIN32-NEXT: vmv.x.s a3, v22
+; ZVFHMIN32-NEXT: vmv.x.s a4, v8
+; ZVFHMIN32-NEXT: vmv.x.s a6, v11
+; ZVFHMIN32-NEXT: vmv.x.s a7, v13
+; ZVFHMIN32-NEXT: vmv.x.s t0, v15
+; ZVFHMIN32-NEXT: vmv.x.s t1, v17
+; ZVFHMIN32-NEXT: vmv.x.s t2, v19
+; ZVFHMIN32-NEXT: vmv.x.s t3, v21
+; ZVFHMIN32-NEXT: vmv.x.s t4, v23
+; ZVFHMIN32-NEXT: fmv.h.x fa5, a5
+; ZVFHMIN32-NEXT: fadd.h fa5, fa0, fa5
+; ZVFHMIN32-NEXT: fmv.h.x fa4, t4
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, t3
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, t2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, t1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, t0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a7
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a6
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a4
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v14
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v12
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v10
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: lh a0, 32(sp)
+; ZVFHMIN32-NEXT: lh a1, 34(sp)
+; ZVFHMIN32-NEXT: lh a2, 36(sp)
+; ZVFHMIN32-NEXT: lh a3, 38(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 40(sp)
+; ZVFHMIN32-NEXT: lh a1, 42(sp)
+; ZVFHMIN32-NEXT: lh a2, 44(sp)
+; ZVFHMIN32-NEXT: lh a3, 46(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 48(sp)
+; ZVFHMIN32-NEXT: lh a1, 50(sp)
+; ZVFHMIN32-NEXT: lh a2, 52(sp)
+; ZVFHMIN32-NEXT: lh a3, 54(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 56(sp)
+; ZVFHMIN32-NEXT: lh a1, 58(sp)
+; ZVFHMIN32-NEXT: lh a2, 60(sp)
+; ZVFHMIN32-NEXT: lh a3, 62(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: fadd.h fa0, fa5, fa4
+; ZVFHMIN32-NEXT: addi sp, s0, -128
+; ZVFHMIN32-NEXT: .cfi_def_cfa sp, 128
+; ZVFHMIN32-NEXT: lw ra, 124(sp) # 4-byte Folded Reload
+; ZVFHMIN32-NEXT: lw s0, 120(sp) # 4-byte Folded Reload
+; ZVFHMIN32-NEXT: .cfi_restore ra
+; ZVFHMIN32-NEXT: .cfi_restore s0
+; ZVFHMIN32-NEXT: addi sp, sp, 128
+; ZVFHMIN32-NEXT: .cfi_def_cfa_offset 0
+; ZVFHMIN32-NEXT: ret
+;
+; ZVFHMIN64-LABEL: vreduce_ord_fadd_v32f16:
+; ZVFHMIN64: # %bb.0:
+; ZVFHMIN64-NEXT: addi sp, sp, -128
+; ZVFHMIN64-NEXT: .cfi_def_cfa_offset 128
+; ZVFHMIN64-NEXT: sd ra, 120(sp) # 8-byte Folded Spill
+; ZVFHMIN64-NEXT: sd s0, 112(sp) # 8-byte Folded Spill
+; ZVFHMIN64-NEXT: .cfi_offset ra, -8
+; ZVFHMIN64-NEXT: .cfi_offset s0, -16
+; ZVFHMIN64-NEXT: addi s0, sp, 128
+; ZVFHMIN64-NEXT: .cfi_def_cfa s0, 0
+; ZVFHMIN64-NEXT: andi sp, sp, -64
+; ZVFHMIN64-NEXT: li a1, 32
+; ZVFHMIN64-NEXT: vsetvli zero, a1, e16, m4, ta, ma
+; ZVFHMIN64-NEXT: vle16.v v8, (a0)
+; ZVFHMIN64-NEXT: mv a0, sp
+; ZVFHMIN64-NEXT: vse16.v v8, (a0)
+; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFHMIN64-NEXT: vslidedown.vi v16, v8, 15
+; ZVFHMIN64-NEXT: vslidedown.vi v18, v8, 14
+; ZVFHMIN64-NEXT: vslidedown.vi v20, v8, 13
+; ZVFHMIN64-NEXT: vslidedown.vi v10, v8, 12
+; ZVFHMIN64-NEXT: vslidedown.vi v12, v8, 11
+; ZVFHMIN64-NEXT: vslidedown.vi v14, v8, 10
+; ZVFHMIN64-NEXT: vslidedown.vi v22, v8, 9
+; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFHMIN64-NEXT: vslidedown.vi v11, v8, 7
+; ZVFHMIN64-NEXT: vslidedown.vi v13, v8, 6
+; ZVFHMIN64-NEXT: vslidedown.vi v15, v8, 5
+; ZVFHMIN64-NEXT: vslidedown.vi v17, v8, 4
+; ZVFHMIN64-NEXT: vslidedown.vi v19, v8, 3
+; ZVFHMIN64-NEXT: vslidedown.vi v21, v8, 2
+; ZVFHMIN64-NEXT: vslidedown.vi v23, v8, 1
+; ZVFHMIN64-NEXT: vmv.x.s a5, v8
+; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFHMIN64-NEXT: vslidedown.vi v8, v8, 8
+; ZVFHMIN64-NEXT: vmv.x.s a0, v16
+; ZVFHMIN64-NEXT: vmv.x.s a1, v18
+; ZVFHMIN64-NEXT: vmv.x.s a2, v20
+; ZVFHMIN64-NEXT: vmv.x.s a3, v22
+; ZVFHMIN64-NEXT: vmv.x.s a4, v8
+; ZVFHMIN64-NEXT: vmv.x.s a6, v11
+; ZVFHMIN64-NEXT: vmv.x.s a7, v13
+; ZVFHMIN64-NEXT: vmv.x.s t0, v15
+; ZVFHMIN64-NEXT: vmv.x.s t1, v17
+; ZVFHMIN64-NEXT: vmv.x.s t2, v19
+; ZVFHMIN64-NEXT: vmv.x.s t3, v21
+; ZVFHMIN64-NEXT: vmv.x.s t4, v23
+; ZVFHMIN64-NEXT: fmv.h.x fa5, a5
+; ZVFHMIN64-NEXT: fadd.h fa5, fa0, fa5
+; ZVFHMIN64-NEXT: fmv.h.x fa4, t4
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, t3
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, t2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, t1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, t0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a7
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a6
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a4
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v14
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v12
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v10
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: lh a0, 32(sp)
+; ZVFHMIN64-NEXT: lh a1, 34(sp)
+; ZVFHMIN64-NEXT: lh a2, 36(sp)
+; ZVFHMIN64-NEXT: lh a3, 38(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 40(sp)
+; ZVFHMIN64-NEXT: lh a1, 42(sp)
+; ZVFHMIN64-NEXT: lh a2, 44(sp)
+; ZVFHMIN64-NEXT: lh a3, 46(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 48(sp)
+; ZVFHMIN64-NEXT: lh a1, 50(sp)
+; ZVFHMIN64-NEXT: lh a2, 52(sp)
+; ZVFHMIN64-NEXT: lh a3, 54(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 56(sp)
+; ZVFHMIN64-NEXT: lh a1, 58(sp)
+; ZVFHMIN64-NEXT: lh a2, 60(sp)
+; ZVFHMIN64-NEXT: lh a3, 62(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: fadd.h fa0, fa5, fa4
+; ZVFHMIN64-NEXT: addi sp, s0, -128
+; ZVFHMIN64-NEXT: .cfi_def_cfa sp, 128
+; ZVFHMIN64-NEXT: ld ra, 120(sp) # 8-byte Folded Reload
+; ZVFHMIN64-NEXT: ld s0, 112(sp) # 8-byte Folded Reload
+; ZVFHMIN64-NEXT: .cfi_restore ra
+; ZVFHMIN64-NEXT: .cfi_restore s0
+; ZVFHMIN64-NEXT: addi sp, sp, 128
+; ZVFHMIN64-NEXT: .cfi_def_cfa_offset 0
+; ZVFHMIN64-NEXT: ret
%v = load <32 x half>, ptr %x
%red = call half @llvm.vector.reduce.fadd.v32f16(half %s, <32 x half> %v)
ret half %red
}
define half @vreduce_fadd_v64f16(ptr %x, half %s) {
-; CHECK-LABEL: vreduce_fadd_v64f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, 64
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vfmv.s.f v16, fa0
-; CHECK-NEXT: vfredusum.vs v8, v8, v16
-; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: vreduce_fadd_v64f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: li a1, 64
+; ZVFH-NEXT: vsetvli zero, a1, e16, m8, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vfmv.s.f v16, fa0
+; ZVFH-NEXT: vfredusum.vs v8, v8, v16
+; ZVFH-NEXT: vfmv.f.s fa0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN32-LABEL: vreduce_fadd_v64f16:
+; ZVFHMIN32: # %bb.0:
+; ZVFHMIN32-NEXT: addi sp, sp, -256
+; ZVFHMIN32-NEXT: .cfi_def_cfa_offset 256
+; ZVFHMIN32-NEXT: sw ra, 252(sp) # 4-byte Folded Spill
+; ZVFHMIN32-NEXT: sw s0, 248(sp) # 4-byte Folded Spill
+; ZVFHMIN32-NEXT: .cfi_offset ra, -4
+; ZVFHMIN32-NEXT: .cfi_offset s0, -8
+; ZVFHMIN32-NEXT: addi s0, sp, 256
+; ZVFHMIN32-NEXT: .cfi_def_cfa s0, 0
+; ZVFHMIN32-NEXT: andi sp, sp, -128
+; ZVFHMIN32-NEXT: li a1, 64
+; ZVFHMIN32-NEXT: vsetvli zero, a1, e16, m8, ta, ma
+; ZVFHMIN32-NEXT: vle16.v v8, (a0)
+; ZVFHMIN32-NEXT: mv a0, sp
+; ZVFHMIN32-NEXT: vse16.v v8, (a0)
+; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFHMIN32-NEXT: vslidedown.vi v18, v8, 15
+; ZVFHMIN32-NEXT: vslidedown.vi v20, v8, 14
+; ZVFHMIN32-NEXT: vslidedown.vi v22, v8, 13
+; ZVFHMIN32-NEXT: vslidedown.vi v10, v8, 12
+; ZVFHMIN32-NEXT: vslidedown.vi v12, v8, 11
+; ZVFHMIN32-NEXT: vslidedown.vi v14, v8, 10
+; ZVFHMIN32-NEXT: vslidedown.vi v16, v8, 9
+; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFHMIN32-NEXT: vslidedown.vi v11, v8, 7
+; ZVFHMIN32-NEXT: vslidedown.vi v13, v8, 6
+; ZVFHMIN32-NEXT: vslidedown.vi v15, v8, 5
+; ZVFHMIN32-NEXT: vslidedown.vi v17, v8, 4
+; ZVFHMIN32-NEXT: vslidedown.vi v19, v8, 3
+; ZVFHMIN32-NEXT: vslidedown.vi v21, v8, 2
+; ZVFHMIN32-NEXT: vmv.x.s a3, v8
+; ZVFHMIN32-NEXT: vslidedown.vi v23, v8, 1
+; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFHMIN32-NEXT: vslidedown.vi v8, v8, 8
+; ZVFHMIN32-NEXT: vmv.x.s a0, v18
+; ZVFHMIN32-NEXT: vmv.x.s a1, v20
+; ZVFHMIN32-NEXT: vmv.x.s a2, v22
+; ZVFHMIN32-NEXT: fmv.h.x fa5, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v23
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v21
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v19
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v17
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v15
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v13
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v11
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v8
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v16
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v14
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v12
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v10
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: lh a0, 32(sp)
+; ZVFHMIN32-NEXT: lh a1, 34(sp)
+; ZVFHMIN32-NEXT: lh a2, 36(sp)
+; ZVFHMIN32-NEXT: lh a3, 38(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 40(sp)
+; ZVFHMIN32-NEXT: lh a1, 42(sp)
+; ZVFHMIN32-NEXT: lh a2, 44(sp)
+; ZVFHMIN32-NEXT: lh a3, 46(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 48(sp)
+; ZVFHMIN32-NEXT: lh a1, 50(sp)
+; ZVFHMIN32-NEXT: lh a2, 52(sp)
+; ZVFHMIN32-NEXT: lh a3, 54(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 56(sp)
+; ZVFHMIN32-NEXT: lh a1, 58(sp)
+; ZVFHMIN32-NEXT: lh a2, 60(sp)
+; ZVFHMIN32-NEXT: lh a3, 62(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 64(sp)
+; ZVFHMIN32-NEXT: lh a1, 66(sp)
+; ZVFHMIN32-NEXT: lh a2, 68(sp)
+; ZVFHMIN32-NEXT: lh a3, 70(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 72(sp)
+; ZVFHMIN32-NEXT: lh a1, 74(sp)
+; ZVFHMIN32-NEXT: lh a2, 76(sp)
+; ZVFHMIN32-NEXT: lh a3, 78(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 80(sp)
+; ZVFHMIN32-NEXT: lh a1, 82(sp)
+; ZVFHMIN32-NEXT: lh a2, 84(sp)
+; ZVFHMIN32-NEXT: lh a3, 86(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 88(sp)
+; ZVFHMIN32-NEXT: lh a1, 90(sp)
+; ZVFHMIN32-NEXT: lh a2, 92(sp)
+; ZVFHMIN32-NEXT: lh a3, 94(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 96(sp)
+; ZVFHMIN32-NEXT: lh a1, 98(sp)
+; ZVFHMIN32-NEXT: lh a2, 100(sp)
+; ZVFHMIN32-NEXT: lh a3, 102(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 104(sp)
+; ZVFHMIN32-NEXT: lh a1, 106(sp)
+; ZVFHMIN32-NEXT: lh a2, 108(sp)
+; ZVFHMIN32-NEXT: lh a3, 110(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 112(sp)
+; ZVFHMIN32-NEXT: lh a1, 114(sp)
+; ZVFHMIN32-NEXT: lh a2, 116(sp)
+; ZVFHMIN32-NEXT: lh a3, 118(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 120(sp)
+; ZVFHMIN32-NEXT: lh a1, 122(sp)
+; ZVFHMIN32-NEXT: lh a2, 124(sp)
+; ZVFHMIN32-NEXT: lh a3, 126(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fadd.h fa0, fa0, fa5
+; ZVFHMIN32-NEXT: addi sp, s0, -256
+; ZVFHMIN32-NEXT: .cfi_def_cfa sp, 256
+; ZVFHMIN32-NEXT: lw ra, 252(sp) # 4-byte Folded Reload
+; ZVFHMIN32-NEXT: lw s0, 248(sp) # 4-byte Folded Reload
+; ZVFHMIN32-NEXT: .cfi_restore ra
+; ZVFHMIN32-NEXT: .cfi_restore s0
+; ZVFHMIN32-NEXT: addi sp, sp, 256
+; ZVFHMIN32-NEXT: .cfi_def_cfa_offset 0
+; ZVFHMIN32-NEXT: ret
+;
+; ZVFHMIN64-LABEL: vreduce_fadd_v64f16:
+; ZVFHMIN64: # %bb.0:
+; ZVFHMIN64-NEXT: addi sp, sp, -256
+; ZVFHMIN64-NEXT: .cfi_def_cfa_offset 256
+; ZVFHMIN64-NEXT: sd ra, 248(sp) # 8-byte Folded Spill
+; ZVFHMIN64-NEXT: sd s0, 240(sp) # 8-byte Folded Spill
+; ZVFHMIN64-NEXT: .cfi_offset ra, -8
+; ZVFHMIN64-NEXT: .cfi_offset s0, -16
+; ZVFHMIN64-NEXT: addi s0, sp, 256
+; ZVFHMIN64-NEXT: .cfi_def_cfa s0, 0
+; ZVFHMIN64-NEXT: andi sp, sp, -128
+; ZVFHMIN64-NEXT: li a1, 64
+; ZVFHMIN64-NEXT: vsetvli zero, a1, e16, m8, ta, ma
+; ZVFHMIN64-NEXT: vle16.v v8, (a0)
+; ZVFHMIN64-NEXT: mv a0, sp
+; ZVFHMIN64-NEXT: vse16.v v8, (a0)
+; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFHMIN64-NEXT: vslidedown.vi v18, v8, 15
+; ZVFHMIN64-NEXT: vslidedown.vi v20, v8, 14
+; ZVFHMIN64-NEXT: vslidedown.vi v22, v8, 13
+; ZVFHMIN64-NEXT: vslidedown.vi v10, v8, 12
+; ZVFHMIN64-NEXT: vslidedown.vi v12, v8, 11
+; ZVFHMIN64-NEXT: vslidedown.vi v14, v8, 10
+; ZVFHMIN64-NEXT: vslidedown.vi v16, v8, 9
+; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFHMIN64-NEXT: vslidedown.vi v11, v8, 7
+; ZVFHMIN64-NEXT: vslidedown.vi v13, v8, 6
+; ZVFHMIN64-NEXT: vslidedown.vi v15, v8, 5
+; ZVFHMIN64-NEXT: vslidedown.vi v17, v8, 4
+; ZVFHMIN64-NEXT: vslidedown.vi v19, v8, 3
+; ZVFHMIN64-NEXT: vslidedown.vi v21, v8, 2
+; ZVFHMIN64-NEXT: vmv.x.s a3, v8
+; ZVFHMIN64-NEXT: vslidedown.vi v23, v8, 1
+; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFHMIN64-NEXT: vslidedown.vi v8, v8, 8
+; ZVFHMIN64-NEXT: vmv.x.s a0, v18
+; ZVFHMIN64-NEXT: vmv.x.s a1, v20
+; ZVFHMIN64-NEXT: vmv.x.s a2, v22
+; ZVFHMIN64-NEXT: fmv.h.x fa5, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v23
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v21
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v19
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v17
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v15
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v13
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v11
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v8
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v16
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v14
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v12
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v10
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: lh a0, 32(sp)
+; ZVFHMIN64-NEXT: lh a1, 34(sp)
+; ZVFHMIN64-NEXT: lh a2, 36(sp)
+; ZVFHMIN64-NEXT: lh a3, 38(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 40(sp)
+; ZVFHMIN64-NEXT: lh a1, 42(sp)
+; ZVFHMIN64-NEXT: lh a2, 44(sp)
+; ZVFHMIN64-NEXT: lh a3, 46(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 48(sp)
+; ZVFHMIN64-NEXT: lh a1, 50(sp)
+; ZVFHMIN64-NEXT: lh a2, 52(sp)
+; ZVFHMIN64-NEXT: lh a3, 54(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 56(sp)
+; ZVFHMIN64-NEXT: lh a1, 58(sp)
+; ZVFHMIN64-NEXT: lh a2, 60(sp)
+; ZVFHMIN64-NEXT: lh a3, 62(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 64(sp)
+; ZVFHMIN64-NEXT: lh a1, 66(sp)
+; ZVFHMIN64-NEXT: lh a2, 68(sp)
+; ZVFHMIN64-NEXT: lh a3, 70(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 72(sp)
+; ZVFHMIN64-NEXT: lh a1, 74(sp)
+; ZVFHMIN64-NEXT: lh a2, 76(sp)
+; ZVFHMIN64-NEXT: lh a3, 78(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 80(sp)
+; ZVFHMIN64-NEXT: lh a1, 82(sp)
+; ZVFHMIN64-NEXT: lh a2, 84(sp)
+; ZVFHMIN64-NEXT: lh a3, 86(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 88(sp)
+; ZVFHMIN64-NEXT: lh a1, 90(sp)
+; ZVFHMIN64-NEXT: lh a2, 92(sp)
+; ZVFHMIN64-NEXT: lh a3, 94(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 96(sp)
+; ZVFHMIN64-NEXT: lh a1, 98(sp)
+; ZVFHMIN64-NEXT: lh a2, 100(sp)
+; ZVFHMIN64-NEXT: lh a3, 102(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 104(sp)
+; ZVFHMIN64-NEXT: lh a1, 106(sp)
+; ZVFHMIN64-NEXT: lh a2, 108(sp)
+; ZVFHMIN64-NEXT: lh a3, 110(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 112(sp)
+; ZVFHMIN64-NEXT: lh a1, 114(sp)
+; ZVFHMIN64-NEXT: lh a2, 116(sp)
+; ZVFHMIN64-NEXT: lh a3, 118(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 120(sp)
+; ZVFHMIN64-NEXT: lh a1, 122(sp)
+; ZVFHMIN64-NEXT: lh a2, 124(sp)
+; ZVFHMIN64-NEXT: lh a3, 126(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fadd.h fa0, fa0, fa5
+; ZVFHMIN64-NEXT: addi sp, s0, -256
+; ZVFHMIN64-NEXT: .cfi_def_cfa sp, 256
+; ZVFHMIN64-NEXT: ld ra, 248(sp) # 8-byte Folded Reload
+; ZVFHMIN64-NEXT: ld s0, 240(sp) # 8-byte Folded Reload
+; ZVFHMIN64-NEXT: .cfi_restore ra
+; ZVFHMIN64-NEXT: .cfi_restore s0
+; ZVFHMIN64-NEXT: addi sp, sp, 256
+; ZVFHMIN64-NEXT: .cfi_def_cfa_offset 0
+; ZVFHMIN64-NEXT: ret
%v = load <64 x half>, ptr %x
%red = call reassoc half @llvm.vector.reduce.fadd.v64f16(half %s, <64 x half> %v)
ret half %red
}
define half @vreduce_ord_fadd_v64f16(ptr %x, half %s) {
-; CHECK-LABEL: vreduce_ord_fadd_v64f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, 64
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vfmv.s.f v16, fa0
-; CHECK-NEXT: vfredosum.vs v8, v8, v16
-; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: vreduce_ord_fadd_v64f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: li a1, 64
+; ZVFH-NEXT: vsetvli zero, a1, e16, m8, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vfmv.s.f v16, fa0
+; ZVFH-NEXT: vfredosum.vs v8, v8, v16
+; ZVFH-NEXT: vfmv.f.s fa0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN32-LABEL: vreduce_ord_fadd_v64f16:
+; ZVFHMIN32: # %bb.0:
+; ZVFHMIN32-NEXT: addi sp, sp, -256
+; ZVFHMIN32-NEXT: .cfi_def_cfa_offset 256
+; ZVFHMIN32-NEXT: sw ra, 252(sp) # 4-byte Folded Spill
+; ZVFHMIN32-NEXT: sw s0, 248(sp) # 4-byte Folded Spill
+; ZVFHMIN32-NEXT: .cfi_offset ra, -4
+; ZVFHMIN32-NEXT: .cfi_offset s0, -8
+; ZVFHMIN32-NEXT: addi s0, sp, 256
+; ZVFHMIN32-NEXT: .cfi_def_cfa s0, 0
+; ZVFHMIN32-NEXT: andi sp, sp, -128
+; ZVFHMIN32-NEXT: li a1, 64
+; ZVFHMIN32-NEXT: vsetvli zero, a1, e16, m8, ta, ma
+; ZVFHMIN32-NEXT: vle16.v v8, (a0)
+; ZVFHMIN32-NEXT: mv a0, sp
+; ZVFHMIN32-NEXT: vse16.v v8, (a0)
+; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFHMIN32-NEXT: vslidedown.vi v18, v8, 15
+; ZVFHMIN32-NEXT: vslidedown.vi v20, v8, 14
+; ZVFHMIN32-NEXT: vslidedown.vi v22, v8, 13
+; ZVFHMIN32-NEXT: vslidedown.vi v10, v8, 12
+; ZVFHMIN32-NEXT: vslidedown.vi v12, v8, 11
+; ZVFHMIN32-NEXT: vslidedown.vi v14, v8, 10
+; ZVFHMIN32-NEXT: vslidedown.vi v16, v8, 9
+; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFHMIN32-NEXT: vslidedown.vi v11, v8, 7
+; ZVFHMIN32-NEXT: vslidedown.vi v13, v8, 6
+; ZVFHMIN32-NEXT: vslidedown.vi v15, v8, 5
+; ZVFHMIN32-NEXT: vslidedown.vi v17, v8, 4
+; ZVFHMIN32-NEXT: vslidedown.vi v19, v8, 3
+; ZVFHMIN32-NEXT: vslidedown.vi v21, v8, 2
+; ZVFHMIN32-NEXT: vslidedown.vi v23, v8, 1
+; ZVFHMIN32-NEXT: vmv.x.s a3, v8
+; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFHMIN32-NEXT: vslidedown.vi v8, v8, 8
+; ZVFHMIN32-NEXT: vmv.x.s a0, v18
+; ZVFHMIN32-NEXT: vmv.x.s a1, v20
+; ZVFHMIN32-NEXT: vmv.x.s a2, v22
+; ZVFHMIN32-NEXT: fmv.h.x fa5, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v23
+; ZVFHMIN32-NEXT: fadd.h fa5, fa0, fa5
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v21
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v19
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v17
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v15
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v13
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v11
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v8
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v16
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v14
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v12
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v10
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: lh a0, 32(sp)
+; ZVFHMIN32-NEXT: lh a1, 34(sp)
+; ZVFHMIN32-NEXT: lh a2, 36(sp)
+; ZVFHMIN32-NEXT: lh a3, 38(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 40(sp)
+; ZVFHMIN32-NEXT: lh a1, 42(sp)
+; ZVFHMIN32-NEXT: lh a2, 44(sp)
+; ZVFHMIN32-NEXT: lh a3, 46(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 48(sp)
+; ZVFHMIN32-NEXT: lh a1, 50(sp)
+; ZVFHMIN32-NEXT: lh a2, 52(sp)
+; ZVFHMIN32-NEXT: lh a3, 54(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 56(sp)
+; ZVFHMIN32-NEXT: lh a1, 58(sp)
+; ZVFHMIN32-NEXT: lh a2, 60(sp)
+; ZVFHMIN32-NEXT: lh a3, 62(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 64(sp)
+; ZVFHMIN32-NEXT: lh a1, 66(sp)
+; ZVFHMIN32-NEXT: lh a2, 68(sp)
+; ZVFHMIN32-NEXT: lh a3, 70(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 72(sp)
+; ZVFHMIN32-NEXT: lh a1, 74(sp)
+; ZVFHMIN32-NEXT: lh a2, 76(sp)
+; ZVFHMIN32-NEXT: lh a3, 78(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 80(sp)
+; ZVFHMIN32-NEXT: lh a1, 82(sp)
+; ZVFHMIN32-NEXT: lh a2, 84(sp)
+; ZVFHMIN32-NEXT: lh a3, 86(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 88(sp)
+; ZVFHMIN32-NEXT: lh a1, 90(sp)
+; ZVFHMIN32-NEXT: lh a2, 92(sp)
+; ZVFHMIN32-NEXT: lh a3, 94(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 96(sp)
+; ZVFHMIN32-NEXT: lh a1, 98(sp)
+; ZVFHMIN32-NEXT: lh a2, 100(sp)
+; ZVFHMIN32-NEXT: lh a3, 102(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 104(sp)
+; ZVFHMIN32-NEXT: lh a1, 106(sp)
+; ZVFHMIN32-NEXT: lh a2, 108(sp)
+; ZVFHMIN32-NEXT: lh a3, 110(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 112(sp)
+; ZVFHMIN32-NEXT: lh a1, 114(sp)
+; ZVFHMIN32-NEXT: lh a2, 116(sp)
+; ZVFHMIN32-NEXT: lh a3, 118(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 120(sp)
+; ZVFHMIN32-NEXT: lh a1, 122(sp)
+; ZVFHMIN32-NEXT: lh a2, 124(sp)
+; ZVFHMIN32-NEXT: lh a3, 126(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: fadd.h fa0, fa5, fa4
+; ZVFHMIN32-NEXT: addi sp, s0, -256
+; ZVFHMIN32-NEXT: .cfi_def_cfa sp, 256
+; ZVFHMIN32-NEXT: lw ra, 252(sp) # 4-byte Folded Reload
+; ZVFHMIN32-NEXT: lw s0, 248(sp) # 4-byte Folded Reload
+; ZVFHMIN32-NEXT: .cfi_restore ra
+; ZVFHMIN32-NEXT: .cfi_restore s0
+; ZVFHMIN32-NEXT: addi sp, sp, 256
+; ZVFHMIN32-NEXT: .cfi_def_cfa_offset 0
+; ZVFHMIN32-NEXT: ret
+;
+; ZVFHMIN64-LABEL: vreduce_ord_fadd_v64f16:
+; ZVFHMIN64: # %bb.0:
+; ZVFHMIN64-NEXT: addi sp, sp, -256
+; ZVFHMIN64-NEXT: .cfi_def_cfa_offset 256
+; ZVFHMIN64-NEXT: sd ra, 248(sp) # 8-byte Folded Spill
+; ZVFHMIN64-NEXT: sd s0, 240(sp) # 8-byte Folded Spill
+; ZVFHMIN64-NEXT: .cfi_offset ra, -8
+; ZVFHMIN64-NEXT: .cfi_offset s0, -16
+; ZVFHMIN64-NEXT: addi s0, sp, 256
+; ZVFHMIN64-NEXT: .cfi_def_cfa s0, 0
+; ZVFHMIN64-NEXT: andi sp, sp, -128
+; ZVFHMIN64-NEXT: li a1, 64
+; ZVFHMIN64-NEXT: vsetvli zero, a1, e16, m8, ta, ma
+; ZVFHMIN64-NEXT: vle16.v v8, (a0)
+; ZVFHMIN64-NEXT: mv a0, sp
+; ZVFHMIN64-NEXT: vse16.v v8, (a0)
+; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFHMIN64-NEXT: vslidedown.vi v18, v8, 15
+; ZVFHMIN64-NEXT: vslidedown.vi v20, v8, 14
+; ZVFHMIN64-NEXT: vslidedown.vi v22, v8, 13
+; ZVFHMIN64-NEXT: vslidedown.vi v10, v8, 12
+; ZVFHMIN64-NEXT: vslidedown.vi v12, v8, 11
+; ZVFHMIN64-NEXT: vslidedown.vi v14, v8, 10
+; ZVFHMIN64-NEXT: vslidedown.vi v16, v8, 9
+; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFHMIN64-NEXT: vslidedown.vi v11, v8, 7
+; ZVFHMIN64-NEXT: vslidedown.vi v13, v8, 6
+; ZVFHMIN64-NEXT: vslidedown.vi v15, v8, 5
+; ZVFHMIN64-NEXT: vslidedown.vi v17, v8, 4
+; ZVFHMIN64-NEXT: vslidedown.vi v19, v8, 3
+; ZVFHMIN64-NEXT: vslidedown.vi v21, v8, 2
+; ZVFHMIN64-NEXT: vslidedown.vi v23, v8, 1
+; ZVFHMIN64-NEXT: vmv.x.s a3, v8
+; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFHMIN64-NEXT: vslidedown.vi v8, v8, 8
+; ZVFHMIN64-NEXT: vmv.x.s a0, v18
+; ZVFHMIN64-NEXT: vmv.x.s a1, v20
+; ZVFHMIN64-NEXT: vmv.x.s a2, v22
+; ZVFHMIN64-NEXT: fmv.h.x fa5, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v23
+; ZVFHMIN64-NEXT: fadd.h fa5, fa0, fa5
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v21
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v19
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v17
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v15
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v13
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v11
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v8
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v16
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v14
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v12
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v10
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: lh a0, 32(sp)
+; ZVFHMIN64-NEXT: lh a1, 34(sp)
+; ZVFHMIN64-NEXT: lh a2, 36(sp)
+; ZVFHMIN64-NEXT: lh a3, 38(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 40(sp)
+; ZVFHMIN64-NEXT: lh a1, 42(sp)
+; ZVFHMIN64-NEXT: lh a2, 44(sp)
+; ZVFHMIN64-NEXT: lh a3, 46(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 48(sp)
+; ZVFHMIN64-NEXT: lh a1, 50(sp)
+; ZVFHMIN64-NEXT: lh a2, 52(sp)
+; ZVFHMIN64-NEXT: lh a3, 54(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 56(sp)
+; ZVFHMIN64-NEXT: lh a1, 58(sp)
+; ZVFHMIN64-NEXT: lh a2, 60(sp)
+; ZVFHMIN64-NEXT: lh a3, 62(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 64(sp)
+; ZVFHMIN64-NEXT: lh a1, 66(sp)
+; ZVFHMIN64-NEXT: lh a2, 68(sp)
+; ZVFHMIN64-NEXT: lh a3, 70(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 72(sp)
+; ZVFHMIN64-NEXT: lh a1, 74(sp)
+; ZVFHMIN64-NEXT: lh a2, 76(sp)
+; ZVFHMIN64-NEXT: lh a3, 78(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 80(sp)
+; ZVFHMIN64-NEXT: lh a1, 82(sp)
+; ZVFHMIN64-NEXT: lh a2, 84(sp)
+; ZVFHMIN64-NEXT: lh a3, 86(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 88(sp)
+; ZVFHMIN64-NEXT: lh a1, 90(sp)
+; ZVFHMIN64-NEXT: lh a2, 92(sp)
+; ZVFHMIN64-NEXT: lh a3, 94(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 96(sp)
+; ZVFHMIN64-NEXT: lh a1, 98(sp)
+; ZVFHMIN64-NEXT: lh a2, 100(sp)
+; ZVFHMIN64-NEXT: lh a3, 102(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 104(sp)
+; ZVFHMIN64-NEXT: lh a1, 106(sp)
+; ZVFHMIN64-NEXT: lh a2, 108(sp)
+; ZVFHMIN64-NEXT: lh a3, 110(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 112(sp)
+; ZVFHMIN64-NEXT: lh a1, 114(sp)
+; ZVFHMIN64-NEXT: lh a2, 116(sp)
+; ZVFHMIN64-NEXT: lh a3, 118(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 120(sp)
+; ZVFHMIN64-NEXT: lh a1, 122(sp)
+; ZVFHMIN64-NEXT: lh a2, 124(sp)
+; ZVFHMIN64-NEXT: lh a3, 126(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: fadd.h fa0, fa5, fa4
+; ZVFHMIN64-NEXT: addi sp, s0, -256
+; ZVFHMIN64-NEXT: .cfi_def_cfa sp, 256
+; ZVFHMIN64-NEXT: ld ra, 248(sp) # 8-byte Folded Reload
+; ZVFHMIN64-NEXT: ld s0, 240(sp) # 8-byte Folded Reload
+; ZVFHMIN64-NEXT: .cfi_restore ra
+; ZVFHMIN64-NEXT: .cfi_restore s0
+; ZVFHMIN64-NEXT: addi sp, sp, 256
+; ZVFHMIN64-NEXT: .cfi_def_cfa_offset 0
+; ZVFHMIN64-NEXT: ret
%v = load <64 x half>, ptr %x
%red = call half @llvm.vector.reduce.fadd.v64f16(half %s, <64 x half> %v)
ret half %red
}
define half @vreduce_fadd_v128f16(ptr %x, half %s) {
-; CHECK-LABEL: vreduce_fadd_v128f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, 64
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: addi a0, a0, 128
-; CHECK-NEXT: vle16.v v16, (a0)
-; CHECK-NEXT: vfadd.vv v8, v8, v16
-; CHECK-NEXT: vfmv.s.f v16, fa0
-; CHECK-NEXT: vfredusum.vs v8, v8, v16
-; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: vreduce_fadd_v128f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: li a1, 64
+; ZVFH-NEXT: vsetvli zero, a1, e16, m8, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: addi a0, a0, 128
+; ZVFH-NEXT: vle16.v v16, (a0)
+; ZVFH-NEXT: vfadd.vv v8, v8, v16
+; ZVFH-NEXT: vfmv.s.f v16, fa0
+; ZVFH-NEXT: vfredusum.vs v8, v8, v16
+; ZVFH-NEXT: vfmv.f.s fa0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN32-LABEL: vreduce_fadd_v128f16:
+; ZVFHMIN32: # %bb.0:
+; ZVFHMIN32-NEXT: addi sp, sp, -192
+; ZVFHMIN32-NEXT: .cfi_def_cfa_offset 192
+; ZVFHMIN32-NEXT: sw ra, 188(sp) # 4-byte Folded Spill
+; ZVFHMIN32-NEXT: sw s0, 184(sp) # 4-byte Folded Spill
+; ZVFHMIN32-NEXT: .cfi_offset ra, -4
+; ZVFHMIN32-NEXT: .cfi_offset s0, -8
+; ZVFHMIN32-NEXT: addi s0, sp, 192
+; ZVFHMIN32-NEXT: .cfi_def_cfa s0, 0
+; ZVFHMIN32-NEXT: andi sp, sp, -64
+; ZVFHMIN32-NEXT: addi a2, a0, 128
+; ZVFHMIN32-NEXT: li a3, 64
+; ZVFHMIN32-NEXT: li a1, 32
+; ZVFHMIN32-NEXT: vsetvli zero, a3, e16, m8, ta, ma
+; ZVFHMIN32-NEXT: vle16.v v16, (a0)
+; ZVFHMIN32-NEXT: vle16.v v8, (a2)
+; ZVFHMIN32-NEXT: mv a2, sp
+; ZVFHMIN32-NEXT: addi a0, sp, 64
+; ZVFHMIN32-NEXT: vsetvli zero, a1, e16, m4, ta, ma
+; ZVFHMIN32-NEXT: vfwcvt.f.f.v v24, v16
+; ZVFHMIN32-NEXT: vfwcvt.f.f.v v0, v8
+; ZVFHMIN32-NEXT: vsetvli zero, a1, e16, m8, ta, ma
+; ZVFHMIN32-NEXT: vslidedown.vx v16, v16, a1
+; ZVFHMIN32-NEXT: vslidedown.vx v8, v8, a1
+; ZVFHMIN32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
+; ZVFHMIN32-NEXT: vfadd.vv v24, v24, v0
+; ZVFHMIN32-NEXT: vsetvli zero, zero, e16, m4, ta, ma
+; ZVFHMIN32-NEXT: vfwcvt.f.f.v v0, v16
+; ZVFHMIN32-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN32-NEXT: vfncvt.f.f.w v12, v24
+; ZVFHMIN32-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; ZVFHMIN32-NEXT: vfadd.vv v16, v0, v16
+; ZVFHMIN32-NEXT: vse16.v v12, (a2)
+; ZVFHMIN32-NEXT: vsetvli zero, zero, e16, m4, ta, ma
+; ZVFHMIN32-NEXT: vfncvt.f.f.w v8, v16
+; ZVFHMIN32-NEXT: vmv.x.s a2, v12
+; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFHMIN32-NEXT: vslidedown.vi v28, v12, 1
+; ZVFHMIN32-NEXT: vslidedown.vi v29, v12, 2
+; ZVFHMIN32-NEXT: vslidedown.vi v30, v12, 3
+; ZVFHMIN32-NEXT: vslidedown.vi v31, v12, 4
+; ZVFHMIN32-NEXT: vslidedown.vi v7, v12, 5
+; ZVFHMIN32-NEXT: vslidedown.vi v6, v12, 6
+; ZVFHMIN32-NEXT: vslidedown.vi v5, v12, 7
+; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFHMIN32-NEXT: vslidedown.vi v14, v12, 8
+; ZVFHMIN32-NEXT: vslidedown.vi v16, v12, 9
+; ZVFHMIN32-NEXT: vslidedown.vi v18, v12, 10
+; ZVFHMIN32-NEXT: vslidedown.vi v20, v12, 11
+; ZVFHMIN32-NEXT: vslidedown.vi v22, v12, 12
+; ZVFHMIN32-NEXT: vslidedown.vi v24, v12, 13
+; ZVFHMIN32-NEXT: vslidedown.vi v26, v12, 14
+; ZVFHMIN32-NEXT: vslidedown.vi v12, v12, 15
+; ZVFHMIN32-NEXT: vsetvli zero, a1, e16, m4, ta, ma
+; ZVFHMIN32-NEXT: vse16.v v8, (a0)
+; ZVFHMIN32-NEXT: fmv.h.x fa5, a2
+; ZVFHMIN32-NEXT: vmv.x.s a0, v28
+; ZVFHMIN32-NEXT: vmv.x.s a1, v29
+; ZVFHMIN32-NEXT: vmv.x.s a2, v30
+; ZVFHMIN32-NEXT: vmv.x.s a3, v31
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: vmv.x.s a0, v7
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: vmv.x.s a1, v6
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: vmv.x.s a2, v5
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v14
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: vmv.x.s a0, v16
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: vmv.x.s a1, v18
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: vmv.x.s a2, v20
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v22
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: vmv.x.s a0, v24
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: vmv.x.s a1, v26
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: vmv.x.s a2, v12
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: lh a0, 32(sp)
+; ZVFHMIN32-NEXT: lh a1, 34(sp)
+; ZVFHMIN32-NEXT: lh a2, 36(sp)
+; ZVFHMIN32-NEXT: lh a3, 38(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 40(sp)
+; ZVFHMIN32-NEXT: lh a1, 42(sp)
+; ZVFHMIN32-NEXT: lh a2, 44(sp)
+; ZVFHMIN32-NEXT: lh a3, 46(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 48(sp)
+; ZVFHMIN32-NEXT: lh a1, 50(sp)
+; ZVFHMIN32-NEXT: lh a2, 52(sp)
+; ZVFHMIN32-NEXT: lh a3, 54(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a3, 56(sp)
+; ZVFHMIN32-NEXT: lh a0, 58(sp)
+; ZVFHMIN32-NEXT: lh a1, 60(sp)
+; ZVFHMIN32-NEXT: lh a2, 62(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v8
+; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFHMIN32-NEXT: vslidedown.vi v24, v8, 1
+; ZVFHMIN32-NEXT: vslidedown.vi v25, v8, 2
+; ZVFHMIN32-NEXT: vslidedown.vi v26, v8, 3
+; ZVFHMIN32-NEXT: vslidedown.vi v27, v8, 4
+; ZVFHMIN32-NEXT: vslidedown.vi v28, v8, 5
+; ZVFHMIN32-NEXT: vslidedown.vi v29, v8, 6
+; ZVFHMIN32-NEXT: vslidedown.vi v30, v8, 7
+; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFHMIN32-NEXT: vslidedown.vi v10, v8, 8
+; ZVFHMIN32-NEXT: vslidedown.vi v12, v8, 9
+; ZVFHMIN32-NEXT: vslidedown.vi v14, v8, 10
+; ZVFHMIN32-NEXT: vslidedown.vi v16, v8, 11
+; ZVFHMIN32-NEXT: vslidedown.vi v18, v8, 12
+; ZVFHMIN32-NEXT: vslidedown.vi v20, v8, 13
+; ZVFHMIN32-NEXT: vslidedown.vi v22, v8, 14
+; ZVFHMIN32-NEXT: vslidedown.vi v8, v8, 15
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a0, v24
+; ZVFHMIN32-NEXT: vmv.x.s a1, v25
+; ZVFHMIN32-NEXT: vmv.x.s a2, v26
+; ZVFHMIN32-NEXT: vmv.x.s a3, v27
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: vmv.x.s a0, v28
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: vmv.x.s a1, v29
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: vmv.x.s a2, v30
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v10
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: vmv.x.s a0, v12
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: vmv.x.s a1, v14
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: vmv.x.s a2, v16
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v18
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: vmv.x.s a0, v20
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: vmv.x.s a1, v22
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: vmv.x.s a2, v8
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: lh a0, 96(sp)
+; ZVFHMIN32-NEXT: lh a1, 98(sp)
+; ZVFHMIN32-NEXT: lh a2, 100(sp)
+; ZVFHMIN32-NEXT: lh a3, 102(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 104(sp)
+; ZVFHMIN32-NEXT: lh a1, 106(sp)
+; ZVFHMIN32-NEXT: lh a2, 108(sp)
+; ZVFHMIN32-NEXT: lh a3, 110(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 112(sp)
+; ZVFHMIN32-NEXT: lh a1, 114(sp)
+; ZVFHMIN32-NEXT: lh a2, 116(sp)
+; ZVFHMIN32-NEXT: lh a3, 118(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 120(sp)
+; ZVFHMIN32-NEXT: lh a1, 122(sp)
+; ZVFHMIN32-NEXT: lh a2, 124(sp)
+; ZVFHMIN32-NEXT: lh a3, 126(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fadd.h fa0, fa0, fa5
+; ZVFHMIN32-NEXT: addi sp, s0, -192
+; ZVFHMIN32-NEXT: .cfi_def_cfa sp, 192
+; ZVFHMIN32-NEXT: lw ra, 188(sp) # 4-byte Folded Reload
+; ZVFHMIN32-NEXT: lw s0, 184(sp) # 4-byte Folded Reload
+; ZVFHMIN32-NEXT: .cfi_restore ra
+; ZVFHMIN32-NEXT: .cfi_restore s0
+; ZVFHMIN32-NEXT: addi sp, sp, 192
+; ZVFHMIN32-NEXT: .cfi_def_cfa_offset 0
+; ZVFHMIN32-NEXT: ret
+;
+; ZVFHMIN64-LABEL: vreduce_fadd_v128f16:
+; ZVFHMIN64: # %bb.0:
+; ZVFHMIN64-NEXT: addi sp, sp, -192
+; ZVFHMIN64-NEXT: .cfi_def_cfa_offset 192
+; ZVFHMIN64-NEXT: sd ra, 184(sp) # 8-byte Folded Spill
+; ZVFHMIN64-NEXT: sd s0, 176(sp) # 8-byte Folded Spill
+; ZVFHMIN64-NEXT: .cfi_offset ra, -8
+; ZVFHMIN64-NEXT: .cfi_offset s0, -16
+; ZVFHMIN64-NEXT: addi s0, sp, 192
+; ZVFHMIN64-NEXT: .cfi_def_cfa s0, 0
+; ZVFHMIN64-NEXT: andi sp, sp, -64
+; ZVFHMIN64-NEXT: addi a2, a0, 128
+; ZVFHMIN64-NEXT: li a3, 64
+; ZVFHMIN64-NEXT: li a1, 32
+; ZVFHMIN64-NEXT: vsetvli zero, a3, e16, m8, ta, ma
+; ZVFHMIN64-NEXT: vle16.v v16, (a0)
+; ZVFHMIN64-NEXT: vle16.v v8, (a2)
+; ZVFHMIN64-NEXT: mv a2, sp
+; ZVFHMIN64-NEXT: addi a0, sp, 64
+; ZVFHMIN64-NEXT: vsetvli zero, a1, e16, m4, ta, ma
+; ZVFHMIN64-NEXT: vfwcvt.f.f.v v24, v16
+; ZVFHMIN64-NEXT: vfwcvt.f.f.v v0, v8
+; ZVFHMIN64-NEXT: vsetvli zero, a1, e16, m8, ta, ma
+; ZVFHMIN64-NEXT: vslidedown.vx v16, v16, a1
+; ZVFHMIN64-NEXT: vslidedown.vx v8, v8, a1
+; ZVFHMIN64-NEXT: vsetvli zero, a1, e32, m8, ta, ma
+; ZVFHMIN64-NEXT: vfadd.vv v24, v24, v0
+; ZVFHMIN64-NEXT: vsetvli zero, zero, e16, m4, ta, ma
+; ZVFHMIN64-NEXT: vfwcvt.f.f.v v0, v16
+; ZVFHMIN64-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN64-NEXT: vfncvt.f.f.w v12, v24
+; ZVFHMIN64-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; ZVFHMIN64-NEXT: vfadd.vv v16, v0, v16
+; ZVFHMIN64-NEXT: vse16.v v12, (a2)
+; ZVFHMIN64-NEXT: vsetvli zero, zero, e16, m4, ta, ma
+; ZVFHMIN64-NEXT: vfncvt.f.f.w v8, v16
+; ZVFHMIN64-NEXT: vmv.x.s a2, v12
+; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFHMIN64-NEXT: vslidedown.vi v28, v12, 1
+; ZVFHMIN64-NEXT: vslidedown.vi v29, v12, 2
+; ZVFHMIN64-NEXT: vslidedown.vi v30, v12, 3
+; ZVFHMIN64-NEXT: vslidedown.vi v31, v12, 4
+; ZVFHMIN64-NEXT: vslidedown.vi v7, v12, 5
+; ZVFHMIN64-NEXT: vslidedown.vi v6, v12, 6
+; ZVFHMIN64-NEXT: vslidedown.vi v5, v12, 7
+; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFHMIN64-NEXT: vslidedown.vi v14, v12, 8
+; ZVFHMIN64-NEXT: vslidedown.vi v16, v12, 9
+; ZVFHMIN64-NEXT: vslidedown.vi v18, v12, 10
+; ZVFHMIN64-NEXT: vslidedown.vi v20, v12, 11
+; ZVFHMIN64-NEXT: vslidedown.vi v22, v12, 12
+; ZVFHMIN64-NEXT: vslidedown.vi v24, v12, 13
+; ZVFHMIN64-NEXT: vslidedown.vi v26, v12, 14
+; ZVFHMIN64-NEXT: vslidedown.vi v12, v12, 15
+; ZVFHMIN64-NEXT: vsetvli zero, a1, e16, m4, ta, ma
+; ZVFHMIN64-NEXT: vse16.v v8, (a0)
+; ZVFHMIN64-NEXT: fmv.h.x fa5, a2
+; ZVFHMIN64-NEXT: vmv.x.s a0, v28
+; ZVFHMIN64-NEXT: vmv.x.s a1, v29
+; ZVFHMIN64-NEXT: vmv.x.s a2, v30
+; ZVFHMIN64-NEXT: vmv.x.s a3, v31
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: vmv.x.s a0, v7
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: vmv.x.s a1, v6
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: vmv.x.s a2, v5
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v14
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: vmv.x.s a0, v16
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: vmv.x.s a1, v18
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: vmv.x.s a2, v20
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v22
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: vmv.x.s a0, v24
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: vmv.x.s a1, v26
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: vmv.x.s a2, v12
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: lh a0, 32(sp)
+; ZVFHMIN64-NEXT: lh a1, 34(sp)
+; ZVFHMIN64-NEXT: lh a2, 36(sp)
+; ZVFHMIN64-NEXT: lh a3, 38(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 40(sp)
+; ZVFHMIN64-NEXT: lh a1, 42(sp)
+; ZVFHMIN64-NEXT: lh a2, 44(sp)
+; ZVFHMIN64-NEXT: lh a3, 46(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 48(sp)
+; ZVFHMIN64-NEXT: lh a1, 50(sp)
+; ZVFHMIN64-NEXT: lh a2, 52(sp)
+; ZVFHMIN64-NEXT: lh a3, 54(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a3, 56(sp)
+; ZVFHMIN64-NEXT: lh a0, 58(sp)
+; ZVFHMIN64-NEXT: lh a1, 60(sp)
+; ZVFHMIN64-NEXT: lh a2, 62(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v8
+; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFHMIN64-NEXT: vslidedown.vi v24, v8, 1
+; ZVFHMIN64-NEXT: vslidedown.vi v25, v8, 2
+; ZVFHMIN64-NEXT: vslidedown.vi v26, v8, 3
+; ZVFHMIN64-NEXT: vslidedown.vi v27, v8, 4
+; ZVFHMIN64-NEXT: vslidedown.vi v28, v8, 5
+; ZVFHMIN64-NEXT: vslidedown.vi v29, v8, 6
+; ZVFHMIN64-NEXT: vslidedown.vi v30, v8, 7
+; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFHMIN64-NEXT: vslidedown.vi v10, v8, 8
+; ZVFHMIN64-NEXT: vslidedown.vi v12, v8, 9
+; ZVFHMIN64-NEXT: vslidedown.vi v14, v8, 10
+; ZVFHMIN64-NEXT: vslidedown.vi v16, v8, 11
+; ZVFHMIN64-NEXT: vslidedown.vi v18, v8, 12
+; ZVFHMIN64-NEXT: vslidedown.vi v20, v8, 13
+; ZVFHMIN64-NEXT: vslidedown.vi v22, v8, 14
+; ZVFHMIN64-NEXT: vslidedown.vi v8, v8, 15
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a0, v24
+; ZVFHMIN64-NEXT: vmv.x.s a1, v25
+; ZVFHMIN64-NEXT: vmv.x.s a2, v26
+; ZVFHMIN64-NEXT: vmv.x.s a3, v27
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: vmv.x.s a0, v28
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: vmv.x.s a1, v29
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: vmv.x.s a2, v30
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v10
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: vmv.x.s a0, v12
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: vmv.x.s a1, v14
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: vmv.x.s a2, v16
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v18
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: vmv.x.s a0, v20
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: vmv.x.s a1, v22
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: vmv.x.s a2, v8
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: lh a0, 96(sp)
+; ZVFHMIN64-NEXT: lh a1, 98(sp)
+; ZVFHMIN64-NEXT: lh a2, 100(sp)
+; ZVFHMIN64-NEXT: lh a3, 102(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 104(sp)
+; ZVFHMIN64-NEXT: lh a1, 106(sp)
+; ZVFHMIN64-NEXT: lh a2, 108(sp)
+; ZVFHMIN64-NEXT: lh a3, 110(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 112(sp)
+; ZVFHMIN64-NEXT: lh a1, 114(sp)
+; ZVFHMIN64-NEXT: lh a2, 116(sp)
+; ZVFHMIN64-NEXT: lh a3, 118(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 120(sp)
+; ZVFHMIN64-NEXT: lh a1, 122(sp)
+; ZVFHMIN64-NEXT: lh a2, 124(sp)
+; ZVFHMIN64-NEXT: lh a3, 126(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fadd.h fa0, fa0, fa5
+; ZVFHMIN64-NEXT: addi sp, s0, -192
+; ZVFHMIN64-NEXT: .cfi_def_cfa sp, 192
+; ZVFHMIN64-NEXT: ld ra, 184(sp) # 8-byte Folded Reload
+; ZVFHMIN64-NEXT: ld s0, 176(sp) # 8-byte Folded Reload
+; ZVFHMIN64-NEXT: .cfi_restore ra
+; ZVFHMIN64-NEXT: .cfi_restore s0
+; ZVFHMIN64-NEXT: addi sp, sp, 192
+; ZVFHMIN64-NEXT: .cfi_def_cfa_offset 0
+; ZVFHMIN64-NEXT: ret
%v = load <128 x half>, ptr %x
%red = call reassoc half @llvm.vector.reduce.fadd.v128f16(half %s, <128 x half> %v)
ret half %red
}
define half @vreduce_ord_fadd_v128f16(ptr %x, half %s) {
-; CHECK-LABEL: vreduce_ord_fadd_v128f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a1, a0, 128
-; CHECK-NEXT: li a2, 64
-; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vle16.v v16, (a1)
-; CHECK-NEXT: vfmv.s.f v24, fa0
-; CHECK-NEXT: vfredosum.vs v8, v8, v24
-; CHECK-NEXT: vfredosum.vs v8, v16, v8
-; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: vreduce_ord_fadd_v128f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: addi a1, a0, 128
+; ZVFH-NEXT: li a2, 64
+; ZVFH-NEXT: vsetvli zero, a2, e16, m8, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vle16.v v16, (a1)
+; ZVFH-NEXT: vfmv.s.f v24, fa0
+; ZVFH-NEXT: vfredosum.vs v8, v8, v24
+; ZVFH-NEXT: vfredosum.vs v8, v16, v8
+; ZVFH-NEXT: vfmv.f.s fa0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN32-LABEL: vreduce_ord_fadd_v128f16:
+; ZVFHMIN32: # %bb.0:
+; ZVFHMIN32-NEXT: addi sp, sp, -384
+; ZVFHMIN32-NEXT: .cfi_def_cfa_offset 384
+; ZVFHMIN32-NEXT: sw ra, 380(sp) # 4-byte Folded Spill
+; ZVFHMIN32-NEXT: sw s0, 376(sp) # 4-byte Folded Spill
+; ZVFHMIN32-NEXT: .cfi_offset ra, -4
+; ZVFHMIN32-NEXT: .cfi_offset s0, -8
+; ZVFHMIN32-NEXT: addi s0, sp, 384
+; ZVFHMIN32-NEXT: .cfi_def_cfa s0, 0
+; ZVFHMIN32-NEXT: andi sp, sp, -128
+; ZVFHMIN32-NEXT: addi a1, a0, 128
+; ZVFHMIN32-NEXT: li a2, 64
+; ZVFHMIN32-NEXT: vsetvli zero, a2, e16, m8, ta, ma
+; ZVFHMIN32-NEXT: vle16.v v8, (a1)
+; ZVFHMIN32-NEXT: mv a1, sp
+; ZVFHMIN32-NEXT: vse16.v v8, (a1)
+; ZVFHMIN32-NEXT: vle16.v v16, (a0)
+; ZVFHMIN32-NEXT: addi a0, sp, 128
+; ZVFHMIN32-NEXT: vse16.v v16, (a0)
+; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFHMIN32-NEXT: vslidedown.vi v10, v16, 15
+; ZVFHMIN32-NEXT: vslidedown.vi v12, v16, 14
+; ZVFHMIN32-NEXT: vslidedown.vi v26, v16, 13
+; ZVFHMIN32-NEXT: vslidedown.vi v14, v16, 12
+; ZVFHMIN32-NEXT: vslidedown.vi v18, v16, 11
+; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFHMIN32-NEXT: vslidedown.vi v15, v16, 7
+; ZVFHMIN32-NEXT: vslidedown.vi v19, v16, 6
+; ZVFHMIN32-NEXT: vslidedown.vi v27, v16, 5
+; ZVFHMIN32-NEXT: vslidedown.vi v30, v16, 4
+; ZVFHMIN32-NEXT: vslidedown.vi v31, v16, 3
+; ZVFHMIN32-NEXT: vslidedown.vi v28, v16, 2
+; ZVFHMIN32-NEXT: vmv.x.s a3, v16
+; ZVFHMIN32-NEXT: vslidedown.vi v29, v16, 1
+; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFHMIN32-NEXT: vslidedown.vi v20, v16, 10
+; ZVFHMIN32-NEXT: vslidedown.vi v22, v16, 9
+; ZVFHMIN32-NEXT: vslidedown.vi v24, v16, 8
+; ZVFHMIN32-NEXT: vmv.x.s a0, v10
+; ZVFHMIN32-NEXT: vmv.x.s a1, v12
+; ZVFHMIN32-NEXT: vslidedown.vi v12, v8, 15
+; ZVFHMIN32-NEXT: vmv.x.s a2, v26
+; ZVFHMIN32-NEXT: vslidedown.vi v10, v8, 14
+; ZVFHMIN32-NEXT: fmv.h.x fa5, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v29
+; ZVFHMIN32-NEXT: fadd.h fa5, fa0, fa5
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v28
+; ZVFHMIN32-NEXT: vslidedown.vi v28, v8, 13
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v31
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v30
+; ZVFHMIN32-NEXT: vslidedown.vi v16, v8, 12
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v27
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v19
+; ZVFHMIN32-NEXT: vslidedown.vi v26, v8, 11
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v15
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v24
+; ZVFHMIN32-NEXT: vslidedown.vi v24, v8, 10
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v22
+; ZVFHMIN32-NEXT: vslidedown.vi v22, v8, 9
+; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFHMIN32-NEXT: vslidedown.vi v11, v8, 7
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v20
+; ZVFHMIN32-NEXT: vslidedown.vi v13, v8, 6
+; ZVFHMIN32-NEXT: vslidedown.vi v15, v8, 5
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v18
+; ZVFHMIN32-NEXT: vslidedown.vi v17, v8, 4
+; ZVFHMIN32-NEXT: vslidedown.vi v18, v8, 3
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v14
+; ZVFHMIN32-NEXT: vslidedown.vi v14, v8, 2
+; ZVFHMIN32-NEXT: vslidedown.vi v19, v8, 1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: lh a0, 160(sp)
+; ZVFHMIN32-NEXT: lh a1, 162(sp)
+; ZVFHMIN32-NEXT: lh a2, 164(sp)
+; ZVFHMIN32-NEXT: lh a3, 166(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 168(sp)
+; ZVFHMIN32-NEXT: lh a1, 170(sp)
+; ZVFHMIN32-NEXT: lh a2, 172(sp)
+; ZVFHMIN32-NEXT: lh a3, 174(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 176(sp)
+; ZVFHMIN32-NEXT: lh a1, 178(sp)
+; ZVFHMIN32-NEXT: lh a2, 180(sp)
+; ZVFHMIN32-NEXT: lh a3, 182(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 184(sp)
+; ZVFHMIN32-NEXT: lh a1, 186(sp)
+; ZVFHMIN32-NEXT: lh a2, 188(sp)
+; ZVFHMIN32-NEXT: lh a3, 190(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 192(sp)
+; ZVFHMIN32-NEXT: lh a1, 194(sp)
+; ZVFHMIN32-NEXT: lh a2, 196(sp)
+; ZVFHMIN32-NEXT: lh a3, 198(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 200(sp)
+; ZVFHMIN32-NEXT: lh a1, 202(sp)
+; ZVFHMIN32-NEXT: lh a2, 204(sp)
+; ZVFHMIN32-NEXT: lh a3, 206(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 208(sp)
+; ZVFHMIN32-NEXT: lh a1, 210(sp)
+; ZVFHMIN32-NEXT: lh a2, 212(sp)
+; ZVFHMIN32-NEXT: lh a3, 214(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 216(sp)
+; ZVFHMIN32-NEXT: lh a1, 218(sp)
+; ZVFHMIN32-NEXT: lh a2, 220(sp)
+; ZVFHMIN32-NEXT: lh a3, 222(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 224(sp)
+; ZVFHMIN32-NEXT: lh a1, 226(sp)
+; ZVFHMIN32-NEXT: lh a2, 228(sp)
+; ZVFHMIN32-NEXT: lh a3, 230(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 232(sp)
+; ZVFHMIN32-NEXT: lh a1, 234(sp)
+; ZVFHMIN32-NEXT: lh a2, 236(sp)
+; ZVFHMIN32-NEXT: lh a3, 238(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 240(sp)
+; ZVFHMIN32-NEXT: lh a1, 242(sp)
+; ZVFHMIN32-NEXT: lh a2, 244(sp)
+; ZVFHMIN32-NEXT: lh a3, 246(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 248(sp)
+; ZVFHMIN32-NEXT: lh a1, 250(sp)
+; ZVFHMIN32-NEXT: lh a2, 252(sp)
+; ZVFHMIN32-NEXT: lh a3, 254(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: vmv.x.s a0, v8
+; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFHMIN32-NEXT: vslidedown.vi v8, v8, 8
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: vmv.x.s a1, v12
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: vmv.x.s a2, v10
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v28
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: vmv.x.s a0, v19
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: vmv.x.s a0, v14
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: vmv.x.s a0, v18
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: vmv.x.s a0, v17
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: vmv.x.s a0, v15
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: vmv.x.s a0, v13
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: vmv.x.s a0, v11
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: vmv.x.s a0, v8
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: vmv.x.s a0, v22
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: vmv.x.s a0, v24
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: vmv.x.s a0, v26
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: vmv.x.s a0, v16
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: lh a0, 32(sp)
+; ZVFHMIN32-NEXT: lh a1, 34(sp)
+; ZVFHMIN32-NEXT: lh a2, 36(sp)
+; ZVFHMIN32-NEXT: lh a3, 38(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 40(sp)
+; ZVFHMIN32-NEXT: lh a1, 42(sp)
+; ZVFHMIN32-NEXT: lh a2, 44(sp)
+; ZVFHMIN32-NEXT: lh a3, 46(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 48(sp)
+; ZVFHMIN32-NEXT: lh a1, 50(sp)
+; ZVFHMIN32-NEXT: lh a2, 52(sp)
+; ZVFHMIN32-NEXT: lh a3, 54(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 56(sp)
+; ZVFHMIN32-NEXT: lh a1, 58(sp)
+; ZVFHMIN32-NEXT: lh a2, 60(sp)
+; ZVFHMIN32-NEXT: lh a3, 62(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 64(sp)
+; ZVFHMIN32-NEXT: lh a1, 66(sp)
+; ZVFHMIN32-NEXT: lh a2, 68(sp)
+; ZVFHMIN32-NEXT: lh a3, 70(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 72(sp)
+; ZVFHMIN32-NEXT: lh a1, 74(sp)
+; ZVFHMIN32-NEXT: lh a2, 76(sp)
+; ZVFHMIN32-NEXT: lh a3, 78(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 80(sp)
+; ZVFHMIN32-NEXT: lh a1, 82(sp)
+; ZVFHMIN32-NEXT: lh a2, 84(sp)
+; ZVFHMIN32-NEXT: lh a3, 86(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 88(sp)
+; ZVFHMIN32-NEXT: lh a1, 90(sp)
+; ZVFHMIN32-NEXT: lh a2, 92(sp)
+; ZVFHMIN32-NEXT: lh a3, 94(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 96(sp)
+; ZVFHMIN32-NEXT: lh a1, 98(sp)
+; ZVFHMIN32-NEXT: lh a2, 100(sp)
+; ZVFHMIN32-NEXT: lh a3, 102(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 104(sp)
+; ZVFHMIN32-NEXT: lh a1, 106(sp)
+; ZVFHMIN32-NEXT: lh a2, 108(sp)
+; ZVFHMIN32-NEXT: lh a3, 110(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 112(sp)
+; ZVFHMIN32-NEXT: lh a1, 114(sp)
+; ZVFHMIN32-NEXT: lh a2, 116(sp)
+; ZVFHMIN32-NEXT: lh a3, 118(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: lh a0, 120(sp)
+; ZVFHMIN32-NEXT: lh a1, 122(sp)
+; ZVFHMIN32-NEXT: lh a2, 124(sp)
+; ZVFHMIN32-NEXT: lh a3, 126(sp)
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN32-NEXT: fadd.h fa0, fa5, fa4
+; ZVFHMIN32-NEXT: addi sp, s0, -384
+; ZVFHMIN32-NEXT: .cfi_def_cfa sp, 384
+; ZVFHMIN32-NEXT: lw ra, 380(sp) # 4-byte Folded Reload
+; ZVFHMIN32-NEXT: lw s0, 376(sp) # 4-byte Folded Reload
+; ZVFHMIN32-NEXT: .cfi_restore ra
+; ZVFHMIN32-NEXT: .cfi_restore s0
+; ZVFHMIN32-NEXT: addi sp, sp, 384
+; ZVFHMIN32-NEXT: .cfi_def_cfa_offset 0
+; ZVFHMIN32-NEXT: ret
+;
+; ZVFHMIN64-LABEL: vreduce_ord_fadd_v128f16:
+; ZVFHMIN64: # %bb.0:
+; ZVFHMIN64-NEXT: addi sp, sp, -384
+; ZVFHMIN64-NEXT: .cfi_def_cfa_offset 384
+; ZVFHMIN64-NEXT: sd ra, 376(sp) # 8-byte Folded Spill
+; ZVFHMIN64-NEXT: sd s0, 368(sp) # 8-byte Folded Spill
+; ZVFHMIN64-NEXT: .cfi_offset ra, -8
+; ZVFHMIN64-NEXT: .cfi_offset s0, -16
+; ZVFHMIN64-NEXT: addi s0, sp, 384
+; ZVFHMIN64-NEXT: .cfi_def_cfa s0, 0
+; ZVFHMIN64-NEXT: andi sp, sp, -128
+; ZVFHMIN64-NEXT: addi a1, a0, 128
+; ZVFHMIN64-NEXT: li a2, 64
+; ZVFHMIN64-NEXT: vsetvli zero, a2, e16, m8, ta, ma
+; ZVFHMIN64-NEXT: vle16.v v8, (a1)
+; ZVFHMIN64-NEXT: mv a1, sp
+; ZVFHMIN64-NEXT: vse16.v v8, (a1)
+; ZVFHMIN64-NEXT: vle16.v v16, (a0)
+; ZVFHMIN64-NEXT: addi a0, sp, 128
+; ZVFHMIN64-NEXT: vse16.v v16, (a0)
+; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFHMIN64-NEXT: vslidedown.vi v10, v16, 15
+; ZVFHMIN64-NEXT: vslidedown.vi v12, v16, 14
+; ZVFHMIN64-NEXT: vslidedown.vi v26, v16, 13
+; ZVFHMIN64-NEXT: vslidedown.vi v14, v16, 12
+; ZVFHMIN64-NEXT: vslidedown.vi v18, v16, 11
+; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFHMIN64-NEXT: vslidedown.vi v15, v16, 7
+; ZVFHMIN64-NEXT: vslidedown.vi v19, v16, 6
+; ZVFHMIN64-NEXT: vslidedown.vi v27, v16, 5
+; ZVFHMIN64-NEXT: vslidedown.vi v30, v16, 4
+; ZVFHMIN64-NEXT: vslidedown.vi v31, v16, 3
+; ZVFHMIN64-NEXT: vslidedown.vi v28, v16, 2
+; ZVFHMIN64-NEXT: vmv.x.s a3, v16
+; ZVFHMIN64-NEXT: vslidedown.vi v29, v16, 1
+; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFHMIN64-NEXT: vslidedown.vi v20, v16, 10
+; ZVFHMIN64-NEXT: vslidedown.vi v22, v16, 9
+; ZVFHMIN64-NEXT: vslidedown.vi v24, v16, 8
+; ZVFHMIN64-NEXT: vmv.x.s a0, v10
+; ZVFHMIN64-NEXT: vmv.x.s a1, v12
+; ZVFHMIN64-NEXT: vslidedown.vi v12, v8, 15
+; ZVFHMIN64-NEXT: vmv.x.s a2, v26
+; ZVFHMIN64-NEXT: vslidedown.vi v10, v8, 14
+; ZVFHMIN64-NEXT: fmv.h.x fa5, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v29
+; ZVFHMIN64-NEXT: fadd.h fa5, fa0, fa5
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v28
+; ZVFHMIN64-NEXT: vslidedown.vi v28, v8, 13
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v31
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v30
+; ZVFHMIN64-NEXT: vslidedown.vi v16, v8, 12
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v27
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v19
+; ZVFHMIN64-NEXT: vslidedown.vi v26, v8, 11
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v15
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v24
+; ZVFHMIN64-NEXT: vslidedown.vi v24, v8, 10
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v22
+; ZVFHMIN64-NEXT: vslidedown.vi v22, v8, 9
+; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFHMIN64-NEXT: vslidedown.vi v11, v8, 7
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v20
+; ZVFHMIN64-NEXT: vslidedown.vi v13, v8, 6
+; ZVFHMIN64-NEXT: vslidedown.vi v15, v8, 5
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v18
+; ZVFHMIN64-NEXT: vslidedown.vi v17, v8, 4
+; ZVFHMIN64-NEXT: vslidedown.vi v18, v8, 3
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v14
+; ZVFHMIN64-NEXT: vslidedown.vi v14, v8, 2
+; ZVFHMIN64-NEXT: vslidedown.vi v19, v8, 1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: lh a0, 160(sp)
+; ZVFHMIN64-NEXT: lh a1, 162(sp)
+; ZVFHMIN64-NEXT: lh a2, 164(sp)
+; ZVFHMIN64-NEXT: lh a3, 166(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 168(sp)
+; ZVFHMIN64-NEXT: lh a1, 170(sp)
+; ZVFHMIN64-NEXT: lh a2, 172(sp)
+; ZVFHMIN64-NEXT: lh a3, 174(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 176(sp)
+; ZVFHMIN64-NEXT: lh a1, 178(sp)
+; ZVFHMIN64-NEXT: lh a2, 180(sp)
+; ZVFHMIN64-NEXT: lh a3, 182(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 184(sp)
+; ZVFHMIN64-NEXT: lh a1, 186(sp)
+; ZVFHMIN64-NEXT: lh a2, 188(sp)
+; ZVFHMIN64-NEXT: lh a3, 190(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 192(sp)
+; ZVFHMIN64-NEXT: lh a1, 194(sp)
+; ZVFHMIN64-NEXT: lh a2, 196(sp)
+; ZVFHMIN64-NEXT: lh a3, 198(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 200(sp)
+; ZVFHMIN64-NEXT: lh a1, 202(sp)
+; ZVFHMIN64-NEXT: lh a2, 204(sp)
+; ZVFHMIN64-NEXT: lh a3, 206(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 208(sp)
+; ZVFHMIN64-NEXT: lh a1, 210(sp)
+; ZVFHMIN64-NEXT: lh a2, 212(sp)
+; ZVFHMIN64-NEXT: lh a3, 214(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 216(sp)
+; ZVFHMIN64-NEXT: lh a1, 218(sp)
+; ZVFHMIN64-NEXT: lh a2, 220(sp)
+; ZVFHMIN64-NEXT: lh a3, 222(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 224(sp)
+; ZVFHMIN64-NEXT: lh a1, 226(sp)
+; ZVFHMIN64-NEXT: lh a2, 228(sp)
+; ZVFHMIN64-NEXT: lh a3, 230(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 232(sp)
+; ZVFHMIN64-NEXT: lh a1, 234(sp)
+; ZVFHMIN64-NEXT: lh a2, 236(sp)
+; ZVFHMIN64-NEXT: lh a3, 238(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 240(sp)
+; ZVFHMIN64-NEXT: lh a1, 242(sp)
+; ZVFHMIN64-NEXT: lh a2, 244(sp)
+; ZVFHMIN64-NEXT: lh a3, 246(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 248(sp)
+; ZVFHMIN64-NEXT: lh a1, 250(sp)
+; ZVFHMIN64-NEXT: lh a2, 252(sp)
+; ZVFHMIN64-NEXT: lh a3, 254(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: vmv.x.s a0, v8
+; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFHMIN64-NEXT: vslidedown.vi v8, v8, 8
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: vmv.x.s a1, v12
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: vmv.x.s a2, v10
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v28
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: vmv.x.s a0, v19
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: vmv.x.s a0, v14
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: vmv.x.s a0, v18
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: vmv.x.s a0, v17
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: vmv.x.s a0, v15
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: vmv.x.s a0, v13
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: vmv.x.s a0, v11
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: vmv.x.s a0, v8
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: vmv.x.s a0, v22
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: vmv.x.s a0, v24
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: vmv.x.s a0, v26
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: vmv.x.s a0, v16
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: lh a0, 32(sp)
+; ZVFHMIN64-NEXT: lh a1, 34(sp)
+; ZVFHMIN64-NEXT: lh a2, 36(sp)
+; ZVFHMIN64-NEXT: lh a3, 38(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 40(sp)
+; ZVFHMIN64-NEXT: lh a1, 42(sp)
+; ZVFHMIN64-NEXT: lh a2, 44(sp)
+; ZVFHMIN64-NEXT: lh a3, 46(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 48(sp)
+; ZVFHMIN64-NEXT: lh a1, 50(sp)
+; ZVFHMIN64-NEXT: lh a2, 52(sp)
+; ZVFHMIN64-NEXT: lh a3, 54(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 56(sp)
+; ZVFHMIN64-NEXT: lh a1, 58(sp)
+; ZVFHMIN64-NEXT: lh a2, 60(sp)
+; ZVFHMIN64-NEXT: lh a3, 62(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 64(sp)
+; ZVFHMIN64-NEXT: lh a1, 66(sp)
+; ZVFHMIN64-NEXT: lh a2, 68(sp)
+; ZVFHMIN64-NEXT: lh a3, 70(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 72(sp)
+; ZVFHMIN64-NEXT: lh a1, 74(sp)
+; ZVFHMIN64-NEXT: lh a2, 76(sp)
+; ZVFHMIN64-NEXT: lh a3, 78(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 80(sp)
+; ZVFHMIN64-NEXT: lh a1, 82(sp)
+; ZVFHMIN64-NEXT: lh a2, 84(sp)
+; ZVFHMIN64-NEXT: lh a3, 86(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 88(sp)
+; ZVFHMIN64-NEXT: lh a1, 90(sp)
+; ZVFHMIN64-NEXT: lh a2, 92(sp)
+; ZVFHMIN64-NEXT: lh a3, 94(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 96(sp)
+; ZVFHMIN64-NEXT: lh a1, 98(sp)
+; ZVFHMIN64-NEXT: lh a2, 100(sp)
+; ZVFHMIN64-NEXT: lh a3, 102(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 104(sp)
+; ZVFHMIN64-NEXT: lh a1, 106(sp)
+; ZVFHMIN64-NEXT: lh a2, 108(sp)
+; ZVFHMIN64-NEXT: lh a3, 110(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 112(sp)
+; ZVFHMIN64-NEXT: lh a1, 114(sp)
+; ZVFHMIN64-NEXT: lh a2, 116(sp)
+; ZVFHMIN64-NEXT: lh a3, 118(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: lh a0, 120(sp)
+; ZVFHMIN64-NEXT: lh a1, 122(sp)
+; ZVFHMIN64-NEXT: lh a2, 124(sp)
+; ZVFHMIN64-NEXT: lh a3, 126(sp)
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
+; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
+; ZVFHMIN64-NEXT: fadd.h fa0, fa5, fa4
+; ZVFHMIN64-NEXT: addi sp, s0, -384
+; ZVFHMIN64-NEXT: .cfi_def_cfa sp, 384
+; ZVFHMIN64-NEXT: ld ra, 376(sp) # 8-byte Folded Reload
+; ZVFHMIN64-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
+; ZVFHMIN64-NEXT: .cfi_restore ra
+; ZVFHMIN64-NEXT: .cfi_restore s0
+; ZVFHMIN64-NEXT: addi sp, sp, 384
+; ZVFHMIN64-NEXT: .cfi_def_cfa_offset 0
+; ZVFHMIN64-NEXT: ret
%v = load <128 x half>, ptr %x
%red = call half @llvm.vector.reduce.fadd.v128f16(half %s, <128 x half> %v)
ret half %red
@@ -285,15 +3568,25 @@ define float @vreduce_fwadd_v1f32(<1 x half> %v, float %s) {
}
define float @vreduce_ord_fwadd_v1f32(<1 x half> %v, float %s) {
-; CHECK-LABEL: vreduce_ord_fwadd_v1f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
-; CHECK-NEXT: vfwredosum.vs v8, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: vreduce_ord_fwadd_v1f32:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; ZVFH-NEXT: vfmv.s.f v9, fa0
+; ZVFH-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; ZVFH-NEXT: vfwredosum.vs v8, v8, v9
+; ZVFH-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFH-NEXT: vfmv.f.s fa0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: vreduce_ord_fwadd_v1f32:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfmv.s.f v8, fa0
+; ZVFHMIN-NEXT: vfredosum.vs v8, v9, v8
+; ZVFHMIN-NEXT: vfmv.f.s fa0, v8
+; ZVFHMIN-NEXT: ret
%e = fpext <1 x half> %v to <1 x float>
%red = call float @llvm.vector.reduce.fadd.v1f32(float %s, <1 x float> %e)
ret float %red
@@ -328,16 +3621,27 @@ define float @vreduce_ord_fadd_v2f32(ptr %x, float %s) {
}
define float @vreduce_fwadd_v2f32(ptr %x, float %s) {
-; CHECK-LABEL: vreduce_fwadd_v2f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vfwredusum.vs v8, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: vreduce_fwadd_v2f32:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vfmv.s.f v9, fa0
+; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFH-NEXT: vfwredusum.vs v8, v8, v9
+; ZVFH-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFH-NEXT: vfmv.f.s fa0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: vreduce_fwadd_v2f32:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a0)
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfmv.s.f v8, fa0
+; ZVFHMIN-NEXT: vfredusum.vs v8, v9, v8
+; ZVFHMIN-NEXT: vfmv.f.s fa0, v8
+; ZVFHMIN-NEXT: ret
%v = load <2 x half>, ptr %x
%e = fpext <2 x half> %v to <2 x float>
%red = call reassoc float @llvm.vector.reduce.fadd.v2f32(float %s, <2 x float> %e)
@@ -345,16 +3649,27 @@ define float @vreduce_fwadd_v2f32(ptr %x, float %s) {
}
define float @vreduce_ord_fwadd_v2f32(ptr %x, float %s) {
-; CHECK-LABEL: vreduce_ord_fwadd_v2f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vfwredosum.vs v8, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: vreduce_ord_fwadd_v2f32:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vfmv.s.f v9, fa0
+; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFH-NEXT: vfwredosum.vs v8, v8, v9
+; ZVFH-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFH-NEXT: vfmv.f.s fa0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: vreduce_ord_fwadd_v2f32:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a0)
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfmv.s.f v8, fa0
+; ZVFHMIN-NEXT: vfredosum.vs v8, v9, v8
+; ZVFHMIN-NEXT: vfmv.f.s fa0, v8
+; ZVFHMIN-NEXT: ret
%v = load <2 x half>, ptr %x
%e = fpext <2 x half> %v to <2 x float>
%red = call float @llvm.vector.reduce.fadd.v2f32(float %s, <2 x float> %e)
@@ -390,16 +3705,27 @@ define float @vreduce_ord_fadd_v4f32(ptr %x, float %s) {
}
define float @vreduce_fwadd_v4f32(ptr %x, float %s) {
-; CHECK-LABEL: vreduce_fwadd_v4f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vfwredusum.vs v8, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: vreduce_fwadd_v4f32:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vfmv.s.f v9, fa0
+; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFH-NEXT: vfwredusum.vs v8, v8, v9
+; ZVFH-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFH-NEXT: vfmv.f.s fa0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: vreduce_fwadd_v4f32:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a0)
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vfmv.s.f v8, fa0
+; ZVFHMIN-NEXT: vfredusum.vs v8, v9, v8
+; ZVFHMIN-NEXT: vfmv.f.s fa0, v8
+; ZVFHMIN-NEXT: ret
%v = load <4 x half>, ptr %x
%e = fpext <4 x half> %v to <4 x float>
%red = call reassoc float @llvm.vector.reduce.fadd.v4f32(float %s, <4 x float> %e)
@@ -407,16 +3733,27 @@ define float @vreduce_fwadd_v4f32(ptr %x, float %s) {
}
define float @vreduce_ord_fwadd_v4f32(ptr %x, float %s) {
-; CHECK-LABEL: vreduce_ord_fwadd_v4f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vfwredosum.vs v8, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: vreduce_ord_fwadd_v4f32:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vfmv.s.f v9, fa0
+; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFH-NEXT: vfwredosum.vs v8, v8, v9
+; ZVFH-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFH-NEXT: vfmv.f.s fa0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: vreduce_ord_fwadd_v4f32:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a0)
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vfmv.s.f v8, fa0
+; ZVFHMIN-NEXT: vfredosum.vs v8, v9, v8
+; ZVFHMIN-NEXT: vfmv.f.s fa0, v8
+; ZVFHMIN-NEXT: ret
%v = load <4 x half>, ptr %x
%e = fpext <4 x half> %v to <4 x float>
%red = call float @llvm.vector.reduce.fadd.v4f32(float %s, <4 x float> %e)
@@ -524,16 +3861,27 @@ define float @vreduce_ord_fadd_v8f32(ptr %x, float %s) {
}
define float @vreduce_fwadd_v8f32(ptr %x, float %s) {
-; CHECK-LABEL: vreduce_fwadd_v8f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; CHECK-NEXT: vfwredusum.vs v8, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: vreduce_fwadd_v8f32:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vfmv.s.f v9, fa0
+; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFH-NEXT: vfwredusum.vs v8, v8, v9
+; ZVFH-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFH-NEXT: vfmv.f.s fa0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: vreduce_fwadd_v8f32:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vle16.v v10, (a0)
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vfmv.s.f v10, fa0
+; ZVFHMIN-NEXT: vfredusum.vs v8, v8, v10
+; ZVFHMIN-NEXT: vfmv.f.s fa0, v8
+; ZVFHMIN-NEXT: ret
%v = load <8 x half>, ptr %x
%e = fpext <8 x half> %v to <8 x float>
%red = call reassoc float @llvm.vector.reduce.fadd.v8f32(float %s, <8 x float> %e)
@@ -541,16 +3889,27 @@ define float @vreduce_fwadd_v8f32(ptr %x, float %s) {
}
define float @vreduce_ord_fwadd_v8f32(ptr %x, float %s) {
-; CHECK-LABEL: vreduce_ord_fwadd_v8f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; CHECK-NEXT: vfwredosum.vs v8, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: vreduce_ord_fwadd_v8f32:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vfmv.s.f v9, fa0
+; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFH-NEXT: vfwredosum.vs v8, v8, v9
+; ZVFH-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFH-NEXT: vfmv.f.s fa0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: vreduce_ord_fwadd_v8f32:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vle16.v v10, (a0)
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vfmv.s.f v10, fa0
+; ZVFHMIN-NEXT: vfredosum.vs v8, v8, v10
+; ZVFHMIN-NEXT: vfmv.f.s fa0, v8
+; ZVFHMIN-NEXT: ret
%v = load <8 x half>, ptr %x
%e = fpext <8 x half> %v to <8 x float>
%red = call float @llvm.vector.reduce.fadd.v8f32(float %s, <8 x float> %e)
@@ -586,16 +3945,27 @@ define float @vreduce_ord_fadd_v16f32(ptr %x, float %s) {
}
define float @vreduce_fwadd_v16f32(ptr %x, float %s) {
-; CHECK-LABEL: vreduce_fwadd_v16f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vfmv.s.f v10, fa0
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; CHECK-NEXT: vfwredusum.vs v8, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: vreduce_fwadd_v16f32:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vfmv.s.f v10, fa0
+; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vfwredusum.vs v8, v8, v10
+; ZVFH-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFH-NEXT: vfmv.f.s fa0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: vreduce_fwadd_v16f32:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vle16.v v12, (a0)
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v12
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.s.f v12, fa0
+; ZVFHMIN-NEXT: vfredusum.vs v8, v8, v12
+; ZVFHMIN-NEXT: vfmv.f.s fa0, v8
+; ZVFHMIN-NEXT: ret
%v = load <16 x half>, ptr %x
%e = fpext <16 x half> %v to <16 x float>
%red = call reassoc float @llvm.vector.reduce.fadd.v16f32(float %s, <16 x float> %e)
@@ -603,16 +3973,27 @@ define float @vreduce_fwadd_v16f32(ptr %x, float %s) {
}
define float @vreduce_ord_fwadd_v16f32(ptr %x, float %s) {
-; CHECK-LABEL: vreduce_ord_fwadd_v16f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vfmv.s.f v10, fa0
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; CHECK-NEXT: vfwredosum.vs v8, v8, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: vreduce_ord_fwadd_v16f32:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vfmv.s.f v10, fa0
+; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vfwredosum.vs v8, v8, v10
+; ZVFH-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFH-NEXT: vfmv.f.s fa0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: vreduce_ord_fwadd_v16f32:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vle16.v v12, (a0)
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v12
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.s.f v12, fa0
+; ZVFHMIN-NEXT: vfredosum.vs v8, v8, v12
+; ZVFHMIN-NEXT: vfmv.f.s fa0, v8
+; ZVFHMIN-NEXT: ret
%v = load <16 x half>, ptr %x
%e = fpext <16 x half> %v to <16 x float>
%red = call float @llvm.vector.reduce.fadd.v16f32(float %s, <16 x float> %e)
@@ -650,17 +4031,29 @@ define float @vreduce_ord_fadd_v32f32(ptr %x, float %s) {
}
define float @vreduce_fwadd_v32f32(ptr %x, float %s) {
-; CHECK-LABEL: vreduce_fwadd_v32f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, 32
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vfmv.s.f v12, fa0
-; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfwredusum.vs v8, v8, v12
-; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: vreduce_fwadd_v32f32:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: li a1, 32
+; ZVFH-NEXT: vsetvli zero, a1, e32, m8, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vfmv.s.f v12, fa0
+; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, ma
+; ZVFH-NEXT: vfwredusum.vs v8, v8, v12
+; ZVFH-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; ZVFH-NEXT: vfmv.f.s fa0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: vreduce_fwadd_v32f32:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: li a1, 32
+; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vle16.v v16, (a0)
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; ZVFHMIN-NEXT: vfmv.s.f v16, fa0
+; ZVFHMIN-NEXT: vfredusum.vs v8, v8, v16
+; ZVFHMIN-NEXT: vfmv.f.s fa0, v8
+; ZVFHMIN-NEXT: ret
%v = load <32 x half>, ptr %x
%e = fpext <32 x half> %v to <32 x float>
%red = call reassoc float @llvm.vector.reduce.fadd.v32f32(float %s, <32 x float> %e)
@@ -668,17 +4061,29 @@ define float @vreduce_fwadd_v32f32(ptr %x, float %s) {
}
define float @vreduce_ord_fwadd_v32f32(ptr %x, float %s) {
-; CHECK-LABEL: vreduce_ord_fwadd_v32f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, 32
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vfmv.s.f v12, fa0
-; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfwredosum.vs v8, v8, v12
-; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: vreduce_ord_fwadd_v32f32:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: li a1, 32
+; ZVFH-NEXT: vsetvli zero, a1, e32, m8, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vfmv.s.f v12, fa0
+; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, ma
+; ZVFH-NEXT: vfwredosum.vs v8, v8, v12
+; ZVFH-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; ZVFH-NEXT: vfmv.f.s fa0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: vreduce_ord_fwadd_v32f32:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: li a1, 32
+; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vle16.v v16, (a0)
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; ZVFHMIN-NEXT: vfmv.s.f v16, fa0
+; ZVFHMIN-NEXT: vfredosum.vs v8, v8, v16
+; ZVFHMIN-NEXT: vfmv.f.s fa0, v8
+; ZVFHMIN-NEXT: ret
%v = load <32 x half>, ptr %x
%e = fpext <32 x half> %v to <32 x float>
%red = call float @llvm.vector.reduce.fadd.v32f32(float %s, <32 x float> %e)
@@ -722,21 +4127,40 @@ define float @vreduce_ord_fadd_v64f32(ptr %x, float %s) {
}
define float @vreduce_fwadd_v64f32(ptr %x, float %s) {
-; CHECK-LABEL: vreduce_fwadd_v64f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, 64
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: li a0, 32
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vslidedown.vx v16, v8, a0
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vfwadd.vv v24, v8, v16
-; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfmv.s.f v8, fa0
-; CHECK-NEXT: vfredusum.vs v8, v24, v8
-; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: vreduce_fwadd_v64f32:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: li a1, 64
+; ZVFH-NEXT: vsetvli zero, a1, e16, m8, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: li a0, 32
+; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFH-NEXT: vslidedown.vx v16, v8, a0
+; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; ZVFH-NEXT: vfwadd.vv v24, v8, v16
+; ZVFH-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; ZVFH-NEXT: vfmv.s.f v8, fa0
+; ZVFH-NEXT: vfredusum.vs v8, v24, v8
+; ZVFH-NEXT: vfmv.f.s fa0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: vreduce_fwadd_v64f32:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: li a1, 64
+; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a0)
+; ZVFHMIN-NEXT: li a0, 32
+; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a0
+; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; ZVFHMIN-NEXT: vfadd.vv v8, v16, v24
+; ZVFHMIN-NEXT: vfmv.s.f v16, fa0
+; ZVFHMIN-NEXT: vfredusum.vs v8, v8, v16
+; ZVFHMIN-NEXT: vfmv.f.s fa0, v8
+; ZVFHMIN-NEXT: ret
%v = load <64 x half>, ptr %x
%e = fpext <64 x half> %v to <64 x float>
%red = call reassoc float @llvm.vector.reduce.fadd.v64f32(float %s, <64 x float> %e)
@@ -744,22 +4168,41 @@ define float @vreduce_fwadd_v64f32(ptr %x, float %s) {
}
define float @vreduce_ord_fwadd_v64f32(ptr %x, float %s) {
-; CHECK-LABEL: vreduce_ord_fwadd_v64f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, 64
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: li a0, 32
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vfmv.s.f v24, fa0
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vslidedown.vx v16, v8, a0
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vfwredosum.vs v8, v8, v24
-; CHECK-NEXT: vfwredosum.vs v8, v16, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: vreduce_ord_fwadd_v64f32:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: li a1, 64
+; ZVFH-NEXT: vsetvli zero, a1, e16, m8, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: li a0, 32
+; ZVFH-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; ZVFH-NEXT: vfmv.s.f v24, fa0
+; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFH-NEXT: vslidedown.vx v16, v8, a0
+; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; ZVFH-NEXT: vfwredosum.vs v8, v8, v24
+; ZVFH-NEXT: vfwredosum.vs v8, v16, v8
+; ZVFH-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; ZVFH-NEXT: vfmv.f.s fa0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: vreduce_ord_fwadd_v64f32:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: li a1, 64
+; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a0)
+; ZVFHMIN-NEXT: li a0, 32
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vfmv.s.f v7, fa0
+; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vslidedown.vx v16, v8, a0
+; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; ZVFHMIN-NEXT: vfredosum.vs v16, v24, v7
+; ZVFHMIN-NEXT: vfredosum.vs v8, v8, v16
+; ZVFHMIN-NEXT: vfmv.f.s fa0, v8
+; ZVFHMIN-NEXT: ret
%v = load <64 x half>, ptr %x
%e = fpext <64 x half> %v to <64 x float>
%red = call float @llvm.vector.reduce.fadd.v64f32(float %s, <64 x float> %e)
@@ -1144,69 +4587,661 @@ define double @vreduce_ord_fwadd_v32f64(ptr %x, double %s) {
}
define half @vreduce_fmin_v2f16(ptr %x) {
-; CHECK-LABEL: vreduce_fmin_v2f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vfredmin.vs v8, v8, v8
-; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: vreduce_fmin_v2f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vfredmin.vs v8, v8, v8
+; ZVFH-NEXT: vfmv.f.s fa0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: vreduce_fmin_v2f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a0)
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfredmin.vs v8, v9, v9
+; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
+; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
+; ZVFHMIN-NEXT: ret
%v = load <2 x half>, ptr %x
%red = call half @llvm.vector.reduce.fmin.v2f16(<2 x half> %v)
ret half %red
}
define half @vreduce_fmin_v4f16(ptr %x) {
-; CHECK-LABEL: vreduce_fmin_v4f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vfredmin.vs v8, v8, v8
-; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: vreduce_fmin_v4f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vfredmin.vs v8, v8, v8
+; ZVFH-NEXT: vfmv.f.s fa0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: vreduce_fmin_v4f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a0)
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vfredmin.vs v8, v9, v9
+; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
+; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
+; ZVFHMIN-NEXT: ret
%v = load <4 x half>, ptr %x
%red = call half @llvm.vector.reduce.fmin.v4f16(<4 x half> %v)
ret half %red
}
define half @vreduce_fmin_v4f16_nonans(ptr %x) {
-; CHECK-LABEL: vreduce_fmin_v4f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vfredmin.vs v8, v8, v8
-; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: vreduce_fmin_v4f16_nonans:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vfredmin.vs v8, v8, v8
+; ZVFH-NEXT: vfmv.f.s fa0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: vreduce_fmin_v4f16_nonans:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a0)
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vfredmin.vs v8, v9, v9
+; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
+; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
+; ZVFHMIN-NEXT: ret
%v = load <4 x half>, ptr %x
%red = call nnan half @llvm.vector.reduce.fmin.v4f16(<4 x half> %v)
ret half %red
}
define half @vreduce_fmin_v4f16_nonans_noinfs(ptr %x) {
-; CHECK-LABEL: vreduce_fmin_v4f16_nonans_noinfs:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vfredmin.vs v8, v8, v8
-; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: vreduce_fmin_v4f16_nonans_noinfs:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vfredmin.vs v8, v8, v8
+; ZVFH-NEXT: vfmv.f.s fa0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: vreduce_fmin_v4f16_nonans_noinfs:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a0)
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vfredmin.vs v8, v9, v9
+; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
+; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
+; ZVFHMIN-NEXT: ret
%v = load <4 x half>, ptr %x
%red = call nnan ninf half @llvm.vector.reduce.fmin.v4f16(<4 x half> %v)
ret half %red
}
define half @vreduce_fmin_v128f16(ptr %x) {
-; CHECK-LABEL: vreduce_fmin_v128f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, 64
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: addi a0, a0, 128
-; CHECK-NEXT: vle16.v v16, (a0)
-; CHECK-NEXT: vfmin.vv v8, v8, v16
-; CHECK-NEXT: vfredmin.vs v8, v8, v8
-; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: vreduce_fmin_v128f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: li a1, 64
+; ZVFH-NEXT: vsetvli zero, a1, e16, m8, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: addi a0, a0, 128
+; ZVFH-NEXT: vle16.v v16, (a0)
+; ZVFH-NEXT: vfmin.vv v8, v8, v16
+; ZVFH-NEXT: vfredmin.vs v8, v8, v8
+; ZVFH-NEXT: vfmv.f.s fa0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN32-LABEL: vreduce_fmin_v128f16:
+; ZVFHMIN32: # %bb.0:
+; ZVFHMIN32-NEXT: addi sp, sp, -192
+; ZVFHMIN32-NEXT: .cfi_def_cfa_offset 192
+; ZVFHMIN32-NEXT: sw ra, 188(sp) # 4-byte Folded Spill
+; ZVFHMIN32-NEXT: sw s0, 184(sp) # 4-byte Folded Spill
+; ZVFHMIN32-NEXT: .cfi_offset ra, -4
+; ZVFHMIN32-NEXT: .cfi_offset s0, -8
+; ZVFHMIN32-NEXT: addi s0, sp, 192
+; ZVFHMIN32-NEXT: .cfi_def_cfa s0, 0
+; ZVFHMIN32-NEXT: andi sp, sp, -64
+; ZVFHMIN32-NEXT: addi a2, a0, 128
+; ZVFHMIN32-NEXT: li a3, 64
+; ZVFHMIN32-NEXT: li a1, 32
+; ZVFHMIN32-NEXT: vsetvli zero, a3, e16, m8, ta, ma
+; ZVFHMIN32-NEXT: vle16.v v16, (a0)
+; ZVFHMIN32-NEXT: vle16.v v8, (a2)
+; ZVFHMIN32-NEXT: mv a2, sp
+; ZVFHMIN32-NEXT: addi a0, sp, 64
+; ZVFHMIN32-NEXT: vsetvli zero, a1, e16, m4, ta, ma
+; ZVFHMIN32-NEXT: vfwcvt.f.f.v v24, v16
+; ZVFHMIN32-NEXT: vfwcvt.f.f.v v0, v8
+; ZVFHMIN32-NEXT: vsetvli zero, a1, e16, m8, ta, ma
+; ZVFHMIN32-NEXT: vslidedown.vx v16, v16, a1
+; ZVFHMIN32-NEXT: vslidedown.vx v8, v8, a1
+; ZVFHMIN32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
+; ZVFHMIN32-NEXT: vfmin.vv v24, v24, v0
+; ZVFHMIN32-NEXT: vsetvli zero, zero, e16, m4, ta, ma
+; ZVFHMIN32-NEXT: vfwcvt.f.f.v v0, v16
+; ZVFHMIN32-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN32-NEXT: vfncvt.f.f.w v12, v24
+; ZVFHMIN32-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; ZVFHMIN32-NEXT: vfmin.vv v16, v0, v16
+; ZVFHMIN32-NEXT: vse16.v v12, (a2)
+; ZVFHMIN32-NEXT: vsetvli zero, zero, e16, m4, ta, ma
+; ZVFHMIN32-NEXT: vfncvt.f.f.w v8, v16
+; ZVFHMIN32-NEXT: vmv.x.s a2, v12
+; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFHMIN32-NEXT: vslidedown.vi v20, v12, 1
+; ZVFHMIN32-NEXT: vslidedown.vi v21, v12, 2
+; ZVFHMIN32-NEXT: vslidedown.vi v30, v12, 3
+; ZVFHMIN32-NEXT: vslidedown.vi v31, v12, 4
+; ZVFHMIN32-NEXT: vslidedown.vi v7, v12, 5
+; ZVFHMIN32-NEXT: vslidedown.vi v6, v12, 6
+; ZVFHMIN32-NEXT: vslidedown.vi v5, v12, 7
+; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFHMIN32-NEXT: vslidedown.vi v14, v12, 8
+; ZVFHMIN32-NEXT: vslidedown.vi v16, v12, 9
+; ZVFHMIN32-NEXT: vslidedown.vi v18, v12, 10
+; ZVFHMIN32-NEXT: vslidedown.vi v22, v12, 11
+; ZVFHMIN32-NEXT: vslidedown.vi v24, v12, 12
+; ZVFHMIN32-NEXT: vslidedown.vi v26, v12, 13
+; ZVFHMIN32-NEXT: vslidedown.vi v28, v12, 14
+; ZVFHMIN32-NEXT: vslidedown.vi v12, v12, 15
+; ZVFHMIN32-NEXT: vsetvli zero, a1, e16, m4, ta, ma
+; ZVFHMIN32-NEXT: vse16.v v8, (a0)
+; ZVFHMIN32-NEXT: fmv.h.x fa5, a2
+; ZVFHMIN32-NEXT: vmv.x.s a1, v20
+; ZVFHMIN32-NEXT: vmv.x.s a2, v21
+; ZVFHMIN32-NEXT: vmv.x.s t3, v30
+; ZVFHMIN32-NEXT: vmv.x.s t4, v31
+; ZVFHMIN32-NEXT: vmv.x.s t1, v7
+; ZVFHMIN32-NEXT: vmv.x.s t2, v6
+; ZVFHMIN32-NEXT: vmv.x.s a6, v5
+; ZVFHMIN32-NEXT: vmv.x.s a5, v14
+; ZVFHMIN32-NEXT: vmv.x.s a3, v16
+; ZVFHMIN32-NEXT: vmv.x.s a0, v18
+; ZVFHMIN32-NEXT: vmv.x.s a7, v22
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: vmv.x.s t0, v24
+; ZVFHMIN32-NEXT: fmv.h.x fa3, a2
+; ZVFHMIN32-NEXT: vmv.x.s a4, v26
+; ZVFHMIN32-NEXT: fmv.h.x fa2, t3
+; ZVFHMIN32-NEXT: vmv.x.s a1, v28
+; ZVFHMIN32-NEXT: fmv.h.x fa1, t4
+; ZVFHMIN32-NEXT: vmv.x.s a2, v12
+; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFHMIN32-NEXT: vslidedown.vi v22, v8, 6
+; ZVFHMIN32-NEXT: vslidedown.vi v23, v8, 7
+; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFHMIN32-NEXT: vslidedown.vi v10, v8, 8
+; ZVFHMIN32-NEXT: vslidedown.vi v12, v8, 9
+; ZVFHMIN32-NEXT: vslidedown.vi v14, v8, 10
+; ZVFHMIN32-NEXT: vslidedown.vi v18, v8, 13
+; ZVFHMIN32-NEXT: vslidedown.vi v20, v8, 14
+; ZVFHMIN32-NEXT: vslidedown.vi v16, v8, 15
+; ZVFHMIN32-NEXT: fmv.h.x fa0, t1
+; ZVFHMIN32-NEXT: fmv.h.x ft0, t2
+; ZVFHMIN32-NEXT: fmin.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a6
+; ZVFHMIN32-NEXT: fmin.h fa3, fa3, fa2
+; ZVFHMIN32-NEXT: fmv.h.x fa2, a5
+; ZVFHMIN32-NEXT: fmin.h fa1, fa1, fa0
+; ZVFHMIN32-NEXT: fmv.h.x fa0, a7
+; ZVFHMIN32-NEXT: fmin.h fa4, fa4, fa2
+; ZVFHMIN32-NEXT: fmv.h.x fa2, t0
+; ZVFHMIN32-NEXT: fmin.h fa2, fa0, fa2
+; ZVFHMIN32-NEXT: fmv.h.x fa0, a3
+; ZVFHMIN32-NEXT: fmin.h fa5, fa5, fa3
+; ZVFHMIN32-NEXT: fmv.h.x fa3, a4
+; ZVFHMIN32-NEXT: vmv.x.s a3, v22
+; ZVFHMIN32-NEXT: vmv.x.s a4, v23
+; ZVFHMIN32-NEXT: vmv.x.s a5, v18
+; ZVFHMIN32-NEXT: vmv.x.s a6, v20
+; ZVFHMIN32-NEXT: fmin.h fa1, fa1, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a3
+; ZVFHMIN32-NEXT: fmin.h fa4, fa4, fa0
+; ZVFHMIN32-NEXT: fmv.h.x fa0, a4
+; ZVFHMIN32-NEXT: fmin.h fa3, fa2, fa3
+; ZVFHMIN32-NEXT: fmv.h.x fa2, a5
+; ZVFHMIN32-NEXT: fmin.h fa0, ft0, fa0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a6
+; ZVFHMIN32-NEXT: fmin.h fa2, fa2, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a0
+; ZVFHMIN32-NEXT: fmin.h fa5, fa5, fa1
+; ZVFHMIN32-NEXT: fmv.h.x fa1, a1
+; ZVFHMIN32-NEXT: fmin.h fa4, fa4, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a2
+; ZVFHMIN32-NEXT: lh a1, 32(sp)
+; ZVFHMIN32-NEXT: lh a7, 34(sp)
+; ZVFHMIN32-NEXT: lh a5, 36(sp)
+; ZVFHMIN32-NEXT: lh a2, 38(sp)
+; ZVFHMIN32-NEXT: lh t0, 56(sp)
+; ZVFHMIN32-NEXT: lh t1, 58(sp)
+; ZVFHMIN32-NEXT: lh a6, 60(sp)
+; ZVFHMIN32-NEXT: lh a0, 62(sp)
+; ZVFHMIN32-NEXT: vmv.x.s a3, v10
+; ZVFHMIN32-NEXT: vmv.x.s a4, v12
+; ZVFHMIN32-NEXT: vmv.x.s t2, v14
+; ZVFHMIN32-NEXT: fmin.h fa3, fa3, fa1
+; ZVFHMIN32-NEXT: fmv.h.x fa1, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v16
+; ZVFHMIN32-NEXT: fmin.h fa1, fa0, fa1
+; ZVFHMIN32-NEXT: fmv.h.x fa0, a3
+; ZVFHMIN32-NEXT: fmin.h fa2, fa2, fa0
+; ZVFHMIN32-NEXT: fmv.h.x fa0, a4
+; ZVFHMIN32-NEXT: fmin.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, t2
+; ZVFHMIN32-NEXT: fmin.h fa3, fa3, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a1
+; ZVFHMIN32-NEXT: lh a1, 96(sp)
+; ZVFHMIN32-NEXT: lh t2, 98(sp)
+; ZVFHMIN32-NEXT: lh a4, 100(sp)
+; ZVFHMIN32-NEXT: lh a3, 102(sp)
+; ZVFHMIN32-NEXT: fmin.h fa1, fa1, fa0
+; ZVFHMIN32-NEXT: fmv.h.x fa0, a7
+; ZVFHMIN32-NEXT: fmin.h fa5, fa5, fa3
+; ZVFHMIN32-NEXT: fmv.h.x fa3, t0
+; ZVFHMIN32-NEXT: fmin.h fa0, ft0, fa0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, t1
+; ZVFHMIN32-NEXT: fmin.h fa3, fa3, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a1
+; ZVFHMIN32-NEXT: lh a1, 104(sp)
+; ZVFHMIN32-NEXT: lh a7, 106(sp)
+; ZVFHMIN32-NEXT: lh t0, 108(sp)
+; ZVFHMIN32-NEXT: lh t1, 110(sp)
+; ZVFHMIN32-NEXT: fmin.h fa4, fa1, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa1, a7
+; ZVFHMIN32-NEXT: fmin.h fa2, fa2, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, t0
+; ZVFHMIN32-NEXT: vslidedown.vi v10, v8, 11
+; ZVFHMIN32-NEXT: vslidedown.vi v12, v8, 12
+; ZVFHMIN32-NEXT: fmin.h fa1, fa1, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a5
+; ZVFHMIN32-NEXT: vmv.x.s a5, v10
+; ZVFHMIN32-NEXT: fmin.h fa0, fa0, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a6
+; ZVFHMIN32-NEXT: vmv.x.s a6, v12
+; ZVFHMIN32-NEXT: fmin.h fa3, fa3, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a5
+; ZVFHMIN32-NEXT: fmin.h fa4, fa4, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, t2
+; ZVFHMIN32-NEXT: fmin.h fa2, fa2, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, t1
+; ZVFHMIN32-NEXT: fmin.h fa1, fa1, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a2
+; ZVFHMIN32-NEXT: lh a5, 112(sp)
+; ZVFHMIN32-NEXT: lh a7, 114(sp)
+; ZVFHMIN32-NEXT: lh t0, 116(sp)
+; ZVFHMIN32-NEXT: lh a2, 118(sp)
+; ZVFHMIN32-NEXT: fmin.h fa0, fa0, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a0
+; ZVFHMIN32-NEXT: fmin.h fa3, fa3, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a6
+; ZVFHMIN32-NEXT: fmin.h fa4, fa4, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a4
+; ZVFHMIN32-NEXT: fmin.h fa2, fa2, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a5
+; ZVFHMIN32-NEXT: lh a0, 40(sp)
+; ZVFHMIN32-NEXT: lh a4, 42(sp)
+; ZVFHMIN32-NEXT: lh a5, 44(sp)
+; ZVFHMIN32-NEXT: lh a6, 46(sp)
+; ZVFHMIN32-NEXT: fmin.h fa1, fa1, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a0
+; ZVFHMIN32-NEXT: vmv.x.s a0, v8
+; ZVFHMIN32-NEXT: fmin.h fa0, fa0, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a0
+; ZVFHMIN32-NEXT: fmin.h fa3, fa3, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a3
+; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFHMIN32-NEXT: vslidedown.vi v9, v8, 1
+; ZVFHMIN32-NEXT: vslidedown.vi v10, v8, 2
+; ZVFHMIN32-NEXT: vslidedown.vi v11, v8, 3
+; ZVFHMIN32-NEXT: vslidedown.vi v12, v8, 4
+; ZVFHMIN32-NEXT: fmin.h fa2, fa2, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a7
+; ZVFHMIN32-NEXT: vmv.x.s a0, v9
+; ZVFHMIN32-NEXT: fmin.h fa1, fa1, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a4
+; ZVFHMIN32-NEXT: vmv.x.s a3, v10
+; ZVFHMIN32-NEXT: fmin.h fa0, fa0, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a0
+; ZVFHMIN32-NEXT: vmv.x.s a0, v11
+; ZVFHMIN32-NEXT: fmin.h fa3, fa3, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a1
+; ZVFHMIN32-NEXT: fmin.h fa2, fa2, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, t0
+; ZVFHMIN32-NEXT: fmin.h fa1, fa1, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a5
+; ZVFHMIN32-NEXT: fmin.h fa0, fa0, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a3
+; ZVFHMIN32-NEXT: lh a1, 120(sp)
+; ZVFHMIN32-NEXT: lh a3, 122(sp)
+; ZVFHMIN32-NEXT: lh a4, 124(sp)
+; ZVFHMIN32-NEXT: lh a5, 126(sp)
+; ZVFHMIN32-NEXT: fmin.h fa3, fa3, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a2
+; ZVFHMIN32-NEXT: fmin.h fa1, fa1, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a6
+; ZVFHMIN32-NEXT: fmin.h fa0, fa0, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a0
+; ZVFHMIN32-NEXT: fmin.h fa3, fa3, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a1
+; ZVFHMIN32-NEXT: lh a0, 48(sp)
+; ZVFHMIN32-NEXT: lh a1, 50(sp)
+; ZVFHMIN32-NEXT: lh a2, 52(sp)
+; ZVFHMIN32-NEXT: lh a6, 54(sp)
+; ZVFHMIN32-NEXT: fmin.h fa1, fa1, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a0
+; ZVFHMIN32-NEXT: vmv.x.s a0, v12
+; ZVFHMIN32-NEXT: fmin.h fa0, fa0, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a0
+; ZVFHMIN32-NEXT: fmin.h fa3, fa3, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a3
+; ZVFHMIN32-NEXT: vslidedown.vi v8, v8, 5
+; ZVFHMIN32-NEXT: fmin.h fa1, fa1, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a1
+; ZVFHMIN32-NEXT: vmv.x.s a0, v8
+; ZVFHMIN32-NEXT: fmin.h fa0, fa0, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a0
+; ZVFHMIN32-NEXT: fmin.h fa3, fa3, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a4
+; ZVFHMIN32-NEXT: fmin.h fa1, fa1, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a2
+; ZVFHMIN32-NEXT: fmin.h fa0, fa0, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a6
+; ZVFHMIN32-NEXT: fmin.h fa0, fa0, ft0
+; ZVFHMIN32-NEXT: fmin.h fa5, fa5, fa0
+; ZVFHMIN32-NEXT: fmin.h fa5, fa5, fa3
+; ZVFHMIN32-NEXT: fmin.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmin.h fa5, fa5, fa2
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a5
+; ZVFHMIN32-NEXT: fmin.h fa4, fa1, fa4
+; ZVFHMIN32-NEXT: fmin.h fa0, fa5, fa4
+; ZVFHMIN32-NEXT: addi sp, s0, -192
+; ZVFHMIN32-NEXT: .cfi_def_cfa sp, 192
+; ZVFHMIN32-NEXT: lw ra, 188(sp) # 4-byte Folded Reload
+; ZVFHMIN32-NEXT: lw s0, 184(sp) # 4-byte Folded Reload
+; ZVFHMIN32-NEXT: .cfi_restore ra
+; ZVFHMIN32-NEXT: .cfi_restore s0
+; ZVFHMIN32-NEXT: addi sp, sp, 192
+; ZVFHMIN32-NEXT: .cfi_def_cfa_offset 0
+; ZVFHMIN32-NEXT: ret
+;
+; ZVFHMIN64-LABEL: vreduce_fmin_v128f16:
+; ZVFHMIN64: # %bb.0:
+; ZVFHMIN64-NEXT: addi sp, sp, -192
+; ZVFHMIN64-NEXT: .cfi_def_cfa_offset 192
+; ZVFHMIN64-NEXT: sd ra, 184(sp) # 8-byte Folded Spill
+; ZVFHMIN64-NEXT: sd s0, 176(sp) # 8-byte Folded Spill
+; ZVFHMIN64-NEXT: .cfi_offset ra, -8
+; ZVFHMIN64-NEXT: .cfi_offset s0, -16
+; ZVFHMIN64-NEXT: addi s0, sp, 192
+; ZVFHMIN64-NEXT: .cfi_def_cfa s0, 0
+; ZVFHMIN64-NEXT: andi sp, sp, -64
+; ZVFHMIN64-NEXT: addi a2, a0, 128
+; ZVFHMIN64-NEXT: li a3, 64
+; ZVFHMIN64-NEXT: li a1, 32
+; ZVFHMIN64-NEXT: vsetvli zero, a3, e16, m8, ta, ma
+; ZVFHMIN64-NEXT: vle16.v v16, (a0)
+; ZVFHMIN64-NEXT: vle16.v v8, (a2)
+; ZVFHMIN64-NEXT: mv a2, sp
+; ZVFHMIN64-NEXT: addi a0, sp, 64
+; ZVFHMIN64-NEXT: vsetvli zero, a1, e16, m4, ta, ma
+; ZVFHMIN64-NEXT: vfwcvt.f.f.v v24, v16
+; ZVFHMIN64-NEXT: vfwcvt.f.f.v v0, v8
+; ZVFHMIN64-NEXT: vsetvli zero, a1, e16, m8, ta, ma
+; ZVFHMIN64-NEXT: vslidedown.vx v16, v16, a1
+; ZVFHMIN64-NEXT: vslidedown.vx v8, v8, a1
+; ZVFHMIN64-NEXT: vsetvli zero, a1, e32, m8, ta, ma
+; ZVFHMIN64-NEXT: vfmin.vv v24, v24, v0
+; ZVFHMIN64-NEXT: vsetvli zero, zero, e16, m4, ta, ma
+; ZVFHMIN64-NEXT: vfwcvt.f.f.v v0, v16
+; ZVFHMIN64-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN64-NEXT: vfncvt.f.f.w v12, v24
+; ZVFHMIN64-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; ZVFHMIN64-NEXT: vfmin.vv v16, v0, v16
+; ZVFHMIN64-NEXT: vse16.v v12, (a2)
+; ZVFHMIN64-NEXT: vsetvli zero, zero, e16, m4, ta, ma
+; ZVFHMIN64-NEXT: vfncvt.f.f.w v8, v16
+; ZVFHMIN64-NEXT: vmv.x.s a2, v12
+; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFHMIN64-NEXT: vslidedown.vi v20, v12, 1
+; ZVFHMIN64-NEXT: vslidedown.vi v21, v12, 2
+; ZVFHMIN64-NEXT: vslidedown.vi v30, v12, 3
+; ZVFHMIN64-NEXT: vslidedown.vi v31, v12, 4
+; ZVFHMIN64-NEXT: vslidedown.vi v7, v12, 5
+; ZVFHMIN64-NEXT: vslidedown.vi v6, v12, 6
+; ZVFHMIN64-NEXT: vslidedown.vi v5, v12, 7
+; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFHMIN64-NEXT: vslidedown.vi v14, v12, 8
+; ZVFHMIN64-NEXT: vslidedown.vi v16, v12, 9
+; ZVFHMIN64-NEXT: vslidedown.vi v18, v12, 10
+; ZVFHMIN64-NEXT: vslidedown.vi v22, v12, 11
+; ZVFHMIN64-NEXT: vslidedown.vi v24, v12, 12
+; ZVFHMIN64-NEXT: vslidedown.vi v26, v12, 13
+; ZVFHMIN64-NEXT: vslidedown.vi v28, v12, 14
+; ZVFHMIN64-NEXT: vslidedown.vi v12, v12, 15
+; ZVFHMIN64-NEXT: vsetvli zero, a1, e16, m4, ta, ma
+; ZVFHMIN64-NEXT: vse16.v v8, (a0)
+; ZVFHMIN64-NEXT: fmv.h.x fa5, a2
+; ZVFHMIN64-NEXT: vmv.x.s a1, v20
+; ZVFHMIN64-NEXT: vmv.x.s a2, v21
+; ZVFHMIN64-NEXT: vmv.x.s t3, v30
+; ZVFHMIN64-NEXT: vmv.x.s t4, v31
+; ZVFHMIN64-NEXT: vmv.x.s t1, v7
+; ZVFHMIN64-NEXT: vmv.x.s t2, v6
+; ZVFHMIN64-NEXT: vmv.x.s a6, v5
+; ZVFHMIN64-NEXT: vmv.x.s a5, v14
+; ZVFHMIN64-NEXT: vmv.x.s a3, v16
+; ZVFHMIN64-NEXT: vmv.x.s a0, v18
+; ZVFHMIN64-NEXT: vmv.x.s a7, v22
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: vmv.x.s t0, v24
+; ZVFHMIN64-NEXT: fmv.h.x fa3, a2
+; ZVFHMIN64-NEXT: vmv.x.s a4, v26
+; ZVFHMIN64-NEXT: fmv.h.x fa2, t3
+; ZVFHMIN64-NEXT: vmv.x.s a1, v28
+; ZVFHMIN64-NEXT: fmv.h.x fa1, t4
+; ZVFHMIN64-NEXT: vmv.x.s a2, v12
+; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFHMIN64-NEXT: vslidedown.vi v22, v8, 6
+; ZVFHMIN64-NEXT: vslidedown.vi v23, v8, 7
+; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFHMIN64-NEXT: vslidedown.vi v10, v8, 8
+; ZVFHMIN64-NEXT: vslidedown.vi v12, v8, 9
+; ZVFHMIN64-NEXT: vslidedown.vi v14, v8, 10
+; ZVFHMIN64-NEXT: vslidedown.vi v18, v8, 13
+; ZVFHMIN64-NEXT: vslidedown.vi v20, v8, 14
+; ZVFHMIN64-NEXT: vslidedown.vi v16, v8, 15
+; ZVFHMIN64-NEXT: fmv.h.x fa0, t1
+; ZVFHMIN64-NEXT: fmv.h.x ft0, t2
+; ZVFHMIN64-NEXT: fmin.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a6
+; ZVFHMIN64-NEXT: fmin.h fa3, fa3, fa2
+; ZVFHMIN64-NEXT: fmv.h.x fa2, a5
+; ZVFHMIN64-NEXT: fmin.h fa1, fa1, fa0
+; ZVFHMIN64-NEXT: fmv.h.x fa0, a7
+; ZVFHMIN64-NEXT: fmin.h fa4, fa4, fa2
+; ZVFHMIN64-NEXT: fmv.h.x fa2, t0
+; ZVFHMIN64-NEXT: fmin.h fa2, fa0, fa2
+; ZVFHMIN64-NEXT: fmv.h.x fa0, a3
+; ZVFHMIN64-NEXT: fmin.h fa5, fa5, fa3
+; ZVFHMIN64-NEXT: fmv.h.x fa3, a4
+; ZVFHMIN64-NEXT: vmv.x.s a3, v22
+; ZVFHMIN64-NEXT: vmv.x.s a4, v23
+; ZVFHMIN64-NEXT: vmv.x.s a5, v18
+; ZVFHMIN64-NEXT: vmv.x.s a6, v20
+; ZVFHMIN64-NEXT: fmin.h fa1, fa1, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a3
+; ZVFHMIN64-NEXT: fmin.h fa4, fa4, fa0
+; ZVFHMIN64-NEXT: fmv.h.x fa0, a4
+; ZVFHMIN64-NEXT: fmin.h fa3, fa2, fa3
+; ZVFHMIN64-NEXT: fmv.h.x fa2, a5
+; ZVFHMIN64-NEXT: fmin.h fa0, ft0, fa0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a6
+; ZVFHMIN64-NEXT: fmin.h fa2, fa2, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a0
+; ZVFHMIN64-NEXT: fmin.h fa5, fa5, fa1
+; ZVFHMIN64-NEXT: fmv.h.x fa1, a1
+; ZVFHMIN64-NEXT: fmin.h fa4, fa4, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a2
+; ZVFHMIN64-NEXT: lh a1, 32(sp)
+; ZVFHMIN64-NEXT: lh a7, 34(sp)
+; ZVFHMIN64-NEXT: lh a5, 36(sp)
+; ZVFHMIN64-NEXT: lh a2, 38(sp)
+; ZVFHMIN64-NEXT: lh t0, 56(sp)
+; ZVFHMIN64-NEXT: lh t1, 58(sp)
+; ZVFHMIN64-NEXT: lh a6, 60(sp)
+; ZVFHMIN64-NEXT: lh a0, 62(sp)
+; ZVFHMIN64-NEXT: vmv.x.s a3, v10
+; ZVFHMIN64-NEXT: vmv.x.s a4, v12
+; ZVFHMIN64-NEXT: vmv.x.s t2, v14
+; ZVFHMIN64-NEXT: fmin.h fa3, fa3, fa1
+; ZVFHMIN64-NEXT: fmv.h.x fa1, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v16
+; ZVFHMIN64-NEXT: fmin.h fa1, fa0, fa1
+; ZVFHMIN64-NEXT: fmv.h.x fa0, a3
+; ZVFHMIN64-NEXT: fmin.h fa2, fa2, fa0
+; ZVFHMIN64-NEXT: fmv.h.x fa0, a4
+; ZVFHMIN64-NEXT: fmin.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, t2
+; ZVFHMIN64-NEXT: fmin.h fa3, fa3, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a1
+; ZVFHMIN64-NEXT: lh a1, 96(sp)
+; ZVFHMIN64-NEXT: lh t2, 98(sp)
+; ZVFHMIN64-NEXT: lh a4, 100(sp)
+; ZVFHMIN64-NEXT: lh a3, 102(sp)
+; ZVFHMIN64-NEXT: fmin.h fa1, fa1, fa0
+; ZVFHMIN64-NEXT: fmv.h.x fa0, a7
+; ZVFHMIN64-NEXT: fmin.h fa5, fa5, fa3
+; ZVFHMIN64-NEXT: fmv.h.x fa3, t0
+; ZVFHMIN64-NEXT: fmin.h fa0, ft0, fa0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, t1
+; ZVFHMIN64-NEXT: fmin.h fa3, fa3, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a1
+; ZVFHMIN64-NEXT: lh a1, 104(sp)
+; ZVFHMIN64-NEXT: lh a7, 106(sp)
+; ZVFHMIN64-NEXT: lh t0, 108(sp)
+; ZVFHMIN64-NEXT: lh t1, 110(sp)
+; ZVFHMIN64-NEXT: fmin.h fa4, fa1, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa1, a7
+; ZVFHMIN64-NEXT: fmin.h fa2, fa2, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, t0
+; ZVFHMIN64-NEXT: vslidedown.vi v10, v8, 11
+; ZVFHMIN64-NEXT: vslidedown.vi v12, v8, 12
+; ZVFHMIN64-NEXT: fmin.h fa1, fa1, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a5
+; ZVFHMIN64-NEXT: vmv.x.s a5, v10
+; ZVFHMIN64-NEXT: fmin.h fa0, fa0, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a6
+; ZVFHMIN64-NEXT: vmv.x.s a6, v12
+; ZVFHMIN64-NEXT: fmin.h fa3, fa3, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a5
+; ZVFHMIN64-NEXT: fmin.h fa4, fa4, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, t2
+; ZVFHMIN64-NEXT: fmin.h fa2, fa2, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, t1
+; ZVFHMIN64-NEXT: fmin.h fa1, fa1, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a2
+; ZVFHMIN64-NEXT: lh a5, 112(sp)
+; ZVFHMIN64-NEXT: lh a7, 114(sp)
+; ZVFHMIN64-NEXT: lh t0, 116(sp)
+; ZVFHMIN64-NEXT: lh a2, 118(sp)
+; ZVFHMIN64-NEXT: fmin.h fa0, fa0, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a0
+; ZVFHMIN64-NEXT: fmin.h fa3, fa3, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a6
+; ZVFHMIN64-NEXT: fmin.h fa4, fa4, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a4
+; ZVFHMIN64-NEXT: fmin.h fa2, fa2, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a5
+; ZVFHMIN64-NEXT: lh a0, 40(sp)
+; ZVFHMIN64-NEXT: lh a4, 42(sp)
+; ZVFHMIN64-NEXT: lh a5, 44(sp)
+; ZVFHMIN64-NEXT: lh a6, 46(sp)
+; ZVFHMIN64-NEXT: fmin.h fa1, fa1, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a0
+; ZVFHMIN64-NEXT: vmv.x.s a0, v8
+; ZVFHMIN64-NEXT: fmin.h fa0, fa0, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a0
+; ZVFHMIN64-NEXT: fmin.h fa3, fa3, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a3
+; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFHMIN64-NEXT: vslidedown.vi v9, v8, 1
+; ZVFHMIN64-NEXT: vslidedown.vi v10, v8, 2
+; ZVFHMIN64-NEXT: vslidedown.vi v11, v8, 3
+; ZVFHMIN64-NEXT: vslidedown.vi v12, v8, 4
+; ZVFHMIN64-NEXT: fmin.h fa2, fa2, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a7
+; ZVFHMIN64-NEXT: vmv.x.s a0, v9
+; ZVFHMIN64-NEXT: fmin.h fa1, fa1, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a4
+; ZVFHMIN64-NEXT: vmv.x.s a3, v10
+; ZVFHMIN64-NEXT: fmin.h fa0, fa0, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a0
+; ZVFHMIN64-NEXT: vmv.x.s a0, v11
+; ZVFHMIN64-NEXT: fmin.h fa3, fa3, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a1
+; ZVFHMIN64-NEXT: fmin.h fa2, fa2, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, t0
+; ZVFHMIN64-NEXT: fmin.h fa1, fa1, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a5
+; ZVFHMIN64-NEXT: fmin.h fa0, fa0, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a3
+; ZVFHMIN64-NEXT: lh a1, 120(sp)
+; ZVFHMIN64-NEXT: lh a3, 122(sp)
+; ZVFHMIN64-NEXT: lh a4, 124(sp)
+; ZVFHMIN64-NEXT: lh a5, 126(sp)
+; ZVFHMIN64-NEXT: fmin.h fa3, fa3, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a2
+; ZVFHMIN64-NEXT: fmin.h fa1, fa1, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a6
+; ZVFHMIN64-NEXT: fmin.h fa0, fa0, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a0
+; ZVFHMIN64-NEXT: fmin.h fa3, fa3, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a1
+; ZVFHMIN64-NEXT: lh a0, 48(sp)
+; ZVFHMIN64-NEXT: lh a1, 50(sp)
+; ZVFHMIN64-NEXT: lh a2, 52(sp)
+; ZVFHMIN64-NEXT: lh a6, 54(sp)
+; ZVFHMIN64-NEXT: fmin.h fa1, fa1, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a0
+; ZVFHMIN64-NEXT: vmv.x.s a0, v12
+; ZVFHMIN64-NEXT: fmin.h fa0, fa0, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a0
+; ZVFHMIN64-NEXT: fmin.h fa3, fa3, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a3
+; ZVFHMIN64-NEXT: vslidedown.vi v8, v8, 5
+; ZVFHMIN64-NEXT: fmin.h fa1, fa1, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a1
+; ZVFHMIN64-NEXT: vmv.x.s a0, v8
+; ZVFHMIN64-NEXT: fmin.h fa0, fa0, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a0
+; ZVFHMIN64-NEXT: fmin.h fa3, fa3, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a4
+; ZVFHMIN64-NEXT: fmin.h fa1, fa1, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a2
+; ZVFHMIN64-NEXT: fmin.h fa0, fa0, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a6
+; ZVFHMIN64-NEXT: fmin.h fa0, fa0, ft0
+; ZVFHMIN64-NEXT: fmin.h fa5, fa5, fa0
+; ZVFHMIN64-NEXT: fmin.h fa5, fa5, fa3
+; ZVFHMIN64-NEXT: fmin.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmin.h fa5, fa5, fa2
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a5
+; ZVFHMIN64-NEXT: fmin.h fa4, fa1, fa4
+; ZVFHMIN64-NEXT: fmin.h fa0, fa5, fa4
+; ZVFHMIN64-NEXT: addi sp, s0, -192
+; ZVFHMIN64-NEXT: .cfi_def_cfa sp, 192
+; ZVFHMIN64-NEXT: ld ra, 184(sp) # 8-byte Folded Reload
+; ZVFHMIN64-NEXT: ld s0, 176(sp) # 8-byte Folded Reload
+; ZVFHMIN64-NEXT: .cfi_restore ra
+; ZVFHMIN64-NEXT: .cfi_restore s0
+; ZVFHMIN64-NEXT: addi sp, sp, 192
+; ZVFHMIN64-NEXT: .cfi_def_cfa_offset 0
+; ZVFHMIN64-NEXT: ret
%v = load <128 x half>, ptr %x
%red = call half @llvm.vector.reduce.fmin.v128f16(<128 x half> %v)
ret half %red
@@ -1371,69 +5406,661 @@ define double @vreduce_fmin_v32f64(ptr %x) {
}
define half @vreduce_fmax_v2f16(ptr %x) {
-; CHECK-LABEL: vreduce_fmax_v2f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vfredmax.vs v8, v8, v8
-; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: vreduce_fmax_v2f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vfredmax.vs v8, v8, v8
+; ZVFH-NEXT: vfmv.f.s fa0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: vreduce_fmax_v2f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a0)
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfredmax.vs v8, v9, v9
+; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
+; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
+; ZVFHMIN-NEXT: ret
%v = load <2 x half>, ptr %x
%red = call half @llvm.vector.reduce.fmax.v2f16(<2 x half> %v)
ret half %red
}
define half @vreduce_fmax_v4f16(ptr %x) {
-; CHECK-LABEL: vreduce_fmax_v4f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vfredmax.vs v8, v8, v8
-; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: vreduce_fmax_v4f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vfredmax.vs v8, v8, v8
+; ZVFH-NEXT: vfmv.f.s fa0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: vreduce_fmax_v4f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a0)
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vfredmax.vs v8, v9, v9
+; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
+; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
+; ZVFHMIN-NEXT: ret
%v = load <4 x half>, ptr %x
%red = call half @llvm.vector.reduce.fmax.v4f16(<4 x half> %v)
ret half %red
}
define half @vreduce_fmax_v4f16_nonans(ptr %x) {
-; CHECK-LABEL: vreduce_fmax_v4f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vfredmax.vs v8, v8, v8
-; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: vreduce_fmax_v4f16_nonans:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vfredmax.vs v8, v8, v8
+; ZVFH-NEXT: vfmv.f.s fa0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: vreduce_fmax_v4f16_nonans:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a0)
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vfredmax.vs v8, v9, v9
+; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
+; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
+; ZVFHMIN-NEXT: ret
%v = load <4 x half>, ptr %x
%red = call nnan half @llvm.vector.reduce.fmax.v4f16(<4 x half> %v)
ret half %red
}
define half @vreduce_fmax_v4f16_nonans_noinfs(ptr %x) {
-; CHECK-LABEL: vreduce_fmax_v4f16_nonans_noinfs:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vfredmax.vs v8, v8, v8
-; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: vreduce_fmax_v4f16_nonans_noinfs:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vfredmax.vs v8, v8, v8
+; ZVFH-NEXT: vfmv.f.s fa0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: vreduce_fmax_v4f16_nonans_noinfs:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a0)
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vfredmax.vs v8, v9, v9
+; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
+; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
+; ZVFHMIN-NEXT: ret
%v = load <4 x half>, ptr %x
%red = call nnan ninf half @llvm.vector.reduce.fmax.v4f16(<4 x half> %v)
ret half %red
}
define half @vreduce_fmax_v128f16(ptr %x) {
-; CHECK-LABEL: vreduce_fmax_v128f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, 64
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: addi a0, a0, 128
-; CHECK-NEXT: vle16.v v16, (a0)
-; CHECK-NEXT: vfmax.vv v8, v8, v16
-; CHECK-NEXT: vfredmax.vs v8, v8, v8
-; CHECK-NEXT: vfmv.f.s fa0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: vreduce_fmax_v128f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: li a1, 64
+; ZVFH-NEXT: vsetvli zero, a1, e16, m8, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: addi a0, a0, 128
+; ZVFH-NEXT: vle16.v v16, (a0)
+; ZVFH-NEXT: vfmax.vv v8, v8, v16
+; ZVFH-NEXT: vfredmax.vs v8, v8, v8
+; ZVFH-NEXT: vfmv.f.s fa0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN32-LABEL: vreduce_fmax_v128f16:
+; ZVFHMIN32: # %bb.0:
+; ZVFHMIN32-NEXT: addi sp, sp, -192
+; ZVFHMIN32-NEXT: .cfi_def_cfa_offset 192
+; ZVFHMIN32-NEXT: sw ra, 188(sp) # 4-byte Folded Spill
+; ZVFHMIN32-NEXT: sw s0, 184(sp) # 4-byte Folded Spill
+; ZVFHMIN32-NEXT: .cfi_offset ra, -4
+; ZVFHMIN32-NEXT: .cfi_offset s0, -8
+; ZVFHMIN32-NEXT: addi s0, sp, 192
+; ZVFHMIN32-NEXT: .cfi_def_cfa s0, 0
+; ZVFHMIN32-NEXT: andi sp, sp, -64
+; ZVFHMIN32-NEXT: addi a2, a0, 128
+; ZVFHMIN32-NEXT: li a3, 64
+; ZVFHMIN32-NEXT: li a1, 32
+; ZVFHMIN32-NEXT: vsetvli zero, a3, e16, m8, ta, ma
+; ZVFHMIN32-NEXT: vle16.v v16, (a0)
+; ZVFHMIN32-NEXT: vle16.v v8, (a2)
+; ZVFHMIN32-NEXT: mv a2, sp
+; ZVFHMIN32-NEXT: addi a0, sp, 64
+; ZVFHMIN32-NEXT: vsetvli zero, a1, e16, m4, ta, ma
+; ZVFHMIN32-NEXT: vfwcvt.f.f.v v24, v16
+; ZVFHMIN32-NEXT: vfwcvt.f.f.v v0, v8
+; ZVFHMIN32-NEXT: vsetvli zero, a1, e16, m8, ta, ma
+; ZVFHMIN32-NEXT: vslidedown.vx v16, v16, a1
+; ZVFHMIN32-NEXT: vslidedown.vx v8, v8, a1
+; ZVFHMIN32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
+; ZVFHMIN32-NEXT: vfmax.vv v24, v24, v0
+; ZVFHMIN32-NEXT: vsetvli zero, zero, e16, m4, ta, ma
+; ZVFHMIN32-NEXT: vfwcvt.f.f.v v0, v16
+; ZVFHMIN32-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN32-NEXT: vfncvt.f.f.w v12, v24
+; ZVFHMIN32-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; ZVFHMIN32-NEXT: vfmax.vv v16, v0, v16
+; ZVFHMIN32-NEXT: vse16.v v12, (a2)
+; ZVFHMIN32-NEXT: vsetvli zero, zero, e16, m4, ta, ma
+; ZVFHMIN32-NEXT: vfncvt.f.f.w v8, v16
+; ZVFHMIN32-NEXT: vmv.x.s a2, v12
+; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFHMIN32-NEXT: vslidedown.vi v20, v12, 1
+; ZVFHMIN32-NEXT: vslidedown.vi v21, v12, 2
+; ZVFHMIN32-NEXT: vslidedown.vi v30, v12, 3
+; ZVFHMIN32-NEXT: vslidedown.vi v31, v12, 4
+; ZVFHMIN32-NEXT: vslidedown.vi v7, v12, 5
+; ZVFHMIN32-NEXT: vslidedown.vi v6, v12, 6
+; ZVFHMIN32-NEXT: vslidedown.vi v5, v12, 7
+; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFHMIN32-NEXT: vslidedown.vi v14, v12, 8
+; ZVFHMIN32-NEXT: vslidedown.vi v16, v12, 9
+; ZVFHMIN32-NEXT: vslidedown.vi v18, v12, 10
+; ZVFHMIN32-NEXT: vslidedown.vi v22, v12, 11
+; ZVFHMIN32-NEXT: vslidedown.vi v24, v12, 12
+; ZVFHMIN32-NEXT: vslidedown.vi v26, v12, 13
+; ZVFHMIN32-NEXT: vslidedown.vi v28, v12, 14
+; ZVFHMIN32-NEXT: vslidedown.vi v12, v12, 15
+; ZVFHMIN32-NEXT: vsetvli zero, a1, e16, m4, ta, ma
+; ZVFHMIN32-NEXT: vse16.v v8, (a0)
+; ZVFHMIN32-NEXT: fmv.h.x fa5, a2
+; ZVFHMIN32-NEXT: vmv.x.s a1, v20
+; ZVFHMIN32-NEXT: vmv.x.s a2, v21
+; ZVFHMIN32-NEXT: vmv.x.s t3, v30
+; ZVFHMIN32-NEXT: vmv.x.s t4, v31
+; ZVFHMIN32-NEXT: vmv.x.s t1, v7
+; ZVFHMIN32-NEXT: vmv.x.s t2, v6
+; ZVFHMIN32-NEXT: vmv.x.s a6, v5
+; ZVFHMIN32-NEXT: vmv.x.s a5, v14
+; ZVFHMIN32-NEXT: vmv.x.s a3, v16
+; ZVFHMIN32-NEXT: vmv.x.s a0, v18
+; ZVFHMIN32-NEXT: vmv.x.s a7, v22
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN32-NEXT: vmv.x.s t0, v24
+; ZVFHMIN32-NEXT: fmv.h.x fa3, a2
+; ZVFHMIN32-NEXT: vmv.x.s a4, v26
+; ZVFHMIN32-NEXT: fmv.h.x fa2, t3
+; ZVFHMIN32-NEXT: vmv.x.s a1, v28
+; ZVFHMIN32-NEXT: fmv.h.x fa1, t4
+; ZVFHMIN32-NEXT: vmv.x.s a2, v12
+; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFHMIN32-NEXT: vslidedown.vi v22, v8, 6
+; ZVFHMIN32-NEXT: vslidedown.vi v23, v8, 7
+; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFHMIN32-NEXT: vslidedown.vi v10, v8, 8
+; ZVFHMIN32-NEXT: vslidedown.vi v12, v8, 9
+; ZVFHMIN32-NEXT: vslidedown.vi v14, v8, 10
+; ZVFHMIN32-NEXT: vslidedown.vi v18, v8, 13
+; ZVFHMIN32-NEXT: vslidedown.vi v20, v8, 14
+; ZVFHMIN32-NEXT: vslidedown.vi v16, v8, 15
+; ZVFHMIN32-NEXT: fmv.h.x fa0, t1
+; ZVFHMIN32-NEXT: fmv.h.x ft0, t2
+; ZVFHMIN32-NEXT: fmax.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a6
+; ZVFHMIN32-NEXT: fmax.h fa3, fa3, fa2
+; ZVFHMIN32-NEXT: fmv.h.x fa2, a5
+; ZVFHMIN32-NEXT: fmax.h fa1, fa1, fa0
+; ZVFHMIN32-NEXT: fmv.h.x fa0, a7
+; ZVFHMIN32-NEXT: fmax.h fa4, fa4, fa2
+; ZVFHMIN32-NEXT: fmv.h.x fa2, t0
+; ZVFHMIN32-NEXT: fmax.h fa2, fa0, fa2
+; ZVFHMIN32-NEXT: fmv.h.x fa0, a3
+; ZVFHMIN32-NEXT: fmax.h fa5, fa5, fa3
+; ZVFHMIN32-NEXT: fmv.h.x fa3, a4
+; ZVFHMIN32-NEXT: vmv.x.s a3, v22
+; ZVFHMIN32-NEXT: vmv.x.s a4, v23
+; ZVFHMIN32-NEXT: vmv.x.s a5, v18
+; ZVFHMIN32-NEXT: vmv.x.s a6, v20
+; ZVFHMIN32-NEXT: fmax.h fa1, fa1, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a3
+; ZVFHMIN32-NEXT: fmax.h fa4, fa4, fa0
+; ZVFHMIN32-NEXT: fmv.h.x fa0, a4
+; ZVFHMIN32-NEXT: fmax.h fa3, fa2, fa3
+; ZVFHMIN32-NEXT: fmv.h.x fa2, a5
+; ZVFHMIN32-NEXT: fmax.h fa0, ft0, fa0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a6
+; ZVFHMIN32-NEXT: fmax.h fa2, fa2, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a0
+; ZVFHMIN32-NEXT: fmax.h fa5, fa5, fa1
+; ZVFHMIN32-NEXT: fmv.h.x fa1, a1
+; ZVFHMIN32-NEXT: fmax.h fa4, fa4, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a2
+; ZVFHMIN32-NEXT: lh a1, 32(sp)
+; ZVFHMIN32-NEXT: lh a7, 34(sp)
+; ZVFHMIN32-NEXT: lh a5, 36(sp)
+; ZVFHMIN32-NEXT: lh a2, 38(sp)
+; ZVFHMIN32-NEXT: lh t0, 56(sp)
+; ZVFHMIN32-NEXT: lh t1, 58(sp)
+; ZVFHMIN32-NEXT: lh a6, 60(sp)
+; ZVFHMIN32-NEXT: lh a0, 62(sp)
+; ZVFHMIN32-NEXT: vmv.x.s a3, v10
+; ZVFHMIN32-NEXT: vmv.x.s a4, v12
+; ZVFHMIN32-NEXT: vmv.x.s t2, v14
+; ZVFHMIN32-NEXT: fmax.h fa3, fa3, fa1
+; ZVFHMIN32-NEXT: fmv.h.x fa1, a3
+; ZVFHMIN32-NEXT: vmv.x.s a3, v16
+; ZVFHMIN32-NEXT: fmax.h fa1, fa0, fa1
+; ZVFHMIN32-NEXT: fmv.h.x fa0, a3
+; ZVFHMIN32-NEXT: fmax.h fa2, fa2, fa0
+; ZVFHMIN32-NEXT: fmv.h.x fa0, a4
+; ZVFHMIN32-NEXT: fmax.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa4, t2
+; ZVFHMIN32-NEXT: fmax.h fa3, fa3, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a1
+; ZVFHMIN32-NEXT: lh a1, 96(sp)
+; ZVFHMIN32-NEXT: lh t2, 98(sp)
+; ZVFHMIN32-NEXT: lh a4, 100(sp)
+; ZVFHMIN32-NEXT: lh a3, 102(sp)
+; ZVFHMIN32-NEXT: fmax.h fa1, fa1, fa0
+; ZVFHMIN32-NEXT: fmv.h.x fa0, a7
+; ZVFHMIN32-NEXT: fmax.h fa5, fa5, fa3
+; ZVFHMIN32-NEXT: fmv.h.x fa3, t0
+; ZVFHMIN32-NEXT: fmax.h fa0, ft0, fa0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, t1
+; ZVFHMIN32-NEXT: fmax.h fa3, fa3, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a1
+; ZVFHMIN32-NEXT: lh a1, 104(sp)
+; ZVFHMIN32-NEXT: lh a7, 106(sp)
+; ZVFHMIN32-NEXT: lh t0, 108(sp)
+; ZVFHMIN32-NEXT: lh t1, 110(sp)
+; ZVFHMIN32-NEXT: fmax.h fa4, fa1, fa4
+; ZVFHMIN32-NEXT: fmv.h.x fa1, a7
+; ZVFHMIN32-NEXT: fmax.h fa2, fa2, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, t0
+; ZVFHMIN32-NEXT: vslidedown.vi v10, v8, 11
+; ZVFHMIN32-NEXT: vslidedown.vi v12, v8, 12
+; ZVFHMIN32-NEXT: fmax.h fa1, fa1, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a5
+; ZVFHMIN32-NEXT: vmv.x.s a5, v10
+; ZVFHMIN32-NEXT: fmax.h fa0, fa0, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a6
+; ZVFHMIN32-NEXT: vmv.x.s a6, v12
+; ZVFHMIN32-NEXT: fmax.h fa3, fa3, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a5
+; ZVFHMIN32-NEXT: fmax.h fa4, fa4, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, t2
+; ZVFHMIN32-NEXT: fmax.h fa2, fa2, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, t1
+; ZVFHMIN32-NEXT: fmax.h fa1, fa1, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a2
+; ZVFHMIN32-NEXT: lh a5, 112(sp)
+; ZVFHMIN32-NEXT: lh a7, 114(sp)
+; ZVFHMIN32-NEXT: lh t0, 116(sp)
+; ZVFHMIN32-NEXT: lh a2, 118(sp)
+; ZVFHMIN32-NEXT: fmax.h fa0, fa0, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a0
+; ZVFHMIN32-NEXT: fmax.h fa3, fa3, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a6
+; ZVFHMIN32-NEXT: fmax.h fa4, fa4, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a4
+; ZVFHMIN32-NEXT: fmax.h fa2, fa2, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a5
+; ZVFHMIN32-NEXT: lh a0, 40(sp)
+; ZVFHMIN32-NEXT: lh a4, 42(sp)
+; ZVFHMIN32-NEXT: lh a5, 44(sp)
+; ZVFHMIN32-NEXT: lh a6, 46(sp)
+; ZVFHMIN32-NEXT: fmax.h fa1, fa1, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a0
+; ZVFHMIN32-NEXT: vmv.x.s a0, v8
+; ZVFHMIN32-NEXT: fmax.h fa0, fa0, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a0
+; ZVFHMIN32-NEXT: fmax.h fa3, fa3, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a3
+; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFHMIN32-NEXT: vslidedown.vi v9, v8, 1
+; ZVFHMIN32-NEXT: vslidedown.vi v10, v8, 2
+; ZVFHMIN32-NEXT: vslidedown.vi v11, v8, 3
+; ZVFHMIN32-NEXT: vslidedown.vi v12, v8, 4
+; ZVFHMIN32-NEXT: fmax.h fa2, fa2, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a7
+; ZVFHMIN32-NEXT: vmv.x.s a0, v9
+; ZVFHMIN32-NEXT: fmax.h fa1, fa1, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a4
+; ZVFHMIN32-NEXT: vmv.x.s a3, v10
+; ZVFHMIN32-NEXT: fmax.h fa0, fa0, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a0
+; ZVFHMIN32-NEXT: vmv.x.s a0, v11
+; ZVFHMIN32-NEXT: fmax.h fa3, fa3, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a1
+; ZVFHMIN32-NEXT: fmax.h fa2, fa2, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, t0
+; ZVFHMIN32-NEXT: fmax.h fa1, fa1, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a5
+; ZVFHMIN32-NEXT: fmax.h fa0, fa0, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a3
+; ZVFHMIN32-NEXT: lh a1, 120(sp)
+; ZVFHMIN32-NEXT: lh a3, 122(sp)
+; ZVFHMIN32-NEXT: lh a4, 124(sp)
+; ZVFHMIN32-NEXT: lh a5, 126(sp)
+; ZVFHMIN32-NEXT: fmax.h fa3, fa3, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a2
+; ZVFHMIN32-NEXT: fmax.h fa1, fa1, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a6
+; ZVFHMIN32-NEXT: fmax.h fa0, fa0, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a0
+; ZVFHMIN32-NEXT: fmax.h fa3, fa3, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a1
+; ZVFHMIN32-NEXT: lh a0, 48(sp)
+; ZVFHMIN32-NEXT: lh a1, 50(sp)
+; ZVFHMIN32-NEXT: lh a2, 52(sp)
+; ZVFHMIN32-NEXT: lh a6, 54(sp)
+; ZVFHMIN32-NEXT: fmax.h fa1, fa1, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a0
+; ZVFHMIN32-NEXT: vmv.x.s a0, v12
+; ZVFHMIN32-NEXT: fmax.h fa0, fa0, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a0
+; ZVFHMIN32-NEXT: fmax.h fa3, fa3, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a3
+; ZVFHMIN32-NEXT: vslidedown.vi v8, v8, 5
+; ZVFHMIN32-NEXT: fmax.h fa1, fa1, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a1
+; ZVFHMIN32-NEXT: vmv.x.s a0, v8
+; ZVFHMIN32-NEXT: fmax.h fa0, fa0, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a0
+; ZVFHMIN32-NEXT: fmax.h fa3, fa3, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a4
+; ZVFHMIN32-NEXT: fmax.h fa1, fa1, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a2
+; ZVFHMIN32-NEXT: fmax.h fa0, fa0, ft0
+; ZVFHMIN32-NEXT: fmv.h.x ft0, a6
+; ZVFHMIN32-NEXT: fmax.h fa0, fa0, ft0
+; ZVFHMIN32-NEXT: fmax.h fa5, fa5, fa0
+; ZVFHMIN32-NEXT: fmax.h fa5, fa5, fa3
+; ZVFHMIN32-NEXT: fmax.h fa5, fa5, fa4
+; ZVFHMIN32-NEXT: fmax.h fa5, fa5, fa2
+; ZVFHMIN32-NEXT: fmv.h.x fa4, a5
+; ZVFHMIN32-NEXT: fmax.h fa4, fa1, fa4
+; ZVFHMIN32-NEXT: fmax.h fa0, fa5, fa4
+; ZVFHMIN32-NEXT: addi sp, s0, -192
+; ZVFHMIN32-NEXT: .cfi_def_cfa sp, 192
+; ZVFHMIN32-NEXT: lw ra, 188(sp) # 4-byte Folded Reload
+; ZVFHMIN32-NEXT: lw s0, 184(sp) # 4-byte Folded Reload
+; ZVFHMIN32-NEXT: .cfi_restore ra
+; ZVFHMIN32-NEXT: .cfi_restore s0
+; ZVFHMIN32-NEXT: addi sp, sp, 192
+; ZVFHMIN32-NEXT: .cfi_def_cfa_offset 0
+; ZVFHMIN32-NEXT: ret
+;
+; ZVFHMIN64-LABEL: vreduce_fmax_v128f16:
+; ZVFHMIN64: # %bb.0:
+; ZVFHMIN64-NEXT: addi sp, sp, -192
+; ZVFHMIN64-NEXT: .cfi_def_cfa_offset 192
+; ZVFHMIN64-NEXT: sd ra, 184(sp) # 8-byte Folded Spill
+; ZVFHMIN64-NEXT: sd s0, 176(sp) # 8-byte Folded Spill
+; ZVFHMIN64-NEXT: .cfi_offset ra, -8
+; ZVFHMIN64-NEXT: .cfi_offset s0, -16
+; ZVFHMIN64-NEXT: addi s0, sp, 192
+; ZVFHMIN64-NEXT: .cfi_def_cfa s0, 0
+; ZVFHMIN64-NEXT: andi sp, sp, -64
+; ZVFHMIN64-NEXT: addi a2, a0, 128
+; ZVFHMIN64-NEXT: li a3, 64
+; ZVFHMIN64-NEXT: li a1, 32
+; ZVFHMIN64-NEXT: vsetvli zero, a3, e16, m8, ta, ma
+; ZVFHMIN64-NEXT: vle16.v v16, (a0)
+; ZVFHMIN64-NEXT: vle16.v v8, (a2)
+; ZVFHMIN64-NEXT: mv a2, sp
+; ZVFHMIN64-NEXT: addi a0, sp, 64
+; ZVFHMIN64-NEXT: vsetvli zero, a1, e16, m4, ta, ma
+; ZVFHMIN64-NEXT: vfwcvt.f.f.v v24, v16
+; ZVFHMIN64-NEXT: vfwcvt.f.f.v v0, v8
+; ZVFHMIN64-NEXT: vsetvli zero, a1, e16, m8, ta, ma
+; ZVFHMIN64-NEXT: vslidedown.vx v16, v16, a1
+; ZVFHMIN64-NEXT: vslidedown.vx v8, v8, a1
+; ZVFHMIN64-NEXT: vsetvli zero, a1, e32, m8, ta, ma
+; ZVFHMIN64-NEXT: vfmax.vv v24, v24, v0
+; ZVFHMIN64-NEXT: vsetvli zero, zero, e16, m4, ta, ma
+; ZVFHMIN64-NEXT: vfwcvt.f.f.v v0, v16
+; ZVFHMIN64-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN64-NEXT: vfncvt.f.f.w v12, v24
+; ZVFHMIN64-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; ZVFHMIN64-NEXT: vfmax.vv v16, v0, v16
+; ZVFHMIN64-NEXT: vse16.v v12, (a2)
+; ZVFHMIN64-NEXT: vsetvli zero, zero, e16, m4, ta, ma
+; ZVFHMIN64-NEXT: vfncvt.f.f.w v8, v16
+; ZVFHMIN64-NEXT: vmv.x.s a2, v12
+; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFHMIN64-NEXT: vslidedown.vi v20, v12, 1
+; ZVFHMIN64-NEXT: vslidedown.vi v21, v12, 2
+; ZVFHMIN64-NEXT: vslidedown.vi v30, v12, 3
+; ZVFHMIN64-NEXT: vslidedown.vi v31, v12, 4
+; ZVFHMIN64-NEXT: vslidedown.vi v7, v12, 5
+; ZVFHMIN64-NEXT: vslidedown.vi v6, v12, 6
+; ZVFHMIN64-NEXT: vslidedown.vi v5, v12, 7
+; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFHMIN64-NEXT: vslidedown.vi v14, v12, 8
+; ZVFHMIN64-NEXT: vslidedown.vi v16, v12, 9
+; ZVFHMIN64-NEXT: vslidedown.vi v18, v12, 10
+; ZVFHMIN64-NEXT: vslidedown.vi v22, v12, 11
+; ZVFHMIN64-NEXT: vslidedown.vi v24, v12, 12
+; ZVFHMIN64-NEXT: vslidedown.vi v26, v12, 13
+; ZVFHMIN64-NEXT: vslidedown.vi v28, v12, 14
+; ZVFHMIN64-NEXT: vslidedown.vi v12, v12, 15
+; ZVFHMIN64-NEXT: vsetvli zero, a1, e16, m4, ta, ma
+; ZVFHMIN64-NEXT: vse16.v v8, (a0)
+; ZVFHMIN64-NEXT: fmv.h.x fa5, a2
+; ZVFHMIN64-NEXT: vmv.x.s a1, v20
+; ZVFHMIN64-NEXT: vmv.x.s a2, v21
+; ZVFHMIN64-NEXT: vmv.x.s t3, v30
+; ZVFHMIN64-NEXT: vmv.x.s t4, v31
+; ZVFHMIN64-NEXT: vmv.x.s t1, v7
+; ZVFHMIN64-NEXT: vmv.x.s t2, v6
+; ZVFHMIN64-NEXT: vmv.x.s a6, v5
+; ZVFHMIN64-NEXT: vmv.x.s a5, v14
+; ZVFHMIN64-NEXT: vmv.x.s a3, v16
+; ZVFHMIN64-NEXT: vmv.x.s a0, v18
+; ZVFHMIN64-NEXT: vmv.x.s a7, v22
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
+; ZVFHMIN64-NEXT: vmv.x.s t0, v24
+; ZVFHMIN64-NEXT: fmv.h.x fa3, a2
+; ZVFHMIN64-NEXT: vmv.x.s a4, v26
+; ZVFHMIN64-NEXT: fmv.h.x fa2, t3
+; ZVFHMIN64-NEXT: vmv.x.s a1, v28
+; ZVFHMIN64-NEXT: fmv.h.x fa1, t4
+; ZVFHMIN64-NEXT: vmv.x.s a2, v12
+; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFHMIN64-NEXT: vslidedown.vi v22, v8, 6
+; ZVFHMIN64-NEXT: vslidedown.vi v23, v8, 7
+; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; ZVFHMIN64-NEXT: vslidedown.vi v10, v8, 8
+; ZVFHMIN64-NEXT: vslidedown.vi v12, v8, 9
+; ZVFHMIN64-NEXT: vslidedown.vi v14, v8, 10
+; ZVFHMIN64-NEXT: vslidedown.vi v18, v8, 13
+; ZVFHMIN64-NEXT: vslidedown.vi v20, v8, 14
+; ZVFHMIN64-NEXT: vslidedown.vi v16, v8, 15
+; ZVFHMIN64-NEXT: fmv.h.x fa0, t1
+; ZVFHMIN64-NEXT: fmv.h.x ft0, t2
+; ZVFHMIN64-NEXT: fmax.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a6
+; ZVFHMIN64-NEXT: fmax.h fa3, fa3, fa2
+; ZVFHMIN64-NEXT: fmv.h.x fa2, a5
+; ZVFHMIN64-NEXT: fmax.h fa1, fa1, fa0
+; ZVFHMIN64-NEXT: fmv.h.x fa0, a7
+; ZVFHMIN64-NEXT: fmax.h fa4, fa4, fa2
+; ZVFHMIN64-NEXT: fmv.h.x fa2, t0
+; ZVFHMIN64-NEXT: fmax.h fa2, fa0, fa2
+; ZVFHMIN64-NEXT: fmv.h.x fa0, a3
+; ZVFHMIN64-NEXT: fmax.h fa5, fa5, fa3
+; ZVFHMIN64-NEXT: fmv.h.x fa3, a4
+; ZVFHMIN64-NEXT: vmv.x.s a3, v22
+; ZVFHMIN64-NEXT: vmv.x.s a4, v23
+; ZVFHMIN64-NEXT: vmv.x.s a5, v18
+; ZVFHMIN64-NEXT: vmv.x.s a6, v20
+; ZVFHMIN64-NEXT: fmax.h fa1, fa1, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a3
+; ZVFHMIN64-NEXT: fmax.h fa4, fa4, fa0
+; ZVFHMIN64-NEXT: fmv.h.x fa0, a4
+; ZVFHMIN64-NEXT: fmax.h fa3, fa2, fa3
+; ZVFHMIN64-NEXT: fmv.h.x fa2, a5
+; ZVFHMIN64-NEXT: fmax.h fa0, ft0, fa0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a6
+; ZVFHMIN64-NEXT: fmax.h fa2, fa2, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a0
+; ZVFHMIN64-NEXT: fmax.h fa5, fa5, fa1
+; ZVFHMIN64-NEXT: fmv.h.x fa1, a1
+; ZVFHMIN64-NEXT: fmax.h fa4, fa4, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a2
+; ZVFHMIN64-NEXT: lh a1, 32(sp)
+; ZVFHMIN64-NEXT: lh a7, 34(sp)
+; ZVFHMIN64-NEXT: lh a5, 36(sp)
+; ZVFHMIN64-NEXT: lh a2, 38(sp)
+; ZVFHMIN64-NEXT: lh t0, 56(sp)
+; ZVFHMIN64-NEXT: lh t1, 58(sp)
+; ZVFHMIN64-NEXT: lh a6, 60(sp)
+; ZVFHMIN64-NEXT: lh a0, 62(sp)
+; ZVFHMIN64-NEXT: vmv.x.s a3, v10
+; ZVFHMIN64-NEXT: vmv.x.s a4, v12
+; ZVFHMIN64-NEXT: vmv.x.s t2, v14
+; ZVFHMIN64-NEXT: fmax.h fa3, fa3, fa1
+; ZVFHMIN64-NEXT: fmv.h.x fa1, a3
+; ZVFHMIN64-NEXT: vmv.x.s a3, v16
+; ZVFHMIN64-NEXT: fmax.h fa1, fa0, fa1
+; ZVFHMIN64-NEXT: fmv.h.x fa0, a3
+; ZVFHMIN64-NEXT: fmax.h fa2, fa2, fa0
+; ZVFHMIN64-NEXT: fmv.h.x fa0, a4
+; ZVFHMIN64-NEXT: fmax.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa4, t2
+; ZVFHMIN64-NEXT: fmax.h fa3, fa3, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a1
+; ZVFHMIN64-NEXT: lh a1, 96(sp)
+; ZVFHMIN64-NEXT: lh t2, 98(sp)
+; ZVFHMIN64-NEXT: lh a4, 100(sp)
+; ZVFHMIN64-NEXT: lh a3, 102(sp)
+; ZVFHMIN64-NEXT: fmax.h fa1, fa1, fa0
+; ZVFHMIN64-NEXT: fmv.h.x fa0, a7
+; ZVFHMIN64-NEXT: fmax.h fa5, fa5, fa3
+; ZVFHMIN64-NEXT: fmv.h.x fa3, t0
+; ZVFHMIN64-NEXT: fmax.h fa0, ft0, fa0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, t1
+; ZVFHMIN64-NEXT: fmax.h fa3, fa3, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a1
+; ZVFHMIN64-NEXT: lh a1, 104(sp)
+; ZVFHMIN64-NEXT: lh a7, 106(sp)
+; ZVFHMIN64-NEXT: lh t0, 108(sp)
+; ZVFHMIN64-NEXT: lh t1, 110(sp)
+; ZVFHMIN64-NEXT: fmax.h fa4, fa1, fa4
+; ZVFHMIN64-NEXT: fmv.h.x fa1, a7
+; ZVFHMIN64-NEXT: fmax.h fa2, fa2, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, t0
+; ZVFHMIN64-NEXT: vslidedown.vi v10, v8, 11
+; ZVFHMIN64-NEXT: vslidedown.vi v12, v8, 12
+; ZVFHMIN64-NEXT: fmax.h fa1, fa1, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a5
+; ZVFHMIN64-NEXT: vmv.x.s a5, v10
+; ZVFHMIN64-NEXT: fmax.h fa0, fa0, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a6
+; ZVFHMIN64-NEXT: vmv.x.s a6, v12
+; ZVFHMIN64-NEXT: fmax.h fa3, fa3, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a5
+; ZVFHMIN64-NEXT: fmax.h fa4, fa4, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, t2
+; ZVFHMIN64-NEXT: fmax.h fa2, fa2, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, t1
+; ZVFHMIN64-NEXT: fmax.h fa1, fa1, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a2
+; ZVFHMIN64-NEXT: lh a5, 112(sp)
+; ZVFHMIN64-NEXT: lh a7, 114(sp)
+; ZVFHMIN64-NEXT: lh t0, 116(sp)
+; ZVFHMIN64-NEXT: lh a2, 118(sp)
+; ZVFHMIN64-NEXT: fmax.h fa0, fa0, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a0
+; ZVFHMIN64-NEXT: fmax.h fa3, fa3, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a6
+; ZVFHMIN64-NEXT: fmax.h fa4, fa4, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a4
+; ZVFHMIN64-NEXT: fmax.h fa2, fa2, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a5
+; ZVFHMIN64-NEXT: lh a0, 40(sp)
+; ZVFHMIN64-NEXT: lh a4, 42(sp)
+; ZVFHMIN64-NEXT: lh a5, 44(sp)
+; ZVFHMIN64-NEXT: lh a6, 46(sp)
+; ZVFHMIN64-NEXT: fmax.h fa1, fa1, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a0
+; ZVFHMIN64-NEXT: vmv.x.s a0, v8
+; ZVFHMIN64-NEXT: fmax.h fa0, fa0, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a0
+; ZVFHMIN64-NEXT: fmax.h fa3, fa3, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a3
+; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; ZVFHMIN64-NEXT: vslidedown.vi v9, v8, 1
+; ZVFHMIN64-NEXT: vslidedown.vi v10, v8, 2
+; ZVFHMIN64-NEXT: vslidedown.vi v11, v8, 3
+; ZVFHMIN64-NEXT: vslidedown.vi v12, v8, 4
+; ZVFHMIN64-NEXT: fmax.h fa2, fa2, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a7
+; ZVFHMIN64-NEXT: vmv.x.s a0, v9
+; ZVFHMIN64-NEXT: fmax.h fa1, fa1, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a4
+; ZVFHMIN64-NEXT: vmv.x.s a3, v10
+; ZVFHMIN64-NEXT: fmax.h fa0, fa0, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a0
+; ZVFHMIN64-NEXT: vmv.x.s a0, v11
+; ZVFHMIN64-NEXT: fmax.h fa3, fa3, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a1
+; ZVFHMIN64-NEXT: fmax.h fa2, fa2, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, t0
+; ZVFHMIN64-NEXT: fmax.h fa1, fa1, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a5
+; ZVFHMIN64-NEXT: fmax.h fa0, fa0, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a3
+; ZVFHMIN64-NEXT: lh a1, 120(sp)
+; ZVFHMIN64-NEXT: lh a3, 122(sp)
+; ZVFHMIN64-NEXT: lh a4, 124(sp)
+; ZVFHMIN64-NEXT: lh a5, 126(sp)
+; ZVFHMIN64-NEXT: fmax.h fa3, fa3, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a2
+; ZVFHMIN64-NEXT: fmax.h fa1, fa1, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a6
+; ZVFHMIN64-NEXT: fmax.h fa0, fa0, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a0
+; ZVFHMIN64-NEXT: fmax.h fa3, fa3, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a1
+; ZVFHMIN64-NEXT: lh a0, 48(sp)
+; ZVFHMIN64-NEXT: lh a1, 50(sp)
+; ZVFHMIN64-NEXT: lh a2, 52(sp)
+; ZVFHMIN64-NEXT: lh a6, 54(sp)
+; ZVFHMIN64-NEXT: fmax.h fa1, fa1, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a0
+; ZVFHMIN64-NEXT: vmv.x.s a0, v12
+; ZVFHMIN64-NEXT: fmax.h fa0, fa0, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a0
+; ZVFHMIN64-NEXT: fmax.h fa3, fa3, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a3
+; ZVFHMIN64-NEXT: vslidedown.vi v8, v8, 5
+; ZVFHMIN64-NEXT: fmax.h fa1, fa1, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a1
+; ZVFHMIN64-NEXT: vmv.x.s a0, v8
+; ZVFHMIN64-NEXT: fmax.h fa0, fa0, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a0
+; ZVFHMIN64-NEXT: fmax.h fa3, fa3, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a4
+; ZVFHMIN64-NEXT: fmax.h fa1, fa1, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a2
+; ZVFHMIN64-NEXT: fmax.h fa0, fa0, ft0
+; ZVFHMIN64-NEXT: fmv.h.x ft0, a6
+; ZVFHMIN64-NEXT: fmax.h fa0, fa0, ft0
+; ZVFHMIN64-NEXT: fmax.h fa5, fa5, fa0
+; ZVFHMIN64-NEXT: fmax.h fa5, fa5, fa3
+; ZVFHMIN64-NEXT: fmax.h fa5, fa5, fa4
+; ZVFHMIN64-NEXT: fmax.h fa5, fa5, fa2
+; ZVFHMIN64-NEXT: fmv.h.x fa4, a5
+; ZVFHMIN64-NEXT: fmax.h fa4, fa1, fa4
+; ZVFHMIN64-NEXT: fmax.h fa0, fa5, fa4
+; ZVFHMIN64-NEXT: addi sp, s0, -192
+; ZVFHMIN64-NEXT: .cfi_def_cfa sp, 192
+; ZVFHMIN64-NEXT: ld ra, 184(sp) # 8-byte Folded Reload
+; ZVFHMIN64-NEXT: ld s0, 176(sp) # 8-byte Folded Reload
+; ZVFHMIN64-NEXT: .cfi_restore ra
+; ZVFHMIN64-NEXT: .cfi_restore s0
+; ZVFHMIN64-NEXT: addi sp, sp, 192
+; ZVFHMIN64-NEXT: .cfi_def_cfa_offset 0
+; ZVFHMIN64-NEXT: ret
%v = load <128 x half>, ptr %x
%red = call half @llvm.vector.reduce.fmax.v128f16(<128 x half> %v)
ret half %red
>From 291e78abc0adc2b9dc1c05078800b71c9f21c79c Mon Sep 17 00:00:00 2001
From: Brandon Wu <brandon.wu at sifive.com>
Date: Tue, 28 Apr 2026 18:04:48 +0800
Subject: [PATCH 2/3] [llvm][RISCV] Promote VECREDUCE_FADD to f32 on zvfhmin
and zvfbfmin
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 2 +
.../RISCV/rvv/fixed-vectors-reduction-fp.ll | 490 +++---------------
2 files changed, 67 insertions(+), 425 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 29847a060bb11..04dbc634f7a6b 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1169,6 +1169,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
ISD::STRICT_FDIV,
ISD::STRICT_FSQRT,
ISD::STRICT_FMA,
+ ISD::VECREDUCE_FADD,
ISD::VECREDUCE_FMIN,
ISD::VECREDUCE_FMAX,
ISD::VECREDUCE_FMINIMUM,
@@ -1187,6 +1188,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
ISD::FNEARBYINT,
ISD::STRICT_FDIV,
ISD::STRICT_FSQRT,
+ ISD::VECREDUCE_FADD,
ISD::VECREDUCE_FMIN,
ISD::VECREDUCE_FMAX,
ISD::VECREDUCE_FMINIMUM,
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
index 443aec860b83f..736eb15d6fd9c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
@@ -55,14 +55,16 @@ define half @vreduce_fadd_v2f16(ptr %x, half %s) {
;
; ZVFHMIN-LABEL: vreduce_fadd_v2f16:
; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vle16.v v8, (a0)
-; ZVFHMIN-NEXT: vmv.x.s a0, v8
-; ZVFHMIN-NEXT: vslidedown.vi v8, v8, 1
-; ZVFHMIN-NEXT: fmv.h.x fa5, a0
-; ZVFHMIN-NEXT: vmv.x.s a0, v8
-; ZVFHMIN-NEXT: fmv.h.x fa4, a0
-; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN-NEXT: lui a0, 524288
+; ZVFHMIN-NEXT: vmv.s.x v9, a0
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfredusum.vs v8, v10, v9
+; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
+; ZVFHMIN-NEXT: fcvt.h.s fa5, fa5
; ZVFHMIN-NEXT: fadd.h fa0, fa0, fa5
; ZVFHMIN-NEXT: ret
%v = load <2 x half>, ptr %x
@@ -109,22 +111,16 @@ define half @vreduce_fadd_v4f16(ptr %x, half %s) {
;
; ZVFHMIN-LABEL: vreduce_fadd_v4f16:
; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVFHMIN-NEXT: vle16.v v8, (a0)
-; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 3
-; ZVFHMIN-NEXT: vmv.x.s a0, v8
-; ZVFHMIN-NEXT: fmv.h.x fa5, a0
-; ZVFHMIN-NEXT: vmv.x.s a0, v9
-; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 2
-; ZVFHMIN-NEXT: vslidedown.vi v8, v8, 1
-; ZVFHMIN-NEXT: fmv.h.x fa4, a0
-; ZVFHMIN-NEXT: vmv.x.s a0, v9
-; ZVFHMIN-NEXT: fmv.h.x fa3, a0
-; ZVFHMIN-NEXT: vmv.x.s a0, v8
-; ZVFHMIN-NEXT: fmv.h.x fa2, a0
-; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa2
-; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa3
-; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN-NEXT: lui a0, 524288
+; ZVFHMIN-NEXT: vmv.s.x v9, a0
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vfredusum.vs v8, v10, v9
+; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
+; ZVFHMIN-NEXT: fcvt.h.s fa5, fa5
; ZVFHMIN-NEXT: fadd.h fa0, fa0, fa5
; ZVFHMIN-NEXT: ret
%v = load <4 x half>, ptr %x
@@ -180,33 +176,18 @@ define half @vreduce_fadd_v7f16(ptr %x, half %s) {
; ZVFHMIN-LABEL: vreduce_fadd_v7f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetivli zero, 7, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vle16.v v8, (a0)
-; ZVFHMIN-NEXT: vmv.x.s a0, v8
-; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 1
-; ZVFHMIN-NEXT: fmv.h.x fa5, a0
-; ZVFHMIN-NEXT: vmv.x.s a0, v9
-; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 2
-; ZVFHMIN-NEXT: fmv.h.x fa4, a0
-; ZVFHMIN-NEXT: vmv.x.s a0, v9
-; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 3
-; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN-NEXT: fmv.h.x fa4, a0
-; ZVFHMIN-NEXT: vmv.x.s a0, v9
-; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 4
-; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN-NEXT: fmv.h.x fa4, a0
-; ZVFHMIN-NEXT: vmv.x.s a0, v9
-; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 5
-; ZVFHMIN-NEXT: vslidedown.vi v8, v8, 6
-; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN-NEXT: fmv.h.x fa4, a0
-; ZVFHMIN-NEXT: vmv.x.s a0, v9
-; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN-NEXT: fmv.h.x fa4, a0
-; ZVFHMIN-NEXT: vmv.x.s a0, v8
-; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN-NEXT: fmv.h.x fa4, a0
-; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN-NEXT: vle16.v v10, (a0)
+; ZVFHMIN-NEXT: lui a0, 1048568
+; ZVFHMIN-NEXT: vmv.s.x v8, a0
+; ZVFHMIN-NEXT: lui a0, 524288
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vslideup.vi v10, v8, 7
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmv.s.x v10, a0
+; ZVFHMIN-NEXT: vfredusum.vs v8, v8, v10
+; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
+; ZVFHMIN-NEXT: fcvt.h.s fa5, fa5
; ZVFHMIN-NEXT: fadd.h fa0, fa0, fa5
; ZVFHMIN-NEXT: ret
%v = load <7 x half>, ptr %x
@@ -226,38 +207,16 @@ define half @vreduce_fadd_v8f16(ptr %x, half %s) {
;
; ZVFHMIN-LABEL: vreduce_fadd_v8f16:
; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vle16.v v8, (a0)
-; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 7
-; ZVFHMIN-NEXT: vmv.x.s a0, v8
-; ZVFHMIN-NEXT: fmv.h.x fa5, a0
-; ZVFHMIN-NEXT: vmv.x.s a0, v9
-; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 6
-; ZVFHMIN-NEXT: fmv.h.x fa4, a0
-; ZVFHMIN-NEXT: vmv.x.s a0, v9
-; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 5
-; ZVFHMIN-NEXT: fmv.h.x fa3, a0
-; ZVFHMIN-NEXT: vmv.x.s a0, v9
-; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 4
-; ZVFHMIN-NEXT: fmv.h.x fa2, a0
-; ZVFHMIN-NEXT: vmv.x.s a0, v9
-; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 3
-; ZVFHMIN-NEXT: fmv.h.x fa1, a0
-; ZVFHMIN-NEXT: vmv.x.s a0, v9
-; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 2
-; ZVFHMIN-NEXT: vslidedown.vi v8, v8, 1
-; ZVFHMIN-NEXT: fmv.h.x ft0, a0
-; ZVFHMIN-NEXT: vmv.x.s a0, v9
-; ZVFHMIN-NEXT: fmv.h.x ft1, a0
-; ZVFHMIN-NEXT: vmv.x.s a0, v8
-; ZVFHMIN-NEXT: fmv.h.x ft2, a0
-; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft2
-; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft1
-; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft0
-; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa1
-; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa2
-; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa3
-; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vle16.v v10, (a0)
+; ZVFHMIN-NEXT: lui a0, 524288
+; ZVFHMIN-NEXT: vmv.s.x v11, a0
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vfredusum.vs v8, v8, v11
+; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
+; ZVFHMIN-NEXT: fcvt.h.s fa5, fa5
; ZVFHMIN-NEXT: fadd.h fa0, fa0, fa5
; ZVFHMIN-NEXT: ret
%v = load <8 x half>, ptr %x
@@ -328,71 +287,16 @@ define half @vreduce_fadd_v16f16(ptr %x, half %s) {
;
; ZVFHMIN-LABEL: vreduce_fadd_v16f16:
; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vle16.v v8, (a0)
-; ZVFHMIN-NEXT: vslidedown.vi v10, v8, 15
-; ZVFHMIN-NEXT: vslidedown.vi v12, v8, 14
-; ZVFHMIN-NEXT: vslidedown.vi v14, v8, 13
-; ZVFHMIN-NEXT: vmv.x.s a0, v10
-; ZVFHMIN-NEXT: vslidedown.vi v10, v8, 12
-; ZVFHMIN-NEXT: vmv.x.s a1, v12
-; ZVFHMIN-NEXT: vslidedown.vi v12, v8, 11
-; ZVFHMIN-NEXT: vmv.x.s a2, v14
-; ZVFHMIN-NEXT: vslidedown.vi v14, v8, 10
-; ZVFHMIN-NEXT: vmv.x.s a3, v10
-; ZVFHMIN-NEXT: vslidedown.vi v10, v8, 9
-; ZVFHMIN-NEXT: vmv.x.s a4, v12
-; ZVFHMIN-NEXT: vslidedown.vi v12, v8, 8
-; ZVFHMIN-NEXT: vmv.x.s a5, v14
-; ZVFHMIN-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vi v9, v8, 7
-; ZVFHMIN-NEXT: vslidedown.vi v11, v8, 6
-; ZVFHMIN-NEXT: vmv.x.s a6, v10
-; ZVFHMIN-NEXT: vslidedown.vi v10, v8, 5
-; ZVFHMIN-NEXT: vslidedown.vi v13, v8, 4
-; ZVFHMIN-NEXT: vmv.x.s a7, v12
-; ZVFHMIN-NEXT: vslidedown.vi v12, v8, 3
-; ZVFHMIN-NEXT: vslidedown.vi v14, v8, 2
-; ZVFHMIN-NEXT: vmv.x.s t0, v8
-; ZVFHMIN-NEXT: vslidedown.vi v8, v8, 1
-; ZVFHMIN-NEXT: vmv.x.s t1, v9
-; ZVFHMIN-NEXT: vmv.x.s t2, v11
-; ZVFHMIN-NEXT: vmv.x.s t3, v10
-; ZVFHMIN-NEXT: fmv.h.x fa5, t0
-; ZVFHMIN-NEXT: fmv.h.x fa4, a0
-; ZVFHMIN-NEXT: fmv.h.x fa3, a1
-; ZVFHMIN-NEXT: fmv.h.x fa2, a2
-; ZVFHMIN-NEXT: fmv.h.x fa1, a3
-; ZVFHMIN-NEXT: fmv.h.x ft0, a4
-; ZVFHMIN-NEXT: fmv.h.x ft1, a5
-; ZVFHMIN-NEXT: fmv.h.x ft2, a6
-; ZVFHMIN-NEXT: fmv.h.x ft3, a7
-; ZVFHMIN-NEXT: fmv.h.x ft4, t1
-; ZVFHMIN-NEXT: fmv.h.x ft5, t2
-; ZVFHMIN-NEXT: fmv.h.x ft6, t3
-; ZVFHMIN-NEXT: vmv.x.s a0, v13
-; ZVFHMIN-NEXT: fmv.h.x ft7, a0
-; ZVFHMIN-NEXT: vmv.x.s a0, v12
-; ZVFHMIN-NEXT: fmv.h.x fa6, a0
-; ZVFHMIN-NEXT: vmv.x.s a0, v14
-; ZVFHMIN-NEXT: fmv.h.x fa7, a0
-; ZVFHMIN-NEXT: vmv.x.s a0, v8
-; ZVFHMIN-NEXT: fmv.h.x ft8, a0
-; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft8
-; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa7
-; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa6
-; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft7
-; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft6
-; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft5
-; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft4
-; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft3
-; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft2
-; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft1
-; ZVFHMIN-NEXT: fadd.h fa5, fa5, ft0
-; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa1
-; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa2
-; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa3
-; ZVFHMIN-NEXT: fadd.h fa5, fa5, fa4
+; ZVFHMIN-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vle16.v v12, (a0)
+; ZVFHMIN-NEXT: lui a0, 524288
+; ZVFHMIN-NEXT: vmv.s.x v14, a0
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v12
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfredusum.vs v8, v8, v14
+; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
+; ZVFHMIN-NEXT: fcvt.h.s fa5, fa5
; ZVFHMIN-NEXT: fadd.h fa0, fa0, fa5
; ZVFHMIN-NEXT: ret
%v = load <16 x half>, ptr %x
@@ -495,285 +399,21 @@ define half @vreduce_fadd_v32f16(ptr %x, half %s) {
; ZVFH-NEXT: vfmv.f.s fa0, v8
; ZVFH-NEXT: ret
;
-; ZVFHMIN32-LABEL: vreduce_fadd_v32f16:
-; ZVFHMIN32: # %bb.0:
-; ZVFHMIN32-NEXT: addi sp, sp, -128
-; ZVFHMIN32-NEXT: .cfi_def_cfa_offset 128
-; ZVFHMIN32-NEXT: sw ra, 124(sp) # 4-byte Folded Spill
-; ZVFHMIN32-NEXT: sw s0, 120(sp) # 4-byte Folded Spill
-; ZVFHMIN32-NEXT: .cfi_offset ra, -4
-; ZVFHMIN32-NEXT: .cfi_offset s0, -8
-; ZVFHMIN32-NEXT: addi s0, sp, 128
-; ZVFHMIN32-NEXT: .cfi_def_cfa s0, 0
-; ZVFHMIN32-NEXT: andi sp, sp, -64
-; ZVFHMIN32-NEXT: li a1, 32
-; ZVFHMIN32-NEXT: vsetvli zero, a1, e16, m4, ta, ma
-; ZVFHMIN32-NEXT: vle16.v v8, (a0)
-; ZVFHMIN32-NEXT: mv a0, sp
-; ZVFHMIN32-NEXT: vse16.v v8, (a0)
-; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m2, ta, ma
-; ZVFHMIN32-NEXT: vslidedown.vi v16, v8, 15
-; ZVFHMIN32-NEXT: vslidedown.vi v18, v8, 14
-; ZVFHMIN32-NEXT: vslidedown.vi v20, v8, 13
-; ZVFHMIN32-NEXT: vslidedown.vi v10, v8, 12
-; ZVFHMIN32-NEXT: vslidedown.vi v12, v8, 11
-; ZVFHMIN32-NEXT: vslidedown.vi v14, v8, 10
-; ZVFHMIN32-NEXT: vslidedown.vi v22, v8, 9
-; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; ZVFHMIN32-NEXT: vslidedown.vi v11, v8, 7
-; ZVFHMIN32-NEXT: vslidedown.vi v13, v8, 6
-; ZVFHMIN32-NEXT: vslidedown.vi v15, v8, 5
-; ZVFHMIN32-NEXT: vslidedown.vi v17, v8, 4
-; ZVFHMIN32-NEXT: vslidedown.vi v19, v8, 3
-; ZVFHMIN32-NEXT: vslidedown.vi v21, v8, 2
-; ZVFHMIN32-NEXT: vmv.x.s a5, v8
-; ZVFHMIN32-NEXT: vslidedown.vi v23, v8, 1
-; ZVFHMIN32-NEXT: vsetivli zero, 1, e16, m2, ta, ma
-; ZVFHMIN32-NEXT: vslidedown.vi v8, v8, 8
-; ZVFHMIN32-NEXT: vmv.x.s a0, v16
-; ZVFHMIN32-NEXT: vmv.x.s a1, v18
-; ZVFHMIN32-NEXT: vmv.x.s a2, v20
-; ZVFHMIN32-NEXT: vmv.x.s a3, v22
-; ZVFHMIN32-NEXT: vmv.x.s a4, v8
-; ZVFHMIN32-NEXT: vmv.x.s a6, v11
-; ZVFHMIN32-NEXT: vmv.x.s a7, v13
-; ZVFHMIN32-NEXT: vmv.x.s t0, v15
-; ZVFHMIN32-NEXT: vmv.x.s t1, v17
-; ZVFHMIN32-NEXT: vmv.x.s t2, v19
-; ZVFHMIN32-NEXT: vmv.x.s t3, v21
-; ZVFHMIN32-NEXT: vmv.x.s t4, v23
-; ZVFHMIN32-NEXT: fmv.h.x fa5, a5
-; ZVFHMIN32-NEXT: fmv.h.x fa4, t4
-; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN32-NEXT: fmv.h.x fa4, t3
-; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN32-NEXT: fmv.h.x fa4, t2
-; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN32-NEXT: fmv.h.x fa4, t1
-; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN32-NEXT: fmv.h.x fa4, t0
-; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN32-NEXT: fmv.h.x fa4, a7
-; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN32-NEXT: fmv.h.x fa4, a6
-; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN32-NEXT: fmv.h.x fa4, a4
-; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
-; ZVFHMIN32-NEXT: vmv.x.s a3, v14
-; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
-; ZVFHMIN32-NEXT: vmv.x.s a3, v12
-; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
-; ZVFHMIN32-NEXT: vmv.x.s a3, v10
-; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
-; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
-; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
-; ZVFHMIN32-NEXT: lh a0, 32(sp)
-; ZVFHMIN32-NEXT: lh a1, 34(sp)
-; ZVFHMIN32-NEXT: lh a2, 36(sp)
-; ZVFHMIN32-NEXT: lh a3, 38(sp)
-; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
-; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
-; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
-; ZVFHMIN32-NEXT: lh a0, 40(sp)
-; ZVFHMIN32-NEXT: lh a1, 42(sp)
-; ZVFHMIN32-NEXT: lh a2, 44(sp)
-; ZVFHMIN32-NEXT: lh a3, 46(sp)
-; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
-; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
-; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
-; ZVFHMIN32-NEXT: lh a0, 48(sp)
-; ZVFHMIN32-NEXT: lh a1, 50(sp)
-; ZVFHMIN32-NEXT: lh a2, 52(sp)
-; ZVFHMIN32-NEXT: lh a3, 54(sp)
-; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
-; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
-; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
-; ZVFHMIN32-NEXT: lh a0, 56(sp)
-; ZVFHMIN32-NEXT: lh a1, 58(sp)
-; ZVFHMIN32-NEXT: lh a2, 60(sp)
-; ZVFHMIN32-NEXT: lh a3, 62(sp)
-; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN32-NEXT: fmv.h.x fa4, a0
-; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN32-NEXT: fmv.h.x fa4, a1
-; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN32-NEXT: fmv.h.x fa4, a2
-; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN32-NEXT: fmv.h.x fa4, a3
-; ZVFHMIN32-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN32-NEXT: fadd.h fa0, fa0, fa5
-; ZVFHMIN32-NEXT: addi sp, s0, -128
-; ZVFHMIN32-NEXT: .cfi_def_cfa sp, 128
-; ZVFHMIN32-NEXT: lw ra, 124(sp) # 4-byte Folded Reload
-; ZVFHMIN32-NEXT: lw s0, 120(sp) # 4-byte Folded Reload
-; ZVFHMIN32-NEXT: .cfi_restore ra
-; ZVFHMIN32-NEXT: .cfi_restore s0
-; ZVFHMIN32-NEXT: addi sp, sp, 128
-; ZVFHMIN32-NEXT: .cfi_def_cfa_offset 0
-; ZVFHMIN32-NEXT: ret
-;
-; ZVFHMIN64-LABEL: vreduce_fadd_v32f16:
-; ZVFHMIN64: # %bb.0:
-; ZVFHMIN64-NEXT: addi sp, sp, -128
-; ZVFHMIN64-NEXT: .cfi_def_cfa_offset 128
-; ZVFHMIN64-NEXT: sd ra, 120(sp) # 8-byte Folded Spill
-; ZVFHMIN64-NEXT: sd s0, 112(sp) # 8-byte Folded Spill
-; ZVFHMIN64-NEXT: .cfi_offset ra, -8
-; ZVFHMIN64-NEXT: .cfi_offset s0, -16
-; ZVFHMIN64-NEXT: addi s0, sp, 128
-; ZVFHMIN64-NEXT: .cfi_def_cfa s0, 0
-; ZVFHMIN64-NEXT: andi sp, sp, -64
-; ZVFHMIN64-NEXT: li a1, 32
-; ZVFHMIN64-NEXT: vsetvli zero, a1, e16, m4, ta, ma
-; ZVFHMIN64-NEXT: vle16.v v8, (a0)
-; ZVFHMIN64-NEXT: mv a0, sp
-; ZVFHMIN64-NEXT: vse16.v v8, (a0)
-; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m2, ta, ma
-; ZVFHMIN64-NEXT: vslidedown.vi v16, v8, 15
-; ZVFHMIN64-NEXT: vslidedown.vi v18, v8, 14
-; ZVFHMIN64-NEXT: vslidedown.vi v20, v8, 13
-; ZVFHMIN64-NEXT: vslidedown.vi v10, v8, 12
-; ZVFHMIN64-NEXT: vslidedown.vi v12, v8, 11
-; ZVFHMIN64-NEXT: vslidedown.vi v14, v8, 10
-; ZVFHMIN64-NEXT: vslidedown.vi v22, v8, 9
-; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; ZVFHMIN64-NEXT: vslidedown.vi v11, v8, 7
-; ZVFHMIN64-NEXT: vslidedown.vi v13, v8, 6
-; ZVFHMIN64-NEXT: vslidedown.vi v15, v8, 5
-; ZVFHMIN64-NEXT: vslidedown.vi v17, v8, 4
-; ZVFHMIN64-NEXT: vslidedown.vi v19, v8, 3
-; ZVFHMIN64-NEXT: vslidedown.vi v21, v8, 2
-; ZVFHMIN64-NEXT: vmv.x.s a5, v8
-; ZVFHMIN64-NEXT: vslidedown.vi v23, v8, 1
-; ZVFHMIN64-NEXT: vsetivli zero, 1, e16, m2, ta, ma
-; ZVFHMIN64-NEXT: vslidedown.vi v8, v8, 8
-; ZVFHMIN64-NEXT: vmv.x.s a0, v16
-; ZVFHMIN64-NEXT: vmv.x.s a1, v18
-; ZVFHMIN64-NEXT: vmv.x.s a2, v20
-; ZVFHMIN64-NEXT: vmv.x.s a3, v22
-; ZVFHMIN64-NEXT: vmv.x.s a4, v8
-; ZVFHMIN64-NEXT: vmv.x.s a6, v11
-; ZVFHMIN64-NEXT: vmv.x.s a7, v13
-; ZVFHMIN64-NEXT: vmv.x.s t0, v15
-; ZVFHMIN64-NEXT: vmv.x.s t1, v17
-; ZVFHMIN64-NEXT: vmv.x.s t2, v19
-; ZVFHMIN64-NEXT: vmv.x.s t3, v21
-; ZVFHMIN64-NEXT: vmv.x.s t4, v23
-; ZVFHMIN64-NEXT: fmv.h.x fa5, a5
-; ZVFHMIN64-NEXT: fmv.h.x fa4, t4
-; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN64-NEXT: fmv.h.x fa4, t3
-; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN64-NEXT: fmv.h.x fa4, t2
-; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN64-NEXT: fmv.h.x fa4, t1
-; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN64-NEXT: fmv.h.x fa4, t0
-; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN64-NEXT: fmv.h.x fa4, a7
-; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN64-NEXT: fmv.h.x fa4, a6
-; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN64-NEXT: fmv.h.x fa4, a4
-; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
-; ZVFHMIN64-NEXT: vmv.x.s a3, v14
-; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
-; ZVFHMIN64-NEXT: vmv.x.s a3, v12
-; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
-; ZVFHMIN64-NEXT: vmv.x.s a3, v10
-; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
-; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
-; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
-; ZVFHMIN64-NEXT: lh a0, 32(sp)
-; ZVFHMIN64-NEXT: lh a1, 34(sp)
-; ZVFHMIN64-NEXT: lh a2, 36(sp)
-; ZVFHMIN64-NEXT: lh a3, 38(sp)
-; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
-; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
-; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
-; ZVFHMIN64-NEXT: lh a0, 40(sp)
-; ZVFHMIN64-NEXT: lh a1, 42(sp)
-; ZVFHMIN64-NEXT: lh a2, 44(sp)
-; ZVFHMIN64-NEXT: lh a3, 46(sp)
-; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
-; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
-; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
-; ZVFHMIN64-NEXT: lh a0, 48(sp)
-; ZVFHMIN64-NEXT: lh a1, 50(sp)
-; ZVFHMIN64-NEXT: lh a2, 52(sp)
-; ZVFHMIN64-NEXT: lh a3, 54(sp)
-; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
-; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
-; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
-; ZVFHMIN64-NEXT: lh a0, 56(sp)
-; ZVFHMIN64-NEXT: lh a1, 58(sp)
-; ZVFHMIN64-NEXT: lh a2, 60(sp)
-; ZVFHMIN64-NEXT: lh a3, 62(sp)
-; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN64-NEXT: fmv.h.x fa4, a0
-; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN64-NEXT: fmv.h.x fa4, a1
-; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN64-NEXT: fmv.h.x fa4, a2
-; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN64-NEXT: fmv.h.x fa4, a3
-; ZVFHMIN64-NEXT: fadd.h fa5, fa5, fa4
-; ZVFHMIN64-NEXT: fadd.h fa0, fa0, fa5
-; ZVFHMIN64-NEXT: addi sp, s0, -128
-; ZVFHMIN64-NEXT: .cfi_def_cfa sp, 128
-; ZVFHMIN64-NEXT: ld ra, 120(sp) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT: ld s0, 112(sp) # 8-byte Folded Reload
-; ZVFHMIN64-NEXT: .cfi_restore ra
-; ZVFHMIN64-NEXT: .cfi_restore s0
-; ZVFHMIN64-NEXT: addi sp, sp, 128
-; ZVFHMIN64-NEXT: .cfi_def_cfa_offset 0
-; ZVFHMIN64-NEXT: ret
+; ZVFHMIN-LABEL: vreduce_fadd_v32f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: li a1, 32
+; ZVFHMIN-NEXT: vsetvli zero, a1, e32, m8, ta, ma
+; ZVFHMIN-NEXT: vle16.v v16, (a0)
+; ZVFHMIN-NEXT: lui a0, 524288
+; ZVFHMIN-NEXT: vmv.s.x v20, a0
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; ZVFHMIN-NEXT: vfredusum.vs v8, v8, v20
+; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
+; ZVFHMIN-NEXT: fcvt.h.s fa5, fa5
+; ZVFHMIN-NEXT: fadd.h fa0, fa0, fa5
+; ZVFHMIN-NEXT: ret
%v = load <32 x half>, ptr %x
%red = call reassoc half @llvm.vector.reduce.fadd.v32f16(half %s, <32 x half> %v)
ret half %red
>From cb34ab7ce4866cf5bb7411fda24a51910352d53b Mon Sep 17 00:00:00 2001
From: Brandon Wu <brandon.wu at sifive.com>
Date: Tue, 28 Apr 2026 18:45:44 +0800
Subject: [PATCH 3/3] fixup! add scalable test
---
.../RISCV/rvv/vreductions-fp-sdnode-bf16.ll | 60 +++++++++++++
.../RISCV/rvv/vreductions-fp-sdnode-f16.ll | 84 +++++++++++++++++++
2 files changed, 144 insertions(+)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode-bf16.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode-bf16.ll
index 1c42cd29deca9..7fff34153adcd 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode-bf16.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode-bf16.ll
@@ -134,3 +134,63 @@ define bfloat @vreduce_fmaximum_nnan_nxv4bf16(<vscale x 4 x bfloat> %val) {
ret bfloat %s
}
+
+define bfloat @vreduce_fadd_nxv1bf16(<vscale x 1 x bfloat> %v, bfloat %s) {
+; CHECK-LABEL: vreduce_fadd_nxv1bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
+; CHECK-NEXT: lui a0, 524288
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: vfredusum.vs v8, v9, v8
+; CHECK-NEXT: vfmv.f.s fa5, v8
+; CHECK-NEXT: fcvt.bf16.s fa5, fa5
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa5
+; CHECK-NEXT: fcvt.s.bf16 fa4, fa0
+; CHECK-NEXT: fadd.s fa5, fa4, fa5
+; CHECK-NEXT: fcvt.bf16.s fa0, fa5
+; CHECK-NEXT: ret
+ %red = call reassoc bfloat @llvm.vector.reduce.fadd.nxv1bf16(bfloat %s, <vscale x 1 x bfloat> %v)
+ ret bfloat %red
+}
+
+define bfloat @vreduce_fadd_nxv2bf16(<vscale x 2 x bfloat> %v, bfloat %s) {
+; CHECK-LABEL: vreduce_fadd_nxv2bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 524288
+; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: vfredusum.vs v8, v9, v8
+; CHECK-NEXT: vfmv.f.s fa5, v8
+; CHECK-NEXT: fcvt.bf16.s fa5, fa5
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa5
+; CHECK-NEXT: fcvt.s.bf16 fa4, fa0
+; CHECK-NEXT: fadd.s fa5, fa4, fa5
+; CHECK-NEXT: fcvt.bf16.s fa0, fa5
+; CHECK-NEXT: ret
+ %red = call reassoc bfloat @llvm.vector.reduce.fadd.nxv2bf16(bfloat %s, <vscale x 2 x bfloat> %v)
+ ret bfloat %red
+}
+
+define bfloat @vreduce_fadd_nxv4bf16(<vscale x 4 x bfloat> %v, bfloat %s) {
+; CHECK-LABEL: vreduce_fadd_nxv4bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 524288
+; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
+; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: vfredusum.vs v8, v10, v8
+; CHECK-NEXT: vfmv.f.s fa5, v8
+; CHECK-NEXT: fcvt.bf16.s fa5, fa5
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa5
+; CHECK-NEXT: fcvt.s.bf16 fa4, fa0
+; CHECK-NEXT: fadd.s fa5, fa4, fa5
+; CHECK-NEXT: fcvt.bf16.s fa0, fa5
+; CHECK-NEXT: ret
+ %red = call reassoc bfloat @llvm.vector.reduce.fadd.nxv4bf16(bfloat %s, <vscale x 4 x bfloat> %v)
+ ret bfloat %red
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode-f16.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode-f16.ll
index 93b12ad14d7e1..11066e575aa66 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode-f16.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode-f16.ll
@@ -212,3 +212,87 @@ define half @vreduce_fmaximum_nnan_nxv4f16(<vscale x 4 x half> %val) {
ret half %s
}
+
+define half @vreduce_fadd_nxv1f16(<vscale x 1 x half> %v, half %s) {
+; ZVFH-LABEL: vreduce_fadd_nxv1f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; ZVFH-NEXT: vfmv.s.f v9, fa0
+; ZVFH-NEXT: vfredusum.vs v8, v8, v9
+; ZVFH-NEXT: vfmv.f.s fa0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: vreduce_fadd_nxv1f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: lui a0, 524288
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmv.s.x v8, a0
+; ZVFHMIN-NEXT: vfredusum.vs v8, v9, v8
+; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
+; ZVFHMIN-NEXT: fcvt.h.s fa5, fa5
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa5
+; ZVFHMIN-NEXT: fcvt.s.h fa4, fa0
+; ZVFHMIN-NEXT: fadd.s fa5, fa4, fa5
+; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
+; ZVFHMIN-NEXT: ret
+ %red = call reassoc half @llvm.vector.reduce.fadd.nxv1f16(half %s, <vscale x 1 x half> %v)
+ ret half %red
+}
+
+define half @vreduce_fadd_nxv2f16(<vscale x 2 x half> %v, half %s) {
+; ZVFH-LABEL: vreduce_fadd_nxv2f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; ZVFH-NEXT: vfmv.s.f v9, fa0
+; ZVFH-NEXT: vfredusum.vs v8, v8, v9
+; ZVFH-NEXT: vfmv.f.s fa0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: vreduce_fadd_nxv2f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: lui a0, 524288
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vmv.s.x v8, a0
+; ZVFHMIN-NEXT: vfredusum.vs v8, v9, v8
+; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
+; ZVFHMIN-NEXT: fcvt.h.s fa5, fa5
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa5
+; ZVFHMIN-NEXT: fcvt.s.h fa4, fa0
+; ZVFHMIN-NEXT: fadd.s fa5, fa4, fa5
+; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
+; ZVFHMIN-NEXT: ret
+ %red = call reassoc half @llvm.vector.reduce.fadd.nxv2f16(half %s, <vscale x 2 x half> %v)
+ ret half %red
+}
+
+define half @vreduce_fadd_nxv4f16(<vscale x 4 x half> %v, half %s) {
+; ZVFH-LABEL: vreduce_fadd_nxv4f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVFH-NEXT: vfmv.s.f v9, fa0
+; ZVFH-NEXT: vfredusum.vs v8, v8, v9
+; ZVFH-NEXT: vfmv.f.s fa0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: vreduce_fadd_nxv4f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: lui a0, 524288
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmv.s.x v8, a0
+; ZVFHMIN-NEXT: vfredusum.vs v8, v10, v8
+; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
+; ZVFHMIN-NEXT: fcvt.h.s fa5, fa5
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa5
+; ZVFHMIN-NEXT: fcvt.s.h fa4, fa0
+; ZVFHMIN-NEXT: fadd.s fa5, fa4, fa5
+; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
+; ZVFHMIN-NEXT: ret
+ %red = call reassoc half @llvm.vector.reduce.fadd.nxv4f16(half %s, <vscale x 4 x half> %v)
+ ret half %red
+}
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