[llvm] [AMDGPU] Enable lane masks tracking in coexec scheduler. (PR #194578)

[Petr Kurapov via llvm-commits]

https://github.com/kurapov-peter created https://github.com/llvm/llvm-project/pull/194578

This should have been always enabled to prevent the scheduler to silently produce invalid IR.

>From f6a3c2863e0af2a2b504875cb886b62e50f391ca Mon Sep 17 00:00:00 2001
From: Petr Kurapov <petr.kurapov at amd.com>
Date: Tue, 28 Apr 2026 04:41:36 -0500
Subject: [PATCH] [AMDGPU] Enable lane masks tracking in coexec scheduler.

---
 llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp | 1 +
 1 file changed, 1 insertion(+)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
index d83f8fee2b2fe..fd73654e1452d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
@@ -424,6 +424,7 @@ void AMDGPUCoExecSchedStrategy::initPolicy(MachineBasicBlock::iterator Begin,
          "coexec scheduler only supports top-down scheduling");
   RegionPolicy.OnlyTopDown = true;
   RegionPolicy.OnlyBottomUp = false;
+  RegionPolicy.ShouldTrackLaneMasks = true;
 }
 
 void AMDGPUCoExecSchedStrategy::initialize(ScheduleDAGMI *DAG) {