[llvm] ac41786 - [AArch64][SDAG] Fix invalid index into STEP_VECTOR operand (#193236)

[via llvm-commits]

Author: Harry Ramsey
Date: 2026-04-28T09:58:11+01:00
New Revision: ac41786510b4636c3f1f24a167479a3f39337677

URL: https://github.com/llvm/llvm-project/commit/ac41786510b4636c3f1f24a167479a3f39337677
DIFF: https://github.com/llvm/llvm-project/commit/ac41786510b4636c3f1f24a167479a3f39337677.diff

LOG: [AArch64][SDAG] Fix invalid index into STEP_VECTOR operand (#193236)

This commit fixes an invalid index into STEP_VECTOR constant operand
trying to find a more optimal addressing type.
 
Related Issue:
https://github.com/llvm/llvm-project/issues/193014#event-24715078836

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    llvm/test/CodeGen/AArch64/sve-gather-scatter-addr-opts.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 8d8727593ada7..52b416fdd755b 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -26361,17 +26361,6 @@ static bool findMoreOptimalIndexType(const MaskedGatherScatterSDNode *N,
   if (Index.getOpcode() == ISD::STEP_VECTOR) {
     Stride = cast<ConstantSDNode>(Index.getOperand(0))->getSExtValue();
   }
-  // Match:
-  //   Index = step(const) << shift(const)
-  else if (Index.getOpcode() == ISD::SHL &&
-           Index.getOperand(0).getOpcode() == ISD::STEP_VECTOR) {
-    SDValue RHS = Index.getOperand(1);
-    if (auto *Shift =
-            dyn_cast_or_null<ConstantSDNode>(DAG.getSplatValue(RHS))) {
-      int64_t Step = (int64_t)Index.getOperand(0).getConstantOperandVal(1);
-      Stride = Step << Shift->getZExtValue();
-    }
-  }
 
   // Return early because no supported pattern is found.
   if (Stride == 0)

diff  --git a/llvm/test/CodeGen/AArch64/sve-gather-scatter-addr-opts.ll b/llvm/test/CodeGen/AArch64/sve-gather-scatter-addr-opts.ll
index 9f5e0eb9878c2..9f20457916988 100644
--- a/llvm/test/CodeGen/AArch64/sve-gather-scatter-addr-opts.ll
+++ b/llvm/test/CodeGen/AArch64/sve-gather-scatter-addr-opts.ll
@@ -457,6 +457,27 @@ define void @masked_scatter_nxv4i32_u32s8_offsets(ptr %base, <vscale x 4 x i8> %
   ret void
 }
 
+define <vscale x 4 x ptr> @masked_scatter_shift_left(ptr %base, <vscale x 4 x i1> %mask) #0 {
+; CHECK-LABEL: masked_scatter_shift_left:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    index z0.d, x0, #8
+; CHECK-NEXT:    mov w8, #64 // =0x40
+; CHECK-NEXT:    movi v3.2d, #0000000000000000
+; CHECK-NEXT:    index z2.s, #0, w8
+; CHECK-NEXT:    mov z1.d, z0.d
+; CHECK-NEXT:    st1b { z3.s }, p0, [x0, z2.s, sxtw]
+; CHECK-NEXT:    incd z1.d, all, mul #8
+; CHECK-NEXT:    ret
+entry:
+  %step = call <vscale x 4 x i64> @llvm.stepvector.nxv4i64()
+  %step_shifted = shl <vscale x 4 x i64> %step, splat (i64 2)
+  %step_aligned = and <vscale x 4 x i64> %step_shifted, splat (i64 4294967292)
+  %ptrs = getelementptr [16 x i8], ptr %base, <vscale x 4 x i64> %step_aligned
+  call void @llvm.masked.scatter.nxv8i8.nxv8p0(<vscale x 4 x i8> zeroinitializer, <vscale x 4 x ptr> %ptrs, <vscale x 4 x i1> %mask)
+  %result = getelementptr [2 x i8], ptr %base, <vscale x 4 x i64> %step_aligned
+  ret <vscale x 4 x ptr> %result
+}
+
 attributes #0 = { "target-features"="+sve" vscale_range(1, 16) }
 
 declare <vscale x 2 x i64> @llvm.masked.gather.nxv2i64(<vscale x 2 x ptr>, i32, <vscale x 2 x i1>, <vscale x 2 x i64>)