[llvm] 2552635 - [LoongArch][NFC] Add tests for VBITCLRI, VBITSETI, and VBITREVI (#193718)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 28 01:57:29 PDT 2026
Author: hev
Date: 2026-04-28T16:57:24+08:00
New Revision: 255263560860a50ef6c083df815e2bd1577debd8
URL: https://github.com/llvm/llvm-project/commit/255263560860a50ef6c083df815e2bd1577debd8
DIFF: https://github.com/llvm/llvm-project/commit/255263560860a50ef6c083df815e2bd1577debd8.diff
LOG: [LoongArch][NFC] Add tests for VBITCLRI, VBITSETI, and VBITREVI (#193718)
Added:
llvm/test/CodeGen/LoongArch/lasx/bitclr.ll
llvm/test/CodeGen/LoongArch/lasx/bitrev.ll
llvm/test/CodeGen/LoongArch/lasx/bitset.ll
llvm/test/CodeGen/LoongArch/lsx/bitclr.ll
llvm/test/CodeGen/LoongArch/lsx/bitrev.ll
llvm/test/CodeGen/LoongArch/lsx/bitset.ll
Modified:
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/LoongArch/lasx/bitclr.ll b/llvm/test/CodeGen/LoongArch/lasx/bitclr.ll
new file mode 100644
index 0000000000000..f4b6990a8d932
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lasx/bitclr.ll
@@ -0,0 +1,96 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
+
+define <32 x i8> @bitclri_v32i8(<32 x i8> %a) nounwind {
+; CHECK-LABEL: bitclri_v32i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvbitclri.b $xr0, $xr0, 2
+; CHECK-NEXT: ret
+entry:
+ %0 = and <32 x i8> %a, splat (i8 -5)
+ ret <32 x i8> %0
+}
+
+define <16 x i16> @bitclri_v16i16(<16 x i16> %a) nounwind {
+; CHECK-LABEL: bitclri_v16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvbitclri.h $xr0, $xr0, 2
+; CHECK-NEXT: ret
+entry:
+ %0 = and <16 x i16> %a, splat (i16 -5)
+ ret <16 x i16> %0
+}
+
+define <8 x i32> @bitclri_v8i32(<8 x i32> %a) nounwind {
+; CHECK-LABEL: bitclri_v8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvbitclri.w $xr0, $xr0, 2
+; CHECK-NEXT: ret
+entry:
+ %0 = and <8 x i32> %a, splat (i32 -5)
+ ret <8 x i32> %0
+}
+
+define <4 x i64> @bitclri_v4i64(<4 x i64> %a) nounwind {
+; CHECK-LABEL: bitclri_v4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvbitclri.d $xr0, $xr0, 2
+; CHECK-NEXT: ret
+entry:
+ %0 = and <4 x i64> %a, splat (i64 -5)
+ ret <4 x i64> %0
+}
+
+define <8 x i32> @bitclri_v32i8_v8i32(<8 x i32> %a) nounwind {
+; CHECK-LABEL: bitclri_v32i8_v8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvandi.b $xr0, $xr0, 251
+; CHECK-NEXT: ret
+entry:
+ %0 = and <8 x i32> %a, splat (i32 -67372037)
+ ret <8 x i32> %0
+}
+
+define <8 x i32> @bitclri_v16i16_v8i32(<8 x i32> %a) nounwind {
+; CHECK-LABEL: bitclri_v16i16_v8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvrepli.h $xr1, -5
+; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
+; CHECK-NEXT: ret
+entry:
+ %0 = and <8 x i32> %a, splat (i32 -262149)
+ ret <8 x i32> %0
+}
+
+define <4 x i64> @bitclri_v32i8_v4i64(<4 x i64> %a) nounwind {
+; CHECK-LABEL: bitclri_v32i8_v4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvandi.b $xr0, $xr0, 251
+; CHECK-NEXT: ret
+entry:
+ %0 = and <4 x i64> %a, splat (i64 -289360691352306693)
+ ret <4 x i64> %0
+}
+
+define <4 x i64> @bitclri_v16i16_v4i64(<4 x i64> %a) nounwind {
+; CHECK-LABEL: bitclri_v16i16_v4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvrepli.h $xr1, -5
+; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
+; CHECK-NEXT: ret
+entry:
+ %0 = and <4 x i64> %a, splat (i64 -1125917086973957)
+ ret <4 x i64> %0
+}
+
+define <4 x i64> @bitclri_v8i32_v4i64(<4 x i64> %a) nounwind {
+; CHECK-LABEL: bitclri_v8i32_v4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvrepli.w $xr1, -5
+; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1
+; CHECK-NEXT: ret
+entry:
+ %0 = and <4 x i64> %a, splat (i64 -17179869189)
+ ret <4 x i64> %0
+}
diff --git a/llvm/test/CodeGen/LoongArch/lasx/bitrev.ll b/llvm/test/CodeGen/LoongArch/lasx/bitrev.ll
new file mode 100644
index 0000000000000..3f21722b454f0
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lasx/bitrev.ll
@@ -0,0 +1,96 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
+
+define <32 x i8> @bitrevi_v32i8(<32 x i8> %a) nounwind {
+; CHECK-LABEL: bitrevi_v32i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvbitrevi.b $xr0, $xr0, 2
+; CHECK-NEXT: ret
+entry:
+ %0 = xor <32 x i8> %a, splat (i8 4)
+ ret <32 x i8> %0
+}
+
+define <16 x i16> @bitrevi_v16i16(<16 x i16> %a) nounwind {
+; CHECK-LABEL: bitrevi_v16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvbitrevi.h $xr0, $xr0, 2
+; CHECK-NEXT: ret
+entry:
+ %0 = xor <16 x i16> %a, splat (i16 4)
+ ret <16 x i16> %0
+}
+
+define <8 x i32> @bitrevi_v8i32(<8 x i32> %a) nounwind {
+; CHECK-LABEL: bitrevi_v8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvbitrevi.w $xr0, $xr0, 2
+; CHECK-NEXT: ret
+entry:
+ %0 = xor <8 x i32> %a, splat (i32 4)
+ ret <8 x i32> %0
+}
+
+define <4 x i64> @bitrevi_v4i64(<4 x i64> %a) nounwind {
+; CHECK-LABEL: bitrevi_v4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvbitrevi.d $xr0, $xr0, 2
+; CHECK-NEXT: ret
+entry:
+ %0 = xor <4 x i64> %a, splat (i64 4)
+ ret <4 x i64> %0
+}
+
+define <8 x i32> @bitrevi_v32i8_v8i32(<8 x i32> %a) nounwind {
+; CHECK-LABEL: bitrevi_v32i8_v8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvxori.b $xr0, $xr0, 4
+; CHECK-NEXT: ret
+entry:
+ %0 = xor <8 x i32> %a, splat (i32 67372036)
+ ret <8 x i32> %0
+}
+
+define <8 x i32> @bitrevi_v16i16_v8i32(<8 x i32> %a) nounwind {
+; CHECK-LABEL: bitrevi_v16i16_v8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvrepli.h $xr1, 4
+; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr1
+; CHECK-NEXT: ret
+entry:
+ %0 = xor <8 x i32> %a, splat (i32 262148)
+ ret <8 x i32> %0
+}
+
+define <4 x i64> @bitrevi_v32i8_v4i64(<4 x i64> %a) nounwind {
+; CHECK-LABEL: bitrevi_v32i8_v4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvxori.b $xr0, $xr0, 4
+; CHECK-NEXT: ret
+entry:
+ %0 = xor <4 x i64> %a, splat (i64 289360691352306692)
+ ret <4 x i64> %0
+}
+
+define <4 x i64> @bitrevi_v16i16_v4i64(<4 x i64> %a) nounwind {
+; CHECK-LABEL: bitrevi_v16i16_v4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvrepli.h $xr1, 4
+; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr1
+; CHECK-NEXT: ret
+entry:
+ %0 = xor <4 x i64> %a, splat (i64 1125917086973956)
+ ret <4 x i64> %0
+}
+
+define <4 x i64> @bitrevi_v8i32_v4i64(<4 x i64> %a) nounwind {
+; CHECK-LABEL: bitrevi_v8i32_v4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvrepli.w $xr1, 4
+; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr1
+; CHECK-NEXT: ret
+entry:
+ %0 = xor <4 x i64> %a, splat (i64 17179869188)
+ ret <4 x i64> %0
+}
diff --git a/llvm/test/CodeGen/LoongArch/lasx/bitset.ll b/llvm/test/CodeGen/LoongArch/lasx/bitset.ll
new file mode 100644
index 0000000000000..517f0629a5242
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lasx/bitset.ll
@@ -0,0 +1,96 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
+
+define <32 x i8> @bitseti_v32i8(<32 x i8> %a) nounwind {
+; CHECK-LABEL: bitseti_v32i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvbitseti.b $xr0, $xr0, 2
+; CHECK-NEXT: ret
+entry:
+ %0 = or <32 x i8> %a, splat (i8 4)
+ ret <32 x i8> %0
+}
+
+define <16 x i16> @bitseti_v16i16(<16 x i16> %a) nounwind {
+; CHECK-LABEL: bitseti_v16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvbitseti.h $xr0, $xr0, 2
+; CHECK-NEXT: ret
+entry:
+ %0 = or <16 x i16> %a, splat (i16 4)
+ ret <16 x i16> %0
+}
+
+define <8 x i32> @bitseti_v8i32(<8 x i32> %a) nounwind {
+; CHECK-LABEL: bitseti_v8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvbitseti.w $xr0, $xr0, 2
+; CHECK-NEXT: ret
+entry:
+ %0 = or <8 x i32> %a, splat (i32 4)
+ ret <8 x i32> %0
+}
+
+define <4 x i64> @bitseti_v4i64(<4 x i64> %a) nounwind {
+; CHECK-LABEL: bitseti_v4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvbitseti.d $xr0, $xr0, 2
+; CHECK-NEXT: ret
+entry:
+ %0 = or <4 x i64> %a, splat (i64 4)
+ ret <4 x i64> %0
+}
+
+define <8 x i32> @bitseti_v32i8_v8i32(<8 x i32> %a) nounwind {
+; CHECK-LABEL: bitseti_v32i8_v8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvori.b $xr0, $xr0, 4
+; CHECK-NEXT: ret
+entry:
+ %0 = or <8 x i32> %a, splat (i32 67372036)
+ ret <8 x i32> %0
+}
+
+define <8 x i32> @bitseti_v16i16_v8i32(<8 x i32> %a) nounwind {
+; CHECK-LABEL: bitseti_v16i16_v8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvrepli.h $xr1, 4
+; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1
+; CHECK-NEXT: ret
+entry:
+ %0 = or <8 x i32> %a, splat (i32 262148)
+ ret <8 x i32> %0
+}
+
+define <4 x i64> @bitseti_v32i8_v4i64(<4 x i64> %a) nounwind {
+; CHECK-LABEL: bitseti_v32i8_v4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvori.b $xr0, $xr0, 4
+; CHECK-NEXT: ret
+entry:
+ %0 = or <4 x i64> %a, splat (i64 289360691352306692)
+ ret <4 x i64> %0
+}
+
+define <4 x i64> @bitseti_v16i16_v4i64(<4 x i64> %a) nounwind {
+; CHECK-LABEL: bitseti_v16i16_v4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvrepli.h $xr1, 4
+; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1
+; CHECK-NEXT: ret
+entry:
+ %0 = or <4 x i64> %a, splat (i64 1125917086973956)
+ ret <4 x i64> %0
+}
+
+define <4 x i64> @bitseti_v8i32_v4i64(<4 x i64> %a) nounwind {
+; CHECK-LABEL: bitseti_v8i32_v4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvrepli.w $xr1, 4
+; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1
+; CHECK-NEXT: ret
+entry:
+ %0 = or <4 x i64> %a, splat (i64 17179869188)
+ ret <4 x i64> %0
+}
diff --git a/llvm/test/CodeGen/LoongArch/lsx/bitclr.ll b/llvm/test/CodeGen/LoongArch/lsx/bitclr.ll
new file mode 100644
index 0000000000000..cc41e2fa213fa
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lsx/bitclr.ll
@@ -0,0 +1,96 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
+
+define <16 x i8> @bitclri_v16i8(<16 x i8> %a) nounwind {
+; CHECK-LABEL: bitclri_v16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vbitclri.b $vr0, $vr0, 2
+; CHECK-NEXT: ret
+entry:
+ %0 = and <16 x i8> %a, splat (i8 -5)
+ ret <16 x i8> %0
+}
+
+define <8 x i16> @bitclri_v8i16(<8 x i16> %a) nounwind {
+; CHECK-LABEL: bitclri_v8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vbitclri.h $vr0, $vr0, 2
+; CHECK-NEXT: ret
+entry:
+ %0 = and <8 x i16> %a, splat (i16 -5)
+ ret <8 x i16> %0
+}
+
+define <4 x i32> @bitclri_v4i32(<4 x i32> %a) nounwind {
+; CHECK-LABEL: bitclri_v4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vbitclri.w $vr0, $vr0, 2
+; CHECK-NEXT: ret
+entry:
+ %0 = and <4 x i32> %a, splat (i32 -5)
+ ret <4 x i32> %0
+}
+
+define <2 x i64> @bitclri_v2i64(<2 x i64> %a) nounwind {
+; CHECK-LABEL: bitclri_v2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vbitclri.d $vr0, $vr0, 2
+; CHECK-NEXT: ret
+entry:
+ %0 = and <2 x i64> %a, splat (i64 -5)
+ ret <2 x i64> %0
+}
+
+define <4 x i32> @bitclri_v16i8_v4i32(<4 x i32> %a) nounwind {
+; CHECK-LABEL: bitclri_v16i8_v4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vandi.b $vr0, $vr0, 251
+; CHECK-NEXT: ret
+entry:
+ %0 = and <4 x i32> %a, splat (i32 -67372037)
+ ret <4 x i32> %0
+}
+
+define <4 x i32> @bitclri_v8i16_v4i32(<4 x i32> %a) nounwind {
+; CHECK-LABEL: bitclri_v8i16_v4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vrepli.h $vr1, -5
+; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
+; CHECK-NEXT: ret
+entry:
+ %0 = and <4 x i32> %a, splat (i32 -262149)
+ ret <4 x i32> %0
+}
+
+define <2 x i64> @bitclri_v16i8_v2i64(<2 x i64> %a) nounwind {
+; CHECK-LABEL: bitclri_v16i8_v2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vandi.b $vr0, $vr0, 251
+; CHECK-NEXT: ret
+entry:
+ %0 = and <2 x i64> %a, splat (i64 -289360691352306693)
+ ret <2 x i64> %0
+}
+
+define <2 x i64> @bitclri_v8i16_v2i64(<2 x i64> %a) nounwind {
+; CHECK-LABEL: bitclri_v8i16_v2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vrepli.h $vr1, -5
+; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
+; CHECK-NEXT: ret
+entry:
+ %0 = and <2 x i64> %a, splat (i64 -1125917086973957)
+ ret <2 x i64> %0
+}
+
+define <2 x i64> @bitclri_v4i32_v2i64(<2 x i64> %a) nounwind {
+; CHECK-LABEL: bitclri_v4i32_v2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vrepli.w $vr1, -5
+; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
+; CHECK-NEXT: ret
+entry:
+ %0 = and <2 x i64> %a, splat (i64 -17179869189)
+ ret <2 x i64> %0
+}
diff --git a/llvm/test/CodeGen/LoongArch/lsx/bitrev.ll b/llvm/test/CodeGen/LoongArch/lsx/bitrev.ll
new file mode 100644
index 0000000000000..9d5685f4679ee
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lsx/bitrev.ll
@@ -0,0 +1,96 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
+
+define <16 x i8> @bitrevi_v16i8(<16 x i8> %a) nounwind {
+; CHECK-LABEL: bitrevi_v16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vbitrevi.b $vr0, $vr0, 2
+; CHECK-NEXT: ret
+entry:
+ %0 = xor <16 x i8> %a, splat (i8 4)
+ ret <16 x i8> %0
+}
+
+define <8 x i16> @bitrevi_v8i16(<8 x i16> %a) nounwind {
+; CHECK-LABEL: bitrevi_v8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vbitrevi.h $vr0, $vr0, 2
+; CHECK-NEXT: ret
+entry:
+ %0 = xor <8 x i16> %a, splat (i16 4)
+ ret <8 x i16> %0
+}
+
+define <4 x i32> @bitrevi_v4i32(<4 x i32> %a) nounwind {
+; CHECK-LABEL: bitrevi_v4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vbitrevi.w $vr0, $vr0, 2
+; CHECK-NEXT: ret
+entry:
+ %0 = xor <4 x i32> %a, splat (i32 4)
+ ret <4 x i32> %0
+}
+
+define <2 x i64> @bitrevi_v2i64(<2 x i64> %a) nounwind {
+; CHECK-LABEL: bitrevi_v2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vbitrevi.d $vr0, $vr0, 2
+; CHECK-NEXT: ret
+entry:
+ %0 = xor <2 x i64> %a, splat (i64 4)
+ ret <2 x i64> %0
+}
+
+define <4 x i32> @bitrevi_v16i8_v4i32(<4 x i32> %a) nounwind {
+; CHECK-LABEL: bitrevi_v16i8_v4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vxori.b $vr0, $vr0, 4
+; CHECK-NEXT: ret
+entry:
+ %0 = xor <4 x i32> %a, splat (i32 67372036)
+ ret <4 x i32> %0
+}
+
+define <4 x i32> @bitrevi_v8i16_v4i32(<4 x i32> %a) nounwind {
+; CHECK-LABEL: bitrevi_v8i16_v4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vrepli.h $vr1, 4
+; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1
+; CHECK-NEXT: ret
+entry:
+ %0 = xor <4 x i32> %a, splat (i32 262148)
+ ret <4 x i32> %0
+}
+
+define <2 x i64> @bitrevi_v16i8_v2i64(<2 x i64> %a) nounwind {
+; CHECK-LABEL: bitrevi_v16i8_v2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vxori.b $vr0, $vr0, 4
+; CHECK-NEXT: ret
+entry:
+ %0 = xor <2 x i64> %a, splat (i64 289360691352306692)
+ ret <2 x i64> %0
+}
+
+define <2 x i64> @bitrevi_v8i16_v2i64(<2 x i64> %a) nounwind {
+; CHECK-LABEL: bitrevi_v8i16_v2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vrepli.h $vr1, 4
+; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1
+; CHECK-NEXT: ret
+entry:
+ %0 = xor <2 x i64> %a, splat (i64 1125917086973956)
+ ret <2 x i64> %0
+}
+
+define <2 x i64> @bitrevi_v4i32_v2i64(<2 x i64> %a) nounwind {
+; CHECK-LABEL: bitrevi_v4i32_v2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vrepli.w $vr1, 4
+; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1
+; CHECK-NEXT: ret
+entry:
+ %0 = xor <2 x i64> %a, splat (i64 17179869188)
+ ret <2 x i64> %0
+}
diff --git a/llvm/test/CodeGen/LoongArch/lsx/bitset.ll b/llvm/test/CodeGen/LoongArch/lsx/bitset.ll
new file mode 100644
index 0000000000000..79ac3a86c9613
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lsx/bitset.ll
@@ -0,0 +1,96 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
+
+define <16 x i8> @bitseti_v16i8(<16 x i8> %a) nounwind {
+; CHECK-LABEL: bitseti_v16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vbitseti.b $vr0, $vr0, 2
+; CHECK-NEXT: ret
+entry:
+ %0 = or <16 x i8> %a, splat (i8 4)
+ ret <16 x i8> %0
+}
+
+define <8 x i16> @bitseti_v8i16(<8 x i16> %a) nounwind {
+; CHECK-LABEL: bitseti_v8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vbitseti.h $vr0, $vr0, 2
+; CHECK-NEXT: ret
+entry:
+ %0 = or <8 x i16> %a, splat (i16 4)
+ ret <8 x i16> %0
+}
+
+define <4 x i32> @bitseti_v4i32(<4 x i32> %a) nounwind {
+; CHECK-LABEL: bitseti_v4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vbitseti.w $vr0, $vr0, 2
+; CHECK-NEXT: ret
+entry:
+ %0 = or <4 x i32> %a, splat (i32 4)
+ ret <4 x i32> %0
+}
+
+define <2 x i64> @bitseti_v2i64(<2 x i64> %a) nounwind {
+; CHECK-LABEL: bitseti_v2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vbitseti.d $vr0, $vr0, 2
+; CHECK-NEXT: ret
+entry:
+ %0 = or <2 x i64> %a, splat (i64 4)
+ ret <2 x i64> %0
+}
+
+define <4 x i32> @bitseti_v16i8_v4i32(<4 x i32> %a) nounwind {
+; CHECK-LABEL: bitseti_v16i8_v4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vori.b $vr0, $vr0, 4
+; CHECK-NEXT: ret
+entry:
+ %0 = or <4 x i32> %a, splat (i32 67372036)
+ ret <4 x i32> %0
+}
+
+define <4 x i32> @bitseti_v8i16_v4i32(<4 x i32> %a) nounwind {
+; CHECK-LABEL: bitseti_v8i16_v4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vrepli.h $vr1, 4
+; CHECK-NEXT: vor.v $vr0, $vr0, $vr1
+; CHECK-NEXT: ret
+entry:
+ %0 = or <4 x i32> %a, splat (i32 262148)
+ ret <4 x i32> %0
+}
+
+define <2 x i64> @bitseti_v16i8_v2i64(<2 x i64> %a) nounwind {
+; CHECK-LABEL: bitseti_v16i8_v2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vori.b $vr0, $vr0, 4
+; CHECK-NEXT: ret
+entry:
+ %0 = or <2 x i64> %a, splat (i64 289360691352306692)
+ ret <2 x i64> %0
+}
+
+define <2 x i64> @bitseti_v8i16_v2i64(<2 x i64> %a) nounwind {
+; CHECK-LABEL: bitseti_v8i16_v2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vrepli.h $vr1, 4
+; CHECK-NEXT: vor.v $vr0, $vr0, $vr1
+; CHECK-NEXT: ret
+entry:
+ %0 = or <2 x i64> %a, splat (i64 1125917086973956)
+ ret <2 x i64> %0
+}
+
+define <2 x i64> @bitseti_v4i32_v2i64(<2 x i64> %a) nounwind {
+; CHECK-LABEL: bitseti_v4i32_v2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vrepli.w $vr1, 4
+; CHECK-NEXT: vor.v $vr0, $vr0, $vr1
+; CHECK-NEXT: ret
+entry:
+ %0 = or <2 x i64> %a, splat (i64 17179869188)
+ ret <2 x i64> %0
+}
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