[llvm] [ARM] Fuse SETCC into SELECT_CC in LowerSELECT (PR #194481)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 27 15:55:00 PDT 2026
https://github.com/LumioseSil updated https://github.com/llvm/llvm-project/pull/194481
>From 15c069088ba678f966130d3450d98ccba39a807f Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Mon, 27 Apr 2026 18:47:43 -0400
Subject: [PATCH] [ARM] Fuse SETCC into SELECT_CC in LowerSELECT
This matches what we do for AArch64, allows reuse of SetCC, and ARM's BooleanContents value is ZeroOrOne, not undefined, so we can get rid of the Cond since it will always be optimized out anyway.
---
llvm/lib/Target/ARM/ARMISelLowering.cpp | 22 +-
llvm/test/CodeGen/Thumb2/mve-fmas.ll | 595 +++--
.../CodeGen/Thumb2/mve-fptosi-sat-vector.ll | 1226 ++++++----
.../CodeGen/Thumb2/mve-fptoui-sat-vector.ll | 962 +++++---
llvm/test/CodeGen/Thumb2/mve-pred-vselect.ll | 30 +-
.../CodeGen/Thumb2/mve-saturating-arith.ll | 60 +-
llvm/test/CodeGen/Thumb2/mve-vcmpf.ll | 996 +++-----
llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll | 1936 ++++++----------
llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll | 2046 +++++++----------
9 files changed, 3562 insertions(+), 4311 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 17d57c1a24407..3939eab30fa58 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -4910,14 +4910,20 @@ SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
}
}
- // ARM's BooleanContents value is UndefinedBooleanContent. Mask out the
- // undefined bits before doing a full-word comparison with zero.
- Cond = DAG.getNode(ISD::AND, dl, Cond.getValueType(), Cond,
- DAG.getConstant(1, dl, Cond.getValueType()));
-
- return DAG.getSelectCC(dl, Cond,
- DAG.getConstant(0, dl, Cond.getValueType()),
- SelectTrue, SelectFalse, ISD::SETNE);
+ // Lower it the same way as we would lower a SELECT_CC node.
+ ISD::CondCode CC;
+ SDValue LHS, RHS;
+ if (Cond.getOpcode() == ISD::SETCC) {
+ LHS = Cond.getOperand(0);
+ RHS = Cond.getOperand(1);
+ CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
+ } else {
+ LHS = Cond;
+ RHS = DAG.getConstant(0, dl, Cond.getValueType());
+ CC = ISD::SETNE;
+ }
+
+ return DAG.getSelectCC(dl, LHS, RHS, SelectTrue, SelectFalse, CC);
}
static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
diff --git a/llvm/test/CodeGen/Thumb2/mve-fmas.ll b/llvm/test/CodeGen/Thumb2/mve-fmas.ll
index 94921c78ad912..7be93817ce907 100644
--- a/llvm/test/CodeGen/Thumb2/mve-fmas.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-fmas.ll
@@ -400,79 +400,68 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_v1_pred(<8 x half> %src1, <8 x half> %
;
; CHECK-MVE-LABEL: vfma16_v1_pred:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vmovx.f16 s14, s4
; CHECK-MVE-NEXT: vmovx.f16 s13, s0
-; CHECK-MVE-NEXT: vcmp.f16 s14, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s8
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vmovx.f16 s14, s4
; CHECK-MVE-NEXT: vmov.f32 s15, s13
; CHECK-MVE-NEXT: vmla.f16 s15, s14, s12
-; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: vmov.f32 s14, s0
-; CHECK-MVE-NEXT: vmla.f16 s14, s4, s8
+; CHECK-MVE-NEXT: vldr.16 s12, .LCPI10_0
+; CHECK-MVE-NEXT: vcmp.f16 s12, s14
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f16 s12, s4
+; CHECK-MVE-NEXT: vselgt.f16 s14, s15, s13
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vmov.f32 s13, s0
+; CHECK-MVE-NEXT: vmla.f16 s13, s4, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s5
+; CHECK-MVE-NEXT: vcmp.f16 s12, s8
; CHECK-MVE-NEXT: vmovx.f16 s4, s9
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s12, s13, s15
+; CHECK-MVE-NEXT: vselgt.f16 s0, s13, s0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s8, #0
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s0, s14
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vins.f16 s0, s12
-; CHECK-MVE-NEXT: vmovx.f16 s12, s1
-; CHECK-MVE-NEXT: vmov.f32 s14, s12
-; CHECK-MVE-NEXT: vcmp.f16 s5, #0
-; CHECK-MVE-NEXT: vmla.f16 s14, s8, s4
+; CHECK-MVE-NEXT: vins.f16 s0, s14
+; CHECK-MVE-NEXT: vmovx.f16 s14, s1
+; CHECK-MVE-NEXT: vmov.f32 s13, s14
+; CHECK-MVE-NEXT: vcmp.f16 s12, s5
+; CHECK-MVE-NEXT: vmla.f16 s13, s8, s4
; CHECK-MVE-NEXT: vmov.f32 s8, s1
; CHECK-MVE-NEXT: vmla.f16 s8, s5, s9
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s14
+; CHECK-MVE-NEXT: vselgt.f16 s4, s13, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s12, s2
-; CHECK-MVE-NEXT: vmov.f32 s14, s12
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s1, s8
+; CHECK-MVE-NEXT: vmovx.f16 s14, s2
+; CHECK-MVE-NEXT: vmov.f32 s5, s14
+; CHECK-MVE-NEXT: vselgt.f16 s1, s8, s1
; CHECK-MVE-NEXT: vmovx.f16 s8, s6
-; CHECK-MVE-NEXT: vcmp.f16 s8, #0
+; CHECK-MVE-NEXT: vcmp.f16 s12, s8
; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s4, s10
-; CHECK-MVE-NEXT: vmla.f16 s14, s8, s4
-; CHECK-MVE-NEXT: vcmp.f16 s6, #0
+; CHECK-MVE-NEXT: vmla.f16 s5, s8, s4
+; CHECK-MVE-NEXT: vcmp.f16 s12, s6
; CHECK-MVE-NEXT: vmov.f32 s8, s2
; CHECK-MVE-NEXT: vmla.f16 s8, s6, s10
; CHECK-MVE-NEXT: vmovx.f16 s6, s7
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s14
+; CHECK-MVE-NEXT: vselgt.f16 s4, s5, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s6, #0
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s2, s8
+; CHECK-MVE-NEXT: vcmp.f16 s12, s6
+; CHECK-MVE-NEXT: vselgt.f16 s2, s8, s2
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s3
; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmov.f32 s10, s8
; CHECK-MVE-NEXT: vmla.f16 s10, s6, s4
-; CHECK-MVE-NEXT: vcmp.f16 s7, #0
+; CHECK-MVE-NEXT: vcmp.f16 s12, s7
; CHECK-MVE-NEXT: vmov.f32 s6, s3
; CHECK-MVE-NEXT: vmla.f16 s6, s7, s11
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s10
+; CHECK-MVE-NEXT: vselgt.f16 s4, s10, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s3, s6
+; CHECK-MVE-NEXT: vselgt.f16 s3, s6, s3
; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr
+; CHECK-MVE-NEXT: .p2align 1
+; CHECK-MVE-NEXT: @ %bb.1:
+; CHECK-MVE-NEXT: .LCPI10_0:
+; CHECK-MVE-NEXT: .short 0x0000 @ half 0
entry:
%0 = fmul <8 x half> %src2, %src3
%1 = fadd <8 x half> %src1, %0
@@ -497,79 +486,68 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_v2_pred(<8 x half> %src1, <8 x half> %
;
; CHECK-MVE-LABEL: vfma16_v2_pred:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vmovx.f16 s14, s4
; CHECK-MVE-NEXT: vmovx.f16 s13, s0
-; CHECK-MVE-NEXT: vcmp.f16 s14, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s8
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vmovx.f16 s14, s4
; CHECK-MVE-NEXT: vmov.f32 s15, s13
; CHECK-MVE-NEXT: vmla.f16 s15, s14, s12
-; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: vmov.f32 s14, s0
-; CHECK-MVE-NEXT: vmla.f16 s14, s4, s8
+; CHECK-MVE-NEXT: vldr.16 s12, .LCPI11_0
+; CHECK-MVE-NEXT: vcmp.f16 s12, s14
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f16 s12, s4
+; CHECK-MVE-NEXT: vselgt.f16 s14, s15, s13
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vmov.f32 s13, s0
+; CHECK-MVE-NEXT: vmla.f16 s13, s4, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s5
+; CHECK-MVE-NEXT: vcmp.f16 s12, s8
; CHECK-MVE-NEXT: vmovx.f16 s4, s9
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s12, s13, s15
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s8, #0
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s0, s14
+; CHECK-MVE-NEXT: vselgt.f16 s0, s13, s0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vins.f16 s0, s12
-; CHECK-MVE-NEXT: vmovx.f16 s12, s1
-; CHECK-MVE-NEXT: vmov.f32 s14, s12
-; CHECK-MVE-NEXT: vcmp.f16 s5, #0
-; CHECK-MVE-NEXT: vmla.f16 s14, s8, s4
+; CHECK-MVE-NEXT: vins.f16 s0, s14
+; CHECK-MVE-NEXT: vmovx.f16 s14, s1
+; CHECK-MVE-NEXT: vmov.f32 s13, s14
+; CHECK-MVE-NEXT: vcmp.f16 s12, s5
+; CHECK-MVE-NEXT: vmla.f16 s13, s8, s4
; CHECK-MVE-NEXT: vmov.f32 s8, s1
; CHECK-MVE-NEXT: vmla.f16 s8, s5, s9
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s14
+; CHECK-MVE-NEXT: vselgt.f16 s4, s13, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s12, s2
-; CHECK-MVE-NEXT: vmov.f32 s14, s12
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s1, s8
+; CHECK-MVE-NEXT: vmovx.f16 s14, s2
+; CHECK-MVE-NEXT: vmov.f32 s5, s14
+; CHECK-MVE-NEXT: vselgt.f16 s1, s8, s1
; CHECK-MVE-NEXT: vmovx.f16 s8, s6
-; CHECK-MVE-NEXT: vcmp.f16 s8, #0
+; CHECK-MVE-NEXT: vcmp.f16 s12, s8
; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s4, s10
-; CHECK-MVE-NEXT: vmla.f16 s14, s8, s4
-; CHECK-MVE-NEXT: vcmp.f16 s6, #0
+; CHECK-MVE-NEXT: vmla.f16 s5, s8, s4
+; CHECK-MVE-NEXT: vcmp.f16 s12, s6
; CHECK-MVE-NEXT: vmov.f32 s8, s2
; CHECK-MVE-NEXT: vmla.f16 s8, s6, s10
; CHECK-MVE-NEXT: vmovx.f16 s6, s7
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s14
+; CHECK-MVE-NEXT: vselgt.f16 s4, s5, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s6, #0
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s2, s8
+; CHECK-MVE-NEXT: vcmp.f16 s12, s6
+; CHECK-MVE-NEXT: vselgt.f16 s2, s8, s2
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s3
; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmov.f32 s10, s8
; CHECK-MVE-NEXT: vmla.f16 s10, s6, s4
-; CHECK-MVE-NEXT: vcmp.f16 s7, #0
+; CHECK-MVE-NEXT: vcmp.f16 s12, s7
; CHECK-MVE-NEXT: vmov.f32 s6, s3
; CHECK-MVE-NEXT: vmla.f16 s6, s7, s11
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s10
+; CHECK-MVE-NEXT: vselgt.f16 s4, s10, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s3, s6
+; CHECK-MVE-NEXT: vselgt.f16 s3, s6, s3
; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr
+; CHECK-MVE-NEXT: .p2align 1
+; CHECK-MVE-NEXT: @ %bb.1:
+; CHECK-MVE-NEXT: .LCPI11_0:
+; CHECK-MVE-NEXT: .short 0x0000 @ half 0
entry:
%0 = fmul <8 x half> %src2, %src3
%1 = fadd <8 x half> %0, %src1
@@ -594,79 +572,68 @@ define arm_aapcs_vfpcc <8 x half> @vfms16_pred(<8 x half> %src1, <8 x half> %src
;
; CHECK-MVE-LABEL: vfms16_pred:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vmovx.f16 s14, s4
; CHECK-MVE-NEXT: vmovx.f16 s13, s0
-; CHECK-MVE-NEXT: vcmp.f16 s14, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s8
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vmovx.f16 s14, s4
; CHECK-MVE-NEXT: vmov.f32 s15, s13
; CHECK-MVE-NEXT: vmls.f16 s15, s14, s12
-; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: vmov.f32 s14, s0
-; CHECK-MVE-NEXT: vmls.f16 s14, s4, s8
+; CHECK-MVE-NEXT: vldr.16 s12, .LCPI12_0
+; CHECK-MVE-NEXT: vcmp.f16 s12, s14
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f16 s12, s4
+; CHECK-MVE-NEXT: vselgt.f16 s14, s15, s13
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vmov.f32 s13, s0
+; CHECK-MVE-NEXT: vmls.f16 s13, s4, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s5
+; CHECK-MVE-NEXT: vcmp.f16 s12, s8
; CHECK-MVE-NEXT: vmovx.f16 s4, s9
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s12, s13, s15
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s8, #0
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s0, s14
+; CHECK-MVE-NEXT: vselgt.f16 s0, s13, s0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vins.f16 s0, s12
-; CHECK-MVE-NEXT: vmovx.f16 s12, s1
-; CHECK-MVE-NEXT: vmov.f32 s14, s12
-; CHECK-MVE-NEXT: vcmp.f16 s5, #0
-; CHECK-MVE-NEXT: vmls.f16 s14, s8, s4
+; CHECK-MVE-NEXT: vins.f16 s0, s14
+; CHECK-MVE-NEXT: vmovx.f16 s14, s1
+; CHECK-MVE-NEXT: vmov.f32 s13, s14
+; CHECK-MVE-NEXT: vcmp.f16 s12, s5
+; CHECK-MVE-NEXT: vmls.f16 s13, s8, s4
; CHECK-MVE-NEXT: vmov.f32 s8, s1
; CHECK-MVE-NEXT: vmls.f16 s8, s5, s9
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s14
+; CHECK-MVE-NEXT: vselgt.f16 s4, s13, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s12, s2
-; CHECK-MVE-NEXT: vmov.f32 s14, s12
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s1, s8
+; CHECK-MVE-NEXT: vmovx.f16 s14, s2
+; CHECK-MVE-NEXT: vmov.f32 s5, s14
+; CHECK-MVE-NEXT: vselgt.f16 s1, s8, s1
; CHECK-MVE-NEXT: vmovx.f16 s8, s6
-; CHECK-MVE-NEXT: vcmp.f16 s8, #0
+; CHECK-MVE-NEXT: vcmp.f16 s12, s8
; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s4, s10
-; CHECK-MVE-NEXT: vmls.f16 s14, s8, s4
-; CHECK-MVE-NEXT: vcmp.f16 s6, #0
+; CHECK-MVE-NEXT: vmls.f16 s5, s8, s4
+; CHECK-MVE-NEXT: vcmp.f16 s12, s6
; CHECK-MVE-NEXT: vmov.f32 s8, s2
; CHECK-MVE-NEXT: vmls.f16 s8, s6, s10
; CHECK-MVE-NEXT: vmovx.f16 s6, s7
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s14
+; CHECK-MVE-NEXT: vselgt.f16 s4, s5, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s6, #0
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s2, s8
+; CHECK-MVE-NEXT: vcmp.f16 s12, s6
+; CHECK-MVE-NEXT: vselgt.f16 s2, s8, s2
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s3
; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmov.f32 s10, s8
; CHECK-MVE-NEXT: vmls.f16 s10, s6, s4
-; CHECK-MVE-NEXT: vcmp.f16 s7, #0
+; CHECK-MVE-NEXT: vcmp.f16 s12, s7
; CHECK-MVE-NEXT: vmov.f32 s6, s3
; CHECK-MVE-NEXT: vmls.f16 s6, s7, s11
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s10
+; CHECK-MVE-NEXT: vselgt.f16 s4, s10, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s3, s6
+; CHECK-MVE-NEXT: vselgt.f16 s3, s6, s3
; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr
+; CHECK-MVE-NEXT: .p2align 1
+; CHECK-MVE-NEXT: @ %bb.1:
+; CHECK-MVE-NEXT: .LCPI12_0:
+; CHECK-MVE-NEXT: .short 0x0000 @ half 0
entry:
%0 = fmul <8 x half> %src2, %src3
%1 = fsub <8 x half> %src1, %0
@@ -696,76 +663,65 @@ define arm_aapcs_vfpcc <8 x half> @vfmar16_pred(<8 x half> %src1, <8 x half> %sr
;
; CHECK-MVE-LABEL: vfmar16_pred:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vmovx.f16 s10, s4
-; CHECK-MVE-NEXT: vmovx.f16 s12, s0
-; CHECK-MVE-NEXT: vcmp.f16 s10, #0
+; CHECK-MVE-NEXT: vldr.16 s10, .LCPI13_0
+; CHECK-MVE-NEXT: vmovx.f16 s12, s4
+; CHECK-MVE-NEXT: vmovx.f16 s14, s0
; CHECK-MVE-NEXT: vcvtb.f16.f32 s8, s8
+; CHECK-MVE-NEXT: vcmp.f16 s10, s12
+; CHECK-MVE-NEXT: vmov.f32 s9, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmov.f32 s14, s12
-; CHECK-MVE-NEXT: vmla.f16 s14, s10, s8
-; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s10, s12, s14
+; CHECK-MVE-NEXT: vmla.f16 s9, s12, s8
+; CHECK-MVE-NEXT: vcmp.f16 s10, s4
+; CHECK-MVE-NEXT: vselgt.f16 s12, s9, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmov.f32 s12, s0
-; CHECK-MVE-NEXT: vmla.f16 s12, s4, s8
+; CHECK-MVE-NEXT: vmov.f32 s14, s0
+; CHECK-MVE-NEXT: vmla.f16 s14, s4, s8
; CHECK-MVE-NEXT: vmovx.f16 s4, s5
-; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s0, s12
+; CHECK-MVE-NEXT: vcmp.f16 s10, s4
+; CHECK-MVE-NEXT: vselgt.f16 s0, s14, s0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vins.f16 s0, s10
-; CHECK-MVE-NEXT: vmovx.f16 s10, s1
-; CHECK-MVE-NEXT: vmov.f32 s12, s10
-; CHECK-MVE-NEXT: vcmp.f16 s5, #0
-; CHECK-MVE-NEXT: vmla.f16 s12, s4, s8
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s10, s12
+; CHECK-MVE-NEXT: vins.f16 s0, s12
+; CHECK-MVE-NEXT: vmovx.f16 s12, s1
+; CHECK-MVE-NEXT: vmov.f32 s14, s12
+; CHECK-MVE-NEXT: vcmp.f16 s10, s5
+; CHECK-MVE-NEXT: vmla.f16 s14, s4, s8
+; CHECK-MVE-NEXT: vselgt.f16 s4, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmov.f32 s10, s1
-; CHECK-MVE-NEXT: vmla.f16 s10, s5, s8
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s1, s10
-; CHECK-MVE-NEXT: vmovx.f16 s10, s2
+; CHECK-MVE-NEXT: vmov.f32 s12, s1
+; CHECK-MVE-NEXT: vmla.f16 s12, s5, s8
+; CHECK-MVE-NEXT: vselgt.f16 s1, s12, s1
+; CHECK-MVE-NEXT: vmovx.f16 s12, s2
; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
-; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: vmov.f32 s12, s10
+; CHECK-MVE-NEXT: vcmp.f16 s10, s4
+; CHECK-MVE-NEXT: vmov.f32 s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmla.f16 s12, s4, s8
-; CHECK-MVE-NEXT: vcmp.f16 s6, #0
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s10, s12
+; CHECK-MVE-NEXT: vmla.f16 s14, s4, s8
+; CHECK-MVE-NEXT: vcmp.f16 s10, s6
+; CHECK-MVE-NEXT: vselgt.f16 s4, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmov.f32 s10, s2
-; CHECK-MVE-NEXT: vmla.f16 s10, s6, s8
+; CHECK-MVE-NEXT: vmov.f32 s12, s2
+; CHECK-MVE-NEXT: vmla.f16 s12, s6, s8
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s2, s10
-; CHECK-MVE-NEXT: vmov.f32 s10, s6
+; CHECK-MVE-NEXT: vselgt.f16 s2, s12, s2
+; CHECK-MVE-NEXT: vmov.f32 s12, s6
; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
-; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: vmla.f16 s10, s4, s8
+; CHECK-MVE-NEXT: vcmp.f16 s10, s4
+; CHECK-MVE-NEXT: vmla.f16 s12, s4, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s7, #0
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s10
+; CHECK-MVE-NEXT: vcmp.f16 s10, s7
+; CHECK-MVE-NEXT: vselgt.f16 s4, s12, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.f32 s6, s3
; CHECK-MVE-NEXT: vmla.f16 s6, s7, s8
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s3, s6
+; CHECK-MVE-NEXT: vselgt.f16 s3, s6, s3
; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr
+; CHECK-MVE-NEXT: .p2align 1
+; CHECK-MVE-NEXT: @ %bb.1:
+; CHECK-MVE-NEXT: .LCPI13_0:
+; CHECK-MVE-NEXT: .short 0x0000 @ half 0
entry:
%src3 = fptrunc float %src3o to half
%i = insertelement <8 x half> undef, half %src3, i32 0
@@ -797,75 +753,64 @@ define arm_aapcs_vfpcc <8 x half> @vfma16_pred(<8 x half> %src1, <8 x half> %src
;
; CHECK-MVE-LABEL: vfma16_pred:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vmovx.f16 s10, s4
+; CHECK-MVE-NEXT: vldr.16 s10, .LCPI14_0
+; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vcvtb.f16.f32 s8, s8
-; CHECK-MVE-NEXT: vcmp.f16 s10, #0
-; CHECK-MVE-NEXT: vmovx.f16 s12, s0
+; CHECK-MVE-NEXT: vmovx.f16 s14, s0
+; CHECK-MVE-NEXT: vcmp.f16 s10, s12
+; CHECK-MVE-NEXT: vmov.f32 s9, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmov.f32 s14, s8
-; CHECK-MVE-NEXT: vmla.f16 s14, s12, s10
-; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s10, s12, s14
+; CHECK-MVE-NEXT: vmla.f16 s9, s14, s12
+; CHECK-MVE-NEXT: vcmp.f16 s10, s4
+; CHECK-MVE-NEXT: vselgt.f16 s12, s9, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmov.f32 s12, s8
-; CHECK-MVE-NEXT: vmla.f16 s12, s0, s4
+; CHECK-MVE-NEXT: vmov.f32 s14, s8
+; CHECK-MVE-NEXT: vmla.f16 s14, s0, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s5
-; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s0, s12
+; CHECK-MVE-NEXT: vcmp.f16 s10, s4
+; CHECK-MVE-NEXT: vselgt.f16 s0, s14, s0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vins.f16 s0, s10
-; CHECK-MVE-NEXT: vmovx.f16 s10, s1
-; CHECK-MVE-NEXT: vmov.f32 s12, s8
-; CHECK-MVE-NEXT: vcmp.f16 s5, #0
-; CHECK-MVE-NEXT: vmla.f16 s12, s10, s4
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s10, s12
+; CHECK-MVE-NEXT: vins.f16 s0, s12
+; CHECK-MVE-NEXT: vmovx.f16 s12, s1
+; CHECK-MVE-NEXT: vmov.f32 s14, s8
+; CHECK-MVE-NEXT: vcmp.f16 s10, s5
+; CHECK-MVE-NEXT: vmla.f16 s14, s12, s4
+; CHECK-MVE-NEXT: vselgt.f16 s4, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmov.f32 s10, s8
-; CHECK-MVE-NEXT: vmla.f16 s10, s1, s5
; CHECK-MVE-NEXT: vmov.f32 s12, s8
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s1, s10
-; CHECK-MVE-NEXT: vmovx.f16 s10, s2
+; CHECK-MVE-NEXT: vmla.f16 s12, s1, s5
+; CHECK-MVE-NEXT: vmov.f32 s14, s8
+; CHECK-MVE-NEXT: vselgt.f16 s1, s12, s1
+; CHECK-MVE-NEXT: vmovx.f16 s12, s2
; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
-; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: vmla.f16 s12, s10, s4
+; CHECK-MVE-NEXT: vcmp.f16 s10, s4
+; CHECK-MVE-NEXT: vmla.f16 s14, s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s6, #0
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s10, s12
+; CHECK-MVE-NEXT: vcmp.f16 s10, s6
+; CHECK-MVE-NEXT: vselgt.f16 s4, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmov.f32 s10, s8
-; CHECK-MVE-NEXT: vmla.f16 s10, s2, s6
+; CHECK-MVE-NEXT: vmov.f32 s12, s8
+; CHECK-MVE-NEXT: vmla.f16 s12, s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s2, s10
-; CHECK-MVE-NEXT: vmov.f32 s10, s8
+; CHECK-MVE-NEXT: vselgt.f16 s2, s12, s2
+; CHECK-MVE-NEXT: vmov.f32 s12, s8
; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
-; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: vmla.f16 s10, s6, s4
+; CHECK-MVE-NEXT: vcmp.f16 s10, s4
+; CHECK-MVE-NEXT: vmla.f16 s12, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s7, #0
+; CHECK-MVE-NEXT: vcmp.f16 s10, s7
; CHECK-MVE-NEXT: vmla.f16 s8, s3, s7
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s10
+; CHECK-MVE-NEXT: vselgt.f16 s4, s12, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s3, s8
+; CHECK-MVE-NEXT: vselgt.f16 s3, s8, s3
; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr
+; CHECK-MVE-NEXT: .p2align 1
+; CHECK-MVE-NEXT: @ %bb.1:
+; CHECK-MVE-NEXT: .LCPI14_0:
+; CHECK-MVE-NEXT: .short 0x0000 @ half 0
entry:
%src3 = fptrunc float %src3o to half
%i = insertelement <8 x half> undef, half %src3, i32 0
@@ -893,34 +838,30 @@ define arm_aapcs_vfpcc <4 x float> @vfma32_v1_pred(<4 x float> %src1, <4 x float
;
; CHECK-MVE-LABEL: vfma32_v1_pred:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s4, #0
+; CHECK-MVE-NEXT: vmov.f32 s12, s2
+; CHECK-MVE-NEXT: vmov.f32 s14, s1
+; CHECK-MVE-NEXT: vcmp.f32 s6, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s7, #0
-; CHECK-MVE-NEXT: vmov.f32 s12, s2
-; CHECK-MVE-NEXT: vmov.f32 s14, s3
; CHECK-MVE-NEXT: vmla.f32 s12, s6, s10
-; CHECK-MVE-NEXT: vmov.f32 s10, s1
-; CHECK-MVE-NEXT: vmla.f32 s14, s7, s11
-; CHECK-MVE-NEXT: vmla.f32 s10, s5, s9
-; CHECK-MVE-NEXT: vmov.f32 s9, s0
-; CHECK-MVE-NEXT: cset r0, mi
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s2, s12
+; CHECK-MVE-NEXT: vmov.f32 s10, s3
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vmla.f32 s14, s5, s9
+; CHECK-MVE-NEXT: vmov.f32 s9, s0
; CHECK-MVE-NEXT: vcmp.f32 s5, #0
-; CHECK-MVE-NEXT: vmla.f32 s9, s4, s8
-; CHECK-MVE-NEXT: cset r1, mi
+; CHECK-MVE-NEXT: vmla.f32 s10, s7, s11
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s3, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s6, #0
-; CHECK-MVE-NEXT: cset r2, mi
+; CHECK-MVE-NEXT: vcmp.f32 s4, #0
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s1, s14
+; CHECK-MVE-NEXT: vmla.f32 s9, s4, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, mi
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s12
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s10
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s14
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s0, s9
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s0, s9
; CHECK-MVE-NEXT: bx lr
entry:
%0 = fmul <4 x float> %src2, %src3
@@ -946,34 +887,30 @@ define arm_aapcs_vfpcc <4 x float> @vfma32_v2_pred(<4 x float> %src1, <4 x float
;
; CHECK-MVE-LABEL: vfma32_v2_pred:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s4, #0
+; CHECK-MVE-NEXT: vmov.f32 s12, s2
+; CHECK-MVE-NEXT: vmov.f32 s14, s1
+; CHECK-MVE-NEXT: vcmp.f32 s6, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s7, #0
-; CHECK-MVE-NEXT: vmov.f32 s12, s2
-; CHECK-MVE-NEXT: vmov.f32 s14, s3
; CHECK-MVE-NEXT: vmla.f32 s12, s6, s10
-; CHECK-MVE-NEXT: vmov.f32 s10, s1
-; CHECK-MVE-NEXT: vmla.f32 s14, s7, s11
-; CHECK-MVE-NEXT: vmla.f32 s10, s5, s9
-; CHECK-MVE-NEXT: vmov.f32 s9, s0
-; CHECK-MVE-NEXT: cset r0, mi
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s2, s12
+; CHECK-MVE-NEXT: vmov.f32 s10, s3
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vmla.f32 s14, s5, s9
+; CHECK-MVE-NEXT: vmov.f32 s9, s0
; CHECK-MVE-NEXT: vcmp.f32 s5, #0
-; CHECK-MVE-NEXT: vmla.f32 s9, s4, s8
-; CHECK-MVE-NEXT: cset r1, mi
+; CHECK-MVE-NEXT: vmla.f32 s10, s7, s11
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s3, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s6, #0
-; CHECK-MVE-NEXT: cset r2, mi
+; CHECK-MVE-NEXT: vcmp.f32 s4, #0
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s1, s14
+; CHECK-MVE-NEXT: vmla.f32 s9, s4, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, mi
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s12
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s10
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s14
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s0, s9
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s0, s9
; CHECK-MVE-NEXT: bx lr
entry:
%0 = fmul <4 x float> %src2, %src3
@@ -999,34 +936,30 @@ define arm_aapcs_vfpcc <4 x float> @vfms32_pred(<4 x float> %src1, <4 x float> %
;
; CHECK-MVE-LABEL: vfms32_pred:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s4, #0
+; CHECK-MVE-NEXT: vmov.f32 s12, s2
+; CHECK-MVE-NEXT: vmov.f32 s14, s1
+; CHECK-MVE-NEXT: vcmp.f32 s6, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s7, #0
-; CHECK-MVE-NEXT: vmov.f32 s12, s2
-; CHECK-MVE-NEXT: vmov.f32 s14, s3
; CHECK-MVE-NEXT: vmls.f32 s12, s6, s10
-; CHECK-MVE-NEXT: vmov.f32 s10, s1
-; CHECK-MVE-NEXT: vmls.f32 s14, s7, s11
-; CHECK-MVE-NEXT: vmls.f32 s10, s5, s9
-; CHECK-MVE-NEXT: vmov.f32 s9, s0
-; CHECK-MVE-NEXT: cset r0, mi
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s2, s12
+; CHECK-MVE-NEXT: vmov.f32 s10, s3
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vmls.f32 s14, s5, s9
+; CHECK-MVE-NEXT: vmov.f32 s9, s0
; CHECK-MVE-NEXT: vcmp.f32 s5, #0
-; CHECK-MVE-NEXT: vmls.f32 s9, s4, s8
-; CHECK-MVE-NEXT: cset r1, mi
+; CHECK-MVE-NEXT: vmls.f32 s10, s7, s11
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s3, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s6, #0
-; CHECK-MVE-NEXT: cset r2, mi
+; CHECK-MVE-NEXT: vcmp.f32 s4, #0
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s1, s14
+; CHECK-MVE-NEXT: vmls.f32 s9, s4, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, mi
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s12
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s10
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s14
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s0, s9
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s0, s9
; CHECK-MVE-NEXT: bx lr
entry:
%0 = fmul <4 x float> %src2, %src3
@@ -1055,34 +988,30 @@ define arm_aapcs_vfpcc <4 x float> @vfmar32_pred(<4 x float> %src1, <4 x float>
;
; CHECK-MVE-LABEL: vfmar32_pred:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s4, #0
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s7, #0
; CHECK-MVE-NEXT: vmov.f32 s10, s2
-; CHECK-MVE-NEXT: vmov.f32 s12, s1
-; CHECK-MVE-NEXT: vmov.f32 s14, s3
+; CHECK-MVE-NEXT: vmov.f32 s12, s3
+; CHECK-MVE-NEXT: vmov.f32 s14, s1
; CHECK-MVE-NEXT: vmov.f32 s9, s0
+; CHECK-MVE-NEXT: vcmp.f32 s6, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f32 s7, #0
; CHECK-MVE-NEXT: vmla.f32 s10, s6, s8
-; CHECK-MVE-NEXT: vmla.f32 s12, s5, s8
-; CHECK-MVE-NEXT: vmla.f32 s14, s7, s8
-; CHECK-MVE-NEXT: vmla.f32 s9, s4, s8
-; CHECK-MVE-NEXT: cset r0, mi
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s2, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s5, #0
-; CHECK-MVE-NEXT: cset r1, mi
+; CHECK-MVE-NEXT: vmla.f32 s12, s7, s8
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s3, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s6, #0
-; CHECK-MVE-NEXT: cset r2, mi
+; CHECK-MVE-NEXT: vcmp.f32 s4, #0
+; CHECK-MVE-NEXT: vmla.f32 s14, s5, s8
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s1, s14
+; CHECK-MVE-NEXT: vmla.f32 s9, s4, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, mi
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s10
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s12
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s14
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s0, s9
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s0, s9
; CHECK-MVE-NEXT: bx lr
entry:
%i = insertelement <4 x float> undef, float %src3, i32 0
@@ -1112,33 +1041,29 @@ define arm_aapcs_vfpcc <4 x float> @vfmas32_pred(<4 x float> %src1, <4 x float>
;
; CHECK-MVE-LABEL: vfmas32_pred:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s4, #0
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s7, #0
; CHECK-MVE-NEXT: vmov.f32 s10, s8
; CHECK-MVE-NEXT: vmov.f32 s12, s8
; CHECK-MVE-NEXT: vmov.f32 s14, s8
+; CHECK-MVE-NEXT: vcmp.f32 s6, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f32 s7, #0
; CHECK-MVE-NEXT: vmla.f32 s8, s0, s4
; CHECK-MVE-NEXT: vmla.f32 s10, s2, s6
-; CHECK-MVE-NEXT: vmla.f32 s12, s1, s5
-; CHECK-MVE-NEXT: vmla.f32 s14, s3, s7
-; CHECK-MVE-NEXT: cset r0, mi
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s2, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s5, #0
-; CHECK-MVE-NEXT: cset r1, mi
+; CHECK-MVE-NEXT: vmla.f32 s12, s3, s7
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s3, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s6, #0
-; CHECK-MVE-NEXT: cset r2, mi
+; CHECK-MVE-NEXT: vcmp.f32 s4, #0
+; CHECK-MVE-NEXT: vmla.f32 s14, s1, s5
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s1, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, mi
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s10
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s12
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s14
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s0, s8
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s0, s8
; CHECK-MVE-NEXT: bx lr
entry:
%i = insertelement <4 x float> undef, float %src3, i32 0
diff --git a/llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll b/llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll
index 77548b49d77f2..1feba7540fdea 100644
--- a/llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll
@@ -339,32 +339,34 @@ define arm_aapcs_vfpcc <2 x i32> @test_signed_v2f64_v2i32(<2 x double> %f) {
; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
-; CHECK-NEXT: .pad #16
-; CHECK-NEXT: sub sp, #16
+; CHECK-NEXT: .pad #24
+; CHECK-NEXT: sub sp, #24
; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vldr d0, .LCPI9_0
; CHECK-NEXT: vmov r9, r8, d9
-; CHECK-NEXT: vmov r7, r3, d0
-; CHECK-NEXT: str r3, [sp, #12] @ 4-byte Spill
+; CHECK-NEXT: vmov r11, r10, d0
+; CHECK-NEXT: str.w r11, [sp, #12] @ 4-byte Spill
; CHECK-NEXT: mov r0, r9
; CHECK-NEXT: mov r1, r8
-; CHECK-NEXT: mov r2, r7
+; CHECK-NEXT: mov r2, r11
+; CHECK-NEXT: mov r3, r10
+; CHECK-NEXT: str.w r10, [sp, #16] @ 4-byte Spill
; CHECK-NEXT: bl __aeabi_dcmpge
-; CHECK-NEXT: mov r6, r0
+; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: mov r0, r9
; CHECK-NEXT: mov r1, r8
; CHECK-NEXT: bl __aeabi_d2lz
; CHECK-NEXT: vldr d0, .LCPI9_1
; CHECK-NEXT: mov r5, r0
-; CHECK-NEXT: mov r4, r1
+; CHECK-NEXT: str r1, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: mov r0, r9
; CHECK-NEXT: vmov r2, r3, d0
; CHECK-NEXT: mov r1, r8
-; CHECK-NEXT: vmov r11, r10, d8
-; CHECK-NEXT: cmp r6, #0
-; CHECK-NEXT: strd r2, r3, [sp, #4] @ 8-byte Folded Spill
-; CHECK-NEXT: itt eq
-; CHECK-NEXT: moveq.w r4, #-1
+; CHECK-NEXT: vmov r7, r6, d8
+; CHECK-NEXT: cmp r4, #0
+; CHECK-NEXT: str r3, [sp] @ 4-byte Spill
+; CHECK-NEXT: str r2, [sp, #20] @ 4-byte Spill
+; CHECK-NEXT: it eq
; CHECK-NEXT: moveq.w r5, #-2147483648
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: cmp r0, #0
@@ -372,49 +374,95 @@ define arm_aapcs_vfpcc <2 x i32> @test_signed_v2f64_v2i32(<2 x double> %f) {
; CHECK-NEXT: mov r1, r8
; CHECK-NEXT: mov r2, r9
; CHECK-NEXT: mov r3, r8
-; CHECK-NEXT: itt ne
+; CHECK-NEXT: it ne
; CHECK-NEXT: mvnne r5, #-2147483648
-; CHECK-NEXT: movne r4, #0
; CHECK-NEXT: bl __aeabi_dcmpun
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: itt ne
-; CHECK-NEXT: movne r4, #0
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: mov r1, r6
+; CHECK-NEXT: mov r2, r11
+; CHECK-NEXT: mov r3, r10
+; CHECK-NEXT: it ne
; CHECK-NEXT: movne r5, #0
-; CHECK-NEXT: ldr r3, [sp, #12] @ 4-byte Reload
-; CHECK-NEXT: mov r0, r11
-; CHECK-NEXT: mov r1, r10
-; CHECK-NEXT: mov r2, r7
+; CHECK-NEXT: str r5, [sp, #8] @ 4-byte Spill
; CHECK-NEXT: bl __aeabi_dcmpge
-; CHECK-NEXT: mov r8, r0
-; CHECK-NEXT: mov r0, r11
-; CHECK-NEXT: mov r1, r10
+; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: bl __aeabi_d2lz
-; CHECK-NEXT: mov r7, r0
-; CHECK-NEXT: mov r6, r1
-; CHECK-NEXT: cmp.w r8, #0
-; CHECK-NEXT: itt eq
-; CHECK-NEXT: moveq.w r7, #-2147483648
-; CHECK-NEXT: moveq.w r6, #-1
-; CHECK-NEXT: ldrd r2, r3, [sp, #4] @ 8-byte Folded Reload
-; CHECK-NEXT: mov r0, r11
-; CHECK-NEXT: mov r1, r10
+; CHECK-NEXT: mov r11, r0
+; CHECK-NEXT: cmp r4, #0
+; CHECK-NEXT: it eq
+; CHECK-NEXT: moveq.w r11, #-2147483648
+; CHECK-NEXT: ldr r5, [sp] @ 4-byte Reload
+; CHECK-NEXT: ldr r2, [sp, #20] @ 4-byte Reload
+; CHECK-NEXT: mov r10, r1
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: mov r1, r6
+; CHECK-NEXT: mov r3, r5
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: mov r0, r11
-; CHECK-NEXT: mov r1, r10
-; CHECK-NEXT: mov r2, r11
-; CHECK-NEXT: mov r3, r10
-; CHECK-NEXT: itt ne
-; CHECK-NEXT: movne r6, #0
-; CHECK-NEXT: mvnne r7, #-2147483648
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: mov r1, r6
+; CHECK-NEXT: mov r2, r7
+; CHECK-NEXT: mov r3, r6
+; CHECK-NEXT: it ne
+; CHECK-NEXT: mvnne r11, #-2147483648
; CHECK-NEXT: bl __aeabi_dcmpun
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: itt ne
-; CHECK-NEXT: movne r7, #0
-; CHECK-NEXT: movne r6, #0
-; CHECK-NEXT: vmov q0[2], q0[0], r7, r5
-; CHECK-NEXT: vmov q0[3], q0[1], r6, r4
-; CHECK-NEXT: add sp, #16
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne.w r11, #0
+; CHECK-NEXT: ldrd r2, r3, [sp, #12] @ 8-byte Folded Reload
+; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: mov r1, r8
+; CHECK-NEXT: bl __aeabi_dcmpge
+; CHECK-NEXT: ldr r4, [sp, #4] @ 4-byte Reload
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: it eq
+; CHECK-NEXT: moveq.w r4, #-1
+; CHECK-NEXT: ldr r2, [sp, #20] @ 4-byte Reload
+; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: mov r1, r8
+; CHECK-NEXT: mov r3, r5
+; CHECK-NEXT: bl __aeabi_dcmpgt
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: mov r1, r8
+; CHECK-NEXT: mov r2, r9
+; CHECK-NEXT: mov r3, r8
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne r4, #0
+; CHECK-NEXT: bl __aeabi_dcmpun
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne r4, #0
+; CHECK-NEXT: ldrd r2, r3, [sp, #12] @ 8-byte Folded Reload
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: mov r1, r6
+; CHECK-NEXT: bl __aeabi_dcmpge
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: it eq
+; CHECK-NEXT: moveq.w r10, #-1
+; CHECK-NEXT: ldr r2, [sp, #20] @ 4-byte Reload
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: mov r1, r6
+; CHECK-NEXT: mov r3, r5
+; CHECK-NEXT: bl __aeabi_dcmpgt
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: mov r1, r6
+; CHECK-NEXT: mov r2, r7
+; CHECK-NEXT: mov r3, r6
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne.w r10, #0
+; CHECK-NEXT: bl __aeabi_dcmpun
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne.w r10, #0
+; CHECK-NEXT: ldr r0, [sp, #8] @ 4-byte Reload
+; CHECK-NEXT: vmov q0[2], q0[0], r11, r0
+; CHECK-NEXT: vmov q0[3], q0[1], r10, r4
+; CHECK-NEXT: add sp, #24
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
@@ -2405,32 +2453,34 @@ define arm_aapcs_vfpcc <2 x i8> @test_signed_v2f64_v2i8(<2 x double> %f) {
; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
-; CHECK-NEXT: .pad #16
-; CHECK-NEXT: sub sp, #16
+; CHECK-NEXT: .pad #24
+; CHECK-NEXT: sub sp, #24
; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vldr d0, .LCPI33_0
; CHECK-NEXT: vmov r9, r8, d9
-; CHECK-NEXT: vmov r7, r3, d0
-; CHECK-NEXT: str r3, [sp, #12] @ 4-byte Spill
+; CHECK-NEXT: vmov r11, r10, d0
+; CHECK-NEXT: str.w r11, [sp, #12] @ 4-byte Spill
; CHECK-NEXT: mov r0, r9
; CHECK-NEXT: mov r1, r8
-; CHECK-NEXT: mov r2, r7
+; CHECK-NEXT: mov r2, r11
+; CHECK-NEXT: mov r3, r10
+; CHECK-NEXT: str.w r10, [sp, #16] @ 4-byte Spill
; CHECK-NEXT: bl __aeabi_dcmpge
-; CHECK-NEXT: mov r6, r0
+; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: mov r0, r9
; CHECK-NEXT: mov r1, r8
; CHECK-NEXT: bl __aeabi_d2lz
; CHECK-NEXT: vldr d0, .LCPI33_1
; CHECK-NEXT: mov r5, r0
-; CHECK-NEXT: mov r4, r1
+; CHECK-NEXT: str r1, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: mov r0, r9
; CHECK-NEXT: vmov r2, r3, d0
; CHECK-NEXT: mov r1, r8
-; CHECK-NEXT: vmov r11, r10, d8
-; CHECK-NEXT: cmp r6, #0
-; CHECK-NEXT: strd r2, r3, [sp, #4] @ 8-byte Folded Spill
-; CHECK-NEXT: itt eq
-; CHECK-NEXT: moveq.w r4, #-1
+; CHECK-NEXT: vmov r7, r6, d8
+; CHECK-NEXT: cmp r4, #0
+; CHECK-NEXT: str r3, [sp] @ 4-byte Spill
+; CHECK-NEXT: str r2, [sp, #20] @ 4-byte Spill
+; CHECK-NEXT: it eq
; CHECK-NEXT: mvneq r5, #127
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: cmp r0, #0
@@ -2438,49 +2488,95 @@ define arm_aapcs_vfpcc <2 x i8> @test_signed_v2f64_v2i8(<2 x double> %f) {
; CHECK-NEXT: mov r1, r8
; CHECK-NEXT: mov r2, r9
; CHECK-NEXT: mov r3, r8
-; CHECK-NEXT: itt ne
+; CHECK-NEXT: it ne
; CHECK-NEXT: movne r5, #127
-; CHECK-NEXT: movne r4, #0
; CHECK-NEXT: bl __aeabi_dcmpun
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: itt ne
-; CHECK-NEXT: movne r4, #0
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: mov r1, r6
+; CHECK-NEXT: mov r2, r11
+; CHECK-NEXT: mov r3, r10
+; CHECK-NEXT: it ne
; CHECK-NEXT: movne r5, #0
-; CHECK-NEXT: ldr r3, [sp, #12] @ 4-byte Reload
-; CHECK-NEXT: mov r0, r11
-; CHECK-NEXT: mov r1, r10
-; CHECK-NEXT: mov r2, r7
+; CHECK-NEXT: str r5, [sp, #8] @ 4-byte Spill
; CHECK-NEXT: bl __aeabi_dcmpge
-; CHECK-NEXT: mov r8, r0
-; CHECK-NEXT: mov r0, r11
-; CHECK-NEXT: mov r1, r10
+; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: bl __aeabi_d2lz
-; CHECK-NEXT: mov r7, r0
-; CHECK-NEXT: mov r6, r1
-; CHECK-NEXT: cmp.w r8, #0
-; CHECK-NEXT: itt eq
-; CHECK-NEXT: mvneq r7, #127
-; CHECK-NEXT: moveq.w r6, #-1
-; CHECK-NEXT: ldrd r2, r3, [sp, #4] @ 8-byte Folded Reload
-; CHECK-NEXT: mov r0, r11
-; CHECK-NEXT: mov r1, r10
+; CHECK-NEXT: mov r11, r0
+; CHECK-NEXT: cmp r4, #0
+; CHECK-NEXT: it eq
+; CHECK-NEXT: mvneq r11, #127
+; CHECK-NEXT: ldr r5, [sp] @ 4-byte Reload
+; CHECK-NEXT: ldr r2, [sp, #20] @ 4-byte Reload
+; CHECK-NEXT: mov r10, r1
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: mov r1, r6
+; CHECK-NEXT: mov r3, r5
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: mov r0, r11
-; CHECK-NEXT: mov r1, r10
-; CHECK-NEXT: mov r2, r11
-; CHECK-NEXT: mov r3, r10
-; CHECK-NEXT: itt ne
-; CHECK-NEXT: movne r6, #0
-; CHECK-NEXT: movne r7, #127
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: mov r1, r6
+; CHECK-NEXT: mov r2, r7
+; CHECK-NEXT: mov r3, r6
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne.w r11, #127
; CHECK-NEXT: bl __aeabi_dcmpun
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: itt ne
-; CHECK-NEXT: movne r7, #0
-; CHECK-NEXT: movne r6, #0
-; CHECK-NEXT: vmov q0[2], q0[0], r7, r5
-; CHECK-NEXT: vmov q0[3], q0[1], r6, r4
-; CHECK-NEXT: add sp, #16
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne.w r11, #0
+; CHECK-NEXT: ldrd r2, r3, [sp, #12] @ 8-byte Folded Reload
+; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: mov r1, r8
+; CHECK-NEXT: bl __aeabi_dcmpge
+; CHECK-NEXT: ldr r4, [sp, #4] @ 4-byte Reload
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: it eq
+; CHECK-NEXT: moveq.w r4, #-1
+; CHECK-NEXT: ldr r2, [sp, #20] @ 4-byte Reload
+; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: mov r1, r8
+; CHECK-NEXT: mov r3, r5
+; CHECK-NEXT: bl __aeabi_dcmpgt
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: mov r1, r8
+; CHECK-NEXT: mov r2, r9
+; CHECK-NEXT: mov r3, r8
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne r4, #0
+; CHECK-NEXT: bl __aeabi_dcmpun
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne r4, #0
+; CHECK-NEXT: ldrd r2, r3, [sp, #12] @ 8-byte Folded Reload
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: mov r1, r6
+; CHECK-NEXT: bl __aeabi_dcmpge
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: it eq
+; CHECK-NEXT: moveq.w r10, #-1
+; CHECK-NEXT: ldr r2, [sp, #20] @ 4-byte Reload
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: mov r1, r6
+; CHECK-NEXT: mov r3, r5
+; CHECK-NEXT: bl __aeabi_dcmpgt
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: mov r1, r6
+; CHECK-NEXT: mov r2, r7
+; CHECK-NEXT: mov r3, r6
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne.w r10, #0
+; CHECK-NEXT: bl __aeabi_dcmpun
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne.w r10, #0
+; CHECK-NEXT: ldr r0, [sp, #8] @ 4-byte Reload
+; CHECK-NEXT: vmov q0[2], q0[0], r11, r0
+; CHECK-NEXT: vmov q0[3], q0[1], r10, r4
+; CHECK-NEXT: add sp, #24
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
@@ -2505,84 +2601,138 @@ define arm_aapcs_vfpcc <2 x i13> @test_signed_v2f64_v2i13(<2 x double> %f) {
; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
-; CHECK-NEXT: .pad #16
-; CHECK-NEXT: sub sp, #16
+; CHECK-NEXT: .pad #24
+; CHECK-NEXT: sub sp, #24
; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vldr d0, .LCPI34_0
-; CHECK-NEXT: vmov r9, r8, d9
-; CHECK-NEXT: vmov r7, r3, d0
-; CHECK-NEXT: str r3, [sp, #12] @ 4-byte Spill
-; CHECK-NEXT: mov r0, r9
-; CHECK-NEXT: mov r1, r8
+; CHECK-NEXT: vmov r8, r9, d9
+; CHECK-NEXT: vmov r7, r4, d0
+; CHECK-NEXT: str r4, [sp, #4] @ 4-byte Spill
+; CHECK-NEXT: mov r0, r8
+; CHECK-NEXT: mov r1, r9
; CHECK-NEXT: mov r2, r7
+; CHECK-NEXT: mov r3, r4
; CHECK-NEXT: bl __aeabi_dcmpge
-; CHECK-NEXT: mov r6, r0
-; CHECK-NEXT: mov r0, r9
-; CHECK-NEXT: mov r1, r8
+; CHECK-NEXT: mov r10, r0
+; CHECK-NEXT: mov r0, r8
+; CHECK-NEXT: mov r1, r9
+; CHECK-NEXT: mov r2, r7
+; CHECK-NEXT: mov r3, r4
+; CHECK-NEXT: str r7, [sp] @ 4-byte Spill
+; CHECK-NEXT: bl __aeabi_dcmpge
+; CHECK-NEXT: mov r11, r0
+; CHECK-NEXT: mov r0, r8
+; CHECK-NEXT: mov r1, r9
; CHECK-NEXT: bl __aeabi_d2lz
; CHECK-NEXT: vldr d0, .LCPI34_1
-; CHECK-NEXT: mov r5, r0
-; CHECK-NEXT: mov r4, r1
-; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: cmp.w r11, #0
+; CHECK-NEXT: mov r6, r1
+; CHECK-NEXT: mov r1, r9
; CHECK-NEXT: vmov r2, r3, d0
-; CHECK-NEXT: mov r1, r8
-; CHECK-NEXT: vmov r11, r10, d8
-; CHECK-NEXT: cmp r6, #0
-; CHECK-NEXT: strd r2, r3, [sp, #4] @ 8-byte Folded Spill
-; CHECK-NEXT: ittt eq
-; CHECK-NEXT: movweq r5, #61440
-; CHECK-NEXT: movteq r5, #65535
-; CHECK-NEXT: moveq.w r4, #-1
+; CHECK-NEXT: vmov r5, r4, d8
+; CHECK-NEXT: str r2, [sp, #20] @ 4-byte Spill
+; CHECK-NEXT: str r3, [sp, #8] @ 4-byte Spill
+; CHECK-NEXT: itt eq
+; CHECK-NEXT: movweq r0, #61440
+; CHECK-NEXT: movteq r0, #65535
+; CHECK-NEXT: str r0, [sp, #12] @ 4-byte Spill
+; CHECK-NEXT: mov r0, r8
+; CHECK-NEXT: cmp.w r10, #0
+; CHECK-NEXT: it eq
+; CHECK-NEXT: moveq.w r6, #-1
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: mov r0, r9
-; CHECK-NEXT: mov r1, r8
-; CHECK-NEXT: mov r2, r9
-; CHECK-NEXT: mov r3, r8
-; CHECK-NEXT: itt ne
-; CHECK-NEXT: movwne r5, #4095
-; CHECK-NEXT: movne r4, #0
+; CHECK-NEXT: mov r0, r8
+; CHECK-NEXT: mov r1, r9
+; CHECK-NEXT: mov r2, r8
+; CHECK-NEXT: mov r3, r9
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne r6, #0
; CHECK-NEXT: bl __aeabi_dcmpun
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: itt ne
-; CHECK-NEXT: movne r4, #0
-; CHECK-NEXT: movne r5, #0
-; CHECK-NEXT: ldr r3, [sp, #12] @ 4-byte Reload
-; CHECK-NEXT: mov r0, r11
-; CHECK-NEXT: mov r1, r10
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne r6, #0
+; CHECK-NEXT: str r6, [sp, #16] @ 4-byte Spill
+; CHECK-NEXT: mov r0, r5
+; CHECK-NEXT: ldr r6, [sp, #4] @ 4-byte Reload
+; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: mov r2, r7
+; CHECK-NEXT: mov r3, r6
; CHECK-NEXT: bl __aeabi_dcmpge
-; CHECK-NEXT: mov r8, r0
-; CHECK-NEXT: mov r0, r11
-; CHECK-NEXT: mov r1, r10
-; CHECK-NEXT: bl __aeabi_d2lz
; CHECK-NEXT: mov r7, r0
-; CHECK-NEXT: mov r6, r1
-; CHECK-NEXT: cmp.w r8, #0
-; CHECK-NEXT: ittt eq
-; CHECK-NEXT: movweq r7, #61440
-; CHECK-NEXT: movteq r7, #65535
-; CHECK-NEXT: moveq.w r6, #-1
-; CHECK-NEXT: ldrd r2, r3, [sp, #4] @ 8-byte Folded Reload
-; CHECK-NEXT: mov r0, r11
-; CHECK-NEXT: mov r1, r10
+; CHECK-NEXT: mov r0, r5
+; CHECK-NEXT: mov r1, r4
+; CHECK-NEXT: bl __aeabi_d2lz
+; CHECK-NEXT: mov r11, r0
+; CHECK-NEXT: cmp r7, #0
+; CHECK-NEXT: itt eq
+; CHECK-NEXT: movweq r11, #61440
+; CHECK-NEXT: movteq r11, #65535
+; CHECK-NEXT: ldr r2, [sp] @ 4-byte Reload
+; CHECK-NEXT: mov r10, r1
+; CHECK-NEXT: mov r0, r5
+; CHECK-NEXT: mov r1, r4
+; CHECK-NEXT: mov r3, r6
+; CHECK-NEXT: bl __aeabi_dcmpge
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: it eq
+; CHECK-NEXT: moveq.w r10, #-1
+; CHECK-NEXT: ldr r6, [sp, #20] @ 4-byte Reload
+; CHECK-NEXT: mov r0, r5
+; CHECK-NEXT: ldr r7, [sp, #8] @ 4-byte Reload
+; CHECK-NEXT: mov r1, r4
+; CHECK-NEXT: mov r2, r6
+; CHECK-NEXT: mov r3, r7
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: mov r0, r11
-; CHECK-NEXT: mov r1, r10
-; CHECK-NEXT: mov r2, r11
-; CHECK-NEXT: mov r3, r10
-; CHECK-NEXT: itt ne
-; CHECK-NEXT: movne r6, #0
+; CHECK-NEXT: mov r0, r5
+; CHECK-NEXT: mov r1, r4
+; CHECK-NEXT: mov r2, r5
+; CHECK-NEXT: mov r3, r4
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne.w r10, #0
+; CHECK-NEXT: bl __aeabi_dcmpun
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: mov r2, r6
+; CHECK-NEXT: mov r0, r8
+; CHECK-NEXT: mov r1, r9
+; CHECK-NEXT: mov r3, r7
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne.w r10, #0
+; CHECK-NEXT: mov r6, r7
+; CHECK-NEXT: bl __aeabi_dcmpgt
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: ldr r7, [sp, #12] @ 4-byte Reload
+; CHECK-NEXT: mov r0, r8
+; CHECK-NEXT: mov r1, r9
+; CHECK-NEXT: mov r2, r8
+; CHECK-NEXT: mov r3, r9
+; CHECK-NEXT: it ne
; CHECK-NEXT: movwne r7, #4095
; CHECK-NEXT: bl __aeabi_dcmpun
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: itt ne
-; CHECK-NEXT: movne r6, #0
+; CHECK-NEXT: it ne
; CHECK-NEXT: movne r7, #0
-; CHECK-NEXT: vmov q0[2], q0[0], r7, r5
-; CHECK-NEXT: vmov q0[3], q0[1], r6, r4
-; CHECK-NEXT: add sp, #16
+; CHECK-NEXT: ldr r2, [sp, #20] @ 4-byte Reload
+; CHECK-NEXT: mov r0, r5
+; CHECK-NEXT: mov r1, r4
+; CHECK-NEXT: mov r3, r6
+; CHECK-NEXT: bl __aeabi_dcmpgt
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: mov r0, r5
+; CHECK-NEXT: mov r1, r4
+; CHECK-NEXT: mov r2, r5
+; CHECK-NEXT: mov r3, r4
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movwne r11, #4095
+; CHECK-NEXT: bl __aeabi_dcmpun
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne.w r11, #0
+; CHECK-NEXT: ldr r0, [sp, #16] @ 4-byte Reload
+; CHECK-NEXT: vmov q0[2], q0[0], r11, r7
+; CHECK-NEXT: vmov q0[3], q0[1], r10, r0
+; CHECK-NEXT: add sp, #24
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
@@ -2607,84 +2757,138 @@ define arm_aapcs_vfpcc <2 x i16> @test_signed_v2f64_v2i16(<2 x double> %f) {
; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
-; CHECK-NEXT: .pad #16
-; CHECK-NEXT: sub sp, #16
+; CHECK-NEXT: .pad #24
+; CHECK-NEXT: sub sp, #24
; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vldr d0, .LCPI35_0
-; CHECK-NEXT: vmov r9, r8, d9
-; CHECK-NEXT: vmov r7, r3, d0
-; CHECK-NEXT: str r3, [sp, #12] @ 4-byte Spill
-; CHECK-NEXT: mov r0, r9
-; CHECK-NEXT: mov r1, r8
+; CHECK-NEXT: vmov r8, r9, d9
+; CHECK-NEXT: vmov r7, r4, d0
+; CHECK-NEXT: str r4, [sp, #4] @ 4-byte Spill
+; CHECK-NEXT: mov r0, r8
+; CHECK-NEXT: mov r1, r9
; CHECK-NEXT: mov r2, r7
+; CHECK-NEXT: mov r3, r4
; CHECK-NEXT: bl __aeabi_dcmpge
-; CHECK-NEXT: mov r6, r0
-; CHECK-NEXT: mov r0, r9
-; CHECK-NEXT: mov r1, r8
+; CHECK-NEXT: mov r10, r0
+; CHECK-NEXT: mov r0, r8
+; CHECK-NEXT: mov r1, r9
+; CHECK-NEXT: mov r2, r7
+; CHECK-NEXT: mov r3, r4
+; CHECK-NEXT: str r7, [sp] @ 4-byte Spill
+; CHECK-NEXT: bl __aeabi_dcmpge
+; CHECK-NEXT: mov r11, r0
+; CHECK-NEXT: mov r0, r8
+; CHECK-NEXT: mov r1, r9
; CHECK-NEXT: bl __aeabi_d2lz
; CHECK-NEXT: vldr d0, .LCPI35_1
-; CHECK-NEXT: mov r5, r0
-; CHECK-NEXT: mov r4, r1
-; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: cmp.w r11, #0
+; CHECK-NEXT: mov r6, r1
+; CHECK-NEXT: mov r1, r9
; CHECK-NEXT: vmov r2, r3, d0
-; CHECK-NEXT: mov r1, r8
-; CHECK-NEXT: vmov r11, r10, d8
-; CHECK-NEXT: cmp r6, #0
-; CHECK-NEXT: strd r2, r3, [sp, #4] @ 8-byte Folded Spill
-; CHECK-NEXT: ittt eq
-; CHECK-NEXT: movweq r5, #32768
-; CHECK-NEXT: movteq r5, #65535
-; CHECK-NEXT: moveq.w r4, #-1
+; CHECK-NEXT: vmov r5, r4, d8
+; CHECK-NEXT: str r2, [sp, #20] @ 4-byte Spill
+; CHECK-NEXT: str r3, [sp, #8] @ 4-byte Spill
+; CHECK-NEXT: itt eq
+; CHECK-NEXT: movweq r0, #32768
+; CHECK-NEXT: movteq r0, #65535
+; CHECK-NEXT: str r0, [sp, #12] @ 4-byte Spill
+; CHECK-NEXT: mov r0, r8
+; CHECK-NEXT: cmp.w r10, #0
+; CHECK-NEXT: it eq
+; CHECK-NEXT: moveq.w r6, #-1
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: mov r0, r9
-; CHECK-NEXT: mov r1, r8
-; CHECK-NEXT: mov r2, r9
-; CHECK-NEXT: mov r3, r8
-; CHECK-NEXT: itt ne
-; CHECK-NEXT: movwne r5, #32767
-; CHECK-NEXT: movne r4, #0
+; CHECK-NEXT: mov r0, r8
+; CHECK-NEXT: mov r1, r9
+; CHECK-NEXT: mov r2, r8
+; CHECK-NEXT: mov r3, r9
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne r6, #0
; CHECK-NEXT: bl __aeabi_dcmpun
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: itt ne
-; CHECK-NEXT: movne r4, #0
-; CHECK-NEXT: movne r5, #0
-; CHECK-NEXT: ldr r3, [sp, #12] @ 4-byte Reload
-; CHECK-NEXT: mov r0, r11
-; CHECK-NEXT: mov r1, r10
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne r6, #0
+; CHECK-NEXT: str r6, [sp, #16] @ 4-byte Spill
+; CHECK-NEXT: mov r0, r5
+; CHECK-NEXT: ldr r6, [sp, #4] @ 4-byte Reload
+; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: mov r2, r7
+; CHECK-NEXT: mov r3, r6
; CHECK-NEXT: bl __aeabi_dcmpge
-; CHECK-NEXT: mov r8, r0
-; CHECK-NEXT: mov r0, r11
-; CHECK-NEXT: mov r1, r10
-; CHECK-NEXT: bl __aeabi_d2lz
; CHECK-NEXT: mov r7, r0
-; CHECK-NEXT: mov r6, r1
-; CHECK-NEXT: cmp.w r8, #0
-; CHECK-NEXT: ittt eq
-; CHECK-NEXT: movweq r7, #32768
-; CHECK-NEXT: movteq r7, #65535
-; CHECK-NEXT: moveq.w r6, #-1
-; CHECK-NEXT: ldrd r2, r3, [sp, #4] @ 8-byte Folded Reload
-; CHECK-NEXT: mov r0, r11
-; CHECK-NEXT: mov r1, r10
+; CHECK-NEXT: mov r0, r5
+; CHECK-NEXT: mov r1, r4
+; CHECK-NEXT: bl __aeabi_d2lz
+; CHECK-NEXT: mov r11, r0
+; CHECK-NEXT: cmp r7, #0
+; CHECK-NEXT: itt eq
+; CHECK-NEXT: movweq r11, #32768
+; CHECK-NEXT: movteq r11, #65535
+; CHECK-NEXT: ldr r2, [sp] @ 4-byte Reload
+; CHECK-NEXT: mov r10, r1
+; CHECK-NEXT: mov r0, r5
+; CHECK-NEXT: mov r1, r4
+; CHECK-NEXT: mov r3, r6
+; CHECK-NEXT: bl __aeabi_dcmpge
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: it eq
+; CHECK-NEXT: moveq.w r10, #-1
+; CHECK-NEXT: ldr r6, [sp, #20] @ 4-byte Reload
+; CHECK-NEXT: mov r0, r5
+; CHECK-NEXT: ldr r7, [sp, #8] @ 4-byte Reload
+; CHECK-NEXT: mov r1, r4
+; CHECK-NEXT: mov r2, r6
+; CHECK-NEXT: mov r3, r7
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: mov r0, r11
-; CHECK-NEXT: mov r1, r10
-; CHECK-NEXT: mov r2, r11
-; CHECK-NEXT: mov r3, r10
-; CHECK-NEXT: itt ne
-; CHECK-NEXT: movne r6, #0
+; CHECK-NEXT: mov r0, r5
+; CHECK-NEXT: mov r1, r4
+; CHECK-NEXT: mov r2, r5
+; CHECK-NEXT: mov r3, r4
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne.w r10, #0
+; CHECK-NEXT: bl __aeabi_dcmpun
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: mov r2, r6
+; CHECK-NEXT: mov r0, r8
+; CHECK-NEXT: mov r1, r9
+; CHECK-NEXT: mov r3, r7
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne.w r10, #0
+; CHECK-NEXT: mov r6, r7
+; CHECK-NEXT: bl __aeabi_dcmpgt
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: ldr r7, [sp, #12] @ 4-byte Reload
+; CHECK-NEXT: mov r0, r8
+; CHECK-NEXT: mov r1, r9
+; CHECK-NEXT: mov r2, r8
+; CHECK-NEXT: mov r3, r9
+; CHECK-NEXT: it ne
; CHECK-NEXT: movwne r7, #32767
; CHECK-NEXT: bl __aeabi_dcmpun
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: itt ne
-; CHECK-NEXT: movne r6, #0
+; CHECK-NEXT: it ne
; CHECK-NEXT: movne r7, #0
-; CHECK-NEXT: vmov q0[2], q0[0], r7, r5
-; CHECK-NEXT: vmov q0[3], q0[1], r6, r4
-; CHECK-NEXT: add sp, #16
+; CHECK-NEXT: ldr r2, [sp, #20] @ 4-byte Reload
+; CHECK-NEXT: mov r0, r5
+; CHECK-NEXT: mov r1, r4
+; CHECK-NEXT: mov r3, r6
+; CHECK-NEXT: bl __aeabi_dcmpgt
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: mov r0, r5
+; CHECK-NEXT: mov r1, r4
+; CHECK-NEXT: mov r2, r5
+; CHECK-NEXT: mov r3, r4
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movwne r11, #32767
+; CHECK-NEXT: bl __aeabi_dcmpun
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne.w r11, #0
+; CHECK-NEXT: ldr r0, [sp, #16] @ 4-byte Reload
+; CHECK-NEXT: vmov q0[2], q0[0], r11, r7
+; CHECK-NEXT: vmov q0[3], q0[1], r10, r0
+; CHECK-NEXT: add sp, #24
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
@@ -2709,94 +2913,144 @@ define arm_aapcs_vfpcc <2 x i19> @test_signed_v2f64_v2i19(<2 x double> %f) {
; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
-; CHECK-NEXT: .pad #24
-; CHECK-NEXT: sub sp, #24
+; CHECK-NEXT: .pad #40
+; CHECK-NEXT: sub sp, #40
; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vldr d0, .LCPI36_0
-; CHECK-NEXT: vmov r5, r4, d9
-; CHECK-NEXT: vmov r7, r6, d0
-; CHECK-NEXT: mov r0, r5
-; CHECK-NEXT: mov r1, r4
-; CHECK-NEXT: mov r2, r7
-; CHECK-NEXT: mov r3, r6
-; CHECK-NEXT: strd r5, r4, [sp, #12] @ 8-byte Folded Spill
+; CHECK-NEXT: vmov r4, r7, d9
+; CHECK-NEXT: vmov r11, r3, d0
+; CHECK-NEXT: str.w r11, [sp, #12] @ 4-byte Spill
+; CHECK-NEXT: mov r0, r4
+; CHECK-NEXT: mov r1, r7
+; CHECK-NEXT: mov r2, r11
+; CHECK-NEXT: mov r8, r3
; CHECK-NEXT: bl __aeabi_dcmpge
-; CHECK-NEXT: str r0, [sp, #4] @ 4-byte Spill
-; CHECK-NEXT: mov r0, r5
-; CHECK-NEXT: mov r1, r4
+; CHECK-NEXT: mov r10, r0
+; CHECK-NEXT: mov r0, r4
+; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: bl __aeabi_d2lz
; CHECK-NEXT: vldr d0, .LCPI36_1
-; CHECK-NEXT: mov r8, r0
-; CHECK-NEXT: vmov r11, r5, d8
-; CHECK-NEXT: mov r9, r1
-; CHECK-NEXT: vmov r10, r0, d0
-; CHECK-NEXT: mov r2, r7
-; CHECK-NEXT: mov r3, r6
+; CHECK-NEXT: mov r6, r1
; CHECK-NEXT: str r0, [sp, #20] @ 4-byte Spill
-; CHECK-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
-; CHECK-NEXT: mov r1, r5
+; CHECK-NEXT: mov r0, r4
+; CHECK-NEXT: vmov r2, r3, d0
+; CHECK-NEXT: mov r1, r7
+; CHECK-NEXT: vmov r5, r9, d8
+; CHECK-NEXT: cmp.w r10, #0
+; CHECK-NEXT: strd r2, r3, [sp, #32] @ 8-byte Folded Spill
+; CHECK-NEXT: it eq
+; CHECK-NEXT: moveq.w r6, #-1
+; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: mov r0, r11
-; CHECK-NEXT: ittt eq
-; CHECK-NEXT: movweq r8, #0
-; CHECK-NEXT: movteq r8, #65532
-; CHECK-NEXT: moveq.w r9, #-1
+; CHECK-NEXT: mov r0, r4
+; CHECK-NEXT: mov r1, r7
+; CHECK-NEXT: mov r2, r4
+; CHECK-NEXT: mov r3, r7
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne r6, #0
+; CHECK-NEXT: str r7, [sp, #16] @ 4-byte Spill
+; CHECK-NEXT: bl __aeabi_dcmpun
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: mov r0, r5
+; CHECK-NEXT: mov r1, r9
+; CHECK-NEXT: mov r2, r11
+; CHECK-NEXT: mov r3, r8
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne r6, #0
+; CHECK-NEXT: str r6, [sp, #24] @ 4-byte Spill
+; CHECK-NEXT: str.w r8, [sp, #28] @ 4-byte Spill
; CHECK-NEXT: bl __aeabi_dcmpge
-; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: mov r0, r11
-; CHECK-NEXT: mov r1, r5
-; CHECK-NEXT: str r5, [sp, #8] @ 4-byte Spill
+; CHECK-NEXT: mov r8, r0
+; CHECK-NEXT: mov r0, r5
+; CHECK-NEXT: mov r1, r9
; CHECK-NEXT: bl __aeabi_d2lz
-; CHECK-NEXT: mov r7, r0
-; CHECK-NEXT: mov r6, r1
-; CHECK-NEXT: cmp r4, #0
-; CHECK-NEXT: ittt eq
-; CHECK-NEXT: moveq r7, #0
-; CHECK-NEXT: movteq r7, #65532
-; CHECK-NEXT: moveq.w r6, #-1
-; CHECK-NEXT: ldr r3, [sp, #20] @ 4-byte Reload
-; CHECK-NEXT: mov r0, r11
-; CHECK-NEXT: mov r1, r5
-; CHECK-NEXT: mov r2, r10
+; CHECK-NEXT: mov r10, r1
+; CHECK-NEXT: cmp.w r8, #0
+; CHECK-NEXT: it eq
+; CHECK-NEXT: moveq.w r10, #-1
+; CHECK-NEXT: ldr r6, [sp, #32] @ 4-byte Reload
+; CHECK-NEXT: ldr r3, [sp, #36] @ 4-byte Reload
+; CHECK-NEXT: mov r11, r0
+; CHECK-NEXT: mov r0, r5
+; CHECK-NEXT: mov r1, r9
+; CHECK-NEXT: mov r2, r6
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: ittt ne
-; CHECK-NEXT: movne r6, #0
-; CHECK-NEXT: movwne r7, #65535
-; CHECK-NEXT: movtne r7, #3
-; CHECK-NEXT: ldr r5, [sp, #12] @ 4-byte Reload
-; CHECK-NEXT: mov r2, r10
-; CHECK-NEXT: ldr r4, [sp, #16] @ 4-byte Reload
-; CHECK-NEXT: ldr r3, [sp, #20] @ 4-byte Reload
; CHECK-NEXT: mov r0, r5
-; CHECK-NEXT: mov r1, r4
+; CHECK-NEXT: mov r1, r9
+; CHECK-NEXT: mov r2, r5
+; CHECK-NEXT: mov r3, r9
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne.w r10, #0
+; CHECK-NEXT: str.w r9, [sp, #4] @ 4-byte Spill
+; CHECK-NEXT: bl __aeabi_dcmpun
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne.w r10, #0
+; CHECK-NEXT: ldr r7, [sp, #16] @ 4-byte Reload
+; CHECK-NEXT: mov r0, r4
+; CHECK-NEXT: ldr.w r9, [sp, #12] @ 4-byte Reload
+; CHECK-NEXT: ldr r3, [sp, #28] @ 4-byte Reload
+; CHECK-NEXT: mov r1, r7
+; CHECK-NEXT: str r4, [sp, #8] @ 4-byte Spill
+; CHECK-NEXT: mov r2, r9
+; CHECK-NEXT: bl __aeabi_dcmpge
+; CHECK-NEXT: ldr.w r8, [sp, #20] @ 4-byte Reload
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: itt eq
+; CHECK-NEXT: movweq r8, #0
+; CHECK-NEXT: movteq r8, #65532
+; CHECK-NEXT: mov r2, r6
+; CHECK-NEXT: ldr r6, [sp, #36] @ 4-byte Reload
+; CHECK-NEXT: mov r0, r4
+; CHECK-NEXT: mov r1, r7
+; CHECK-NEXT: mov r3, r6
; CHECK-NEXT: bl __aeabi_dcmpgt
+; CHECK-NEXT: ldr r4, [sp, #4] @ 4-byte Reload
+; CHECK-NEXT: mov r2, r9
+; CHECK-NEXT: ldr r3, [sp, #28] @ 4-byte Reload
+; CHECK-NEXT: str r0, [sp, #20] @ 4-byte Spill
+; CHECK-NEXT: mov r0, r5
+; CHECK-NEXT: mov r1, r4
+; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: itt eq
+; CHECK-NEXT: movweq r11, #0
+; CHECK-NEXT: movteq r11, #65532
+; CHECK-NEXT: ldr r2, [sp, #32] @ 4-byte Reload
; CHECK-NEXT: mov r0, r5
; CHECK-NEXT: mov r1, r4
-; CHECK-NEXT: mov r2, r5
-; CHECK-NEXT: mov r3, r4
-; CHECK-NEXT: ittt ne
-; CHECK-NEXT: movne.w r9, #0
+; CHECK-NEXT: mov r3, r6
+; CHECK-NEXT: bl __aeabi_dcmpgt
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: itt ne
+; CHECK-NEXT: movwne r11, #65535
+; CHECK-NEXT: movtne r11, #3
+; CHECK-NEXT: ldr r0, [sp, #20] @ 4-byte Reload
+; CHECK-NEXT: mov r1, r7
+; CHECK-NEXT: mov r3, r7
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: itt ne
; CHECK-NEXT: movwne r8, #65535
; CHECK-NEXT: movtne r8, #3
+; CHECK-NEXT: ldr r0, [sp, #8] @ 4-byte Reload
+; CHECK-NEXT: mov r2, r0
; CHECK-NEXT: bl __aeabi_dcmpun
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: itt ne
-; CHECK-NEXT: movne.w r9, #0
+; CHECK-NEXT: mov r0, r5
+; CHECK-NEXT: mov r1, r4
+; CHECK-NEXT: mov r2, r5
+; CHECK-NEXT: mov r3, r4
+; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r8, #0
-; CHECK-NEXT: ldr r1, [sp, #8] @ 4-byte Reload
-; CHECK-NEXT: mov r0, r11
-; CHECK-NEXT: mov r2, r11
-; CHECK-NEXT: mov r3, r1
; CHECK-NEXT: bl __aeabi_dcmpun
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: itt ne
-; CHECK-NEXT: movne r6, #0
-; CHECK-NEXT: movne r7, #0
-; CHECK-NEXT: vmov q0[2], q0[0], r7, r8
-; CHECK-NEXT: vmov q0[3], q0[1], r6, r9
-; CHECK-NEXT: add sp, #24
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne.w r11, #0
+; CHECK-NEXT: ldr r0, [sp, #24] @ 4-byte Reload
+; CHECK-NEXT: vmov q0[2], q0[0], r11, r8
+; CHECK-NEXT: vmov q0[3], q0[1], r10, r0
+; CHECK-NEXT: add sp, #40
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
@@ -2821,32 +3075,34 @@ define arm_aapcs_vfpcc <2 x i32> @test_signed_v2f64_v2i32_duplicate(<2 x double>
; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
-; CHECK-NEXT: .pad #16
-; CHECK-NEXT: sub sp, #16
+; CHECK-NEXT: .pad #24
+; CHECK-NEXT: sub sp, #24
; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vldr d0, .LCPI37_0
; CHECK-NEXT: vmov r9, r8, d9
-; CHECK-NEXT: vmov r7, r3, d0
-; CHECK-NEXT: str r3, [sp, #12] @ 4-byte Spill
+; CHECK-NEXT: vmov r11, r10, d0
+; CHECK-NEXT: str.w r11, [sp, #12] @ 4-byte Spill
; CHECK-NEXT: mov r0, r9
; CHECK-NEXT: mov r1, r8
-; CHECK-NEXT: mov r2, r7
+; CHECK-NEXT: mov r2, r11
+; CHECK-NEXT: mov r3, r10
+; CHECK-NEXT: str.w r10, [sp, #16] @ 4-byte Spill
; CHECK-NEXT: bl __aeabi_dcmpge
-; CHECK-NEXT: mov r6, r0
+; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: mov r0, r9
; CHECK-NEXT: mov r1, r8
; CHECK-NEXT: bl __aeabi_d2lz
; CHECK-NEXT: vldr d0, .LCPI37_1
; CHECK-NEXT: mov r5, r0
-; CHECK-NEXT: mov r4, r1
+; CHECK-NEXT: str r1, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: mov r0, r9
; CHECK-NEXT: vmov r2, r3, d0
; CHECK-NEXT: mov r1, r8
-; CHECK-NEXT: vmov r11, r10, d8
-; CHECK-NEXT: cmp r6, #0
-; CHECK-NEXT: strd r2, r3, [sp, #4] @ 8-byte Folded Spill
-; CHECK-NEXT: itt eq
-; CHECK-NEXT: moveq.w r4, #-1
+; CHECK-NEXT: vmov r7, r6, d8
+; CHECK-NEXT: cmp r4, #0
+; CHECK-NEXT: str r3, [sp] @ 4-byte Spill
+; CHECK-NEXT: str r2, [sp, #20] @ 4-byte Spill
+; CHECK-NEXT: it eq
; CHECK-NEXT: moveq.w r5, #-2147483648
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: cmp r0, #0
@@ -2854,49 +3110,95 @@ define arm_aapcs_vfpcc <2 x i32> @test_signed_v2f64_v2i32_duplicate(<2 x double>
; CHECK-NEXT: mov r1, r8
; CHECK-NEXT: mov r2, r9
; CHECK-NEXT: mov r3, r8
-; CHECK-NEXT: itt ne
+; CHECK-NEXT: it ne
; CHECK-NEXT: mvnne r5, #-2147483648
-; CHECK-NEXT: movne r4, #0
; CHECK-NEXT: bl __aeabi_dcmpun
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: itt ne
-; CHECK-NEXT: movne r4, #0
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: mov r1, r6
+; CHECK-NEXT: mov r2, r11
+; CHECK-NEXT: mov r3, r10
+; CHECK-NEXT: it ne
; CHECK-NEXT: movne r5, #0
-; CHECK-NEXT: ldr r3, [sp, #12] @ 4-byte Reload
-; CHECK-NEXT: mov r0, r11
-; CHECK-NEXT: mov r1, r10
-; CHECK-NEXT: mov r2, r7
+; CHECK-NEXT: str r5, [sp, #8] @ 4-byte Spill
; CHECK-NEXT: bl __aeabi_dcmpge
-; CHECK-NEXT: mov r8, r0
-; CHECK-NEXT: mov r0, r11
-; CHECK-NEXT: mov r1, r10
+; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: bl __aeabi_d2lz
-; CHECK-NEXT: mov r7, r0
-; CHECK-NEXT: mov r6, r1
-; CHECK-NEXT: cmp.w r8, #0
-; CHECK-NEXT: itt eq
-; CHECK-NEXT: moveq.w r7, #-2147483648
-; CHECK-NEXT: moveq.w r6, #-1
-; CHECK-NEXT: ldrd r2, r3, [sp, #4] @ 8-byte Folded Reload
-; CHECK-NEXT: mov r0, r11
-; CHECK-NEXT: mov r1, r10
+; CHECK-NEXT: mov r11, r0
+; CHECK-NEXT: cmp r4, #0
+; CHECK-NEXT: it eq
+; CHECK-NEXT: moveq.w r11, #-2147483648
+; CHECK-NEXT: ldr r5, [sp] @ 4-byte Reload
+; CHECK-NEXT: ldr r2, [sp, #20] @ 4-byte Reload
+; CHECK-NEXT: mov r10, r1
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: mov r1, r6
+; CHECK-NEXT: mov r3, r5
+; CHECK-NEXT: bl __aeabi_dcmpgt
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: mov r1, r6
+; CHECK-NEXT: mov r2, r7
+; CHECK-NEXT: mov r3, r6
+; CHECK-NEXT: it ne
+; CHECK-NEXT: mvnne r11, #-2147483648
+; CHECK-NEXT: bl __aeabi_dcmpun
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne.w r11, #0
+; CHECK-NEXT: ldrd r2, r3, [sp, #12] @ 8-byte Folded Reload
+; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: mov r1, r8
+; CHECK-NEXT: bl __aeabi_dcmpge
+; CHECK-NEXT: ldr r4, [sp, #4] @ 4-byte Reload
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: it eq
+; CHECK-NEXT: moveq.w r4, #-1
+; CHECK-NEXT: ldr r2, [sp, #20] @ 4-byte Reload
+; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: mov r1, r8
+; CHECK-NEXT: mov r3, r5
+; CHECK-NEXT: bl __aeabi_dcmpgt
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: mov r1, r8
+; CHECK-NEXT: mov r2, r9
+; CHECK-NEXT: mov r3, r8
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne r4, #0
+; CHECK-NEXT: bl __aeabi_dcmpun
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne r4, #0
+; CHECK-NEXT: ldrd r2, r3, [sp, #12] @ 8-byte Folded Reload
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: mov r1, r6
+; CHECK-NEXT: bl __aeabi_dcmpge
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: it eq
+; CHECK-NEXT: moveq.w r10, #-1
+; CHECK-NEXT: ldr r2, [sp, #20] @ 4-byte Reload
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: mov r1, r6
+; CHECK-NEXT: mov r3, r5
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: mov r0, r11
-; CHECK-NEXT: mov r1, r10
-; CHECK-NEXT: mov r2, r11
-; CHECK-NEXT: mov r3, r10
-; CHECK-NEXT: itt ne
-; CHECK-NEXT: movne r6, #0
-; CHECK-NEXT: mvnne r7, #-2147483648
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: mov r1, r6
+; CHECK-NEXT: mov r2, r7
+; CHECK-NEXT: mov r3, r6
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne.w r10, #0
; CHECK-NEXT: bl __aeabi_dcmpun
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: itt ne
-; CHECK-NEXT: movne r7, #0
-; CHECK-NEXT: movne r6, #0
-; CHECK-NEXT: vmov q0[2], q0[0], r7, r5
-; CHECK-NEXT: vmov q0[3], q0[1], r6, r4
-; CHECK-NEXT: add sp, #16
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne.w r10, #0
+; CHECK-NEXT: ldr r0, [sp, #8] @ 4-byte Reload
+; CHECK-NEXT: vmov q0[2], q0[0], r11, r0
+; CHECK-NEXT: vmov q0[3], q0[1], r10, r4
+; CHECK-NEXT: add sp, #24
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
@@ -2921,89 +3223,145 @@ define arm_aapcs_vfpcc <2 x i50> @test_signed_v2f64_v2i50(<2 x double> %f) {
; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
-; CHECK-NEXT: .pad #16
-; CHECK-NEXT: sub sp, #16
+; CHECK-NEXT: .pad #40
+; CHECK-NEXT: sub sp, #40
; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vldr d0, .LCPI38_0
-; CHECK-NEXT: vmov r5, r4, d9
-; CHECK-NEXT: vmov r6, r7, d0
-; CHECK-NEXT: mov r0, r5
-; CHECK-NEXT: mov r1, r4
-; CHECK-NEXT: mov r2, r6
-; CHECK-NEXT: mov r3, r7
-; CHECK-NEXT: strd r4, r5, [sp, #8] @ 8-byte Folded Spill
+; CHECK-NEXT: vmov r7, r6, d9
+; CHECK-NEXT: vmov r9, r8, d0
+; CHECK-NEXT: str.w r8, [sp, #16] @ 4-byte Spill
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: mov r1, r6
+; CHECK-NEXT: mov r2, r9
+; CHECK-NEXT: mov r3, r8
; CHECK-NEXT: bl __aeabi_dcmpge
-; CHECK-NEXT: mov r11, r0
-; CHECK-NEXT: mov r0, r5
-; CHECK-NEXT: mov r1, r4
+; CHECK-NEXT: mov r5, r0
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: bl __aeabi_d2lz
-; CHECK-NEXT: vmov r5, r10, d8
; CHECK-NEXT: vldr d0, .LCPI38_1
-; CHECK-NEXT: cmp.w r11, #0
-; CHECK-NEXT: mov r4, r1
-; CHECK-NEXT: vmov r9, r8, d0
-; CHECK-NEXT: csel r11, r0, r11, ne
-; CHECK-NEXT: mov r2, r6
-; CHECK-NEXT: mov r3, r7
-; CHECK-NEXT: mov r0, r5
-; CHECK-NEXT: mov r1, r10
-; CHECK-NEXT: str.w r9, [sp, #4] @ 4-byte Spill
-; CHECK-NEXT: itt eq
-; CHECK-NEXT: moveq r4, #0
-; CHECK-NEXT: movteq r4, #65534
+; CHECK-NEXT: cmp r5, #0
+; CHECK-NEXT: str r1, [sp, #28] @ 4-byte Spill
+; CHECK-NEXT: csel r5, r0, r5, ne
+; CHECK-NEXT: vmov r2, r3, d0
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: mov r1, r6
+; CHECK-NEXT: vmov r4, r11, d8
+; CHECK-NEXT: str r2, [sp, #12] @ 4-byte Spill
+; CHECK-NEXT: str r3, [sp, #36] @ 4-byte Spill
+; CHECK-NEXT: bl __aeabi_dcmpgt
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: mov r1, r6
+; CHECK-NEXT: mov r2, r7
+; CHECK-NEXT: mov r3, r6
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne.w r5, #-1
+; CHECK-NEXT: str r6, [sp, #20] @ 4-byte Spill
+; CHECK-NEXT: bl __aeabi_dcmpun
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: mov r0, r4
+; CHECK-NEXT: mov r1, r11
+; CHECK-NEXT: mov r2, r9
+; CHECK-NEXT: mov r3, r8
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne r5, #0
+; CHECK-NEXT: str r5, [sp, #32] @ 4-byte Spill
+; CHECK-NEXT: str.w r9, [sp] @ 4-byte Spill
; CHECK-NEXT: bl __aeabi_dcmpge
-; CHECK-NEXT: mov r7, r0
-; CHECK-NEXT: mov r0, r5
-; CHECK-NEXT: mov r1, r10
+; CHECK-NEXT: mov r5, r0
+; CHECK-NEXT: mov r0, r4
+; CHECK-NEXT: mov r1, r11
; CHECK-NEXT: bl __aeabi_d2lz
-; CHECK-NEXT: cmp r7, #0
-; CHECK-NEXT: mov r6, r1
-; CHECK-NEXT: csel r7, r0, r7, ne
-; CHECK-NEXT: mov r0, r5
-; CHECK-NEXT: mov r1, r10
+; CHECK-NEXT: ldr.w r8, [sp, #12] @ 4-byte Reload
+; CHECK-NEXT: cmp r5, #0
+; CHECK-NEXT: ldr r3, [sp, #36] @ 4-byte Reload
+; CHECK-NEXT: mov r10, r1
+; CHECK-NEXT: csel r5, r0, r5, ne
+; CHECK-NEXT: mov r0, r4
+; CHECK-NEXT: mov r1, r11
+; CHECK-NEXT: mov r2, r8
+; CHECK-NEXT: bl __aeabi_dcmpgt
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: mov r0, r4
+; CHECK-NEXT: mov r1, r11
+; CHECK-NEXT: mov r2, r4
+; CHECK-NEXT: mov r3, r11
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne.w r5, #-1
+; CHECK-NEXT: str.w r11, [sp, #4] @ 4-byte Spill
+; CHECK-NEXT: bl __aeabi_dcmpun
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne r5, #0
+; CHECK-NEXT: ldr r6, [sp, #20] @ 4-byte Reload
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: ldr.w r11, [sp, #16] @ 4-byte Reload
; CHECK-NEXT: mov r2, r9
-; CHECK-NEXT: mov r3, r8
+; CHECK-NEXT: str r5, [sp, #24] @ 4-byte Spill
+; CHECK-NEXT: mov r1, r6
+; CHECK-NEXT: str r7, [sp, #8] @ 4-byte Spill
+; CHECK-NEXT: mov r3, r11
+; CHECK-NEXT: bl __aeabi_dcmpge
+; CHECK-NEXT: ldr r5, [sp, #28] @ 4-byte Reload
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: itt eq
-; CHECK-NEXT: moveq r6, #0
-; CHECK-NEXT: movteq r6, #65534
+; CHECK-NEXT: moveq r5, #0
+; CHECK-NEXT: movteq r5, #65534
+; CHECK-NEXT: ldr.w r9, [sp, #36] @ 4-byte Reload
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: mov r1, r6
+; CHECK-NEXT: mov r2, r8
+; CHECK-NEXT: mov r7, r6
+; CHECK-NEXT: mov r3, r9
; CHECK-NEXT: bl __aeabi_dcmpgt
+; CHECK-NEXT: ldr r6, [sp, #4] @ 4-byte Reload
+; CHECK-NEXT: mov r3, r11
+; CHECK-NEXT: ldr r2, [sp] @ 4-byte Reload
+; CHECK-NEXT: str r0, [sp, #28] @ 4-byte Spill
+; CHECK-NEXT: mov r0, r4
+; CHECK-NEXT: mov r1, r6
+; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: ittt ne
-; CHECK-NEXT: movne.w r7, #-1
-; CHECK-NEXT: movwne r6, #65535
-; CHECK-NEXT: movtne r6, #1
-; CHECK-NEXT: ldrd r9, r0, [sp, #8] @ 8-byte Folded Reload
-; CHECK-NEXT: mov r3, r8
-; CHECK-NEXT: ldr r2, [sp, #4] @ 4-byte Reload
-; CHECK-NEXT: mov r1, r9
+; CHECK-NEXT: mov r0, r4
+; CHECK-NEXT: mov r1, r6
+; CHECK-NEXT: mov r2, r8
+; CHECK-NEXT: mov r3, r9
+; CHECK-NEXT: itt eq
+; CHECK-NEXT: movweq r10, #0
+; CHECK-NEXT: movteq r10, #65534
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: ittt ne
-; CHECK-NEXT: movne.w r11, #-1
-; CHECK-NEXT: movwne r4, #65535
-; CHECK-NEXT: movtne r4, #1
-; CHECK-NEXT: ldr r0, [sp, #12] @ 4-byte Reload
-; CHECK-NEXT: mov r1, r9
-; CHECK-NEXT: mov r3, r9
-; CHECK-NEXT: mov r2, r0
-; CHECK-NEXT: bl __aeabi_dcmpun
+; CHECK-NEXT: itt ne
+; CHECK-NEXT: movwne r10, #65535
+; CHECK-NEXT: movtne r10, #1
+; CHECK-NEXT: ldr r0, [sp, #28] @ 4-byte Reload
+; CHECK-NEXT: mov r1, r7
+; CHECK-NEXT: mov r3, r7
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: mov r0, r5
-; CHECK-NEXT: mov r1, r10
-; CHECK-NEXT: mov r2, r5
-; CHECK-NEXT: mov r3, r10
; CHECK-NEXT: itt ne
-; CHECK-NEXT: movne.w r11, #0
-; CHECK-NEXT: movne r4, #0
+; CHECK-NEXT: movwne r5, #65535
+; CHECK-NEXT: movtne r5, #1
+; CHECK-NEXT: ldr r0, [sp, #8] @ 4-byte Reload
+; CHECK-NEXT: mov r2, r0
; CHECK-NEXT: bl __aeabi_dcmpun
; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: ldr r0, [sp, #32] @ 4-byte Reload
+; CHECK-NEXT: ldr r1, [sp, #24] @ 4-byte Reload
+; CHECK-NEXT: mov r2, r4
+; CHECK-NEXT: mov r3, r6
; CHECK-NEXT: it ne
-; CHECK-NEXT: movne r7, #0
-; CHECK-NEXT: vmov q0[2], q0[0], r7, r11
+; CHECK-NEXT: movne r5, #0
+; CHECK-NEXT: vmov q4[2], q4[0], r1, r0
+; CHECK-NEXT: mov r0, r4
+; CHECK-NEXT: mov r1, r6
+; CHECK-NEXT: bl __aeabi_dcmpun
+; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne
-; CHECK-NEXT: movne r6, #0
-; CHECK-NEXT: vmov q0[3], q0[1], r6, r4
-; CHECK-NEXT: add sp, #16
+; CHECK-NEXT: movne.w r10, #0
+; CHECK-NEXT: vmov q4[3], q4[1], r10, r5
+; CHECK-NEXT: vmov q0, q4
+; CHECK-NEXT: add sp, #40
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
@@ -3028,80 +3386,132 @@ define arm_aapcs_vfpcc <2 x i64> @test_signed_v2f64_v2i64(<2 x double> %f) {
; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
-; CHECK-NEXT: .pad #8
-; CHECK-NEXT: sub sp, #8
+; CHECK-NEXT: .pad #32
+; CHECK-NEXT: sub sp, #32
; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vldr d0, .LCPI39_0
; CHECK-NEXT: vmov r8, r7, d9
; CHECK-NEXT: vmov r11, r5, d0
+; CHECK-NEXT: str r5, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: mov r2, r11
; CHECK-NEXT: mov r3, r5
; CHECK-NEXT: bl __aeabi_dcmpge
-; CHECK-NEXT: mov r9, r0
+; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: bl __aeabi_d2lz
; CHECK-NEXT: vldr d0, .LCPI39_1
-; CHECK-NEXT: cmp.w r9, #0
-; CHECK-NEXT: mov r4, r1
-; CHECK-NEXT: csel r9, r0, r9, ne
+; CHECK-NEXT: cmp r4, #0
+; CHECK-NEXT: str r1, [sp, #16] @ 4-byte Spill
+; CHECK-NEXT: csel r4, r0, r4, ne
; CHECK-NEXT: vmov r2, r3, d0
; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: vmov r6, r10, d8
-; CHECK-NEXT: strd r2, r3, [sp] @ 8-byte Folded Spill
-; CHECK-NEXT: it eq
-; CHECK-NEXT: moveq.w r4, #-2147483648
+; CHECK-NEXT: strd r2, r3, [sp, #24] @ 8-byte Folded Spill
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: mov r2, r8
; CHECK-NEXT: mov r3, r7
-; CHECK-NEXT: itt ne
-; CHECK-NEXT: movne.w r9, #-1
-; CHECK-NEXT: mvnne r4, #-2147483648
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne.w r4, #-1
; CHECK-NEXT: bl __aeabi_dcmpun
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov r0, r6
; CHECK-NEXT: mov r1, r10
; CHECK-NEXT: mov r2, r11
; CHECK-NEXT: mov r3, r5
-; CHECK-NEXT: itt ne
+; CHECK-NEXT: it ne
; CHECK-NEXT: movne r4, #0
-; CHECK-NEXT: movne.w r9, #0
+; CHECK-NEXT: str r4, [sp, #20] @ 4-byte Spill
+; CHECK-NEXT: str.w r11, [sp] @ 4-byte Spill
; CHECK-NEXT: bl __aeabi_dcmpge
-; CHECK-NEXT: mov r5, r0
+; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: mov r0, r6
; CHECK-NEXT: mov r1, r10
; CHECK-NEXT: bl __aeabi_d2lz
-; CHECK-NEXT: mov r7, r1
-; CHECK-NEXT: cmp r5, #0
-; CHECK-NEXT: it eq
-; CHECK-NEXT: moveq.w r7, #-2147483648
-; CHECK-NEXT: ldrd r2, r3, [sp] @ 8-byte Folded Reload
-; CHECK-NEXT: csel r5, r0, r5, ne
+; CHECK-NEXT: cmp r4, #0
+; CHECK-NEXT: mov r9, r1
+; CHECK-NEXT: csel r5, r0, r4, ne
+; CHECK-NEXT: ldrd r2, r4, [sp, #24] @ 8-byte Folded Reload
; CHECK-NEXT: mov r0, r6
; CHECK-NEXT: mov r1, r10
+; CHECK-NEXT: mov r3, r4
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov r0, r6
; CHECK-NEXT: mov r1, r10
; CHECK-NEXT: mov r2, r6
; CHECK-NEXT: mov r3, r10
-; CHECK-NEXT: itt ne
-; CHECK-NEXT: mvnne r7, #-2147483648
+; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r5, #-1
+; CHECK-NEXT: str.w r10, [sp, #8] @ 4-byte Spill
; CHECK-NEXT: bl __aeabi_dcmpun
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: itt ne
+; CHECK-NEXT: it ne
; CHECK-NEXT: movne r5, #0
-; CHECK-NEXT: movne r7, #0
-; CHECK-NEXT: vmov q0[2], q0[0], r5, r9
-; CHECK-NEXT: vmov q0[3], q0[1], r7, r4
-; CHECK-NEXT: add sp, #8
+; CHECK-NEXT: mov r2, r11
+; CHECK-NEXT: ldr.w r11, [sp, #4] @ 4-byte Reload
+; CHECK-NEXT: mov r0, r8
+; CHECK-NEXT: mov r1, r7
+; CHECK-NEXT: str r5, [sp, #12] @ 4-byte Spill
+; CHECK-NEXT: mov r3, r11
+; CHECK-NEXT: bl __aeabi_dcmpge
+; CHECK-NEXT: ldr.w r10, [sp, #16] @ 4-byte Reload
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: it eq
+; CHECK-NEXT: moveq.w r10, #-2147483648
+; CHECK-NEXT: ldr r5, [sp, #24] @ 4-byte Reload
+; CHECK-NEXT: mov r0, r8
+; CHECK-NEXT: mov r1, r7
+; CHECK-NEXT: mov r3, r4
+; CHECK-NEXT: mov r2, r5
+; CHECK-NEXT: bl __aeabi_dcmpgt
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: mov r0, r8
+; CHECK-NEXT: mov r1, r7
+; CHECK-NEXT: mov r2, r8
+; CHECK-NEXT: mov r3, r7
+; CHECK-NEXT: it ne
+; CHECK-NEXT: mvnne r10, #-2147483648
+; CHECK-NEXT: bl __aeabi_dcmpun
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne.w r10, #0
+; CHECK-NEXT: ldr r4, [sp, #8] @ 4-byte Reload
+; CHECK-NEXT: mov r0, r6
+; CHECK-NEXT: ldr r2, [sp] @ 4-byte Reload
+; CHECK-NEXT: mov r3, r11
+; CHECK-NEXT: mov r1, r4
+; CHECK-NEXT: bl __aeabi_dcmpge
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: it eq
+; CHECK-NEXT: moveq.w r9, #-2147483648
+; CHECK-NEXT: ldr r3, [sp, #28] @ 4-byte Reload
+; CHECK-NEXT: mov r0, r6
+; CHECK-NEXT: mov r1, r4
+; CHECK-NEXT: mov r2, r5
+; CHECK-NEXT: bl __aeabi_dcmpgt
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: mov r0, r6
+; CHECK-NEXT: mov r1, r4
+; CHECK-NEXT: mov r2, r6
+; CHECK-NEXT: mov r3, r4
+; CHECK-NEXT: it ne
+; CHECK-NEXT: mvnne r9, #-2147483648
+; CHECK-NEXT: bl __aeabi_dcmpun
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne.w r9, #0
+; CHECK-NEXT: ldr r0, [sp, #20] @ 4-byte Reload
+; CHECK-NEXT: ldr r1, [sp, #12] @ 4-byte Reload
+; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
+; CHECK-NEXT: vmov q0[3], q0[1], r9, r10
+; CHECK-NEXT: add sp, #32
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
diff --git a/llvm/test/CodeGen/Thumb2/mve-fptoui-sat-vector.ll b/llvm/test/CodeGen/Thumb2/mve-fptoui-sat-vector.ll
index 1a22270ea0ebe..2cd7ed2ea9f93 100644
--- a/llvm/test/CodeGen/Thumb2/mve-fptoui-sat-vector.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-fptoui-sat-vector.ll
@@ -313,60 +313,102 @@ define arm_aapcs_vfpcc <2 x i32> @test_unsigned_v2f64_v2i32(<2 x double> %f) {
; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
-; CHECK-NEXT: .pad #8
-; CHECK-NEXT: sub sp, #8
+; CHECK-NEXT: .pad #32
+; CHECK-NEXT: sub sp, #32
; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vldr d0, .LCPI9_0
-; CHECK-NEXT: vmov r6, r7, d9
-; CHECK-NEXT: vmov r11, r3, d0
-; CHECK-NEXT: str r3, [sp, #4] @ 4-byte Spill
-; CHECK-NEXT: mov r0, r6
-; CHECK-NEXT: mov r1, r7
-; CHECK-NEXT: mov r2, r11
+; CHECK-NEXT: vmov r9, r10, d9
+; CHECK-NEXT: vmov r6, r3, d0
+; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: mov r1, r10
+; CHECK-NEXT: mov r2, r6
+; CHECK-NEXT: mov r7, r3
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: mov r8, r0
-; CHECK-NEXT: mov r0, r6
-; CHECK-NEXT: mov r1, r7
+; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: mov r1, r10
; CHECK-NEXT: bl __aeabi_d2ulz
; CHECK-NEXT: vldr d0, .LCPI9_1
; CHECK-NEXT: cmp.w r8, #0
-; CHECK-NEXT: csel r9, r0, r8, ne
-; CHECK-NEXT: csel r8, r1, r8, ne
-; CHECK-NEXT: vmov r10, r3, d0
-; CHECK-NEXT: mov r0, r6
-; CHECK-NEXT: mov r1, r7
-; CHECK-NEXT: vmov r5, r4, d8
-; CHECK-NEXT: str r3, [sp] @ 4-byte Spill
-; CHECK-NEXT: mov r2, r10
+; CHECK-NEXT: str r1, [sp, #20] @ 4-byte Spill
+; CHECK-NEXT: csel r4, r0, r8, ne
+; CHECK-NEXT: vmov r2, r3, d0
+; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: mov r1, r10
+; CHECK-NEXT: vmov r11, r5, d8
+; CHECK-NEXT: str r2, [sp, #4] @ 4-byte Spill
+; CHECK-NEXT: str r3, [sp, #28] @ 4-byte Spill
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: itt ne
+; CHECK-NEXT: mov r0, r11
+; CHECK-NEXT: mov r1, r5
+; CHECK-NEXT: mov r2, r6
+; CHECK-NEXT: mov r3, r7
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne.w r4, #-1
+; CHECK-NEXT: str r4, [sp, #24] @ 4-byte Spill
+; CHECK-NEXT: mov r8, r7
+; CHECK-NEXT: str r5, [sp, #8] @ 4-byte Spill
+; CHECK-NEXT: str r6, [sp] @ 4-byte Spill
+; CHECK-NEXT: bl __aeabi_dcmpge
+; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: mov r0, r11
+; CHECK-NEXT: mov r1, r5
+; CHECK-NEXT: bl __aeabi_d2ulz
+; CHECK-NEXT: cmp r4, #0
+; CHECK-NEXT: ldr r3, [sp, #28] @ 4-byte Reload
+; CHECK-NEXT: csel r7, r0, r4, ne
+; CHECK-NEXT: ldr r4, [sp, #4] @ 4-byte Reload
+; CHECK-NEXT: str r1, [sp, #16] @ 4-byte Spill
+; CHECK-NEXT: mov r0, r11
+; CHECK-NEXT: mov r1, r5
+; CHECK-NEXT: mov r2, r4
+; CHECK-NEXT: bl __aeabi_dcmpgt
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: mov r1, r10
+; CHECK-NEXT: mov r2, r6
+; CHECK-NEXT: mov r3, r8
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne.w r7, #-1
+; CHECK-NEXT: str r7, [sp, #12] @ 4-byte Spill
+; CHECK-NEXT: mov r5, r8
+; CHECK-NEXT: bl __aeabi_dcmpge
+; CHECK-NEXT: ldr r7, [sp, #28] @ 4-byte Reload
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: ldr r1, [sp, #20] @ 4-byte Reload
+; CHECK-NEXT: mov r2, r4
+; CHECK-NEXT: mov r6, r4
+; CHECK-NEXT: csel r8, r1, r0, ne
+; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: mov r1, r10
+; CHECK-NEXT: mov r3, r7
+; CHECK-NEXT: bl __aeabi_dcmpgt
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r8, #0
-; CHECK-NEXT: movne.w r9, #-1
-; CHECK-NEXT: ldr r3, [sp, #4] @ 4-byte Reload
-; CHECK-NEXT: mov r0, r5
+; CHECK-NEXT: ldr r4, [sp, #8] @ 4-byte Reload
+; CHECK-NEXT: mov r0, r11
+; CHECK-NEXT: ldr r2, [sp] @ 4-byte Reload
+; CHECK-NEXT: mov r3, r5
; CHECK-NEXT: mov r1, r4
-; CHECK-NEXT: mov r2, r11
; CHECK-NEXT: bl __aeabi_dcmpge
-; CHECK-NEXT: mov r6, r0
-; CHECK-NEXT: mov r0, r5
-; CHECK-NEXT: mov r1, r4
-; CHECK-NEXT: bl __aeabi_d2ulz
-; CHECK-NEXT: ldr r3, [sp] @ 4-byte Reload
-; CHECK-NEXT: cmp r6, #0
-; CHECK-NEXT: csel r7, r1, r6, ne
-; CHECK-NEXT: csel r6, r0, r6, ne
-; CHECK-NEXT: mov r0, r5
+; CHECK-NEXT: ldr r1, [sp, #16] @ 4-byte Reload
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: mov r2, r6
+; CHECK-NEXT: mov r3, r7
+; CHECK-NEXT: csel r5, r1, r0, ne
+; CHECK-NEXT: mov r0, r11
; CHECK-NEXT: mov r1, r4
-; CHECK-NEXT: mov r2, r10
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: itt ne
-; CHECK-NEXT: movne.w r6, #-1
-; CHECK-NEXT: movne r7, #0
-; CHECK-NEXT: vmov q0[2], q0[0], r6, r9
-; CHECK-NEXT: vmov q0[3], q0[1], r7, r8
-; CHECK-NEXT: add sp, #8
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne r5, #0
+; CHECK-NEXT: ldr r0, [sp, #24] @ 4-byte Reload
+; CHECK-NEXT: ldr r1, [sp, #12] @ 4-byte Reload
+; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
+; CHECK-NEXT: vmov q0[3], q0[1], r5, r8
+; CHECK-NEXT: add sp, #32
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
@@ -2023,60 +2065,102 @@ define arm_aapcs_vfpcc <2 x i8> @test_unsigned_v2f64_v2i8(<2 x double> %f) {
; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
-; CHECK-NEXT: .pad #8
-; CHECK-NEXT: sub sp, #8
+; CHECK-NEXT: .pad #32
+; CHECK-NEXT: sub sp, #32
; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vldr d0, .LCPI33_0
-; CHECK-NEXT: vmov r6, r7, d9
-; CHECK-NEXT: vmov r11, r3, d0
-; CHECK-NEXT: str r3, [sp, #4] @ 4-byte Spill
-; CHECK-NEXT: mov r0, r6
-; CHECK-NEXT: mov r1, r7
-; CHECK-NEXT: mov r2, r11
+; CHECK-NEXT: vmov r9, r10, d9
+; CHECK-NEXT: vmov r6, r3, d0
+; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: mov r1, r10
+; CHECK-NEXT: mov r2, r6
+; CHECK-NEXT: mov r7, r3
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: mov r8, r0
-; CHECK-NEXT: mov r0, r6
-; CHECK-NEXT: mov r1, r7
+; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: mov r1, r10
; CHECK-NEXT: bl __aeabi_d2ulz
; CHECK-NEXT: vldr d0, .LCPI33_1
; CHECK-NEXT: cmp.w r8, #0
-; CHECK-NEXT: csel r9, r0, r8, ne
-; CHECK-NEXT: csel r8, r1, r8, ne
-; CHECK-NEXT: vmov r10, r3, d0
-; CHECK-NEXT: mov r0, r6
-; CHECK-NEXT: mov r1, r7
-; CHECK-NEXT: vmov r5, r4, d8
-; CHECK-NEXT: str r3, [sp] @ 4-byte Spill
-; CHECK-NEXT: mov r2, r10
+; CHECK-NEXT: str r1, [sp, #20] @ 4-byte Spill
+; CHECK-NEXT: csel r4, r0, r8, ne
+; CHECK-NEXT: vmov r2, r3, d0
+; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: mov r1, r10
+; CHECK-NEXT: vmov r11, r5, d8
+; CHECK-NEXT: str r2, [sp, #4] @ 4-byte Spill
+; CHECK-NEXT: str r3, [sp, #28] @ 4-byte Spill
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: itt ne
+; CHECK-NEXT: mov r0, r11
+; CHECK-NEXT: mov r1, r5
+; CHECK-NEXT: mov r2, r6
+; CHECK-NEXT: mov r3, r7
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne r4, #255
+; CHECK-NEXT: str r4, [sp, #24] @ 4-byte Spill
+; CHECK-NEXT: mov r8, r7
+; CHECK-NEXT: str r5, [sp, #8] @ 4-byte Spill
+; CHECK-NEXT: str r6, [sp] @ 4-byte Spill
+; CHECK-NEXT: bl __aeabi_dcmpge
+; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: mov r0, r11
+; CHECK-NEXT: mov r1, r5
+; CHECK-NEXT: bl __aeabi_d2ulz
+; CHECK-NEXT: cmp r4, #0
+; CHECK-NEXT: ldr r3, [sp, #28] @ 4-byte Reload
+; CHECK-NEXT: csel r7, r0, r4, ne
+; CHECK-NEXT: ldr r4, [sp, #4] @ 4-byte Reload
+; CHECK-NEXT: str r1, [sp, #16] @ 4-byte Spill
+; CHECK-NEXT: mov r0, r11
+; CHECK-NEXT: mov r1, r5
+; CHECK-NEXT: mov r2, r4
+; CHECK-NEXT: bl __aeabi_dcmpgt
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: mov r1, r10
+; CHECK-NEXT: mov r2, r6
+; CHECK-NEXT: mov r3, r8
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne r7, #255
+; CHECK-NEXT: str r7, [sp, #12] @ 4-byte Spill
+; CHECK-NEXT: mov r5, r8
+; CHECK-NEXT: bl __aeabi_dcmpge
+; CHECK-NEXT: ldr r7, [sp, #28] @ 4-byte Reload
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: ldr r1, [sp, #20] @ 4-byte Reload
+; CHECK-NEXT: mov r2, r4
+; CHECK-NEXT: mov r6, r4
+; CHECK-NEXT: csel r8, r1, r0, ne
+; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: mov r1, r10
+; CHECK-NEXT: mov r3, r7
+; CHECK-NEXT: bl __aeabi_dcmpgt
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r8, #0
-; CHECK-NEXT: movne.w r9, #255
-; CHECK-NEXT: ldr r3, [sp, #4] @ 4-byte Reload
-; CHECK-NEXT: mov r0, r5
+; CHECK-NEXT: ldr r4, [sp, #8] @ 4-byte Reload
+; CHECK-NEXT: mov r0, r11
+; CHECK-NEXT: ldr r2, [sp] @ 4-byte Reload
+; CHECK-NEXT: mov r3, r5
; CHECK-NEXT: mov r1, r4
-; CHECK-NEXT: mov r2, r11
; CHECK-NEXT: bl __aeabi_dcmpge
-; CHECK-NEXT: mov r6, r0
-; CHECK-NEXT: mov r0, r5
-; CHECK-NEXT: mov r1, r4
-; CHECK-NEXT: bl __aeabi_d2ulz
-; CHECK-NEXT: ldr r3, [sp] @ 4-byte Reload
-; CHECK-NEXT: cmp r6, #0
-; CHECK-NEXT: csel r7, r1, r6, ne
-; CHECK-NEXT: csel r6, r0, r6, ne
-; CHECK-NEXT: mov r0, r5
+; CHECK-NEXT: ldr r1, [sp, #16] @ 4-byte Reload
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: mov r2, r6
+; CHECK-NEXT: mov r3, r7
+; CHECK-NEXT: csel r5, r1, r0, ne
+; CHECK-NEXT: mov r0, r11
; CHECK-NEXT: mov r1, r4
-; CHECK-NEXT: mov r2, r10
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: itt ne
-; CHECK-NEXT: movne r6, #255
-; CHECK-NEXT: movne r7, #0
-; CHECK-NEXT: vmov q0[2], q0[0], r6, r9
-; CHECK-NEXT: vmov q0[3], q0[1], r7, r8
-; CHECK-NEXT: add sp, #8
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne r5, #0
+; CHECK-NEXT: ldr r0, [sp, #24] @ 4-byte Reload
+; CHECK-NEXT: ldr r1, [sp, #12] @ 4-byte Reload
+; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
+; CHECK-NEXT: vmov q0[3], q0[1], r5, r8
+; CHECK-NEXT: add sp, #32
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
@@ -2101,60 +2185,102 @@ define arm_aapcs_vfpcc <2 x i13> @test_unsigned_v2f64_v2i13(<2 x double> %f) {
; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
-; CHECK-NEXT: .pad #8
-; CHECK-NEXT: sub sp, #8
+; CHECK-NEXT: .pad #32
+; CHECK-NEXT: sub sp, #32
; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vldr d0, .LCPI34_0
-; CHECK-NEXT: vmov r6, r7, d9
-; CHECK-NEXT: vmov r11, r3, d0
-; CHECK-NEXT: str r3, [sp, #4] @ 4-byte Spill
-; CHECK-NEXT: mov r0, r6
-; CHECK-NEXT: mov r1, r7
-; CHECK-NEXT: mov r2, r11
+; CHECK-NEXT: vmov r9, r10, d9
+; CHECK-NEXT: vmov r6, r3, d0
+; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: mov r1, r10
+; CHECK-NEXT: mov r2, r6
+; CHECK-NEXT: mov r7, r3
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: mov r8, r0
-; CHECK-NEXT: mov r0, r6
-; CHECK-NEXT: mov r1, r7
+; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: mov r1, r10
; CHECK-NEXT: bl __aeabi_d2ulz
; CHECK-NEXT: vldr d0, .LCPI34_1
; CHECK-NEXT: cmp.w r8, #0
-; CHECK-NEXT: csel r9, r0, r8, ne
-; CHECK-NEXT: csel r8, r1, r8, ne
-; CHECK-NEXT: vmov r10, r3, d0
-; CHECK-NEXT: mov r0, r6
-; CHECK-NEXT: mov r1, r7
-; CHECK-NEXT: vmov r5, r4, d8
-; CHECK-NEXT: str r3, [sp] @ 4-byte Spill
-; CHECK-NEXT: mov r2, r10
+; CHECK-NEXT: str r1, [sp, #20] @ 4-byte Spill
+; CHECK-NEXT: csel r4, r0, r8, ne
+; CHECK-NEXT: vmov r2, r3, d0
+; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: mov r1, r10
+; CHECK-NEXT: vmov r11, r5, d8
+; CHECK-NEXT: str r2, [sp, #4] @ 4-byte Spill
+; CHECK-NEXT: str r3, [sp, #28] @ 4-byte Spill
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: itt ne
+; CHECK-NEXT: mov r0, r11
+; CHECK-NEXT: mov r1, r5
+; CHECK-NEXT: mov r2, r6
+; CHECK-NEXT: mov r3, r7
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movwne r4, #8191
+; CHECK-NEXT: str r4, [sp, #24] @ 4-byte Spill
+; CHECK-NEXT: mov r8, r7
+; CHECK-NEXT: str r5, [sp, #8] @ 4-byte Spill
+; CHECK-NEXT: str r6, [sp] @ 4-byte Spill
+; CHECK-NEXT: bl __aeabi_dcmpge
+; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: mov r0, r11
+; CHECK-NEXT: mov r1, r5
+; CHECK-NEXT: bl __aeabi_d2ulz
+; CHECK-NEXT: cmp r4, #0
+; CHECK-NEXT: ldr r3, [sp, #28] @ 4-byte Reload
+; CHECK-NEXT: csel r7, r0, r4, ne
+; CHECK-NEXT: ldr r4, [sp, #4] @ 4-byte Reload
+; CHECK-NEXT: str r1, [sp, #16] @ 4-byte Spill
+; CHECK-NEXT: mov r0, r11
+; CHECK-NEXT: mov r1, r5
+; CHECK-NEXT: mov r2, r4
+; CHECK-NEXT: bl __aeabi_dcmpgt
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: mov r1, r10
+; CHECK-NEXT: mov r2, r6
+; CHECK-NEXT: mov r3, r8
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movwne r7, #8191
+; CHECK-NEXT: str r7, [sp, #12] @ 4-byte Spill
+; CHECK-NEXT: mov r5, r8
+; CHECK-NEXT: bl __aeabi_dcmpge
+; CHECK-NEXT: ldr r7, [sp, #28] @ 4-byte Reload
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: ldr r1, [sp, #20] @ 4-byte Reload
+; CHECK-NEXT: mov r2, r4
+; CHECK-NEXT: mov r6, r4
+; CHECK-NEXT: csel r8, r1, r0, ne
+; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: mov r1, r10
+; CHECK-NEXT: mov r3, r7
+; CHECK-NEXT: bl __aeabi_dcmpgt
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r8, #0
-; CHECK-NEXT: movwne r9, #8191
-; CHECK-NEXT: ldr r3, [sp, #4] @ 4-byte Reload
-; CHECK-NEXT: mov r0, r5
+; CHECK-NEXT: ldr r4, [sp, #8] @ 4-byte Reload
+; CHECK-NEXT: mov r0, r11
+; CHECK-NEXT: ldr r2, [sp] @ 4-byte Reload
+; CHECK-NEXT: mov r3, r5
; CHECK-NEXT: mov r1, r4
-; CHECK-NEXT: mov r2, r11
; CHECK-NEXT: bl __aeabi_dcmpge
-; CHECK-NEXT: mov r6, r0
-; CHECK-NEXT: mov r0, r5
-; CHECK-NEXT: mov r1, r4
-; CHECK-NEXT: bl __aeabi_d2ulz
-; CHECK-NEXT: ldr r3, [sp] @ 4-byte Reload
-; CHECK-NEXT: cmp r6, #0
-; CHECK-NEXT: csel r7, r1, r6, ne
-; CHECK-NEXT: csel r6, r0, r6, ne
-; CHECK-NEXT: mov r0, r5
+; CHECK-NEXT: ldr r1, [sp, #16] @ 4-byte Reload
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: mov r2, r6
+; CHECK-NEXT: mov r3, r7
+; CHECK-NEXT: csel r5, r1, r0, ne
+; CHECK-NEXT: mov r0, r11
; CHECK-NEXT: mov r1, r4
-; CHECK-NEXT: mov r2, r10
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: itt ne
-; CHECK-NEXT: movwne r6, #8191
-; CHECK-NEXT: movne r7, #0
-; CHECK-NEXT: vmov q0[2], q0[0], r6, r9
-; CHECK-NEXT: vmov q0[3], q0[1], r7, r8
-; CHECK-NEXT: add sp, #8
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne r5, #0
+; CHECK-NEXT: ldr r0, [sp, #24] @ 4-byte Reload
+; CHECK-NEXT: ldr r1, [sp, #12] @ 4-byte Reload
+; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
+; CHECK-NEXT: vmov q0[3], q0[1], r5, r8
+; CHECK-NEXT: add sp, #32
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
@@ -2179,60 +2305,102 @@ define arm_aapcs_vfpcc <2 x i16> @test_unsigned_v2f64_v2i16(<2 x double> %f) {
; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
-; CHECK-NEXT: .pad #8
-; CHECK-NEXT: sub sp, #8
+; CHECK-NEXT: .pad #32
+; CHECK-NEXT: sub sp, #32
; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vldr d0, .LCPI35_0
-; CHECK-NEXT: vmov r6, r7, d9
-; CHECK-NEXT: vmov r11, r3, d0
-; CHECK-NEXT: str r3, [sp, #4] @ 4-byte Spill
-; CHECK-NEXT: mov r0, r6
-; CHECK-NEXT: mov r1, r7
-; CHECK-NEXT: mov r2, r11
+; CHECK-NEXT: vmov r9, r10, d9
+; CHECK-NEXT: vmov r6, r3, d0
+; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: mov r1, r10
+; CHECK-NEXT: mov r2, r6
+; CHECK-NEXT: mov r7, r3
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: mov r8, r0
-; CHECK-NEXT: mov r0, r6
-; CHECK-NEXT: mov r1, r7
+; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: mov r1, r10
; CHECK-NEXT: bl __aeabi_d2ulz
; CHECK-NEXT: vldr d0, .LCPI35_1
; CHECK-NEXT: cmp.w r8, #0
-; CHECK-NEXT: csel r9, r0, r8, ne
-; CHECK-NEXT: csel r8, r1, r8, ne
-; CHECK-NEXT: vmov r10, r3, d0
-; CHECK-NEXT: mov r0, r6
-; CHECK-NEXT: mov r1, r7
-; CHECK-NEXT: vmov r5, r4, d8
-; CHECK-NEXT: str r3, [sp] @ 4-byte Spill
-; CHECK-NEXT: mov r2, r10
+; CHECK-NEXT: str r1, [sp, #20] @ 4-byte Spill
+; CHECK-NEXT: csel r4, r0, r8, ne
+; CHECK-NEXT: vmov r2, r3, d0
+; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: mov r1, r10
+; CHECK-NEXT: vmov r11, r5, d8
+; CHECK-NEXT: str r2, [sp, #4] @ 4-byte Spill
+; CHECK-NEXT: str r3, [sp, #28] @ 4-byte Spill
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: itt ne
+; CHECK-NEXT: mov r0, r11
+; CHECK-NEXT: mov r1, r5
+; CHECK-NEXT: mov r2, r6
+; CHECK-NEXT: mov r3, r7
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movwne r4, #65535
+; CHECK-NEXT: str r4, [sp, #24] @ 4-byte Spill
+; CHECK-NEXT: mov r8, r7
+; CHECK-NEXT: str r5, [sp, #8] @ 4-byte Spill
+; CHECK-NEXT: str r6, [sp] @ 4-byte Spill
+; CHECK-NEXT: bl __aeabi_dcmpge
+; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: mov r0, r11
+; CHECK-NEXT: mov r1, r5
+; CHECK-NEXT: bl __aeabi_d2ulz
+; CHECK-NEXT: cmp r4, #0
+; CHECK-NEXT: ldr r3, [sp, #28] @ 4-byte Reload
+; CHECK-NEXT: csel r7, r0, r4, ne
+; CHECK-NEXT: ldr r4, [sp, #4] @ 4-byte Reload
+; CHECK-NEXT: str r1, [sp, #16] @ 4-byte Spill
+; CHECK-NEXT: mov r0, r11
+; CHECK-NEXT: mov r1, r5
+; CHECK-NEXT: mov r2, r4
+; CHECK-NEXT: bl __aeabi_dcmpgt
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: mov r1, r10
+; CHECK-NEXT: mov r2, r6
+; CHECK-NEXT: mov r3, r8
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movwne r7, #65535
+; CHECK-NEXT: str r7, [sp, #12] @ 4-byte Spill
+; CHECK-NEXT: mov r5, r8
+; CHECK-NEXT: bl __aeabi_dcmpge
+; CHECK-NEXT: ldr r7, [sp, #28] @ 4-byte Reload
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: ldr r1, [sp, #20] @ 4-byte Reload
+; CHECK-NEXT: mov r2, r4
+; CHECK-NEXT: mov r6, r4
+; CHECK-NEXT: csel r8, r1, r0, ne
+; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: mov r1, r10
+; CHECK-NEXT: mov r3, r7
+; CHECK-NEXT: bl __aeabi_dcmpgt
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r8, #0
-; CHECK-NEXT: movwne r9, #65535
-; CHECK-NEXT: ldr r3, [sp, #4] @ 4-byte Reload
-; CHECK-NEXT: mov r0, r5
+; CHECK-NEXT: ldr r4, [sp, #8] @ 4-byte Reload
+; CHECK-NEXT: mov r0, r11
+; CHECK-NEXT: ldr r2, [sp] @ 4-byte Reload
+; CHECK-NEXT: mov r3, r5
; CHECK-NEXT: mov r1, r4
-; CHECK-NEXT: mov r2, r11
; CHECK-NEXT: bl __aeabi_dcmpge
-; CHECK-NEXT: mov r6, r0
-; CHECK-NEXT: mov r0, r5
-; CHECK-NEXT: mov r1, r4
-; CHECK-NEXT: bl __aeabi_d2ulz
-; CHECK-NEXT: ldr r3, [sp] @ 4-byte Reload
-; CHECK-NEXT: cmp r6, #0
-; CHECK-NEXT: csel r7, r1, r6, ne
-; CHECK-NEXT: csel r6, r0, r6, ne
-; CHECK-NEXT: mov r0, r5
+; CHECK-NEXT: ldr r1, [sp, #16] @ 4-byte Reload
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: mov r2, r6
+; CHECK-NEXT: mov r3, r7
+; CHECK-NEXT: csel r5, r1, r0, ne
+; CHECK-NEXT: mov r0, r11
; CHECK-NEXT: mov r1, r4
-; CHECK-NEXT: mov r2, r10
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: itt ne
-; CHECK-NEXT: movwne r6, #65535
-; CHECK-NEXT: movne r7, #0
-; CHECK-NEXT: vmov q0[2], q0[0], r6, r9
-; CHECK-NEXT: vmov q0[3], q0[1], r7, r8
-; CHECK-NEXT: add sp, #8
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne r5, #0
+; CHECK-NEXT: ldr r0, [sp, #24] @ 4-byte Reload
+; CHECK-NEXT: ldr r1, [sp, #12] @ 4-byte Reload
+; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
+; CHECK-NEXT: vmov q0[3], q0[1], r5, r8
+; CHECK-NEXT: add sp, #32
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
@@ -2257,66 +2425,98 @@ define arm_aapcs_vfpcc <2 x i19> @test_unsigned_v2f64_v2i19(<2 x double> %f) {
; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
-; CHECK-NEXT: .pad #16
-; CHECK-NEXT: sub sp, #16
+; CHECK-NEXT: .pad #24
+; CHECK-NEXT: sub sp, #24
; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vldr d0, .LCPI36_0
-; CHECK-NEXT: vmov r11, r5, d8
-; CHECK-NEXT: vmov r6, r7, d0
-; CHECK-NEXT: str r5, [sp, #12] @ 4-byte Spill
-; CHECK-NEXT: mov r0, r11
-; CHECK-NEXT: mov r1, r5
-; CHECK-NEXT: mov r2, r6
-; CHECK-NEXT: mov r3, r7
+; CHECK-NEXT: vmov r10, r11, d9
+; CHECK-NEXT: vmov r9, r5, d0
+; CHECK-NEXT: mov r0, r10
+; CHECK-NEXT: mov r1, r11
+; CHECK-NEXT: mov r2, r9
+; CHECK-NEXT: mov r3, r5
; CHECK-NEXT: bl __aeabi_dcmpge
-; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: mov r0, r11
-; CHECK-NEXT: mov r1, r5
+; CHECK-NEXT: mov r8, r0
+; CHECK-NEXT: mov r0, r10
+; CHECK-NEXT: mov r1, r11
; CHECK-NEXT: bl __aeabi_d2ulz
; CHECK-NEXT: vldr d0, .LCPI36_1
-; CHECK-NEXT: vmov r5, r8, d9
-; CHECK-NEXT: cmp r4, #0
-; CHECK-NEXT: vmov r3, r2, d0
-; CHECK-NEXT: csel r9, r1, r4, ne
-; CHECK-NEXT: csel r10, r0, r4, ne
-; CHECK-NEXT: mov r0, r5
-; CHECK-NEXT: mov r1, r8
+; CHECK-NEXT: cmp.w r8, #0
+; CHECK-NEXT: str r0, [sp, #16] @ 4-byte Spill
+; CHECK-NEXT: csel r4, r1, r8, ne
+; CHECK-NEXT: vmov r2, r3, d0
+; CHECK-NEXT: mov r0, r10
+; CHECK-NEXT: mov r1, r11
+; CHECK-NEXT: vmov r7, r6, d8
; CHECK-NEXT: strd r3, r2, [sp, #4] @ 8-byte Folded Spill
-; CHECK-NEXT: mov r2, r6
-; CHECK-NEXT: mov r3, r7
+; CHECK-NEXT: bl __aeabi_dcmpgt
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: mov r1, r6
+; CHECK-NEXT: mov r2, r9
+; CHECK-NEXT: mov r3, r5
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne r4, #0
+; CHECK-NEXT: str r4, [sp, #20] @ 4-byte Spill
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: mov r0, r5
-; CHECK-NEXT: mov r1, r8
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: bl __aeabi_d2ulz
; CHECK-NEXT: cmp r4, #0
-; CHECK-NEXT: ldr r7, [sp, #4] @ 4-byte Reload
-; CHECK-NEXT: csel r6, r0, r4, ne
-; CHECK-NEXT: mov r0, r5
-; CHECK-NEXT: ldr r5, [sp, #8] @ 4-byte Reload
-; CHECK-NEXT: csel r4, r1, r4, ne
-; CHECK-NEXT: mov r1, r8
-; CHECK-NEXT: mov r2, r7
+; CHECK-NEXT: mov r8, r0
+; CHECK-NEXT: csel r0, r1, r4, ne
+; CHECK-NEXT: mov r1, r6
+; CHECK-NEXT: str r0, [sp, #12] @ 4-byte Spill
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: mov r2, r9
; CHECK-NEXT: mov r3, r5
-; CHECK-NEXT: bl __aeabi_dcmpgt
+; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: ittt ne
-; CHECK-NEXT: movne r4, #0
-; CHECK-NEXT: movwne r6, #65535
-; CHECK-NEXT: movtne r6, #7
-; CHECK-NEXT: ldr r1, [sp, #12] @ 4-byte Reload
-; CHECK-NEXT: mov r0, r11
-; CHECK-NEXT: mov r2, r7
+; CHECK-NEXT: mov r1, r11
+; CHECK-NEXT: csel r8, r8, r0, ne
+; CHECK-NEXT: mov r0, r10
+; CHECK-NEXT: mov r2, r9
; CHECK-NEXT: mov r3, r5
+; CHECK-NEXT: bl __aeabi_dcmpge
+; CHECK-NEXT: ldr.w r9, [sp, #8] @ 4-byte Reload
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: ldr r4, [sp, #4] @ 4-byte Reload
+; CHECK-NEXT: ldr r1, [sp, #16] @ 4-byte Reload
+; CHECK-NEXT: mov r2, r9
+; CHECK-NEXT: csel r5, r1, r0, ne
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: mov r1, r6
+; CHECK-NEXT: mov r3, r4
+; CHECK-NEXT: bl __aeabi_dcmpgt
+; CHECK-NEXT: str r0, [sp, #16] @ 4-byte Spill
+; CHECK-NEXT: mov r0, r10
+; CHECK-NEXT: mov r1, r11
+; CHECK-NEXT: mov r2, r9
+; CHECK-NEXT: mov r3, r4
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: ittt ne
-; CHECK-NEXT: movwne r10, #65535
-; CHECK-NEXT: movtne r10, #7
-; CHECK-NEXT: movne.w r9, #0
-; CHECK-NEXT: vmov q0[2], q0[0], r10, r6
-; CHECK-NEXT: vmov q0[3], q0[1], r9, r4
-; CHECK-NEXT: add sp, #16
+; CHECK-NEXT: itt ne
+; CHECK-NEXT: movwne r5, #65535
+; CHECK-NEXT: movtne r5, #7
+; CHECK-NEXT: ldr r0, [sp, #16] @ 4-byte Reload
+; CHECK-NEXT: mov r1, r6
+; CHECK-NEXT: mov r2, r9
+; CHECK-NEXT: mov r3, r4
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: itt ne
+; CHECK-NEXT: movwne r8, #65535
+; CHECK-NEXT: movtne r8, #7
+; CHECK-NEXT: bl __aeabi_dcmpgt
+; CHECK-NEXT: ldr r1, [sp, #12] @ 4-byte Reload
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne r1, #0
+; CHECK-NEXT: ldr r0, [sp, #20] @ 4-byte Reload
+; CHECK-NEXT: vmov q0[2], q0[0], r8, r5
+; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
+; CHECK-NEXT: add sp, #24
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
@@ -2341,60 +2541,102 @@ define arm_aapcs_vfpcc <2 x i32> @test_unsigned_v2f64_v2i32_duplicate(<2 x doubl
; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
-; CHECK-NEXT: .pad #8
-; CHECK-NEXT: sub sp, #8
+; CHECK-NEXT: .pad #32
+; CHECK-NEXT: sub sp, #32
; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vldr d0, .LCPI37_0
-; CHECK-NEXT: vmov r6, r7, d9
-; CHECK-NEXT: vmov r11, r3, d0
-; CHECK-NEXT: str r3, [sp, #4] @ 4-byte Spill
-; CHECK-NEXT: mov r0, r6
-; CHECK-NEXT: mov r1, r7
-; CHECK-NEXT: mov r2, r11
+; CHECK-NEXT: vmov r9, r10, d9
+; CHECK-NEXT: vmov r6, r3, d0
+; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: mov r1, r10
+; CHECK-NEXT: mov r2, r6
+; CHECK-NEXT: mov r7, r3
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: mov r8, r0
-; CHECK-NEXT: mov r0, r6
-; CHECK-NEXT: mov r1, r7
+; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: mov r1, r10
; CHECK-NEXT: bl __aeabi_d2ulz
; CHECK-NEXT: vldr d0, .LCPI37_1
; CHECK-NEXT: cmp.w r8, #0
-; CHECK-NEXT: csel r9, r0, r8, ne
-; CHECK-NEXT: csel r8, r1, r8, ne
-; CHECK-NEXT: vmov r10, r3, d0
-; CHECK-NEXT: mov r0, r6
-; CHECK-NEXT: mov r1, r7
-; CHECK-NEXT: vmov r5, r4, d8
-; CHECK-NEXT: str r3, [sp] @ 4-byte Spill
-; CHECK-NEXT: mov r2, r10
+; CHECK-NEXT: str r1, [sp, #20] @ 4-byte Spill
+; CHECK-NEXT: csel r4, r0, r8, ne
+; CHECK-NEXT: vmov r2, r3, d0
+; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: mov r1, r10
+; CHECK-NEXT: vmov r11, r5, d8
+; CHECK-NEXT: str r2, [sp, #4] @ 4-byte Spill
+; CHECK-NEXT: str r3, [sp, #28] @ 4-byte Spill
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: itt ne
+; CHECK-NEXT: mov r0, r11
+; CHECK-NEXT: mov r1, r5
+; CHECK-NEXT: mov r2, r6
+; CHECK-NEXT: mov r3, r7
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne.w r4, #-1
+; CHECK-NEXT: str r4, [sp, #24] @ 4-byte Spill
+; CHECK-NEXT: mov r8, r7
+; CHECK-NEXT: str r5, [sp, #8] @ 4-byte Spill
+; CHECK-NEXT: str r6, [sp] @ 4-byte Spill
+; CHECK-NEXT: bl __aeabi_dcmpge
+; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: mov r0, r11
+; CHECK-NEXT: mov r1, r5
+; CHECK-NEXT: bl __aeabi_d2ulz
+; CHECK-NEXT: cmp r4, #0
+; CHECK-NEXT: ldr r3, [sp, #28] @ 4-byte Reload
+; CHECK-NEXT: csel r7, r0, r4, ne
+; CHECK-NEXT: ldr r4, [sp, #4] @ 4-byte Reload
+; CHECK-NEXT: str r1, [sp, #16] @ 4-byte Spill
+; CHECK-NEXT: mov r0, r11
+; CHECK-NEXT: mov r1, r5
+; CHECK-NEXT: mov r2, r4
+; CHECK-NEXT: bl __aeabi_dcmpgt
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: mov r1, r10
+; CHECK-NEXT: mov r2, r6
+; CHECK-NEXT: mov r3, r8
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne.w r7, #-1
+; CHECK-NEXT: str r7, [sp, #12] @ 4-byte Spill
+; CHECK-NEXT: mov r5, r8
+; CHECK-NEXT: bl __aeabi_dcmpge
+; CHECK-NEXT: ldr r7, [sp, #28] @ 4-byte Reload
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: ldr r1, [sp, #20] @ 4-byte Reload
+; CHECK-NEXT: mov r2, r4
+; CHECK-NEXT: mov r6, r4
+; CHECK-NEXT: csel r8, r1, r0, ne
+; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: mov r1, r10
+; CHECK-NEXT: mov r3, r7
+; CHECK-NEXT: bl __aeabi_dcmpgt
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r8, #0
-; CHECK-NEXT: movne.w r9, #-1
-; CHECK-NEXT: ldr r3, [sp, #4] @ 4-byte Reload
-; CHECK-NEXT: mov r0, r5
+; CHECK-NEXT: ldr r4, [sp, #8] @ 4-byte Reload
+; CHECK-NEXT: mov r0, r11
+; CHECK-NEXT: ldr r2, [sp] @ 4-byte Reload
+; CHECK-NEXT: mov r3, r5
; CHECK-NEXT: mov r1, r4
-; CHECK-NEXT: mov r2, r11
; CHECK-NEXT: bl __aeabi_dcmpge
-; CHECK-NEXT: mov r6, r0
-; CHECK-NEXT: mov r0, r5
-; CHECK-NEXT: mov r1, r4
-; CHECK-NEXT: bl __aeabi_d2ulz
-; CHECK-NEXT: ldr r3, [sp] @ 4-byte Reload
-; CHECK-NEXT: cmp r6, #0
-; CHECK-NEXT: csel r7, r1, r6, ne
-; CHECK-NEXT: csel r6, r0, r6, ne
-; CHECK-NEXT: mov r0, r5
+; CHECK-NEXT: ldr r1, [sp, #16] @ 4-byte Reload
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: mov r2, r6
+; CHECK-NEXT: mov r3, r7
+; CHECK-NEXT: csel r5, r1, r0, ne
+; CHECK-NEXT: mov r0, r11
; CHECK-NEXT: mov r1, r4
-; CHECK-NEXT: mov r2, r10
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: itt ne
-; CHECK-NEXT: movne.w r6, #-1
-; CHECK-NEXT: movne r7, #0
-; CHECK-NEXT: vmov q0[2], q0[0], r6, r9
-; CHECK-NEXT: vmov q0[3], q0[1], r7, r8
-; CHECK-NEXT: add sp, #8
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne r5, #0
+; CHECK-NEXT: ldr r0, [sp, #24] @ 4-byte Reload
+; CHECK-NEXT: ldr r1, [sp, #12] @ 4-byte Reload
+; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
+; CHECK-NEXT: vmov q0[3], q0[1], r5, r8
+; CHECK-NEXT: add sp, #32
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
@@ -2419,66 +2661,98 @@ define arm_aapcs_vfpcc <2 x i50> @test_unsigned_v2f64_v2i50(<2 x double> %f) {
; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
-; CHECK-NEXT: .pad #16
-; CHECK-NEXT: sub sp, #16
+; CHECK-NEXT: .pad #24
+; CHECK-NEXT: sub sp, #24
; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vldr d0, .LCPI38_0
-; CHECK-NEXT: vmov r11, r5, d8
-; CHECK-NEXT: vmov r6, r7, d0
-; CHECK-NEXT: str r5, [sp, #12] @ 4-byte Spill
-; CHECK-NEXT: mov r0, r11
-; CHECK-NEXT: mov r1, r5
-; CHECK-NEXT: mov r2, r6
-; CHECK-NEXT: mov r3, r7
+; CHECK-NEXT: vmov r10, r11, d9
+; CHECK-NEXT: vmov r9, r5, d0
+; CHECK-NEXT: mov r0, r10
+; CHECK-NEXT: mov r1, r11
+; CHECK-NEXT: mov r2, r9
+; CHECK-NEXT: mov r3, r5
; CHECK-NEXT: bl __aeabi_dcmpge
-; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: mov r0, r11
-; CHECK-NEXT: mov r1, r5
+; CHECK-NEXT: mov r8, r0
+; CHECK-NEXT: mov r0, r10
+; CHECK-NEXT: mov r1, r11
; CHECK-NEXT: bl __aeabi_d2ulz
; CHECK-NEXT: vldr d0, .LCPI38_1
-; CHECK-NEXT: vmov r5, r8, d9
-; CHECK-NEXT: cmp r4, #0
-; CHECK-NEXT: vmov r3, r2, d0
-; CHECK-NEXT: csel r10, r0, r4, ne
-; CHECK-NEXT: csel r9, r1, r4, ne
-; CHECK-NEXT: mov r0, r5
-; CHECK-NEXT: mov r1, r8
+; CHECK-NEXT: cmp.w r8, #0
+; CHECK-NEXT: str r1, [sp, #16] @ 4-byte Spill
+; CHECK-NEXT: csel r4, r0, r8, ne
+; CHECK-NEXT: vmov r2, r3, d0
+; CHECK-NEXT: mov r0, r10
+; CHECK-NEXT: mov r1, r11
+; CHECK-NEXT: vmov r7, r6, d8
; CHECK-NEXT: strd r3, r2, [sp, #4] @ 8-byte Folded Spill
-; CHECK-NEXT: mov r2, r6
-; CHECK-NEXT: mov r3, r7
+; CHECK-NEXT: bl __aeabi_dcmpgt
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: mov r1, r6
+; CHECK-NEXT: mov r2, r9
+; CHECK-NEXT: mov r3, r5
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne.w r4, #-1
+; CHECK-NEXT: str r4, [sp, #20] @ 4-byte Spill
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: mov r0, r5
-; CHECK-NEXT: mov r1, r8
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: bl __aeabi_d2ulz
; CHECK-NEXT: cmp r4, #0
-; CHECK-NEXT: ldr r7, [sp, #4] @ 4-byte Reload
-; CHECK-NEXT: csel r6, r1, r4, ne
-; CHECK-NEXT: csel r4, r0, r4, ne
-; CHECK-NEXT: mov r0, r5
-; CHECK-NEXT: ldr r5, [sp, #8] @ 4-byte Reload
-; CHECK-NEXT: mov r1, r8
-; CHECK-NEXT: mov r2, r7
+; CHECK-NEXT: mov r8, r1
+; CHECK-NEXT: csel r0, r0, r4, ne
+; CHECK-NEXT: mov r1, r6
+; CHECK-NEXT: str r0, [sp, #12] @ 4-byte Spill
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: mov r2, r9
+; CHECK-NEXT: mov r3, r5
+; CHECK-NEXT: bl __aeabi_dcmpge
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: mov r1, r11
+; CHECK-NEXT: csel r8, r8, r0, ne
+; CHECK-NEXT: mov r0, r10
+; CHECK-NEXT: mov r2, r9
+; CHECK-NEXT: mov r3, r5
+; CHECK-NEXT: bl __aeabi_dcmpge
+; CHECK-NEXT: ldr.w r9, [sp, #8] @ 4-byte Reload
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: ldr r5, [sp, #4] @ 4-byte Reload
+; CHECK-NEXT: ldr r1, [sp, #16] @ 4-byte Reload
+; CHECK-NEXT: mov r2, r9
+; CHECK-NEXT: csel r4, r1, r0, ne
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: mov r1, r6
+; CHECK-NEXT: mov r3, r5
+; CHECK-NEXT: bl __aeabi_dcmpgt
+; CHECK-NEXT: str r0, [sp, #16] @ 4-byte Spill
+; CHECK-NEXT: mov r0, r10
+; CHECK-NEXT: mov r1, r11
+; CHECK-NEXT: mov r2, r9
; CHECK-NEXT: mov r3, r5
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: ittt ne
-; CHECK-NEXT: movne.w r4, #-1
-; CHECK-NEXT: movwne r6, #65535
-; CHECK-NEXT: movtne r6, #3
-; CHECK-NEXT: ldr r1, [sp, #12] @ 4-byte Reload
-; CHECK-NEXT: mov r0, r11
-; CHECK-NEXT: mov r2, r7
+; CHECK-NEXT: itt ne
+; CHECK-NEXT: movwne r4, #65535
+; CHECK-NEXT: movtne r4, #3
+; CHECK-NEXT: ldr r0, [sp, #16] @ 4-byte Reload
+; CHECK-NEXT: mov r1, r6
+; CHECK-NEXT: mov r2, r9
; CHECK-NEXT: mov r3, r5
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: itt ne
+; CHECK-NEXT: movwne r8, #65535
+; CHECK-NEXT: movtne r8, #3
; CHECK-NEXT: bl __aeabi_dcmpgt
+; CHECK-NEXT: ldr r1, [sp, #12] @ 4-byte Reload
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: ittt ne
-; CHECK-NEXT: movwne r9, #65535
-; CHECK-NEXT: movtne r9, #3
-; CHECK-NEXT: movne.w r10, #-1
-; CHECK-NEXT: vmov q0[2], q0[0], r10, r4
-; CHECK-NEXT: vmov q0[3], q0[1], r9, r6
-; CHECK-NEXT: add sp, #16
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne.w r1, #-1
+; CHECK-NEXT: ldr r0, [sp, #20] @ 4-byte Reload
+; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
+; CHECK-NEXT: vmov q0[3], q0[1], r8, r4
+; CHECK-NEXT: add sp, #24
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
@@ -2503,60 +2777,102 @@ define arm_aapcs_vfpcc <2 x i64> @test_unsigned_v2f64_v2i64(<2 x double> %f) {
; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
-; CHECK-NEXT: .pad #8
-; CHECK-NEXT: sub sp, #8
+; CHECK-NEXT: .pad #32
+; CHECK-NEXT: sub sp, #32
; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vldr d0, .LCPI39_0
-; CHECK-NEXT: vmov r6, r7, d9
-; CHECK-NEXT: vmov r11, r3, d0
-; CHECK-NEXT: str r3, [sp, #4] @ 4-byte Spill
-; CHECK-NEXT: mov r0, r6
-; CHECK-NEXT: mov r1, r7
-; CHECK-NEXT: mov r2, r11
+; CHECK-NEXT: vmov r9, r10, d9
+; CHECK-NEXT: vmov r6, r3, d0
+; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: mov r1, r10
+; CHECK-NEXT: mov r2, r6
+; CHECK-NEXT: mov r7, r3
; CHECK-NEXT: bl __aeabi_dcmpge
; CHECK-NEXT: mov r8, r0
-; CHECK-NEXT: mov r0, r6
-; CHECK-NEXT: mov r1, r7
+; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: mov r1, r10
; CHECK-NEXT: bl __aeabi_d2ulz
; CHECK-NEXT: vldr d0, .LCPI39_1
; CHECK-NEXT: cmp.w r8, #0
-; CHECK-NEXT: csel r9, r0, r8, ne
-; CHECK-NEXT: csel r8, r1, r8, ne
-; CHECK-NEXT: vmov r10, r3, d0
-; CHECK-NEXT: mov r0, r6
-; CHECK-NEXT: mov r1, r7
-; CHECK-NEXT: vmov r5, r4, d8
-; CHECK-NEXT: str r3, [sp] @ 4-byte Spill
-; CHECK-NEXT: mov r2, r10
+; CHECK-NEXT: str r1, [sp, #20] @ 4-byte Spill
+; CHECK-NEXT: csel r4, r0, r8, ne
+; CHECK-NEXT: vmov r2, r3, d0
+; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: mov r1, r10
+; CHECK-NEXT: vmov r11, r5, d8
+; CHECK-NEXT: str r2, [sp, #4] @ 4-byte Spill
+; CHECK-NEXT: str r3, [sp, #28] @ 4-byte Spill
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: itt ne
+; CHECK-NEXT: mov r0, r11
+; CHECK-NEXT: mov r1, r5
+; CHECK-NEXT: mov r2, r6
+; CHECK-NEXT: mov r3, r7
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne.w r4, #-1
+; CHECK-NEXT: str r4, [sp, #24] @ 4-byte Spill
+; CHECK-NEXT: mov r8, r7
+; CHECK-NEXT: str r5, [sp, #8] @ 4-byte Spill
+; CHECK-NEXT: str r6, [sp] @ 4-byte Spill
+; CHECK-NEXT: bl __aeabi_dcmpge
+; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: mov r0, r11
+; CHECK-NEXT: mov r1, r5
+; CHECK-NEXT: bl __aeabi_d2ulz
+; CHECK-NEXT: cmp r4, #0
+; CHECK-NEXT: ldr r3, [sp, #28] @ 4-byte Reload
+; CHECK-NEXT: csel r7, r0, r4, ne
+; CHECK-NEXT: ldr r4, [sp, #4] @ 4-byte Reload
+; CHECK-NEXT: str r1, [sp, #16] @ 4-byte Spill
+; CHECK-NEXT: mov r0, r11
+; CHECK-NEXT: mov r1, r5
+; CHECK-NEXT: mov r2, r4
+; CHECK-NEXT: bl __aeabi_dcmpgt
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: mov r1, r10
+; CHECK-NEXT: mov r2, r6
+; CHECK-NEXT: mov r3, r8
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne.w r7, #-1
+; CHECK-NEXT: str r7, [sp, #12] @ 4-byte Spill
+; CHECK-NEXT: mov r5, r8
+; CHECK-NEXT: bl __aeabi_dcmpge
+; CHECK-NEXT: ldr r7, [sp, #28] @ 4-byte Reload
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: ldr r1, [sp, #20] @ 4-byte Reload
+; CHECK-NEXT: mov r2, r4
+; CHECK-NEXT: mov r6, r4
+; CHECK-NEXT: csel r8, r1, r0, ne
+; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: mov r1, r10
+; CHECK-NEXT: mov r3, r7
+; CHECK-NEXT: bl __aeabi_dcmpgt
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: it ne
; CHECK-NEXT: movne.w r8, #-1
-; CHECK-NEXT: movne.w r9, #-1
-; CHECK-NEXT: ldr r3, [sp, #4] @ 4-byte Reload
-; CHECK-NEXT: mov r0, r5
+; CHECK-NEXT: ldr r4, [sp, #8] @ 4-byte Reload
+; CHECK-NEXT: mov r0, r11
+; CHECK-NEXT: ldr r2, [sp] @ 4-byte Reload
+; CHECK-NEXT: mov r3, r5
; CHECK-NEXT: mov r1, r4
-; CHECK-NEXT: mov r2, r11
; CHECK-NEXT: bl __aeabi_dcmpge
-; CHECK-NEXT: mov r6, r0
-; CHECK-NEXT: mov r0, r5
-; CHECK-NEXT: mov r1, r4
-; CHECK-NEXT: bl __aeabi_d2ulz
-; CHECK-NEXT: ldr r3, [sp] @ 4-byte Reload
-; CHECK-NEXT: cmp r6, #0
-; CHECK-NEXT: csel r7, r1, r6, ne
-; CHECK-NEXT: csel r6, r0, r6, ne
-; CHECK-NEXT: mov r0, r5
+; CHECK-NEXT: ldr r1, [sp, #16] @ 4-byte Reload
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: mov r2, r6
+; CHECK-NEXT: mov r3, r7
+; CHECK-NEXT: csel r5, r1, r0, ne
+; CHECK-NEXT: mov r0, r11
; CHECK-NEXT: mov r1, r4
-; CHECK-NEXT: mov r2, r10
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: itt ne
-; CHECK-NEXT: movne.w r6, #-1
-; CHECK-NEXT: movne.w r7, #-1
-; CHECK-NEXT: vmov q0[2], q0[0], r6, r9
-; CHECK-NEXT: vmov q0[3], q0[1], r7, r8
-; CHECK-NEXT: add sp, #8
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne.w r5, #-1
+; CHECK-NEXT: ldr r0, [sp, #24] @ 4-byte Reload
+; CHECK-NEXT: ldr r1, [sp, #12] @ 4-byte Reload
+; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
+; CHECK-NEXT: vmov q0[3], q0[1], r5, r8
+; CHECK-NEXT: add sp, #32
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
diff --git a/llvm/test/CodeGen/Thumb2/mve-pred-vselect.ll b/llvm/test/CodeGen/Thumb2/mve-pred-vselect.ll
index ba3d327e00594..1009cf3b9ff34 100644
--- a/llvm/test/CodeGen/Thumb2/mve-pred-vselect.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-pred-vselect.ll
@@ -280,24 +280,24 @@ entry:
define arm_aapcs_vfpcc <2 x i64> @cmpsltz_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {
; CHECK-LABEL: cmpsltz_v2i1:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov r1, s7
-; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: vmov r2, s11
+; CHECK-NEXT: vmov r1, s7
+; CHECK-NEXT: vmov r3, s9
; CHECK-NEXT: vmov r0, s3
-; CHECK-NEXT: vmov r12, s1
-; CHECK-NEXT: asrs r1, r1, #31
-; CHECK-NEXT: cmp.w r3, r2, lsr #31
+; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: vmov r2, s5
-; CHECK-NEXT: it ne
-; CHECK-NEXT: asrne r1, r0, #31
-; CHECK-NEXT: vmov r0, s9
-; CHECK-NEXT: asrs r2, r2, #31
-; CHECK-NEXT: cmp.w r3, r0, lsr #31
-; CHECK-NEXT: it ne
-; CHECK-NEXT: asrne.w r2, r12, #31
-; CHECK-NEXT: bfi r3, r2, #0, #8
-; CHECK-NEXT: bfi r3, r1, #8, #8
-; CHECK-NEXT: vmsr p0, r3
+; CHECK-NEXT: asr.w r1, r1, #31
+; CHECK-NEXT: it mi
+; CHECK-NEXT: asrmi r1, r0, #31
+; CHECK-NEXT: vmov r0, s1
+; CHECK-NEXT: cmp r3, #0
+; CHECK-NEXT: asr.w r2, r2, #31
+; CHECK-NEXT: it mi
+; CHECK-NEXT: asrmi r2, r0, #31
+; CHECK-NEXT: movs r0, #0
+; CHECK-NEXT: bfi r0, r2, #0, #8
+; CHECK-NEXT: bfi r0, r1, #8, #8
+; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
entry:
diff --git a/llvm/test/CodeGen/Thumb2/mve-saturating-arith.ll b/llvm/test/CodeGen/Thumb2/mve-saturating-arith.ll
index 118b8ac6682b2..e309197bfb64f 100644
--- a/llvm/test/CodeGen/Thumb2/mve-saturating-arith.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-saturating-arith.ll
@@ -34,45 +34,45 @@ entry:
define arm_aapcs_vfpcc <2 x i64> @sadd_int64_t(<2 x i64> %src1, <2 x i64> %src2) {
; CHECK-LABEL: sadd_int64_t:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: .save {r4, r5, r6, lr}
-; CHECK-NEXT: push {r4, r5, r6, lr}
+; CHECK-NEXT: .save {r4, r5, r7, lr}
+; CHECK-NEXT: push {r4, r5, r7, lr}
; CHECK-NEXT: vmov r0, r1, d2
; CHECK-NEXT: vmov r2, r3, d0
-; CHECK-NEXT: vmov r4, r5, d1
; CHECK-NEXT: adds.w r12, r2, r0
-; CHECK-NEXT: adc.w r0, r3, r1
+; CHECK-NEXT: vmov r0, r4, d1
+; CHECK-NEXT: adc.w lr, r3, r1
; CHECK-NEXT: subs.w r2, r12, r2
-; CHECK-NEXT: sbcs.w r2, r0, r3
-; CHECK-NEXT: mov.w r3, #0
+; CHECK-NEXT: sbcs.w r2, lr, r3
; CHECK-NEXT: cset r2, lt
-; CHECK-NEXT: cmp.w r3, r1, lsr #31
-; CHECK-NEXT: it ne
-; CHECK-NEXT: eorne r2, r2, #1
-; CHECK-NEXT: rsb.w lr, r2, #0
-; CHECK-NEXT: vmov r2, r1, d3
-; CHECK-NEXT: adds r2, r2, r4
-; CHECK-NEXT: adc.w r6, r5, r1
-; CHECK-NEXT: subs r4, r2, r4
-; CHECK-NEXT: sbcs.w r4, r6, r5
-; CHECK-NEXT: vmov q0[2], q0[0], r12, r2
-; CHECK-NEXT: cset r4, lt
-; CHECK-NEXT: cmp.w r3, r1, lsr #31
-; CHECK-NEXT: it ne
-; CHECK-NEXT: eorne r4, r4, #1
-; CHECK-NEXT: bfi r3, lr, #0, #8
-; CHECK-NEXT: rsbs r1, r4, #0
-; CHECK-NEXT: vmov q0[3], q0[1], r0, r6
-; CHECK-NEXT: bfi r3, r1, #8, #8
-; CHECK-NEXT: asrs r1, r6, #31
-; CHECK-NEXT: asrs r0, r0, #31
-; CHECK-NEXT: vmsr p0, r3
-; CHECK-NEXT: vmov q1[2], q1[0], r0, r1
-; CHECK-NEXT: vmov q1[3], q1[1], r0, r1
+; CHECK-NEXT: cmp r1, #0
+; CHECK-NEXT: it mi
+; CHECK-NEXT: eormi r2, r2, #1
+; CHECK-NEXT: rsbs r1, r2, #0
+; CHECK-NEXT: movs r2, #0
+; CHECK-NEXT: bfi r2, r1, #0, #8
+; CHECK-NEXT: vmov r1, r3, d3
+; CHECK-NEXT: adds r1, r1, r0
+; CHECK-NEXT: adc.w r5, r4, r3
+; CHECK-NEXT: subs r0, r1, r0
+; CHECK-NEXT: sbcs.w r0, r5, r4
+; CHECK-NEXT: vmov q0[2], q0[0], r12, r1
+; CHECK-NEXT: cset r0, lt
+; CHECK-NEXT: cmp r3, #0
+; CHECK-NEXT: it mi
+; CHECK-NEXT: eormi r0, r0, #1
+; CHECK-NEXT: asr.w r1, lr, #31
+; CHECK-NEXT: rsbs r0, r0, #0
+; CHECK-NEXT: vmov q0[3], q0[1], lr, r5
+; CHECK-NEXT: bfi r2, r0, #8, #8
+; CHECK-NEXT: asrs r0, r5, #31
+; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
+; CHECK-NEXT: vmsr p0, r2
+; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
; CHECK-NEXT: adr r0, .LCPI3_0
; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: veor q1, q1, q2
; CHECK-NEXT: vpsel q0, q1, q0
-; CHECK-NEXT: pop {r4, r5, r6, pc}
+; CHECK-NEXT: pop {r4, r5, r7, pc}
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI3_0:
diff --git a/llvm/test/CodeGen/Thumb2/mve-vcmpf.ll b/llvm/test/CodeGen/Thumb2/mve-vcmpf.ll
index cc856730d90cf..0d4cd77d1d1b4 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vcmpf.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vcmpf.ll
@@ -5,26 +5,18 @@
define arm_aapcs_vfpcc <4 x float> @vcmp_oeq_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_oeq_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s3, s7
-; CHECK-MVE-NEXT: cset r0, eq
+; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, s5
-; CHECK-MVE-NEXT: cset r1, eq
+; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, s6
-; CHECK-MVE-NEXT: cset r2, eq
+; CHECK-MVE-NEXT: vcmp.f32 s3, s7
+; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, eq
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s15
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s12
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_oeq_v4f32:
@@ -41,30 +33,26 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_one_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_one_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s3, s7
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: csinc r0, r0, zr, le
+; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, s5
-; CHECK-MVE-NEXT: cset r1, mi
-; CHECK-MVE-NEXT: csinc r1, r1, zr, le
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s14, s10
+; CHECK-MVE-NEXT: vselgt.f32 s2, s10, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, s6
-; CHECK-MVE-NEXT: cset r2, mi
-; CHECK-MVE-NEXT: csinc r2, r2, zr, le
+; CHECK-MVE-NEXT: vcmp.f32 s3, s7
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s13, s9
+; CHECK-MVE-NEXT: vselgt.f32 s1, s9, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, mi
-; CHECK-MVE-NEXT: csinc r3, r3, zr, le
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s15, s11
+; CHECK-MVE-NEXT: vselgt.f32 s3, s11, s15
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s12, s8
+; CHECK-MVE-NEXT: vselgt.f32 s0, s8, s12
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_one_v4f32:
@@ -82,26 +70,18 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_ogt_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ogt_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s3, s7
-; CHECK-MVE-NEXT: cset r0, gt
+; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, s5
-; CHECK-MVE-NEXT: cset r1, gt
+; CHECK-MVE-NEXT: vselgt.f32 s2, s10, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, s6
-; CHECK-MVE-NEXT: cset r2, gt
+; CHECK-MVE-NEXT: vcmp.f32 s3, s7
+; CHECK-MVE-NEXT: vselgt.f32 s1, s9, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, gt
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vselgt.f32 s3, s11, s15
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vselgt.f32 s0, s8, s12
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_ogt_v4f32:
@@ -118,26 +98,18 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_oge_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_oge_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s3, s7
-; CHECK-MVE-NEXT: cset r0, ge
+; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, s5
-; CHECK-MVE-NEXT: cset r1, ge
+; CHECK-MVE-NEXT: vselge.f32 s2, s10, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, s6
-; CHECK-MVE-NEXT: cset r2, ge
+; CHECK-MVE-NEXT: vcmp.f32 s3, s7
+; CHECK-MVE-NEXT: vselge.f32 s1, s9, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, ge
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vselge.f32 s3, s11, s15
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vselge.f32 s0, s8, s12
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_oge_v4f32:
@@ -154,26 +126,18 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_olt_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_olt_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vcmp.f32 s6, s2
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s3, s7
-; CHECK-MVE-NEXT: cset r0, mi
+; CHECK-MVE-NEXT: vcmp.f32 s5, s1
+; CHECK-MVE-NEXT: vselgt.f32 s2, s10, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s1, s5
-; CHECK-MVE-NEXT: cset r1, mi
+; CHECK-MVE-NEXT: vcmp.f32 s7, s3
+; CHECK-MVE-NEXT: vselgt.f32 s1, s9, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, s6
-; CHECK-MVE-NEXT: cset r2, mi
+; CHECK-MVE-NEXT: vcmp.f32 s4, s0
+; CHECK-MVE-NEXT: vselgt.f32 s3, s11, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, mi
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: vselgt.f32 s0, s8, s12
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_olt_v4f32:
@@ -190,26 +154,18 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_ole_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ole_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vcmp.f32 s6, s2
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s3, s7
-; CHECK-MVE-NEXT: cset r0, ls
+; CHECK-MVE-NEXT: vcmp.f32 s5, s1
+; CHECK-MVE-NEXT: vselge.f32 s2, s10, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s1, s5
-; CHECK-MVE-NEXT: cset r1, ls
+; CHECK-MVE-NEXT: vcmp.f32 s7, s3
+; CHECK-MVE-NEXT: vselge.f32 s1, s9, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, s6
-; CHECK-MVE-NEXT: cset r2, ls
+; CHECK-MVE-NEXT: vcmp.f32 s4, s0
+; CHECK-MVE-NEXT: vselge.f32 s3, s11, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, ls
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: vselge.f32 s0, s8, s12
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_ole_v4f32:
@@ -226,30 +182,22 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_ueq_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ueq_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s3, s7
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
+; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, s5
-; CHECK-MVE-NEXT: cset r1, eq
-; CHECK-MVE-NEXT: csinc r1, r1, zr, vc
+; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s14
+; CHECK-MVE-NEXT: vselvs.f32 s2, s10, s2
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, s6
-; CHECK-MVE-NEXT: cset r2, eq
-; CHECK-MVE-NEXT: csinc r2, r2, zr, vc
+; CHECK-MVE-NEXT: vcmp.f32 s3, s7
+; CHECK-MVE-NEXT: vseleq.f32 s6, s9, s13
+; CHECK-MVE-NEXT: vselvs.f32 s1, s9, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, eq
-; CHECK-MVE-NEXT: csinc r3, r3, zr, vc
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vseleq.f32 s0, s11, s15
+; CHECK-MVE-NEXT: vselvs.f32 s3, s11, s0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s12
+; CHECK-MVE-NEXT: vselvs.f32 s0, s8, s0
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_ueq_v4f32:
@@ -295,26 +243,18 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_ugt_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ugt_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vcmp.f32 s6, s2
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s3, s7
-; CHECK-MVE-NEXT: cset r0, hi
+; CHECK-MVE-NEXT: vcmp.f32 s5, s1
+; CHECK-MVE-NEXT: vselge.f32 s2, s14, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s1, s5
-; CHECK-MVE-NEXT: cset r1, hi
+; CHECK-MVE-NEXT: vcmp.f32 s7, s3
+; CHECK-MVE-NEXT: vselge.f32 s1, s13, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, s6
-; CHECK-MVE-NEXT: cset r2, hi
+; CHECK-MVE-NEXT: vcmp.f32 s4, s0
+; CHECK-MVE-NEXT: vselge.f32 s3, s15, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, hi
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: vselge.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_ugt_v4f32:
@@ -331,26 +271,18 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_uge_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_uge_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vcmp.f32 s6, s2
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s3, s7
-; CHECK-MVE-NEXT: cset r0, pl
+; CHECK-MVE-NEXT: vcmp.f32 s5, s1
+; CHECK-MVE-NEXT: vselgt.f32 s2, s14, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s1, s5
-; CHECK-MVE-NEXT: cset r1, pl
+; CHECK-MVE-NEXT: vcmp.f32 s7, s3
+; CHECK-MVE-NEXT: vselgt.f32 s1, s13, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, s6
-; CHECK-MVE-NEXT: cset r2, pl
+; CHECK-MVE-NEXT: vcmp.f32 s4, s0
+; CHECK-MVE-NEXT: vselgt.f32 s3, s15, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, pl
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: vselgt.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_uge_v4f32:
@@ -367,26 +299,18 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_ult_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ult_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s3, s7
-; CHECK-MVE-NEXT: cset r0, lt
+; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, s5
-; CHECK-MVE-NEXT: cset r1, lt
+; CHECK-MVE-NEXT: vselge.f32 s2, s14, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, s6
-; CHECK-MVE-NEXT: cset r2, lt
+; CHECK-MVE-NEXT: vcmp.f32 s3, s7
+; CHECK-MVE-NEXT: vselge.f32 s1, s13, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, lt
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vselge.f32 s3, s15, s11
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vselge.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_ult_v4f32:
@@ -403,26 +327,18 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_ule_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ule_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s3, s7
-; CHECK-MVE-NEXT: cset r0, le
+; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, s5
-; CHECK-MVE-NEXT: cset r1, le
+; CHECK-MVE-NEXT: vselgt.f32 s2, s14, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, s6
-; CHECK-MVE-NEXT: cset r2, le
+; CHECK-MVE-NEXT: vcmp.f32 s3, s7
+; CHECK-MVE-NEXT: vselgt.f32 s1, s13, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, le
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vselgt.f32 s3, s15, s11
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vselgt.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_ule_v4f32:
@@ -439,26 +355,18 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_ord_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ord_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s3, s7
-; CHECK-MVE-NEXT: cset r0, vc
+; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, s5
-; CHECK-MVE-NEXT: cset r1, vc
+; CHECK-MVE-NEXT: vselvs.f32 s2, s14, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, s6
-; CHECK-MVE-NEXT: cset r2, vc
+; CHECK-MVE-NEXT: vcmp.f32 s3, s7
+; CHECK-MVE-NEXT: vselvs.f32 s1, s13, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, vc
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vselvs.f32 s3, s15, s11
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vselvs.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_ord_v4f32:
@@ -476,26 +384,18 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_uno_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_uno_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s3, s7
-; CHECK-MVE-NEXT: cset r0, vs
+; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, s5
-; CHECK-MVE-NEXT: cset r1, vs
+; CHECK-MVE-NEXT: vselvs.f32 s2, s10, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, s6
-; CHECK-MVE-NEXT: cset r2, vs
+; CHECK-MVE-NEXT: vcmp.f32 s3, s7
+; CHECK-MVE-NEXT: vselvs.f32 s1, s9, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, vs
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vselvs.f32 s3, s11, s15
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vselvs.f32 s0, s8, s12
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_uno_v4f32:
@@ -520,62 +420,46 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16
-; CHECK-MVE-NEXT: vmovx.f16 s16, s8
+; CHECK-MVE-NEXT: vmovx.f16 s16, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vmovx.f16 s18, s8
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
-; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: vmovx.f16 s4, s5
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
+; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s12
; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vcmp.f16 s8, s4
-; CHECK-MVE-NEXT: vmovx.f16 s4, s9
+; CHECK-MVE-NEXT: vmovx.f16 s4, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s13
+; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: vins.f16 s0, s16
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s2
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
+; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s13
; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vcmp.f16 s8, s4
-; CHECK-MVE-NEXT: vmovx.f16 s4, s10
+; CHECK-MVE-NEXT: vmovx.f16 s4, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
-; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
+; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s14
; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
-; CHECK-MVE-NEXT: vmovx.f16 s4, s11
+; CHECK-MVE-NEXT: vmovx.f16 s4, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s6, s15
+; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
+; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s15
; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr
@@ -601,52 +485,46 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s12
+; CHECK-MVE-NEXT: vcmp.f16 s0, s4
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s18, s16
; CHECK-MVE-NEXT: vmovx.f16 s4, s5
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: csinc r0, r0, zr, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vselgt.f16 s16, s16, s18
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: csinc r0, r0, zr, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s12, s8
+; CHECK-MVE-NEXT: vselgt.f16 s0, s8, s12
; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s8, s4
; CHECK-MVE-NEXT: vins.f16 s0, s16
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: csinc r0, r0, zr, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselgt.f16 s4, s4, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s13, s9
; CHECK-MVE-NEXT: vmovx.f16 s8, s2
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: csinc r0, r0, zr, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
+; CHECK-MVE-NEXT: vselgt.f16 s1, s9, s13
; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
+; CHECK-MVE-NEXT: vcmp.f16 s2, s6
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: csinc r0, r0, zr, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselgt.f16 s4, s4, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: csinc r0, r0, zr, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s14, s10
+; CHECK-MVE-NEXT: vselgt.f16 s2, s10, s14
; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -654,15 +532,13 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: csinc r0, r0, zr, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s6, s4
+; CHECK-MVE-NEXT: vselgt.f16 s4, s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: csinc r0, r0, zr, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s15, s11
+; CHECK-MVE-NEXT: vselgt.f16 s3, s11, s15
; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr
@@ -687,62 +563,46 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ogt_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16
-; CHECK-MVE-NEXT: vmovx.f16 s16, s8
+; CHECK-MVE-NEXT: vmovx.f16 s16, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vmovx.f16 s18, s8
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
-; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: vmovx.f16 s4, s5
-; CHECK-MVE-NEXT: cset r0, gt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vselgt.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, gt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
+; CHECK-MVE-NEXT: vselgt.f16 s0, s8, s12
; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vcmp.f16 s8, s4
-; CHECK-MVE-NEXT: vmovx.f16 s4, s9
+; CHECK-MVE-NEXT: vmovx.f16 s4, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s13
+; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: vins.f16 s0, s16
-; CHECK-MVE-NEXT: cset r0, gt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselgt.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s2
-; CHECK-MVE-NEXT: cset r0, gt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
+; CHECK-MVE-NEXT: vselgt.f16 s1, s9, s13
; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vcmp.f16 s8, s4
-; CHECK-MVE-NEXT: vmovx.f16 s4, s10
+; CHECK-MVE-NEXT: vmovx.f16 s4, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
-; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
-; CHECK-MVE-NEXT: cset r0, gt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselgt.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, gt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
+; CHECK-MVE-NEXT: vselgt.f16 s2, s10, s14
; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
-; CHECK-MVE-NEXT: vmovx.f16 s4, s11
+; CHECK-MVE-NEXT: vmovx.f16 s4, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s6, s15
+; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
-; CHECK-MVE-NEXT: cset r0, gt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
+; CHECK-MVE-NEXT: vselgt.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, gt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
+; CHECK-MVE-NEXT: vselgt.f16 s3, s11, s15
; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr
@@ -766,62 +626,46 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_oge_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16
-; CHECK-MVE-NEXT: vmovx.f16 s16, s8
+; CHECK-MVE-NEXT: vmovx.f16 s16, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vmovx.f16 s18, s8
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
-; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: vmovx.f16 s4, s5
-; CHECK-MVE-NEXT: cset r0, ge
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vselge.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, ge
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
+; CHECK-MVE-NEXT: vselge.f16 s0, s8, s12
; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vcmp.f16 s8, s4
-; CHECK-MVE-NEXT: vmovx.f16 s4, s9
+; CHECK-MVE-NEXT: vmovx.f16 s4, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s13
+; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: vins.f16 s0, s16
-; CHECK-MVE-NEXT: cset r0, ge
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselge.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s2
-; CHECK-MVE-NEXT: cset r0, ge
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
+; CHECK-MVE-NEXT: vselge.f16 s1, s9, s13
; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vcmp.f16 s8, s4
-; CHECK-MVE-NEXT: vmovx.f16 s4, s10
+; CHECK-MVE-NEXT: vmovx.f16 s4, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
-; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
-; CHECK-MVE-NEXT: cset r0, ge
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselge.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, ge
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
+; CHECK-MVE-NEXT: vselge.f16 s2, s10, s14
; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
-; CHECK-MVE-NEXT: vmovx.f16 s4, s11
+; CHECK-MVE-NEXT: vmovx.f16 s4, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s6, s15
+; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
-; CHECK-MVE-NEXT: cset r0, ge
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
+; CHECK-MVE-NEXT: vselge.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, ge
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
+; CHECK-MVE-NEXT: vselge.f16 s3, s11, s15
; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr
@@ -842,65 +686,49 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_olt_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
-; CHECK-MVE-NEXT: vmovx.f16 s16, s4
-; CHECK-MVE-NEXT: vmovx.f16 s18, s0
+; CHECK-MVE-NEXT: vmovx.f16 s16, s0
+; CHECK-MVE-NEXT: vmovx.f16 s18, s4
; CHECK-MVE-NEXT: vcmp.f16 s18, s16
-; CHECK-MVE-NEXT: vmovx.f16 s16, s8
+; CHECK-MVE-NEXT: vmovx.f16 s16, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s0, s4
-; CHECK-MVE-NEXT: vmovx.f16 s18, s12
-; CHECK-MVE-NEXT: vmovx.f16 s4, s5
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmovx.f16 s18, s8
+; CHECK-MVE-NEXT: vcmp.f16 s4, s0
+; CHECK-MVE-NEXT: vmovx.f16 s4, s1
+; CHECK-MVE-NEXT: vselgt.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
-; CHECK-MVE-NEXT: vmovx.f16 s8, s1
+; CHECK-MVE-NEXT: vselgt.f16 s0, s8, s12
+; CHECK-MVE-NEXT: vmovx.f16 s8, s5
; CHECK-MVE-NEXT: vcmp.f16 s8, s4
-; CHECK-MVE-NEXT: vmovx.f16 s4, s9
+; CHECK-MVE-NEXT: vmovx.f16 s4, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s13
-; CHECK-MVE-NEXT: vcmp.f16 s1, s5
+; CHECK-MVE-NEXT: vmovx.f16 s8, s9
+; CHECK-MVE-NEXT: vcmp.f16 s5, s1
; CHECK-MVE-NEXT: vins.f16 s0, s16
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselgt.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s2
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
+; CHECK-MVE-NEXT: vmovx.f16 s8, s6
+; CHECK-MVE-NEXT: vselgt.f16 s1, s9, s13
; CHECK-MVE-NEXT: vins.f16 s1, s4
-; CHECK-MVE-NEXT: vmovx.f16 s4, s6
+; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s8, s4
-; CHECK-MVE-NEXT: vmovx.f16 s4, s10
+; CHECK-MVE-NEXT: vmovx.f16 s4, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s2, s6
-; CHECK-MVE-NEXT: vmovx.f16 s8, s14
-; CHECK-MVE-NEXT: vmovx.f16 s6, s3
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vmovx.f16 s8, s10
+; CHECK-MVE-NEXT: vcmp.f16 s6, s2
+; CHECK-MVE-NEXT: vmovx.f16 s6, s7
+; CHECK-MVE-NEXT: vselgt.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
+; CHECK-MVE-NEXT: vselgt.f16 s2, s10, s14
; CHECK-MVE-NEXT: vins.f16 s2, s4
-; CHECK-MVE-NEXT: vmovx.f16 s4, s7
+; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
-; CHECK-MVE-NEXT: vmovx.f16 s4, s11
+; CHECK-MVE-NEXT: vmovx.f16 s4, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s6, s15
-; CHECK-MVE-NEXT: vcmp.f16 s3, s7
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
+; CHECK-MVE-NEXT: vmovx.f16 s6, s11
+; CHECK-MVE-NEXT: vcmp.f16 s7, s3
+; CHECK-MVE-NEXT: vselgt.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
+; CHECK-MVE-NEXT: vselgt.f16 s3, s11, s15
; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr
@@ -921,65 +749,49 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ole_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
-; CHECK-MVE-NEXT: vmovx.f16 s16, s4
-; CHECK-MVE-NEXT: vmovx.f16 s18, s0
+; CHECK-MVE-NEXT: vmovx.f16 s16, s0
+; CHECK-MVE-NEXT: vmovx.f16 s18, s4
; CHECK-MVE-NEXT: vcmp.f16 s18, s16
-; CHECK-MVE-NEXT: vmovx.f16 s16, s8
+; CHECK-MVE-NEXT: vmovx.f16 s16, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s0, s4
-; CHECK-MVE-NEXT: vmovx.f16 s18, s12
-; CHECK-MVE-NEXT: vmovx.f16 s4, s5
-; CHECK-MVE-NEXT: cset r0, ls
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vmovx.f16 s18, s8
+; CHECK-MVE-NEXT: vcmp.f16 s4, s0
+; CHECK-MVE-NEXT: vmovx.f16 s4, s1
+; CHECK-MVE-NEXT: vselge.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, ls
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
-; CHECK-MVE-NEXT: vmovx.f16 s8, s1
+; CHECK-MVE-NEXT: vselge.f16 s0, s8, s12
+; CHECK-MVE-NEXT: vmovx.f16 s8, s5
; CHECK-MVE-NEXT: vcmp.f16 s8, s4
-; CHECK-MVE-NEXT: vmovx.f16 s4, s9
+; CHECK-MVE-NEXT: vmovx.f16 s4, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s13
-; CHECK-MVE-NEXT: vcmp.f16 s1, s5
+; CHECK-MVE-NEXT: vmovx.f16 s8, s9
+; CHECK-MVE-NEXT: vcmp.f16 s5, s1
; CHECK-MVE-NEXT: vins.f16 s0, s16
-; CHECK-MVE-NEXT: cset r0, ls
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselge.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s2
-; CHECK-MVE-NEXT: cset r0, ls
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
+; CHECK-MVE-NEXT: vmovx.f16 s8, s6
+; CHECK-MVE-NEXT: vselge.f16 s1, s9, s13
; CHECK-MVE-NEXT: vins.f16 s1, s4
-; CHECK-MVE-NEXT: vmovx.f16 s4, s6
+; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s8, s4
-; CHECK-MVE-NEXT: vmovx.f16 s4, s10
+; CHECK-MVE-NEXT: vmovx.f16 s4, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s2, s6
-; CHECK-MVE-NEXT: vmovx.f16 s8, s14
-; CHECK-MVE-NEXT: vmovx.f16 s6, s3
-; CHECK-MVE-NEXT: cset r0, ls
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vmovx.f16 s8, s10
+; CHECK-MVE-NEXT: vcmp.f16 s6, s2
+; CHECK-MVE-NEXT: vmovx.f16 s6, s7
+; CHECK-MVE-NEXT: vselge.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, ls
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
+; CHECK-MVE-NEXT: vselge.f16 s2, s10, s14
; CHECK-MVE-NEXT: vins.f16 s2, s4
-; CHECK-MVE-NEXT: vmovx.f16 s4, s7
+; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
-; CHECK-MVE-NEXT: vmovx.f16 s4, s11
+; CHECK-MVE-NEXT: vmovx.f16 s4, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s6, s15
-; CHECK-MVE-NEXT: vcmp.f16 s3, s7
-; CHECK-MVE-NEXT: cset r0, ls
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
+; CHECK-MVE-NEXT: vmovx.f16 s6, s11
+; CHECK-MVE-NEXT: vcmp.f16 s7, s3
+; CHECK-MVE-NEXT: vselge.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, ls
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
+; CHECK-MVE-NEXT: vselge.f16 s3, s11, s15
; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr
@@ -1003,70 +815,54 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ueq_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16
-; CHECK-MVE-NEXT: vmovx.f16 s16, s8
+; CHECK-MVE-NEXT: vmovx.f16 s16, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vmovx.f16 s18, s8
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
-; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: vmovx.f16 s4, s5
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
-; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vselvs.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
+; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s12
+; CHECK-MVE-NEXT: vselvs.f16 s0, s8, s0
; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vcmp.f16 s8, s4
-; CHECK-MVE-NEXT: vmovx.f16 s4, s9
+; CHECK-MVE-NEXT: vmovx.f16 s4, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s13
+; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: vins.f16 s0, s16
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
-; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselvs.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vseleq.f16 s8, s9, s13
+; CHECK-MVE-NEXT: vselvs.f16 s1, s9, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s2
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vcmp.f16 s8, s4
-; CHECK-MVE-NEXT: vmovx.f16 s4, s10
+; CHECK-MVE-NEXT: vmovx.f16 s4, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
-; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
-; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselvs.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
+; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s14
+; CHECK-MVE-NEXT: vselvs.f16 s2, s10, s2
; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
-; CHECK-MVE-NEXT: vmovx.f16 s4, s11
+; CHECK-MVE-NEXT: vmovx.f16 s4, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s6, s15
+; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
-; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
+; CHECK-MVE-NEXT: vselvs.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
+; CHECK-MVE-NEXT: vseleq.f16 s6, s11, s15
+; CHECK-MVE-NEXT: vselvs.f16 s3, s11, s6
; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr
@@ -1151,65 +947,49 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ugt_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
-; CHECK-MVE-NEXT: vmovx.f16 s16, s4
-; CHECK-MVE-NEXT: vmovx.f16 s18, s0
+; CHECK-MVE-NEXT: vmovx.f16 s16, s0
+; CHECK-MVE-NEXT: vmovx.f16 s18, s4
; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s12
-; CHECK-MVE-NEXT: vmovx.f16 s4, s5
-; CHECK-MVE-NEXT: cset r0, hi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vcmp.f16 s4, s0
+; CHECK-MVE-NEXT: vmovx.f16 s4, s1
+; CHECK-MVE-NEXT: vselge.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, hi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
-; CHECK-MVE-NEXT: vmovx.f16 s8, s1
+; CHECK-MVE-NEXT: vselge.f16 s0, s12, s8
+; CHECK-MVE-NEXT: vmovx.f16 s8, s5
; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
-; CHECK-MVE-NEXT: vcmp.f16 s1, s5
+; CHECK-MVE-NEXT: vcmp.f16 s5, s1
; CHECK-MVE-NEXT: vins.f16 s0, s16
-; CHECK-MVE-NEXT: cset r0, hi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselge.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s2
-; CHECK-MVE-NEXT: cset r0, hi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
+; CHECK-MVE-NEXT: vmovx.f16 s8, s6
+; CHECK-MVE-NEXT: vselge.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s1, s4
-; CHECK-MVE-NEXT: vmovx.f16 s4, s6
+; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
-; CHECK-MVE-NEXT: vmovx.f16 s6, s3
-; CHECK-MVE-NEXT: cset r0, hi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vcmp.f16 s6, s2
+; CHECK-MVE-NEXT: vmovx.f16 s6, s7
+; CHECK-MVE-NEXT: vselge.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, hi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
+; CHECK-MVE-NEXT: vselge.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s2, s4
-; CHECK-MVE-NEXT: vmovx.f16 s4, s7
+; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s6, s15
-; CHECK-MVE-NEXT: vcmp.f16 s3, s7
-; CHECK-MVE-NEXT: cset r0, hi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
+; CHECK-MVE-NEXT: vcmp.f16 s7, s3
+; CHECK-MVE-NEXT: vselge.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, hi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
+; CHECK-MVE-NEXT: vselge.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr
@@ -1230,65 +1010,49 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_uge_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9}
-; CHECK-MVE-NEXT: vmovx.f16 s16, s4
-; CHECK-MVE-NEXT: vmovx.f16 s18, s0
+; CHECK-MVE-NEXT: vmovx.f16 s16, s0
+; CHECK-MVE-NEXT: vmovx.f16 s18, s4
; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s12
-; CHECK-MVE-NEXT: vmovx.f16 s4, s5
-; CHECK-MVE-NEXT: cset r0, pl
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vcmp.f16 s4, s0
+; CHECK-MVE-NEXT: vmovx.f16 s4, s1
+; CHECK-MVE-NEXT: vselgt.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, pl
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
-; CHECK-MVE-NEXT: vmovx.f16 s8, s1
+; CHECK-MVE-NEXT: vselgt.f16 s0, s12, s8
+; CHECK-MVE-NEXT: vmovx.f16 s8, s5
; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
-; CHECK-MVE-NEXT: vcmp.f16 s1, s5
+; CHECK-MVE-NEXT: vcmp.f16 s5, s1
; CHECK-MVE-NEXT: vins.f16 s0, s16
-; CHECK-MVE-NEXT: cset r0, pl
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselgt.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s2
-; CHECK-MVE-NEXT: cset r0, pl
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
+; CHECK-MVE-NEXT: vmovx.f16 s8, s6
+; CHECK-MVE-NEXT: vselgt.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s1, s4
-; CHECK-MVE-NEXT: vmovx.f16 s4, s6
+; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
-; CHECK-MVE-NEXT: vmovx.f16 s6, s3
-; CHECK-MVE-NEXT: cset r0, pl
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vcmp.f16 s6, s2
+; CHECK-MVE-NEXT: vmovx.f16 s6, s7
+; CHECK-MVE-NEXT: vselgt.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, pl
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
+; CHECK-MVE-NEXT: vselgt.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s2, s4
-; CHECK-MVE-NEXT: vmovx.f16 s4, s7
+; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s6, s15
-; CHECK-MVE-NEXT: vcmp.f16 s3, s7
-; CHECK-MVE-NEXT: cset r0, pl
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
+; CHECK-MVE-NEXT: vcmp.f16 s7, s3
+; CHECK-MVE-NEXT: vselgt.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, pl
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
+; CHECK-MVE-NEXT: vselgt.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr
@@ -1314,16 +1078,12 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ult_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s12
+; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s5
-; CHECK-MVE-NEXT: cset r0, lt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vselge.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, lt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
+; CHECK-MVE-NEXT: vselge.f16 s0, s12, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s9
@@ -1331,29 +1091,21 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ult_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: vins.f16 s0, s16
-; CHECK-MVE-NEXT: cset r0, lt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselge.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s2
-; CHECK-MVE-NEXT: cset r0, lt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
+; CHECK-MVE-NEXT: vselge.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
+; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
-; CHECK-MVE-NEXT: cset r0, lt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselge.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, lt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
+; CHECK-MVE-NEXT: vselge.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -1361,13 +1113,9 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ult_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
-; CHECK-MVE-NEXT: cset r0, lt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
+; CHECK-MVE-NEXT: vselge.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, lt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
+; CHECK-MVE-NEXT: vselge.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr
@@ -1393,16 +1141,12 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ule_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s12
+; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s5
-; CHECK-MVE-NEXT: cset r0, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vselgt.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
+; CHECK-MVE-NEXT: vselgt.f16 s0, s12, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s9
@@ -1410,29 +1154,21 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ule_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: vins.f16 s0, s16
-; CHECK-MVE-NEXT: cset r0, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselgt.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s2
-; CHECK-MVE-NEXT: cset r0, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
+; CHECK-MVE-NEXT: vselgt.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
+; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
-; CHECK-MVE-NEXT: cset r0, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselgt.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
+; CHECK-MVE-NEXT: vselgt.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -1440,13 +1176,9 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ule_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
-; CHECK-MVE-NEXT: cset r0, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
+; CHECK-MVE-NEXT: vselgt.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
+; CHECK-MVE-NEXT: vselgt.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr
@@ -1472,16 +1204,12 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ord_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s12
+; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s5
-; CHECK-MVE-NEXT: cset r0, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vselvs.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
+; CHECK-MVE-NEXT: vselvs.f16 s0, s12, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s9
@@ -1489,29 +1217,21 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ord_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: vins.f16 s0, s16
-; CHECK-MVE-NEXT: cset r0, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselvs.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s2
-; CHECK-MVE-NEXT: cset r0, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
+; CHECK-MVE-NEXT: vselvs.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
+; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
-; CHECK-MVE-NEXT: cset r0, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselvs.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
+; CHECK-MVE-NEXT: vselvs.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
@@ -1519,13 +1239,9 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ord_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
-; CHECK-MVE-NEXT: cset r0, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
+; CHECK-MVE-NEXT: vselvs.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
+; CHECK-MVE-NEXT: vselvs.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr
@@ -1550,62 +1266,46 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_uno_v8f16(<8 x half> %src, <8 x half> %s
; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16
-; CHECK-MVE-NEXT: vmovx.f16 s16, s8
+; CHECK-MVE-NEXT: vmovx.f16 s16, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vmovx.f16 s18, s8
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
-; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: vmovx.f16 s4, s5
-; CHECK-MVE-NEXT: cset r0, vs
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
+; CHECK-MVE-NEXT: vselvs.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, vs
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
+; CHECK-MVE-NEXT: vselvs.f16 s0, s8, s12
; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vcmp.f16 s8, s4
-; CHECK-MVE-NEXT: vmovx.f16 s4, s9
+; CHECK-MVE-NEXT: vmovx.f16 s4, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s13
+; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: vins.f16 s0, s16
-; CHECK-MVE-NEXT: cset r0, vs
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselvs.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s2
-; CHECK-MVE-NEXT: cset r0, vs
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
+; CHECK-MVE-NEXT: vselvs.f16 s1, s9, s13
; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vcmp.f16 s8, s4
-; CHECK-MVE-NEXT: vmovx.f16 s4, s10
+; CHECK-MVE-NEXT: vmovx.f16 s4, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
-; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
-; CHECK-MVE-NEXT: cset r0, vs
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselvs.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, vs
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
+; CHECK-MVE-NEXT: vselvs.f16 s2, s10, s14
; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
-; CHECK-MVE-NEXT: vmovx.f16 s4, s11
+; CHECK-MVE-NEXT: vmovx.f16 s4, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s6, s15
+; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
-; CHECK-MVE-NEXT: cset r0, vs
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
+; CHECK-MVE-NEXT: vselvs.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, vs
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
+; CHECK-MVE-NEXT: vselvs.f16 s3, s11, s15
; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr
diff --git a/llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll b/llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll
index 586b731c934be..018c8f266ea19 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll
@@ -5,26 +5,18 @@
define arm_aapcs_vfpcc <4 x float> @vcmp_oeq_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_oeq_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s3, s4
-; CHECK-MVE-NEXT: cset r0, eq
+; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, s4
-; CHECK-MVE-NEXT: cset r1, eq
+; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, s4
-; CHECK-MVE-NEXT: cset r2, eq
+; CHECK-MVE-NEXT: vcmp.f32 s3, s4
+; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, eq
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s15
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s12
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_oeq_v4f32:
@@ -44,30 +36,26 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_one_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_one_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s3, s4
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: csinc r0, r0, zr, le
+; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, s4
-; CHECK-MVE-NEXT: cset r1, mi
-; CHECK-MVE-NEXT: csinc r1, r1, zr, le
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s14, s10
+; CHECK-MVE-NEXT: vselgt.f32 s2, s10, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, s4
-; CHECK-MVE-NEXT: cset r2, mi
-; CHECK-MVE-NEXT: csinc r2, r2, zr, le
+; CHECK-MVE-NEXT: vcmp.f32 s3, s4
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s13, s9
+; CHECK-MVE-NEXT: vselgt.f32 s1, s9, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, mi
-; CHECK-MVE-NEXT: csinc r3, r3, zr, le
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s15, s11
+; CHECK-MVE-NEXT: vselgt.f32 s3, s11, s15
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s12, s8
+; CHECK-MVE-NEXT: vselgt.f32 s0, s8, s12
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_one_v4f32:
@@ -88,26 +76,18 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_ogt_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ogt_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s3, s4
-; CHECK-MVE-NEXT: cset r0, gt
+; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, s4
-; CHECK-MVE-NEXT: cset r1, gt
+; CHECK-MVE-NEXT: vselgt.f32 s2, s10, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, s4
-; CHECK-MVE-NEXT: cset r2, gt
+; CHECK-MVE-NEXT: vcmp.f32 s3, s4
+; CHECK-MVE-NEXT: vselgt.f32 s1, s9, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, gt
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vselgt.f32 s3, s11, s15
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vselgt.f32 s0, s8, s12
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_ogt_v4f32:
@@ -127,26 +107,18 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_oge_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_oge_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s3, s4
-; CHECK-MVE-NEXT: cset r0, ge
+; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, s4
-; CHECK-MVE-NEXT: cset r1, ge
+; CHECK-MVE-NEXT: vselge.f32 s2, s10, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, s4
-; CHECK-MVE-NEXT: cset r2, ge
+; CHECK-MVE-NEXT: vcmp.f32 s3, s4
+; CHECK-MVE-NEXT: vselge.f32 s1, s9, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, ge
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vselge.f32 s3, s11, s15
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vselge.f32 s0, s8, s12
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_oge_v4f32:
@@ -166,26 +138,18 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_olt_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_olt_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vcmp.f32 s4, s2
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s3, s4
-; CHECK-MVE-NEXT: cset r0, mi
+; CHECK-MVE-NEXT: vcmp.f32 s4, s1
+; CHECK-MVE-NEXT: vselgt.f32 s2, s10, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s1, s4
-; CHECK-MVE-NEXT: cset r1, mi
+; CHECK-MVE-NEXT: vcmp.f32 s4, s3
+; CHECK-MVE-NEXT: vselgt.f32 s1, s9, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, s4
-; CHECK-MVE-NEXT: cset r2, mi
+; CHECK-MVE-NEXT: vcmp.f32 s4, s0
+; CHECK-MVE-NEXT: vselgt.f32 s3, s11, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, mi
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: vselgt.f32 s0, s8, s12
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_olt_v4f32:
@@ -205,26 +169,18 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_ole_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ole_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vcmp.f32 s4, s2
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s3, s4
-; CHECK-MVE-NEXT: cset r0, ls
+; CHECK-MVE-NEXT: vcmp.f32 s4, s1
+; CHECK-MVE-NEXT: vselge.f32 s2, s10, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s1, s4
-; CHECK-MVE-NEXT: cset r1, ls
+; CHECK-MVE-NEXT: vcmp.f32 s4, s3
+; CHECK-MVE-NEXT: vselge.f32 s1, s9, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, s4
-; CHECK-MVE-NEXT: cset r2, ls
+; CHECK-MVE-NEXT: vcmp.f32 s4, s0
+; CHECK-MVE-NEXT: vselge.f32 s3, s11, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, ls
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: vselge.f32 s0, s8, s12
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_ole_v4f32:
@@ -244,30 +200,22 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_ueq_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ueq_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s3, s4
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
+; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, s4
-; CHECK-MVE-NEXT: cset r1, eq
-; CHECK-MVE-NEXT: csinc r1, r1, zr, vc
+; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s14
+; CHECK-MVE-NEXT: vselvs.f32 s2, s10, s2
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, s4
-; CHECK-MVE-NEXT: cset r2, eq
-; CHECK-MVE-NEXT: csinc r2, r2, zr, vc
+; CHECK-MVE-NEXT: vcmp.f32 s3, s4
+; CHECK-MVE-NEXT: vseleq.f32 s6, s9, s13
+; CHECK-MVE-NEXT: vselvs.f32 s1, s9, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, eq
-; CHECK-MVE-NEXT: csinc r3, r3, zr, vc
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vseleq.f32 s0, s11, s15
+; CHECK-MVE-NEXT: vselvs.f32 s3, s11, s0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s12
+; CHECK-MVE-NEXT: vselvs.f32 s0, s8, s0
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_ueq_v4f32:
@@ -319,26 +267,18 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_ugt_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ugt_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vcmp.f32 s4, s2
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s3, s4
-; CHECK-MVE-NEXT: cset r0, hi
+; CHECK-MVE-NEXT: vcmp.f32 s4, s1
+; CHECK-MVE-NEXT: vselge.f32 s2, s14, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s1, s4
-; CHECK-MVE-NEXT: cset r1, hi
+; CHECK-MVE-NEXT: vcmp.f32 s4, s3
+; CHECK-MVE-NEXT: vselge.f32 s1, s13, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, s4
-; CHECK-MVE-NEXT: cset r2, hi
+; CHECK-MVE-NEXT: vcmp.f32 s4, s0
+; CHECK-MVE-NEXT: vselge.f32 s3, s15, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, hi
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: vselge.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_ugt_v4f32:
@@ -358,26 +298,18 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_uge_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_uge_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vcmp.f32 s4, s2
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s3, s4
-; CHECK-MVE-NEXT: cset r0, pl
+; CHECK-MVE-NEXT: vcmp.f32 s4, s1
+; CHECK-MVE-NEXT: vselgt.f32 s2, s14, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s1, s4
-; CHECK-MVE-NEXT: cset r1, pl
+; CHECK-MVE-NEXT: vcmp.f32 s4, s3
+; CHECK-MVE-NEXT: vselgt.f32 s1, s13, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, s4
-; CHECK-MVE-NEXT: cset r2, pl
+; CHECK-MVE-NEXT: vcmp.f32 s4, s0
+; CHECK-MVE-NEXT: vselgt.f32 s3, s15, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, pl
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: vselgt.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_uge_v4f32:
@@ -397,26 +329,18 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_ult_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ult_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s3, s4
-; CHECK-MVE-NEXT: cset r0, lt
+; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, s4
-; CHECK-MVE-NEXT: cset r1, lt
+; CHECK-MVE-NEXT: vselge.f32 s2, s14, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, s4
-; CHECK-MVE-NEXT: cset r2, lt
+; CHECK-MVE-NEXT: vcmp.f32 s3, s4
+; CHECK-MVE-NEXT: vselge.f32 s1, s13, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, lt
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vselge.f32 s3, s15, s11
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vselge.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_ult_v4f32:
@@ -436,26 +360,18 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_ule_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ule_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s3, s4
-; CHECK-MVE-NEXT: cset r0, le
+; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, s4
-; CHECK-MVE-NEXT: cset r1, le
+; CHECK-MVE-NEXT: vselgt.f32 s2, s14, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, s4
-; CHECK-MVE-NEXT: cset r2, le
+; CHECK-MVE-NEXT: vcmp.f32 s3, s4
+; CHECK-MVE-NEXT: vselgt.f32 s1, s13, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, le
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vselgt.f32 s3, s15, s11
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vselgt.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_ule_v4f32:
@@ -475,26 +391,18 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_ord_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ord_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s3, s4
-; CHECK-MVE-NEXT: cset r0, vc
+; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, s4
-; CHECK-MVE-NEXT: cset r1, vc
+; CHECK-MVE-NEXT: vselvs.f32 s2, s14, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, s4
-; CHECK-MVE-NEXT: cset r2, vc
+; CHECK-MVE-NEXT: vcmp.f32 s3, s4
+; CHECK-MVE-NEXT: vselvs.f32 s1, s13, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, vc
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vselvs.f32 s3, s15, s11
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vselvs.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_ord_v4f32:
@@ -515,26 +423,18 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_uno_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_uno_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s3, s4
-; CHECK-MVE-NEXT: cset r0, vs
+; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, s4
-; CHECK-MVE-NEXT: cset r1, vs
+; CHECK-MVE-NEXT: vselvs.f32 s2, s10, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, s4
-; CHECK-MVE-NEXT: cset r2, vs
+; CHECK-MVE-NEXT: vcmp.f32 s3, s4
+; CHECK-MVE-NEXT: vselvs.f32 s1, s9, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, vs
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vselvs.f32 s3, s11, s15
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vselvs.f32 s0, s8, s12
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_uno_v4f32:
@@ -558,60 +458,44 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-LABEL: vcmp_oeq_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s12
+; CHECK-MVE-NEXT: vmovx.f16 s5, s8
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
-; CHECK-MVE-NEXT: vmovx.f16 s6, s8
+; CHECK-MVE-NEXT: vmovx.f16 s6, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
-; CHECK-MVE-NEXT: vmovx.f16 s8, s13
+; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s12
+; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
-; CHECK-MVE-NEXT: vmovx.f16 s6, s9
+; CHECK-MVE-NEXT: vmovx.f16 s6, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s14
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
+; CHECK-MVE-NEXT: vmovx.f16 s8, s10
+; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s13
; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
-; CHECK-MVE-NEXT: vmovx.f16 s6, s10
+; CHECK-MVE-NEXT: vmovx.f16 s6, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s15
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
+; CHECK-MVE-NEXT: vmovx.f16 s8, s11
+; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s14
; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
-; CHECK-MVE-NEXT: vmovx.f16 s6, s11
+; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
+; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s15
; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr
;
@@ -638,15 +522,13 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: csinc r0, r0, zr, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s5, s6
+; CHECK-MVE-NEXT: vselgt.f16 s6, s6, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: csinc r0, r0, zr, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s12, s8
+; CHECK-MVE-NEXT: vselgt.f16 s0, s8, s12
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
@@ -654,47 +536,41 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: csinc r0, r0, zr, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s8, s6
+; CHECK-MVE-NEXT: vselgt.f16 s6, s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s13, s9
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: csinc r0, r0, zr, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
+; CHECK-MVE-NEXT: vselgt.f16 s1, s9, s13
; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: csinc r0, r0, zr, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s8, s6
+; CHECK-MVE-NEXT: vselgt.f16 s6, s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s14, s10
; CHECK-MVE-NEXT: vmovx.f16 s8, s15
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: csinc r0, r0, zr, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
+; CHECK-MVE-NEXT: vselgt.f16 s2, s10, s14
; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: csinc r0, r0, zr, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s8, s6
+; CHECK-MVE-NEXT: vselgt.f16 s6, s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: csinc r0, r0, zr, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s15, s11
+; CHECK-MVE-NEXT: vselgt.f16 s3, s11, s15
; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr
;
@@ -717,60 +593,44 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ogt_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-LABEL: vcmp_ogt_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s12
+; CHECK-MVE-NEXT: vmovx.f16 s5, s8
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
-; CHECK-MVE-NEXT: vmovx.f16 s6, s8
+; CHECK-MVE-NEXT: vmovx.f16 s6, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
-; CHECK-MVE-NEXT: cset r0, gt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
+; CHECK-MVE-NEXT: vselgt.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, gt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
-; CHECK-MVE-NEXT: vmovx.f16 s8, s13
+; CHECK-MVE-NEXT: vselgt.f16 s0, s8, s12
+; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
-; CHECK-MVE-NEXT: vmovx.f16 s6, s9
+; CHECK-MVE-NEXT: vmovx.f16 s6, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
-; CHECK-MVE-NEXT: cset r0, gt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vselgt.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s14
-; CHECK-MVE-NEXT: cset r0, gt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
+; CHECK-MVE-NEXT: vmovx.f16 s8, s10
+; CHECK-MVE-NEXT: vselgt.f16 s1, s9, s13
; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
-; CHECK-MVE-NEXT: vmovx.f16 s6, s10
+; CHECK-MVE-NEXT: vmovx.f16 s6, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
-; CHECK-MVE-NEXT: cset r0, gt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vselgt.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s15
-; CHECK-MVE-NEXT: cset r0, gt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
+; CHECK-MVE-NEXT: vmovx.f16 s8, s11
+; CHECK-MVE-NEXT: vselgt.f16 s2, s10, s14
; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
-; CHECK-MVE-NEXT: vmovx.f16 s6, s11
+; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
-; CHECK-MVE-NEXT: cset r0, gt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vselgt.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, gt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
+; CHECK-MVE-NEXT: vselgt.f16 s3, s11, s15
; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr
;
@@ -792,60 +652,44 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_oge_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-LABEL: vcmp_oge_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s12
+; CHECK-MVE-NEXT: vmovx.f16 s5, s8
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
-; CHECK-MVE-NEXT: vmovx.f16 s6, s8
+; CHECK-MVE-NEXT: vmovx.f16 s6, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
-; CHECK-MVE-NEXT: cset r0, ge
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
+; CHECK-MVE-NEXT: vselge.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, ge
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
-; CHECK-MVE-NEXT: vmovx.f16 s8, s13
+; CHECK-MVE-NEXT: vselge.f16 s0, s8, s12
+; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
-; CHECK-MVE-NEXT: vmovx.f16 s6, s9
+; CHECK-MVE-NEXT: vmovx.f16 s6, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
-; CHECK-MVE-NEXT: cset r0, ge
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vselge.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s14
-; CHECK-MVE-NEXT: cset r0, ge
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
+; CHECK-MVE-NEXT: vmovx.f16 s8, s10
+; CHECK-MVE-NEXT: vselge.f16 s1, s9, s13
; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
-; CHECK-MVE-NEXT: vmovx.f16 s6, s10
+; CHECK-MVE-NEXT: vmovx.f16 s6, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
-; CHECK-MVE-NEXT: cset r0, ge
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vselge.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s15
-; CHECK-MVE-NEXT: cset r0, ge
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
+; CHECK-MVE-NEXT: vmovx.f16 s8, s11
+; CHECK-MVE-NEXT: vselge.f16 s2, s10, s14
; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
-; CHECK-MVE-NEXT: vmovx.f16 s6, s11
+; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
-; CHECK-MVE-NEXT: cset r0, ge
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vselge.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, ge
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
+; CHECK-MVE-NEXT: vselge.f16 s3, s11, s15
; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr
;
@@ -867,60 +711,44 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_olt_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-LABEL: vcmp_olt_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s12
-; CHECK-MVE-NEXT: vcmp.f16 s6, s4
-; CHECK-MVE-NEXT: vmovx.f16 s6, s8
+; CHECK-MVE-NEXT: vmovx.f16 s5, s8
+; CHECK-MVE-NEXT: vcmp.f16 s4, s6
+; CHECK-MVE-NEXT: vmovx.f16 s6, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s0, s4
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
+; CHECK-MVE-NEXT: vcmp.f16 s4, s0
+; CHECK-MVE-NEXT: vselgt.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
-; CHECK-MVE-NEXT: vmovx.f16 s8, s13
+; CHECK-MVE-NEXT: vselgt.f16 s0, s8, s12
+; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
-; CHECK-MVE-NEXT: vcmp.f16 s6, s4
-; CHECK-MVE-NEXT: vmovx.f16 s6, s9
+; CHECK-MVE-NEXT: vcmp.f16 s4, s6
+; CHECK-MVE-NEXT: vmovx.f16 s6, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s1, s4
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vcmp.f16 s4, s1
+; CHECK-MVE-NEXT: vselgt.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s14
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
+; CHECK-MVE-NEXT: vmovx.f16 s8, s10
+; CHECK-MVE-NEXT: vselgt.f16 s1, s9, s13
; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
-; CHECK-MVE-NEXT: vcmp.f16 s6, s4
-; CHECK-MVE-NEXT: vmovx.f16 s6, s10
+; CHECK-MVE-NEXT: vcmp.f16 s4, s6
+; CHECK-MVE-NEXT: vmovx.f16 s6, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s2, s4
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vcmp.f16 s4, s2
+; CHECK-MVE-NEXT: vselgt.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s15
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
+; CHECK-MVE-NEXT: vmovx.f16 s8, s11
+; CHECK-MVE-NEXT: vselgt.f16 s2, s10, s14
; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
-; CHECK-MVE-NEXT: vcmp.f16 s6, s4
-; CHECK-MVE-NEXT: vmovx.f16 s6, s11
+; CHECK-MVE-NEXT: vcmp.f16 s4, s6
+; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s3, s4
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vcmp.f16 s4, s3
+; CHECK-MVE-NEXT: vselgt.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
+; CHECK-MVE-NEXT: vselgt.f16 s3, s11, s15
; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr
;
@@ -942,60 +770,44 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ole_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-LABEL: vcmp_ole_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s12
-; CHECK-MVE-NEXT: vcmp.f16 s6, s4
-; CHECK-MVE-NEXT: vmovx.f16 s6, s8
+; CHECK-MVE-NEXT: vmovx.f16 s5, s8
+; CHECK-MVE-NEXT: vcmp.f16 s4, s6
+; CHECK-MVE-NEXT: vmovx.f16 s6, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s0, s4
-; CHECK-MVE-NEXT: cset r0, ls
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
+; CHECK-MVE-NEXT: vcmp.f16 s4, s0
+; CHECK-MVE-NEXT: vselge.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, ls
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
-; CHECK-MVE-NEXT: vmovx.f16 s8, s13
+; CHECK-MVE-NEXT: vselge.f16 s0, s8, s12
+; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
-; CHECK-MVE-NEXT: vcmp.f16 s6, s4
-; CHECK-MVE-NEXT: vmovx.f16 s6, s9
+; CHECK-MVE-NEXT: vcmp.f16 s4, s6
+; CHECK-MVE-NEXT: vmovx.f16 s6, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s1, s4
-; CHECK-MVE-NEXT: cset r0, ls
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vcmp.f16 s4, s1
+; CHECK-MVE-NEXT: vselge.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s14
-; CHECK-MVE-NEXT: cset r0, ls
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
+; CHECK-MVE-NEXT: vmovx.f16 s8, s10
+; CHECK-MVE-NEXT: vselge.f16 s1, s9, s13
; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
-; CHECK-MVE-NEXT: vcmp.f16 s6, s4
-; CHECK-MVE-NEXT: vmovx.f16 s6, s10
+; CHECK-MVE-NEXT: vcmp.f16 s4, s6
+; CHECK-MVE-NEXT: vmovx.f16 s6, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s2, s4
-; CHECK-MVE-NEXT: cset r0, ls
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vcmp.f16 s4, s2
+; CHECK-MVE-NEXT: vselge.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s15
-; CHECK-MVE-NEXT: cset r0, ls
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
+; CHECK-MVE-NEXT: vmovx.f16 s8, s11
+; CHECK-MVE-NEXT: vselge.f16 s2, s10, s14
; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
-; CHECK-MVE-NEXT: vcmp.f16 s6, s4
-; CHECK-MVE-NEXT: vmovx.f16 s6, s11
+; CHECK-MVE-NEXT: vcmp.f16 s4, s6
+; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s3, s4
-; CHECK-MVE-NEXT: cset r0, ls
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vcmp.f16 s4, s3
+; CHECK-MVE-NEXT: vselge.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, ls
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
+; CHECK-MVE-NEXT: vselge.f16 s3, s11, s15
; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr
;
@@ -1017,68 +829,52 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ueq_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-LABEL: vcmp_ueq_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s12
+; CHECK-MVE-NEXT: vmovx.f16 s5, s8
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
-; CHECK-MVE-NEXT: vmovx.f16 s6, s8
+; CHECK-MVE-NEXT: vmovx.f16 s6, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
-; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
+; CHECK-MVE-NEXT: vselvs.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
-; CHECK-MVE-NEXT: vmovx.f16 s8, s13
+; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s12
+; CHECK-MVE-NEXT: vselvs.f16 s0, s8, s0
+; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
-; CHECK-MVE-NEXT: vmovx.f16 s6, s9
+; CHECK-MVE-NEXT: vmovx.f16 s6, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
-; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vselvs.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s14
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
+; CHECK-MVE-NEXT: vseleq.f16 s8, s9, s13
+; CHECK-MVE-NEXT: vselvs.f16 s1, s9, s8
+; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
-; CHECK-MVE-NEXT: vmovx.f16 s6, s10
+; CHECK-MVE-NEXT: vmovx.f16 s6, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
-; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vselvs.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s15
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
+; CHECK-MVE-NEXT: vmovx.f16 s8, s11
+; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s14
+; CHECK-MVE-NEXT: vselvs.f16 s2, s10, s2
; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
-; CHECK-MVE-NEXT: vmovx.f16 s6, s11
+; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
-; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vselvs.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
+; CHECK-MVE-NEXT: vseleq.f16 s4, s11, s15
+; CHECK-MVE-NEXT: vselvs.f16 s3, s11, s4
; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr
;
@@ -1161,59 +957,43 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ugt_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
-; CHECK-MVE-NEXT: vcmp.f16 s6, s4
+; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s0, s4
-; CHECK-MVE-NEXT: cset r0, hi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
+; CHECK-MVE-NEXT: vcmp.f16 s4, s0
+; CHECK-MVE-NEXT: vselge.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, hi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
+; CHECK-MVE-NEXT: vselge.f16 s0, s12, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
-; CHECK-MVE-NEXT: vcmp.f16 s6, s4
+; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s1, s4
-; CHECK-MVE-NEXT: cset r0, hi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vcmp.f16 s4, s1
+; CHECK-MVE-NEXT: vselge.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
-; CHECK-MVE-NEXT: cset r0, hi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
+; CHECK-MVE-NEXT: vselge.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
-; CHECK-MVE-NEXT: vcmp.f16 s6, s4
+; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s2, s4
-; CHECK-MVE-NEXT: cset r0, hi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vcmp.f16 s4, s2
+; CHECK-MVE-NEXT: vselge.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s15
-; CHECK-MVE-NEXT: cset r0, hi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
+; CHECK-MVE-NEXT: vselge.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
-; CHECK-MVE-NEXT: vcmp.f16 s6, s4
+; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s3, s4
-; CHECK-MVE-NEXT: cset r0, hi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vcmp.f16 s4, s3
+; CHECK-MVE-NEXT: vselge.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, hi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
+; CHECK-MVE-NEXT: vselge.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr
;
@@ -1236,59 +1016,43 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_uge_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
-; CHECK-MVE-NEXT: vcmp.f16 s6, s4
+; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s0, s4
-; CHECK-MVE-NEXT: cset r0, pl
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
+; CHECK-MVE-NEXT: vcmp.f16 s4, s0
+; CHECK-MVE-NEXT: vselgt.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, pl
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
+; CHECK-MVE-NEXT: vselgt.f16 s0, s12, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
-; CHECK-MVE-NEXT: vcmp.f16 s6, s4
+; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s1, s4
-; CHECK-MVE-NEXT: cset r0, pl
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vcmp.f16 s4, s1
+; CHECK-MVE-NEXT: vselgt.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
-; CHECK-MVE-NEXT: cset r0, pl
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
+; CHECK-MVE-NEXT: vselgt.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
-; CHECK-MVE-NEXT: vcmp.f16 s6, s4
+; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s2, s4
-; CHECK-MVE-NEXT: cset r0, pl
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vcmp.f16 s4, s2
+; CHECK-MVE-NEXT: vselgt.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s15
-; CHECK-MVE-NEXT: cset r0, pl
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
+; CHECK-MVE-NEXT: vselgt.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
-; CHECK-MVE-NEXT: vcmp.f16 s6, s4
+; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s3, s4
-; CHECK-MVE-NEXT: cset r0, pl
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vcmp.f16 s4, s3
+; CHECK-MVE-NEXT: vselgt.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, pl
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
+; CHECK-MVE-NEXT: vselgt.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr
;
@@ -1315,13 +1079,9 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ult_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
-; CHECK-MVE-NEXT: cset r0, lt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
+; CHECK-MVE-NEXT: vselge.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, lt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
+; CHECK-MVE-NEXT: vselge.f16 s0, s12, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
@@ -1329,41 +1089,29 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ult_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
-; CHECK-MVE-NEXT: cset r0, lt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vselge.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
-; CHECK-MVE-NEXT: cset r0, lt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
+; CHECK-MVE-NEXT: vselge.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
-; CHECK-MVE-NEXT: cset r0, lt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vselge.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s15
-; CHECK-MVE-NEXT: cset r0, lt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
+; CHECK-MVE-NEXT: vselge.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
-; CHECK-MVE-NEXT: cset r0, lt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vselge.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, lt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
+; CHECK-MVE-NEXT: vselge.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr
;
@@ -1390,13 +1138,9 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ule_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
-; CHECK-MVE-NEXT: cset r0, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
+; CHECK-MVE-NEXT: vselgt.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
+; CHECK-MVE-NEXT: vselgt.f16 s0, s12, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
@@ -1404,41 +1148,29 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ule_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
-; CHECK-MVE-NEXT: cset r0, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vselgt.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
-; CHECK-MVE-NEXT: cset r0, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
+; CHECK-MVE-NEXT: vselgt.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
-; CHECK-MVE-NEXT: cset r0, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vselgt.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s15
-; CHECK-MVE-NEXT: cset r0, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
+; CHECK-MVE-NEXT: vselgt.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
-; CHECK-MVE-NEXT: cset r0, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vselgt.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
+; CHECK-MVE-NEXT: vselgt.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr
;
@@ -1465,13 +1197,9 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ord_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
-; CHECK-MVE-NEXT: cset r0, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
+; CHECK-MVE-NEXT: vselvs.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
+; CHECK-MVE-NEXT: vselvs.f16 s0, s12, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
@@ -1479,41 +1207,29 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ord_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
-; CHECK-MVE-NEXT: cset r0, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vselvs.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
-; CHECK-MVE-NEXT: cset r0, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
+; CHECK-MVE-NEXT: vselvs.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
-; CHECK-MVE-NEXT: cset r0, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vselvs.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s15
-; CHECK-MVE-NEXT: cset r0, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
+; CHECK-MVE-NEXT: vselvs.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
-; CHECK-MVE-NEXT: cset r0, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vselvs.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
+; CHECK-MVE-NEXT: vselvs.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr
;
@@ -1536,60 +1252,44 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_uno_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-LABEL: vcmp_uno_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s12
+; CHECK-MVE-NEXT: vmovx.f16 s5, s8
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
-; CHECK-MVE-NEXT: vmovx.f16 s6, s8
+; CHECK-MVE-NEXT: vmovx.f16 s6, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
-; CHECK-MVE-NEXT: cset r0, vs
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
+; CHECK-MVE-NEXT: vselvs.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, vs
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
-; CHECK-MVE-NEXT: vmovx.f16 s8, s13
+; CHECK-MVE-NEXT: vselvs.f16 s0, s8, s12
+; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
-; CHECK-MVE-NEXT: vmovx.f16 s6, s9
+; CHECK-MVE-NEXT: vmovx.f16 s6, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
-; CHECK-MVE-NEXT: cset r0, vs
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vselvs.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s14
-; CHECK-MVE-NEXT: cset r0, vs
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
+; CHECK-MVE-NEXT: vmovx.f16 s8, s10
+; CHECK-MVE-NEXT: vselvs.f16 s1, s9, s13
; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
-; CHECK-MVE-NEXT: vmovx.f16 s6, s10
+; CHECK-MVE-NEXT: vmovx.f16 s6, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
-; CHECK-MVE-NEXT: cset r0, vs
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vselvs.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s15
-; CHECK-MVE-NEXT: cset r0, vs
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
+; CHECK-MVE-NEXT: vmovx.f16 s8, s11
+; CHECK-MVE-NEXT: vselvs.f16 s2, s10, s14
; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
-; CHECK-MVE-NEXT: vmovx.f16 s6, s11
+; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
-; CHECK-MVE-NEXT: cset r0, vs
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vselvs.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, vs
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
+; CHECK-MVE-NEXT: vselvs.f16 s3, s11, s15
; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr
;
@@ -1614,26 +1314,18 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_oeq_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_oeq_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s4, s0
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s4, s3
-; CHECK-MVE-NEXT: cset r0, eq
+; CHECK-MVE-NEXT: vcmp.f32 s4, s2
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, s1
-; CHECK-MVE-NEXT: cset r1, eq
+; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s4, s2
-; CHECK-MVE-NEXT: cset r2, eq
+; CHECK-MVE-NEXT: vcmp.f32 s4, s3
+; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, eq
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: vcmp.f32 s4, s0
+; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s15
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s12
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_r_oeq_v4f32:
@@ -1653,30 +1345,26 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_one_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_one_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s4, s0
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s4, s3
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: csinc r0, r0, zr, le
+; CHECK-MVE-NEXT: vcmp.f32 s4, s2
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, s1
-; CHECK-MVE-NEXT: cset r1, mi
-; CHECK-MVE-NEXT: csinc r1, r1, zr, le
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s14, s10
+; CHECK-MVE-NEXT: vselgt.f32 s2, s10, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s4, s2
-; CHECK-MVE-NEXT: cset r2, mi
-; CHECK-MVE-NEXT: csinc r2, r2, zr, le
+; CHECK-MVE-NEXT: vcmp.f32 s4, s3
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s13, s9
+; CHECK-MVE-NEXT: vselgt.f32 s1, s9, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, mi
-; CHECK-MVE-NEXT: csinc r3, r3, zr, le
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: vcmp.f32 s4, s0
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s15, s11
+; CHECK-MVE-NEXT: vselgt.f32 s3, s11, s15
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s12, s8
+; CHECK-MVE-NEXT: vselgt.f32 s0, s8, s12
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_r_one_v4f32:
@@ -1697,26 +1385,18 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_ogt_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_ogt_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s4, s0
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s4, s3
-; CHECK-MVE-NEXT: cset r0, gt
+; CHECK-MVE-NEXT: vcmp.f32 s4, s2
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, s1
-; CHECK-MVE-NEXT: cset r1, gt
+; CHECK-MVE-NEXT: vselgt.f32 s2, s10, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s4, s2
-; CHECK-MVE-NEXT: cset r2, gt
+; CHECK-MVE-NEXT: vcmp.f32 s4, s3
+; CHECK-MVE-NEXT: vselgt.f32 s1, s9, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, gt
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: vcmp.f32 s4, s0
+; CHECK-MVE-NEXT: vselgt.f32 s3, s11, s15
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vselgt.f32 s0, s8, s12
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_r_ogt_v4f32:
@@ -1736,26 +1416,18 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_oge_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_oge_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s4, s0
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s4, s3
-; CHECK-MVE-NEXT: cset r0, ge
+; CHECK-MVE-NEXT: vcmp.f32 s4, s2
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, s1
-; CHECK-MVE-NEXT: cset r1, ge
+; CHECK-MVE-NEXT: vselge.f32 s2, s10, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s4, s2
-; CHECK-MVE-NEXT: cset r2, ge
+; CHECK-MVE-NEXT: vcmp.f32 s4, s3
+; CHECK-MVE-NEXT: vselge.f32 s1, s9, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, ge
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: vcmp.f32 s4, s0
+; CHECK-MVE-NEXT: vselge.f32 s3, s11, s15
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vselge.f32 s0, s8, s12
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_r_oge_v4f32:
@@ -1775,26 +1447,18 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_olt_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_olt_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s4, s0
+; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s4, s3
-; CHECK-MVE-NEXT: cset r0, mi
+; CHECK-MVE-NEXT: vcmp.f32 s1, s4
+; CHECK-MVE-NEXT: vselgt.f32 s2, s10, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s4, s1
-; CHECK-MVE-NEXT: cset r1, mi
+; CHECK-MVE-NEXT: vcmp.f32 s3, s4
+; CHECK-MVE-NEXT: vselgt.f32 s1, s9, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s4, s2
-; CHECK-MVE-NEXT: cset r2, mi
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vselgt.f32 s3, s11, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, mi
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: vselgt.f32 s0, s8, s12
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_r_olt_v4f32:
@@ -1814,26 +1478,18 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_ole_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_ole_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s4, s0
+; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s4, s3
-; CHECK-MVE-NEXT: cset r0, ls
+; CHECK-MVE-NEXT: vcmp.f32 s1, s4
+; CHECK-MVE-NEXT: vselge.f32 s2, s10, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s4, s1
-; CHECK-MVE-NEXT: cset r1, ls
+; CHECK-MVE-NEXT: vcmp.f32 s3, s4
+; CHECK-MVE-NEXT: vselge.f32 s1, s9, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s4, s2
-; CHECK-MVE-NEXT: cset r2, ls
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vselge.f32 s3, s11, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, ls
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: vselge.f32 s0, s8, s12
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_r_ole_v4f32:
@@ -1853,30 +1509,22 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_ueq_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_ueq_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s4, s0
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s4, s3
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
+; CHECK-MVE-NEXT: vcmp.f32 s4, s2
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, s1
-; CHECK-MVE-NEXT: cset r1, eq
-; CHECK-MVE-NEXT: csinc r1, r1, zr, vc
+; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s14
+; CHECK-MVE-NEXT: vselvs.f32 s2, s10, s2
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s4, s2
-; CHECK-MVE-NEXT: cset r2, eq
-; CHECK-MVE-NEXT: csinc r2, r2, zr, vc
+; CHECK-MVE-NEXT: vcmp.f32 s4, s3
+; CHECK-MVE-NEXT: vseleq.f32 s6, s9, s13
+; CHECK-MVE-NEXT: vselvs.f32 s1, s9, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, eq
-; CHECK-MVE-NEXT: csinc r3, r3, zr, vc
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: vcmp.f32 s4, s0
+; CHECK-MVE-NEXT: vseleq.f32 s0, s11, s15
+; CHECK-MVE-NEXT: vselvs.f32 s3, s11, s0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s12
+; CHECK-MVE-NEXT: vselvs.f32 s0, s8, s0
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_r_ueq_v4f32:
@@ -1928,26 +1576,18 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_ugt_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_ugt_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s4, s0
+; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s4, s3
-; CHECK-MVE-NEXT: cset r0, hi
+; CHECK-MVE-NEXT: vcmp.f32 s1, s4
+; CHECK-MVE-NEXT: vselge.f32 s2, s14, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s4, s1
-; CHECK-MVE-NEXT: cset r1, hi
+; CHECK-MVE-NEXT: vcmp.f32 s3, s4
+; CHECK-MVE-NEXT: vselge.f32 s1, s13, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s4, s2
-; CHECK-MVE-NEXT: cset r2, hi
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vselge.f32 s3, s15, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, hi
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: vselge.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_r_ugt_v4f32:
@@ -1967,26 +1607,18 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_uge_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_uge_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s4, s0
+; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s4, s3
-; CHECK-MVE-NEXT: cset r0, pl
+; CHECK-MVE-NEXT: vcmp.f32 s1, s4
+; CHECK-MVE-NEXT: vselgt.f32 s2, s14, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s4, s1
-; CHECK-MVE-NEXT: cset r1, pl
+; CHECK-MVE-NEXT: vcmp.f32 s3, s4
+; CHECK-MVE-NEXT: vselgt.f32 s1, s13, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s4, s2
-; CHECK-MVE-NEXT: cset r2, pl
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vselgt.f32 s3, s15, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, pl
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: vselgt.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_r_uge_v4f32:
@@ -2006,26 +1638,18 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_ult_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_ult_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s4, s0
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s4, s3
-; CHECK-MVE-NEXT: cset r0, lt
+; CHECK-MVE-NEXT: vcmp.f32 s4, s2
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, s1
-; CHECK-MVE-NEXT: cset r1, lt
+; CHECK-MVE-NEXT: vselge.f32 s2, s14, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s4, s2
-; CHECK-MVE-NEXT: cset r2, lt
+; CHECK-MVE-NEXT: vcmp.f32 s4, s3
+; CHECK-MVE-NEXT: vselge.f32 s1, s13, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, lt
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: vcmp.f32 s4, s0
+; CHECK-MVE-NEXT: vselge.f32 s3, s15, s11
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vselge.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_r_ult_v4f32:
@@ -2045,26 +1669,18 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_ule_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_ule_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s4, s0
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s4, s3
-; CHECK-MVE-NEXT: cset r0, le
+; CHECK-MVE-NEXT: vcmp.f32 s4, s2
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, s1
-; CHECK-MVE-NEXT: cset r1, le
+; CHECK-MVE-NEXT: vselgt.f32 s2, s14, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s4, s2
-; CHECK-MVE-NEXT: cset r2, le
+; CHECK-MVE-NEXT: vcmp.f32 s4, s3
+; CHECK-MVE-NEXT: vselgt.f32 s1, s13, s9
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f32 s4, s0
+; CHECK-MVE-NEXT: vselgt.f32 s3, s15, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, le
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: vselgt.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_r_ule_v4f32:
@@ -2084,26 +1700,18 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_ord_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_ord_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s4, s0
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s4, s3
-; CHECK-MVE-NEXT: cset r0, vc
+; CHECK-MVE-NEXT: vcmp.f32 s4, s2
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, s1
-; CHECK-MVE-NEXT: cset r1, vc
+; CHECK-MVE-NEXT: vselvs.f32 s2, s14, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s4, s2
-; CHECK-MVE-NEXT: cset r2, vc
+; CHECK-MVE-NEXT: vcmp.f32 s4, s3
+; CHECK-MVE-NEXT: vselvs.f32 s1, s13, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, vc
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: vcmp.f32 s4, s0
+; CHECK-MVE-NEXT: vselvs.f32 s3, s15, s11
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vselvs.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_r_ord_v4f32:
@@ -2124,26 +1732,18 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_uno_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_uno_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s4, s0
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s4, s3
-; CHECK-MVE-NEXT: cset r0, vs
+; CHECK-MVE-NEXT: vcmp.f32 s4, s2
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, s1
-; CHECK-MVE-NEXT: cset r1, vs
+; CHECK-MVE-NEXT: vselvs.f32 s2, s10, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s4, s2
-; CHECK-MVE-NEXT: cset r2, vs
+; CHECK-MVE-NEXT: vcmp.f32 s4, s3
+; CHECK-MVE-NEXT: vselvs.f32 s1, s9, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, vs
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
+; CHECK-MVE-NEXT: vcmp.f32 s4, s0
+; CHECK-MVE-NEXT: vselvs.f32 s3, s11, s15
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vselvs.f32 s0, s8, s12
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_r_uno_v4f32:
@@ -2167,60 +1767,44 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_oeq_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-LABEL: vcmp_r_oeq_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s12
+; CHECK-MVE-NEXT: vmovx.f16 s5, s8
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
-; CHECK-MVE-NEXT: vmovx.f16 s6, s8
+; CHECK-MVE-NEXT: vmovx.f16 s6, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
-; CHECK-MVE-NEXT: vmovx.f16 s8, s13
+; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s12
+; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
-; CHECK-MVE-NEXT: vmovx.f16 s6, s9
+; CHECK-MVE-NEXT: vmovx.f16 s6, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s14
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
+; CHECK-MVE-NEXT: vmovx.f16 s8, s10
+; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s13
; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
-; CHECK-MVE-NEXT: vmovx.f16 s6, s10
+; CHECK-MVE-NEXT: vmovx.f16 s6, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s15
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
+; CHECK-MVE-NEXT: vmovx.f16 s8, s11
+; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s14
; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
-; CHECK-MVE-NEXT: vmovx.f16 s6, s11
+; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
+; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s15
; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr
;
@@ -2247,15 +1831,13 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_one_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: csinc r0, r0, zr, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s5, s6
+; CHECK-MVE-NEXT: vselgt.f16 s6, s6, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: csinc r0, r0, zr, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s12, s8
+; CHECK-MVE-NEXT: vselgt.f16 s0, s8, s12
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
@@ -2263,47 +1845,41 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_one_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: csinc r0, r0, zr, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s8, s6
+; CHECK-MVE-NEXT: vselgt.f16 s6, s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s13, s9
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: csinc r0, r0, zr, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
+; CHECK-MVE-NEXT: vselgt.f16 s1, s9, s13
; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: csinc r0, r0, zr, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s8, s6
+; CHECK-MVE-NEXT: vselgt.f16 s6, s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s14, s10
; CHECK-MVE-NEXT: vmovx.f16 s8, s15
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: csinc r0, r0, zr, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
+; CHECK-MVE-NEXT: vselgt.f16 s2, s10, s14
; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: csinc r0, r0, zr, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s8, s6
+; CHECK-MVE-NEXT: vselgt.f16 s6, s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: csinc r0, r0, zr, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s15, s11
+; CHECK-MVE-NEXT: vselgt.f16 s3, s11, s15
; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr
;
@@ -2326,60 +1902,44 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ogt_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-LABEL: vcmp_r_ogt_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s12
+; CHECK-MVE-NEXT: vmovx.f16 s5, s8
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
-; CHECK-MVE-NEXT: vmovx.f16 s6, s8
+; CHECK-MVE-NEXT: vmovx.f16 s6, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
-; CHECK-MVE-NEXT: cset r0, gt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
+; CHECK-MVE-NEXT: vselgt.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, gt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
-; CHECK-MVE-NEXT: vmovx.f16 s8, s13
+; CHECK-MVE-NEXT: vselgt.f16 s0, s8, s12
+; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
-; CHECK-MVE-NEXT: vmovx.f16 s6, s9
+; CHECK-MVE-NEXT: vmovx.f16 s6, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
-; CHECK-MVE-NEXT: cset r0, gt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vselgt.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s14
-; CHECK-MVE-NEXT: cset r0, gt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
+; CHECK-MVE-NEXT: vmovx.f16 s8, s10
+; CHECK-MVE-NEXT: vselgt.f16 s1, s9, s13
; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
-; CHECK-MVE-NEXT: vmovx.f16 s6, s10
+; CHECK-MVE-NEXT: vmovx.f16 s6, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
-; CHECK-MVE-NEXT: cset r0, gt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vselgt.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s15
-; CHECK-MVE-NEXT: cset r0, gt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
+; CHECK-MVE-NEXT: vmovx.f16 s8, s11
+; CHECK-MVE-NEXT: vselgt.f16 s2, s10, s14
; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
-; CHECK-MVE-NEXT: vmovx.f16 s6, s11
+; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
-; CHECK-MVE-NEXT: cset r0, gt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vselgt.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, gt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
+; CHECK-MVE-NEXT: vselgt.f16 s3, s11, s15
; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr
;
@@ -2401,60 +1961,44 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_oge_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-LABEL: vcmp_r_oge_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s12
+; CHECK-MVE-NEXT: vmovx.f16 s5, s8
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
-; CHECK-MVE-NEXT: vmovx.f16 s6, s8
+; CHECK-MVE-NEXT: vmovx.f16 s6, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
-; CHECK-MVE-NEXT: cset r0, ge
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
+; CHECK-MVE-NEXT: vselge.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, ge
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
-; CHECK-MVE-NEXT: vmovx.f16 s8, s13
+; CHECK-MVE-NEXT: vselge.f16 s0, s8, s12
+; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
-; CHECK-MVE-NEXT: vmovx.f16 s6, s9
+; CHECK-MVE-NEXT: vmovx.f16 s6, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
-; CHECK-MVE-NEXT: cset r0, ge
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vselge.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s14
-; CHECK-MVE-NEXT: cset r0, ge
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
+; CHECK-MVE-NEXT: vmovx.f16 s8, s10
+; CHECK-MVE-NEXT: vselge.f16 s1, s9, s13
; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
-; CHECK-MVE-NEXT: vmovx.f16 s6, s10
+; CHECK-MVE-NEXT: vmovx.f16 s6, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
-; CHECK-MVE-NEXT: cset r0, ge
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vselge.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s15
-; CHECK-MVE-NEXT: cset r0, ge
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
+; CHECK-MVE-NEXT: vmovx.f16 s8, s11
+; CHECK-MVE-NEXT: vselge.f16 s2, s10, s14
; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
-; CHECK-MVE-NEXT: vmovx.f16 s6, s11
+; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
-; CHECK-MVE-NEXT: cset r0, ge
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vselge.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, ge
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
+; CHECK-MVE-NEXT: vselge.f16 s3, s11, s15
; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr
;
@@ -2476,60 +2020,44 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_olt_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-LABEL: vcmp_r_olt_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s12
-; CHECK-MVE-NEXT: vcmp.f16 s4, s6
-; CHECK-MVE-NEXT: vmovx.f16 s6, s8
+; CHECK-MVE-NEXT: vmovx.f16 s5, s8
+; CHECK-MVE-NEXT: vcmp.f16 s6, s4
+; CHECK-MVE-NEXT: vmovx.f16 s6, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s4, s0
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
+; CHECK-MVE-NEXT: vcmp.f16 s0, s4
+; CHECK-MVE-NEXT: vselgt.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
-; CHECK-MVE-NEXT: vmovx.f16 s8, s13
+; CHECK-MVE-NEXT: vselgt.f16 s0, s8, s12
+; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
-; CHECK-MVE-NEXT: vcmp.f16 s4, s6
-; CHECK-MVE-NEXT: vmovx.f16 s6, s9
+; CHECK-MVE-NEXT: vcmp.f16 s6, s4
+; CHECK-MVE-NEXT: vmovx.f16 s6, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s4, s1
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vcmp.f16 s1, s4
+; CHECK-MVE-NEXT: vselgt.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s14
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
+; CHECK-MVE-NEXT: vmovx.f16 s8, s10
+; CHECK-MVE-NEXT: vselgt.f16 s1, s9, s13
; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
-; CHECK-MVE-NEXT: vcmp.f16 s4, s6
-; CHECK-MVE-NEXT: vmovx.f16 s6, s10
+; CHECK-MVE-NEXT: vcmp.f16 s6, s4
+; CHECK-MVE-NEXT: vmovx.f16 s6, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s4, s2
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vcmp.f16 s2, s4
+; CHECK-MVE-NEXT: vselgt.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s15
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
+; CHECK-MVE-NEXT: vmovx.f16 s8, s11
+; CHECK-MVE-NEXT: vselgt.f16 s2, s10, s14
; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
-; CHECK-MVE-NEXT: vcmp.f16 s4, s6
-; CHECK-MVE-NEXT: vmovx.f16 s6, s11
+; CHECK-MVE-NEXT: vcmp.f16 s6, s4
+; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s4, s3
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vcmp.f16 s3, s4
+; CHECK-MVE-NEXT: vselgt.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
+; CHECK-MVE-NEXT: vselgt.f16 s3, s11, s15
; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr
;
@@ -2551,60 +2079,44 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ole_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-LABEL: vcmp_r_ole_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s12
-; CHECK-MVE-NEXT: vcmp.f16 s4, s6
-; CHECK-MVE-NEXT: vmovx.f16 s6, s8
+; CHECK-MVE-NEXT: vmovx.f16 s5, s8
+; CHECK-MVE-NEXT: vcmp.f16 s6, s4
+; CHECK-MVE-NEXT: vmovx.f16 s6, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s4, s0
-; CHECK-MVE-NEXT: cset r0, ls
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
+; CHECK-MVE-NEXT: vcmp.f16 s0, s4
+; CHECK-MVE-NEXT: vselge.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, ls
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
-; CHECK-MVE-NEXT: vmovx.f16 s8, s13
+; CHECK-MVE-NEXT: vselge.f16 s0, s8, s12
+; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
-; CHECK-MVE-NEXT: vcmp.f16 s4, s6
-; CHECK-MVE-NEXT: vmovx.f16 s6, s9
+; CHECK-MVE-NEXT: vcmp.f16 s6, s4
+; CHECK-MVE-NEXT: vmovx.f16 s6, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s4, s1
-; CHECK-MVE-NEXT: cset r0, ls
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vcmp.f16 s1, s4
+; CHECK-MVE-NEXT: vselge.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s14
-; CHECK-MVE-NEXT: cset r0, ls
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
+; CHECK-MVE-NEXT: vmovx.f16 s8, s10
+; CHECK-MVE-NEXT: vselge.f16 s1, s9, s13
; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
-; CHECK-MVE-NEXT: vcmp.f16 s4, s6
-; CHECK-MVE-NEXT: vmovx.f16 s6, s10
+; CHECK-MVE-NEXT: vcmp.f16 s6, s4
+; CHECK-MVE-NEXT: vmovx.f16 s6, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s4, s2
-; CHECK-MVE-NEXT: cset r0, ls
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vcmp.f16 s2, s4
+; CHECK-MVE-NEXT: vselge.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s15
-; CHECK-MVE-NEXT: cset r0, ls
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
+; CHECK-MVE-NEXT: vmovx.f16 s8, s11
+; CHECK-MVE-NEXT: vselge.f16 s2, s10, s14
; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
-; CHECK-MVE-NEXT: vcmp.f16 s4, s6
-; CHECK-MVE-NEXT: vmovx.f16 s6, s11
+; CHECK-MVE-NEXT: vcmp.f16 s6, s4
+; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s4, s3
-; CHECK-MVE-NEXT: cset r0, ls
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vcmp.f16 s3, s4
+; CHECK-MVE-NEXT: vselge.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, ls
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
+; CHECK-MVE-NEXT: vselge.f16 s3, s11, s15
; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr
;
@@ -2626,68 +2138,52 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ueq_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-LABEL: vcmp_r_ueq_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s12
+; CHECK-MVE-NEXT: vmovx.f16 s5, s8
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
-; CHECK-MVE-NEXT: vmovx.f16 s6, s8
+; CHECK-MVE-NEXT: vmovx.f16 s6, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
-; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
+; CHECK-MVE-NEXT: vselvs.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
-; CHECK-MVE-NEXT: vmovx.f16 s8, s13
+; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s12
+; CHECK-MVE-NEXT: vselvs.f16 s0, s8, s0
+; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
-; CHECK-MVE-NEXT: vmovx.f16 s6, s9
+; CHECK-MVE-NEXT: vmovx.f16 s6, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
-; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vselvs.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s14
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
+; CHECK-MVE-NEXT: vseleq.f16 s8, s9, s13
+; CHECK-MVE-NEXT: vselvs.f16 s1, s9, s8
+; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
-; CHECK-MVE-NEXT: vmovx.f16 s6, s10
+; CHECK-MVE-NEXT: vmovx.f16 s6, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
-; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vselvs.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s15
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
+; CHECK-MVE-NEXT: vmovx.f16 s8, s11
+; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s14
+; CHECK-MVE-NEXT: vselvs.f16 s2, s10, s2
; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
-; CHECK-MVE-NEXT: vmovx.f16 s6, s11
+; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
-; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vselvs.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
+; CHECK-MVE-NEXT: vseleq.f16 s4, s11, s15
+; CHECK-MVE-NEXT: vselvs.f16 s3, s11, s4
; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr
;
@@ -2770,59 +2266,43 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ugt_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
-; CHECK-MVE-NEXT: vcmp.f16 s4, s6
+; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s4, s0
-; CHECK-MVE-NEXT: cset r0, hi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
+; CHECK-MVE-NEXT: vcmp.f16 s0, s4
+; CHECK-MVE-NEXT: vselge.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, hi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
+; CHECK-MVE-NEXT: vselge.f16 s0, s12, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
-; CHECK-MVE-NEXT: vcmp.f16 s4, s6
+; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s4, s1
-; CHECK-MVE-NEXT: cset r0, hi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vcmp.f16 s1, s4
+; CHECK-MVE-NEXT: vselge.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
-; CHECK-MVE-NEXT: cset r0, hi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
+; CHECK-MVE-NEXT: vselge.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
-; CHECK-MVE-NEXT: vcmp.f16 s4, s6
+; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s4, s2
-; CHECK-MVE-NEXT: cset r0, hi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vcmp.f16 s2, s4
+; CHECK-MVE-NEXT: vselge.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s15
-; CHECK-MVE-NEXT: cset r0, hi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
+; CHECK-MVE-NEXT: vselge.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
-; CHECK-MVE-NEXT: vcmp.f16 s4, s6
+; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s4, s3
-; CHECK-MVE-NEXT: cset r0, hi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vcmp.f16 s3, s4
+; CHECK-MVE-NEXT: vselge.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, hi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
+; CHECK-MVE-NEXT: vselge.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr
;
@@ -2845,59 +2325,43 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_uge_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
-; CHECK-MVE-NEXT: vcmp.f16 s4, s6
+; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s4, s0
-; CHECK-MVE-NEXT: cset r0, pl
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
+; CHECK-MVE-NEXT: vcmp.f16 s0, s4
+; CHECK-MVE-NEXT: vselgt.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, pl
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
+; CHECK-MVE-NEXT: vselgt.f16 s0, s12, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
-; CHECK-MVE-NEXT: vcmp.f16 s4, s6
+; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s4, s1
-; CHECK-MVE-NEXT: cset r0, pl
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vcmp.f16 s1, s4
+; CHECK-MVE-NEXT: vselgt.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
-; CHECK-MVE-NEXT: cset r0, pl
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
+; CHECK-MVE-NEXT: vselgt.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
-; CHECK-MVE-NEXT: vcmp.f16 s4, s6
+; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s4, s2
-; CHECK-MVE-NEXT: cset r0, pl
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vcmp.f16 s2, s4
+; CHECK-MVE-NEXT: vselgt.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s15
-; CHECK-MVE-NEXT: cset r0, pl
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
+; CHECK-MVE-NEXT: vselgt.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
-; CHECK-MVE-NEXT: vcmp.f16 s4, s6
+; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s4, s3
-; CHECK-MVE-NEXT: cset r0, pl
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vcmp.f16 s3, s4
+; CHECK-MVE-NEXT: vselgt.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, pl
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
+; CHECK-MVE-NEXT: vselgt.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr
;
@@ -2924,13 +2388,9 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ult_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
-; CHECK-MVE-NEXT: cset r0, lt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
+; CHECK-MVE-NEXT: vselge.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, lt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
+; CHECK-MVE-NEXT: vselge.f16 s0, s12, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
@@ -2938,41 +2398,29 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ult_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
-; CHECK-MVE-NEXT: cset r0, lt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vselge.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
-; CHECK-MVE-NEXT: cset r0, lt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
+; CHECK-MVE-NEXT: vselge.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
-; CHECK-MVE-NEXT: cset r0, lt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vselge.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s15
-; CHECK-MVE-NEXT: cset r0, lt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
+; CHECK-MVE-NEXT: vselge.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
-; CHECK-MVE-NEXT: cset r0, lt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vselge.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, lt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
+; CHECK-MVE-NEXT: vselge.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr
;
@@ -2999,13 +2447,9 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ule_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
-; CHECK-MVE-NEXT: cset r0, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
+; CHECK-MVE-NEXT: vselgt.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
+; CHECK-MVE-NEXT: vselgt.f16 s0, s12, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
@@ -3013,41 +2457,29 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ule_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
-; CHECK-MVE-NEXT: cset r0, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vselgt.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
-; CHECK-MVE-NEXT: cset r0, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
+; CHECK-MVE-NEXT: vselgt.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
-; CHECK-MVE-NEXT: cset r0, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vselgt.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s15
-; CHECK-MVE-NEXT: cset r0, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
+; CHECK-MVE-NEXT: vselgt.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
-; CHECK-MVE-NEXT: cset r0, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vselgt.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
+; CHECK-MVE-NEXT: vselgt.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr
;
@@ -3074,13 +2506,9 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ord_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
-; CHECK-MVE-NEXT: cset r0, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
+; CHECK-MVE-NEXT: vselvs.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
+; CHECK-MVE-NEXT: vselvs.f16 s0, s12, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
@@ -3088,41 +2516,29 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ord_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
-; CHECK-MVE-NEXT: cset r0, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vselvs.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
-; CHECK-MVE-NEXT: cset r0, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
+; CHECK-MVE-NEXT: vselvs.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
-; CHECK-MVE-NEXT: cset r0, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vselvs.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s15
-; CHECK-MVE-NEXT: cset r0, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
+; CHECK-MVE-NEXT: vselvs.f16 s2, s14, s10
; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
-; CHECK-MVE-NEXT: cset r0, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vselvs.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
+; CHECK-MVE-NEXT: vselvs.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr
;
@@ -3145,60 +2561,44 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_uno_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-LABEL: vcmp_r_uno_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s12
+; CHECK-MVE-NEXT: vmovx.f16 s5, s8
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
-; CHECK-MVE-NEXT: vmovx.f16 s6, s8
+; CHECK-MVE-NEXT: vmovx.f16 s6, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
-; CHECK-MVE-NEXT: cset r0, vs
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
+; CHECK-MVE-NEXT: vselvs.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, vs
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
-; CHECK-MVE-NEXT: vmovx.f16 s8, s13
+; CHECK-MVE-NEXT: vselvs.f16 s0, s8, s12
+; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
-; CHECK-MVE-NEXT: vmovx.f16 s6, s9
+; CHECK-MVE-NEXT: vmovx.f16 s6, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
-; CHECK-MVE-NEXT: cset r0, vs
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vselvs.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s14
-; CHECK-MVE-NEXT: cset r0, vs
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
+; CHECK-MVE-NEXT: vmovx.f16 s8, s10
+; CHECK-MVE-NEXT: vselvs.f16 s1, s9, s13
; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
-; CHECK-MVE-NEXT: vmovx.f16 s6, s10
+; CHECK-MVE-NEXT: vmovx.f16 s6, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
-; CHECK-MVE-NEXT: cset r0, vs
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vselvs.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s15
-; CHECK-MVE-NEXT: cset r0, vs
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
+; CHECK-MVE-NEXT: vmovx.f16 s8, s11
+; CHECK-MVE-NEXT: vselvs.f16 s2, s10, s14
; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
-; CHECK-MVE-NEXT: vmovx.f16 s6, s11
+; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
-; CHECK-MVE-NEXT: cset r0, vs
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
+; CHECK-MVE-NEXT: vselvs.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, vs
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
+; CHECK-MVE-NEXT: vselvs.f16 s3, s11, s15
; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr
;
@@ -3223,60 +2623,44 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16_bc(<8 x half> %src, half %src2
; CHECK-MVE-LABEL: vcmp_oeq_v8f16_bc:
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s12
+; CHECK-MVE-NEXT: vmovx.f16 s5, s8
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
-; CHECK-MVE-NEXT: vmovx.f16 s6, s8
+; CHECK-MVE-NEXT: vmovx.f16 s6, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
-; CHECK-MVE-NEXT: vmovx.f16 s8, s13
+; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s12
+; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
-; CHECK-MVE-NEXT: vmovx.f16 s6, s9
+; CHECK-MVE-NEXT: vmovx.f16 s6, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s14
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
+; CHECK-MVE-NEXT: vmovx.f16 s8, s10
+; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s13
; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
-; CHECK-MVE-NEXT: vmovx.f16 s6, s10
+; CHECK-MVE-NEXT: vmovx.f16 s6, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s15
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
+; CHECK-MVE-NEXT: vmovx.f16 s8, s11
+; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s14
; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
-; CHECK-MVE-NEXT: vmovx.f16 s6, s11
+; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
+; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s15
; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr
;
diff --git a/llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll b/llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll
index de8b413bf24e5..a507ce0ed5c03 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll
@@ -5,26 +5,18 @@
define arm_aapcs_vfpcc <4 x float> @vcmp_oeq_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_oeq_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
+; CHECK-MVE-NEXT: vseleq.f32 s2, s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s3, #0
-; CHECK-MVE-NEXT: cset r0, eq
+; CHECK-MVE-NEXT: vseleq.f32 s1, s5, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s1, #0
-; CHECK-MVE-NEXT: cset r1, eq
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vseleq.f32 s3, s7, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
-; CHECK-MVE-NEXT: cset r2, eq
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, eq
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
+; CHECK-MVE-NEXT: vseleq.f32 s0, s4, s8
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_oeq_v4f32:
@@ -41,30 +33,26 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_one_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_one_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s10, s6
+; CHECK-MVE-NEXT: vselgt.f32 s2, s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s3, #0
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: csinc r0, r0, zr, le
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s9, s5
+; CHECK-MVE-NEXT: vselgt.f32 s1, s5, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s1, #0
-; CHECK-MVE-NEXT: cset r1, mi
-; CHECK-MVE-NEXT: csinc r1, r1, zr, le
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s11, s7
+; CHECK-MVE-NEXT: vselgt.f32 s3, s7, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
-; CHECK-MVE-NEXT: cset r2, mi
-; CHECK-MVE-NEXT: csinc r2, r2, zr, le
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, mi
-; CHECK-MVE-NEXT: csinc r3, r3, zr, le
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s8, s4
+; CHECK-MVE-NEXT: vselgt.f32 s0, s4, s8
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_one_v4f32:
@@ -82,26 +70,18 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_ogt_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ogt_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
+; CHECK-MVE-NEXT: vselgt.f32 s2, s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s3, #0
-; CHECK-MVE-NEXT: cset r0, gt
+; CHECK-MVE-NEXT: vselgt.f32 s1, s5, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s1, #0
-; CHECK-MVE-NEXT: cset r1, gt
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vselgt.f32 s3, s7, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
-; CHECK-MVE-NEXT: cset r2, gt
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, gt
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
+; CHECK-MVE-NEXT: vselgt.f32 s0, s4, s8
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_ogt_v4f32:
@@ -118,26 +98,18 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_oge_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_oge_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
+; CHECK-MVE-NEXT: vselge.f32 s2, s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s3, #0
-; CHECK-MVE-NEXT: cset r0, ge
+; CHECK-MVE-NEXT: vselge.f32 s1, s5, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s1, #0
-; CHECK-MVE-NEXT: cset r1, ge
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vselge.f32 s3, s7, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
-; CHECK-MVE-NEXT: cset r2, ge
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, ge
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
+; CHECK-MVE-NEXT: vselge.f32 s0, s4, s8
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_oge_v4f32:
@@ -154,26 +126,23 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_olt_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_olt_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s3, #0
-; CHECK-MVE-NEXT: cset r0, mi
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s10, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, #0
-; CHECK-MVE-NEXT: cset r1, mi
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
-; CHECK-MVE-NEXT: cset r2, mi
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, mi
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s9, s5
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s8, s4
+; CHECK-MVE-NEXT: vmov q0, q2
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_olt_v4f32:
@@ -190,26 +159,23 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_ole_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ole_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s3, #0
-; CHECK-MVE-NEXT: cset r0, ls
+; CHECK-MVE-NEXT: it ls
+; CHECK-MVE-NEXT: vmovls.f32 s10, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, #0
-; CHECK-MVE-NEXT: cset r1, ls
+; CHECK-MVE-NEXT: it ls
+; CHECK-MVE-NEXT: vmovls.f32 s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
-; CHECK-MVE-NEXT: cset r2, ls
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, ls
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: it ls
+; CHECK-MVE-NEXT: vmovls.f32 s9, s5
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ls
+; CHECK-MVE-NEXT: vmovls.f32 s8, s4
+; CHECK-MVE-NEXT: vmov q0, q2
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_ole_v4f32:
@@ -226,30 +192,22 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_ueq_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ueq_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
+; CHECK-MVE-NEXT: vseleq.f32 s2, s6, s10
+; CHECK-MVE-NEXT: vselvs.f32 s2, s6, s2
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s3, #0
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
+; CHECK-MVE-NEXT: vseleq.f32 s6, s5, s9
+; CHECK-MVE-NEXT: vselvs.f32 s1, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s1, #0
-; CHECK-MVE-NEXT: cset r1, eq
-; CHECK-MVE-NEXT: csinc r1, r1, zr, vc
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vseleq.f32 s0, s7, s11
+; CHECK-MVE-NEXT: vselvs.f32 s3, s7, s0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
-; CHECK-MVE-NEXT: cset r2, eq
-; CHECK-MVE-NEXT: csinc r2, r2, zr, vc
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, eq
-; CHECK-MVE-NEXT: csinc r3, r3, zr, vc
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
+; CHECK-MVE-NEXT: vseleq.f32 s0, s4, s8
+; CHECK-MVE-NEXT: vselvs.f32 s0, s4, s0
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_ueq_v4f32:
@@ -269,16 +227,21 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_une_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: vmovne.f32 s10, s6
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: vmovne.f32 s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: vmovne.f32 s9, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: vmovne.f32 s8, s4
+; CHECK-MVE-NEXT: vmov q0, q2
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_une_v4f32:
@@ -295,26 +258,23 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_ugt_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ugt_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s3, #0
-; CHECK-MVE-NEXT: cset r0, hi
+; CHECK-MVE-NEXT: it hi
+; CHECK-MVE-NEXT: vmovhi.f32 s10, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, #0
-; CHECK-MVE-NEXT: cset r1, hi
+; CHECK-MVE-NEXT: it hi
+; CHECK-MVE-NEXT: vmovhi.f32 s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
-; CHECK-MVE-NEXT: cset r2, hi
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, hi
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: it hi
+; CHECK-MVE-NEXT: vmovhi.f32 s9, s5
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it hi
+; CHECK-MVE-NEXT: vmovhi.f32 s8, s4
+; CHECK-MVE-NEXT: vmov q0, q2
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_ugt_v4f32:
@@ -331,26 +291,23 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_uge_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_uge_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s3, #0
-; CHECK-MVE-NEXT: cset r0, pl
+; CHECK-MVE-NEXT: it pl
+; CHECK-MVE-NEXT: vmovpl.f32 s10, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, #0
-; CHECK-MVE-NEXT: cset r1, pl
+; CHECK-MVE-NEXT: it pl
+; CHECK-MVE-NEXT: vmovpl.f32 s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
-; CHECK-MVE-NEXT: cset r2, pl
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, pl
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: it pl
+; CHECK-MVE-NEXT: vmovpl.f32 s9, s5
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it pl
+; CHECK-MVE-NEXT: vmovpl.f32 s8, s4
+; CHECK-MVE-NEXT: vmov q0, q2
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_uge_v4f32:
@@ -367,26 +324,23 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_ult_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ult_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s3, #0
-; CHECK-MVE-NEXT: cset r0, lt
+; CHECK-MVE-NEXT: it lt
+; CHECK-MVE-NEXT: vmovlt.f32 s10, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, #0
-; CHECK-MVE-NEXT: cset r1, lt
+; CHECK-MVE-NEXT: it lt
+; CHECK-MVE-NEXT: vmovlt.f32 s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
-; CHECK-MVE-NEXT: cset r2, lt
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, lt
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: it lt
+; CHECK-MVE-NEXT: vmovlt.f32 s9, s5
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it lt
+; CHECK-MVE-NEXT: vmovlt.f32 s8, s4
+; CHECK-MVE-NEXT: vmov q0, q2
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_ult_v4f32:
@@ -403,26 +357,23 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_ule_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ule_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s3, #0
-; CHECK-MVE-NEXT: cset r0, le
+; CHECK-MVE-NEXT: it le
+; CHECK-MVE-NEXT: vmovle.f32 s10, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, #0
-; CHECK-MVE-NEXT: cset r1, le
+; CHECK-MVE-NEXT: it le
+; CHECK-MVE-NEXT: vmovle.f32 s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
-; CHECK-MVE-NEXT: cset r2, le
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, le
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: it le
+; CHECK-MVE-NEXT: vmovle.f32 s9, s5
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it le
+; CHECK-MVE-NEXT: vmovle.f32 s8, s4
+; CHECK-MVE-NEXT: vmov q0, q2
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_ule_v4f32:
@@ -439,26 +390,18 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_ord_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ord_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s0
+; CHECK-MVE-NEXT: vcmp.f32 s2, s2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f32 s1, s1
+; CHECK-MVE-NEXT: vselvs.f32 s2, s10, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s3, s3
-; CHECK-MVE-NEXT: cset r0, vc
+; CHECK-MVE-NEXT: vselvs.f32 s1, s9, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s1, s1
-; CHECK-MVE-NEXT: cset r1, vc
+; CHECK-MVE-NEXT: vcmp.f32 s0, s0
+; CHECK-MVE-NEXT: vselvs.f32 s3, s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, s2
-; CHECK-MVE-NEXT: cset r2, vc
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, vc
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
+; CHECK-MVE-NEXT: vselvs.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_ord_v4f32:
@@ -476,26 +419,18 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_uno_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_uno_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s0
+; CHECK-MVE-NEXT: vcmp.f32 s2, s2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f32 s1, s1
+; CHECK-MVE-NEXT: vselvs.f32 s2, s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s3, s3
-; CHECK-MVE-NEXT: cset r0, vs
+; CHECK-MVE-NEXT: vselvs.f32 s1, s5, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s1, s1
-; CHECK-MVE-NEXT: cset r1, vs
+; CHECK-MVE-NEXT: vcmp.f32 s0, s0
+; CHECK-MVE-NEXT: vselvs.f32 s3, s7, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, s2
-; CHECK-MVE-NEXT: cset r2, vs
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, vs
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
+; CHECK-MVE-NEXT: vselvs.f32 s0, s4, s8
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_uno_v4f32:
@@ -516,60 +451,44 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-LABEL: vcmp_oeq_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s12, s0
-; CHECK-MVE-NEXT: vmovx.f16 s14, s8
+; CHECK-MVE-NEXT: vmovx.f16 s14, s4
; CHECK-MVE-NEXT: vcmp.f16 s12, #0
-; CHECK-MVE-NEXT: vmovx.f16 s12, s4
+; CHECK-MVE-NEXT: vmovx.f16 s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
+; CHECK-MVE-NEXT: vseleq.f16 s0, s4, s8
; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: vmovx.f16 s4, s5
+; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s9
+; CHECK-MVE-NEXT: vmovx.f16 s8, s5
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s10
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
+; CHECK-MVE-NEXT: vmovx.f16 s8, s6
+; CHECK-MVE-NEXT: vseleq.f16 s1, s5, s9
; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: vmovx.f16 s4, s6
+; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
-; CHECK-MVE-NEXT: vmovx.f16 s6, s11
+; CHECK-MVE-NEXT: vseleq.f16 s2, s6, s10
+; CHECK-MVE-NEXT: vmovx.f16 s6, s7
; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: vmovx.f16 s4, s7
+; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
+; CHECK-MVE-NEXT: vseleq.f16 s3, s7, s11
; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -593,47 +512,41 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: csinc r0, r0, zr, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s14, s12
+; CHECK-MVE-NEXT: vselgt.f16 s12, s12, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: csinc r0, r0, zr, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s8, s4
+; CHECK-MVE-NEXT: vselgt.f16 s0, s4, s8
; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s8, s4
; CHECK-MVE-NEXT: vins.f16 s0, s12
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: csinc r0, r0, zr, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselgt.f16 s4, s4, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s9, s5
; CHECK-MVE-NEXT: vmovx.f16 s8, s10
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: csinc r0, r0, zr, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
+; CHECK-MVE-NEXT: vselgt.f16 s1, s5, s9
; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: csinc r0, r0, zr, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s8, s4
+; CHECK-MVE-NEXT: vselgt.f16 s4, s4, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: csinc r0, r0, zr, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s10, s6
+; CHECK-MVE-NEXT: vselgt.f16 s2, s6, s10
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3
@@ -641,15 +554,13 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: csinc r0, r0, zr, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s6, s4
+; CHECK-MVE-NEXT: vselgt.f16 s4, s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: csinc r0, r0, zr, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s11, s7
+; CHECK-MVE-NEXT: vselgt.f16 s3, s7, s11
; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -669,60 +580,44 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ogt_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-LABEL: vcmp_ogt_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s12, s0
-; CHECK-MVE-NEXT: vmovx.f16 s14, s8
+; CHECK-MVE-NEXT: vmovx.f16 s14, s4
; CHECK-MVE-NEXT: vcmp.f16 s12, #0
-; CHECK-MVE-NEXT: vmovx.f16 s12, s4
+; CHECK-MVE-NEXT: vmovx.f16 s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: cset r0, gt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vselgt.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, gt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
+; CHECK-MVE-NEXT: vselgt.f16 s0, s4, s8
; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: vmovx.f16 s4, s5
+; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s9
+; CHECK-MVE-NEXT: vmovx.f16 s8, s5
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
-; CHECK-MVE-NEXT: cset r0, gt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselgt.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s10
-; CHECK-MVE-NEXT: cset r0, gt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
+; CHECK-MVE-NEXT: vmovx.f16 s8, s6
+; CHECK-MVE-NEXT: vselgt.f16 s1, s5, s9
; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: vmovx.f16 s4, s6
+; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
-; CHECK-MVE-NEXT: cset r0, gt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselgt.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, gt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
-; CHECK-MVE-NEXT: vmovx.f16 s6, s11
+; CHECK-MVE-NEXT: vselgt.f16 s2, s6, s10
+; CHECK-MVE-NEXT: vmovx.f16 s6, s7
; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: vmovx.f16 s4, s7
+; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
-; CHECK-MVE-NEXT: cset r0, gt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
+; CHECK-MVE-NEXT: vselgt.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, gt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
+; CHECK-MVE-NEXT: vselgt.f16 s3, s7, s11
; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -741,60 +636,44 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_oge_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-LABEL: vcmp_oge_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s12, s0
-; CHECK-MVE-NEXT: vmovx.f16 s14, s8
+; CHECK-MVE-NEXT: vmovx.f16 s14, s4
; CHECK-MVE-NEXT: vcmp.f16 s12, #0
-; CHECK-MVE-NEXT: vmovx.f16 s12, s4
+; CHECK-MVE-NEXT: vmovx.f16 s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: cset r0, ge
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vselge.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, ge
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
+; CHECK-MVE-NEXT: vselge.f16 s0, s4, s8
; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: vmovx.f16 s4, s5
+; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s9
+; CHECK-MVE-NEXT: vmovx.f16 s8, s5
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
-; CHECK-MVE-NEXT: cset r0, ge
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselge.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s10
-; CHECK-MVE-NEXT: cset r0, ge
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
+; CHECK-MVE-NEXT: vmovx.f16 s8, s6
+; CHECK-MVE-NEXT: vselge.f16 s1, s5, s9
; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: vmovx.f16 s4, s6
+; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
-; CHECK-MVE-NEXT: cset r0, ge
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselge.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, ge
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
-; CHECK-MVE-NEXT: vmovx.f16 s6, s11
+; CHECK-MVE-NEXT: vselge.f16 s2, s6, s10
+; CHECK-MVE-NEXT: vmovx.f16 s6, s7
; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: vmovx.f16 s4, s7
+; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
-; CHECK-MVE-NEXT: cset r0, ge
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
+; CHECK-MVE-NEXT: vselge.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, ge
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
+; CHECK-MVE-NEXT: vselge.f16 s3, s7, s11
; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -812,63 +691,52 @@ entry:
define arm_aapcs_vfpcc <8 x half> @vcmp_olt_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_olt_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vmovx.f16 s12, s0
+; CHECK-MVE-NEXT: vldr.16 s12, .LCPI18_0
+; CHECK-MVE-NEXT: vmovx.f16 s14, s0
+; CHECK-MVE-NEXT: vmovx.f16 s13, s4
+; CHECK-MVE-NEXT: vcmp.f16 s12, s14
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
-; CHECK-MVE-NEXT: vcmp.f16 s12, #0
-; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vcmp.f16 s12, s0
+; CHECK-MVE-NEXT: vselgt.f16 s14, s13, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
+; CHECK-MVE-NEXT: vselgt.f16 s0, s4, s8
; CHECK-MVE-NEXT: vmovx.f16 s4, s1
-; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: vmovx.f16 s4, s5
+; CHECK-MVE-NEXT: vcmp.f16 s12, s4
+; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s9
-; CHECK-MVE-NEXT: vcmp.f16 s1, #0
-; CHECK-MVE-NEXT: vins.f16 s0, s12
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vmovx.f16 s8, s5
+; CHECK-MVE-NEXT: vcmp.f16 s12, s1
+; CHECK-MVE-NEXT: vins.f16 s0, s14
+; CHECK-MVE-NEXT: vselgt.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s10
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
+; CHECK-MVE-NEXT: vmovx.f16 s8, s6
+; CHECK-MVE-NEXT: vselgt.f16 s1, s5, s9
; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2
-; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: vmovx.f16 s4, s6
+; CHECK-MVE-NEXT: vcmp.f16 s12, s4
+; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s2, #0
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vcmp.f16 s12, s2
+; CHECK-MVE-NEXT: vselgt.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
-; CHECK-MVE-NEXT: vmovx.f16 s6, s11
+; CHECK-MVE-NEXT: vselgt.f16 s2, s6, s10
+; CHECK-MVE-NEXT: vmovx.f16 s6, s7
; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3
-; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: vmovx.f16 s4, s7
+; CHECK-MVE-NEXT: vcmp.f16 s12, s4
+; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s3, #0
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
+; CHECK-MVE-NEXT: vcmp.f16 s12, s3
+; CHECK-MVE-NEXT: vselgt.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
+; CHECK-MVE-NEXT: vselgt.f16 s3, s7, s11
; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr
+; CHECK-MVE-NEXT: .p2align 1
+; CHECK-MVE-NEXT: @ %bb.1:
+; CHECK-MVE-NEXT: .LCPI18_0:
+; CHECK-MVE-NEXT: .short 0x0000 @ half 0
;
; CHECK-MVEFP-LABEL: vcmp_olt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry
@@ -884,63 +752,52 @@ entry:
define arm_aapcs_vfpcc <8 x half> @vcmp_ole_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_ole_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vmovx.f16 s12, s0
+; CHECK-MVE-NEXT: vldr.16 s12, .LCPI19_0
+; CHECK-MVE-NEXT: vmovx.f16 s14, s0
+; CHECK-MVE-NEXT: vmovx.f16 s13, s4
+; CHECK-MVE-NEXT: vcmp.f16 s12, s14
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
-; CHECK-MVE-NEXT: vcmp.f16 s12, #0
-; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: cset r0, ls
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vcmp.f16 s12, s0
+; CHECK-MVE-NEXT: vselge.f16 s14, s13, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, ls
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
+; CHECK-MVE-NEXT: vselge.f16 s0, s4, s8
; CHECK-MVE-NEXT: vmovx.f16 s4, s1
-; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: vmovx.f16 s4, s5
+; CHECK-MVE-NEXT: vcmp.f16 s12, s4
+; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s9
-; CHECK-MVE-NEXT: vcmp.f16 s1, #0
-; CHECK-MVE-NEXT: vins.f16 s0, s12
-; CHECK-MVE-NEXT: cset r0, ls
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vmovx.f16 s8, s5
+; CHECK-MVE-NEXT: vcmp.f16 s12, s1
+; CHECK-MVE-NEXT: vins.f16 s0, s14
+; CHECK-MVE-NEXT: vselge.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s10
-; CHECK-MVE-NEXT: cset r0, ls
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
+; CHECK-MVE-NEXT: vmovx.f16 s8, s6
+; CHECK-MVE-NEXT: vselge.f16 s1, s5, s9
; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2
-; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: vmovx.f16 s4, s6
+; CHECK-MVE-NEXT: vcmp.f16 s12, s4
+; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s2, #0
-; CHECK-MVE-NEXT: cset r0, ls
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vcmp.f16 s12, s2
+; CHECK-MVE-NEXT: vselge.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, ls
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
-; CHECK-MVE-NEXT: vmovx.f16 s6, s11
+; CHECK-MVE-NEXT: vselge.f16 s2, s6, s10
+; CHECK-MVE-NEXT: vmovx.f16 s6, s7
; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3
-; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: vmovx.f16 s4, s7
+; CHECK-MVE-NEXT: vcmp.f16 s12, s4
+; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s3, #0
-; CHECK-MVE-NEXT: cset r0, ls
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
+; CHECK-MVE-NEXT: vcmp.f16 s12, s3
+; CHECK-MVE-NEXT: vselge.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, ls
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
+; CHECK-MVE-NEXT: vselge.f16 s3, s7, s11
; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr
+; CHECK-MVE-NEXT: .p2align 1
+; CHECK-MVE-NEXT: @ %bb.1:
+; CHECK-MVE-NEXT: .LCPI19_0:
+; CHECK-MVE-NEXT: .short 0x0000 @ half 0
;
; CHECK-MVEFP-LABEL: vcmp_ole_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry
@@ -957,68 +814,52 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ueq_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-LABEL: vcmp_ueq_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s12, s0
-; CHECK-MVE-NEXT: vmovx.f16 s14, s8
+; CHECK-MVE-NEXT: vmovx.f16 s14, s4
; CHECK-MVE-NEXT: vcmp.f16 s12, #0
-; CHECK-MVE-NEXT: vmovx.f16 s12, s4
+; CHECK-MVE-NEXT: vmovx.f16 s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
-; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vselvs.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
+; CHECK-MVE-NEXT: vseleq.f16 s0, s4, s8
+; CHECK-MVE-NEXT: vmovx.f16 s8, s5
+; CHECK-MVE-NEXT: vselvs.f16 s0, s4, s0
; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: vmovx.f16 s4, s5
+; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
-; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselvs.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s10
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
+; CHECK-MVE-NEXT: vseleq.f16 s8, s5, s9
+; CHECK-MVE-NEXT: vselvs.f16 s1, s5, s8
+; CHECK-MVE-NEXT: vmovx.f16 s8, s6
; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: vmovx.f16 s4, s6
+; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
-; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselvs.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
-; CHECK-MVE-NEXT: vmovx.f16 s6, s11
+; CHECK-MVE-NEXT: vseleq.f16 s2, s6, s10
+; CHECK-MVE-NEXT: vselvs.f16 s2, s6, s2
+; CHECK-MVE-NEXT: vmovx.f16 s6, s7
; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: vmovx.f16 s4, s7
+; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
-; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
+; CHECK-MVE-NEXT: vselvs.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
+; CHECK-MVE-NEXT: vseleq.f16 s6, s7, s11
+; CHECK-MVE-NEXT: vselvs.f16 s3, s7, s6
; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -1093,63 +934,52 @@ entry:
define arm_aapcs_vfpcc <8 x half> @vcmp_ugt_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_ugt_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vmovx.f16 s12, s0
-; CHECK-MVE-NEXT: vmovx.f16 s14, s8
-; CHECK-MVE-NEXT: vcmp.f16 s12, #0
-; CHECK-MVE-NEXT: vmovx.f16 s12, s4
+; CHECK-MVE-NEXT: vldr.16 s12, .LCPI22_0
+; CHECK-MVE-NEXT: vmovx.f16 s14, s0
+; CHECK-MVE-NEXT: vmovx.f16 s13, s8
+; CHECK-MVE-NEXT: vcmp.f16 s12, s14
+; CHECK-MVE-NEXT: vmovx.f16 s14, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: cset r0, hi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vcmp.f16 s12, s0
+; CHECK-MVE-NEXT: vselge.f16 s14, s13, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, hi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
+; CHECK-MVE-NEXT: vselge.f16 s0, s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s1
-; CHECK-MVE-NEXT: vcmp.f16 s4, #0
+; CHECK-MVE-NEXT: vcmp.f16 s12, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s9
-; CHECK-MVE-NEXT: vcmp.f16 s1, #0
-; CHECK-MVE-NEXT: vins.f16 s0, s12
-; CHECK-MVE-NEXT: cset r0, hi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vcmp.f16 s12, s1
+; CHECK-MVE-NEXT: vins.f16 s0, s14
+; CHECK-MVE-NEXT: vselge.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s10
-; CHECK-MVE-NEXT: cset r0, hi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
+; CHECK-MVE-NEXT: vselge.f16 s1, s9, s5
; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2
-; CHECK-MVE-NEXT: vcmp.f16 s4, #0
+; CHECK-MVE-NEXT: vcmp.f16 s12, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s2, #0
-; CHECK-MVE-NEXT: cset r0, hi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vcmp.f16 s12, s2
+; CHECK-MVE-NEXT: vselge.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, hi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
+; CHECK-MVE-NEXT: vselge.f16 s2, s10, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3
-; CHECK-MVE-NEXT: vcmp.f16 s4, #0
+; CHECK-MVE-NEXT: vcmp.f16 s12, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s3, #0
-; CHECK-MVE-NEXT: cset r0, hi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
+; CHECK-MVE-NEXT: vcmp.f16 s12, s3
+; CHECK-MVE-NEXT: vselge.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, hi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
+; CHECK-MVE-NEXT: vselge.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr
+; CHECK-MVE-NEXT: .p2align 1
+; CHECK-MVE-NEXT: @ %bb.1:
+; CHECK-MVE-NEXT: .LCPI22_0:
+; CHECK-MVE-NEXT: .short 0x0000 @ half 0
;
; CHECK-MVEFP-LABEL: vcmp_ugt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry
@@ -1165,63 +995,52 @@ entry:
define arm_aapcs_vfpcc <8 x half> @vcmp_uge_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_uge_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vmovx.f16 s12, s0
-; CHECK-MVE-NEXT: vmovx.f16 s14, s8
-; CHECK-MVE-NEXT: vcmp.f16 s12, #0
-; CHECK-MVE-NEXT: vmovx.f16 s12, s4
+; CHECK-MVE-NEXT: vldr.16 s12, .LCPI23_0
+; CHECK-MVE-NEXT: vmovx.f16 s14, s0
+; CHECK-MVE-NEXT: vmovx.f16 s13, s8
+; CHECK-MVE-NEXT: vcmp.f16 s12, s14
+; CHECK-MVE-NEXT: vmovx.f16 s14, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: cset r0, pl
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vcmp.f16 s12, s0
+; CHECK-MVE-NEXT: vselgt.f16 s14, s13, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, pl
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
+; CHECK-MVE-NEXT: vselgt.f16 s0, s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s1
-; CHECK-MVE-NEXT: vcmp.f16 s4, #0
+; CHECK-MVE-NEXT: vcmp.f16 s12, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s9
-; CHECK-MVE-NEXT: vcmp.f16 s1, #0
-; CHECK-MVE-NEXT: vins.f16 s0, s12
-; CHECK-MVE-NEXT: cset r0, pl
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vcmp.f16 s12, s1
+; CHECK-MVE-NEXT: vins.f16 s0, s14
+; CHECK-MVE-NEXT: vselgt.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s10
-; CHECK-MVE-NEXT: cset r0, pl
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
+; CHECK-MVE-NEXT: vselgt.f16 s1, s9, s5
; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2
-; CHECK-MVE-NEXT: vcmp.f16 s4, #0
+; CHECK-MVE-NEXT: vcmp.f16 s12, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s2, #0
-; CHECK-MVE-NEXT: cset r0, pl
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vcmp.f16 s12, s2
+; CHECK-MVE-NEXT: vselgt.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, pl
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
+; CHECK-MVE-NEXT: vselgt.f16 s2, s10, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3
-; CHECK-MVE-NEXT: vcmp.f16 s4, #0
+; CHECK-MVE-NEXT: vcmp.f16 s12, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s3, #0
-; CHECK-MVE-NEXT: cset r0, pl
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
+; CHECK-MVE-NEXT: vcmp.f16 s12, s3
+; CHECK-MVE-NEXT: vselgt.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, pl
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
+; CHECK-MVE-NEXT: vselgt.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr
+; CHECK-MVE-NEXT: .p2align 1
+; CHECK-MVE-NEXT: @ %bb.1:
+; CHECK-MVE-NEXT: .LCPI23_0:
+; CHECK-MVE-NEXT: .short 0x0000 @ half 0
;
; CHECK-MVEFP-LABEL: vcmp_uge_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry
@@ -1243,13 +1062,9 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ult_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: cset r0, lt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vselge.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, lt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
+; CHECK-MVE-NEXT: vselge.f16 s0, s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s5
@@ -1257,27 +1072,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ult_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
-; CHECK-MVE-NEXT: cset r0, lt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselge.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s10
-; CHECK-MVE-NEXT: cset r0, lt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
+; CHECK-MVE-NEXT: vselge.f16 s1, s9, s5
; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
-; CHECK-MVE-NEXT: cset r0, lt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselge.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, lt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
+; CHECK-MVE-NEXT: vselge.f16 s2, s10, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3
@@ -1285,13 +1092,9 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ult_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
-; CHECK-MVE-NEXT: cset r0, lt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
+; CHECK-MVE-NEXT: vselge.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, lt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
+; CHECK-MVE-NEXT: vselge.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -1315,13 +1118,9 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ule_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: cset r0, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vselgt.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
+; CHECK-MVE-NEXT: vselgt.f16 s0, s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s5
@@ -1329,27 +1128,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ule_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
-; CHECK-MVE-NEXT: cset r0, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselgt.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s10
-; CHECK-MVE-NEXT: cset r0, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
+; CHECK-MVE-NEXT: vselgt.f16 s1, s9, s5
; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
-; CHECK-MVE-NEXT: cset r0, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselgt.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
+; CHECK-MVE-NEXT: vselgt.f16 s2, s10, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3
@@ -1357,13 +1148,9 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ule_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
-; CHECK-MVE-NEXT: cset r0, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
+; CHECK-MVE-NEXT: vselgt.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
+; CHECK-MVE-NEXT: vselgt.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -1387,13 +1174,9 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ord_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s0, s0
-; CHECK-MVE-NEXT: cset r0, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vselvs.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
+; CHECK-MVE-NEXT: vselvs.f16 s0, s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s5
@@ -1401,27 +1184,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ord_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, s1
; CHECK-MVE-NEXT: vins.f16 s0, s12
-; CHECK-MVE-NEXT: cset r0, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselvs.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s10
-; CHECK-MVE-NEXT: cset r0, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
+; CHECK-MVE-NEXT: vselvs.f16 s1, s9, s5
; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s2, s2
-; CHECK-MVE-NEXT: cset r0, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselvs.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
+; CHECK-MVE-NEXT: vselvs.f16 s2, s10, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3
@@ -1429,13 +1204,9 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ord_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s3, s3
-; CHECK-MVE-NEXT: cset r0, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
+; CHECK-MVE-NEXT: vselvs.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
+; CHECK-MVE-NEXT: vselvs.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -1455,60 +1226,44 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_uno_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-LABEL: vcmp_uno_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s12, s0
-; CHECK-MVE-NEXT: vmovx.f16 s14, s8
+; CHECK-MVE-NEXT: vmovx.f16 s14, s4
; CHECK-MVE-NEXT: vcmp.f16 s12, s12
-; CHECK-MVE-NEXT: vmovx.f16 s12, s4
+; CHECK-MVE-NEXT: vmovx.f16 s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s0, s0
-; CHECK-MVE-NEXT: cset r0, vs
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vselvs.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, vs
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
+; CHECK-MVE-NEXT: vselvs.f16 s0, s4, s8
; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s4
-; CHECK-MVE-NEXT: vmovx.f16 s4, s5
+; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s9
+; CHECK-MVE-NEXT: vmovx.f16 s8, s5
; CHECK-MVE-NEXT: vcmp.f16 s1, s1
; CHECK-MVE-NEXT: vins.f16 s0, s12
-; CHECK-MVE-NEXT: cset r0, vs
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselvs.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s10
-; CHECK-MVE-NEXT: cset r0, vs
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
+; CHECK-MVE-NEXT: vmovx.f16 s8, s6
+; CHECK-MVE-NEXT: vselvs.f16 s1, s5, s9
; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s4
-; CHECK-MVE-NEXT: vmovx.f16 s4, s6
+; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s2, s2
-; CHECK-MVE-NEXT: cset r0, vs
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselvs.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, vs
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
-; CHECK-MVE-NEXT: vmovx.f16 s6, s11
+; CHECK-MVE-NEXT: vselvs.f16 s2, s6, s10
+; CHECK-MVE-NEXT: vmovx.f16 s6, s7
; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s4
-; CHECK-MVE-NEXT: vmovx.f16 s4, s7
+; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s3, s3
-; CHECK-MVE-NEXT: cset r0, vs
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
+; CHECK-MVE-NEXT: vselvs.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, vs
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
+; CHECK-MVE-NEXT: vselvs.f16 s3, s7, s11
; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -1530,26 +1285,18 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_oeq_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_oeq_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
+; CHECK-MVE-NEXT: vseleq.f32 s2, s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s3, #0
-; CHECK-MVE-NEXT: cset r0, eq
+; CHECK-MVE-NEXT: vseleq.f32 s1, s5, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s1, #0
-; CHECK-MVE-NEXT: cset r1, eq
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vseleq.f32 s3, s7, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
-; CHECK-MVE-NEXT: cset r2, eq
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, eq
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
+; CHECK-MVE-NEXT: vseleq.f32 s0, s4, s8
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_r_oeq_v4f32:
@@ -1566,30 +1313,26 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_one_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_one_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s10, s6
+; CHECK-MVE-NEXT: vselgt.f32 s2, s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s3, #0
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: csinc r0, r0, zr, le
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s9, s5
+; CHECK-MVE-NEXT: vselgt.f32 s1, s5, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s1, #0
-; CHECK-MVE-NEXT: cset r1, mi
-; CHECK-MVE-NEXT: csinc r1, r1, zr, le
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s11, s7
+; CHECK-MVE-NEXT: vselgt.f32 s3, s7, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
-; CHECK-MVE-NEXT: cset r2, mi
-; CHECK-MVE-NEXT: csinc r2, r2, zr, le
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, mi
-; CHECK-MVE-NEXT: csinc r3, r3, zr, le
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s8, s4
+; CHECK-MVE-NEXT: vselgt.f32 s0, s4, s8
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_r_one_v4f32:
@@ -1607,26 +1350,23 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_ogt_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_ogt_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s3, #0
-; CHECK-MVE-NEXT: cset r0, mi
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s10, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, #0
-; CHECK-MVE-NEXT: cset r1, mi
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
-; CHECK-MVE-NEXT: cset r2, mi
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, mi
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s9, s5
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s8, s4
+; CHECK-MVE-NEXT: vmov q0, q2
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_r_ogt_v4f32:
@@ -1643,26 +1383,23 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_oge_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_oge_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s3, #0
-; CHECK-MVE-NEXT: cset r0, ls
+; CHECK-MVE-NEXT: it ls
+; CHECK-MVE-NEXT: vmovls.f32 s10, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, #0
-; CHECK-MVE-NEXT: cset r1, ls
+; CHECK-MVE-NEXT: it ls
+; CHECK-MVE-NEXT: vmovls.f32 s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
-; CHECK-MVE-NEXT: cset r2, ls
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, ls
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: it ls
+; CHECK-MVE-NEXT: vmovls.f32 s9, s5
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it ls
+; CHECK-MVE-NEXT: vmovls.f32 s8, s4
+; CHECK-MVE-NEXT: vmov q0, q2
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_r_oge_v4f32:
@@ -1679,26 +1416,18 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_olt_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_olt_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
+; CHECK-MVE-NEXT: vselgt.f32 s2, s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s3, #0
-; CHECK-MVE-NEXT: cset r0, gt
+; CHECK-MVE-NEXT: vselgt.f32 s1, s5, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s1, #0
-; CHECK-MVE-NEXT: cset r1, gt
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vselgt.f32 s3, s7, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
-; CHECK-MVE-NEXT: cset r2, gt
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, gt
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
+; CHECK-MVE-NEXT: vselgt.f32 s0, s4, s8
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_r_olt_v4f32:
@@ -1715,26 +1444,18 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_ole_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_ole_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
+; CHECK-MVE-NEXT: vselge.f32 s2, s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s3, #0
-; CHECK-MVE-NEXT: cset r0, ge
+; CHECK-MVE-NEXT: vselge.f32 s1, s5, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s1, #0
-; CHECK-MVE-NEXT: cset r1, ge
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vselge.f32 s3, s7, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
-; CHECK-MVE-NEXT: cset r2, ge
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, ge
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
+; CHECK-MVE-NEXT: vselge.f32 s0, s4, s8
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_r_ole_v4f32:
@@ -1751,30 +1472,22 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_ueq_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_ueq_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
+; CHECK-MVE-NEXT: vseleq.f32 s2, s6, s10
+; CHECK-MVE-NEXT: vselvs.f32 s2, s6, s2
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s3, #0
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
+; CHECK-MVE-NEXT: vseleq.f32 s6, s5, s9
+; CHECK-MVE-NEXT: vselvs.f32 s1, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s1, #0
-; CHECK-MVE-NEXT: cset r1, eq
-; CHECK-MVE-NEXT: csinc r1, r1, zr, vc
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vseleq.f32 s0, s7, s11
+; CHECK-MVE-NEXT: vselvs.f32 s3, s7, s0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
-; CHECK-MVE-NEXT: cset r2, eq
-; CHECK-MVE-NEXT: csinc r2, r2, zr, vc
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, eq
-; CHECK-MVE-NEXT: csinc r3, r3, zr, vc
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
+; CHECK-MVE-NEXT: vseleq.f32 s0, s4, s8
+; CHECK-MVE-NEXT: vselvs.f32 s0, s4, s0
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_r_ueq_v4f32:
@@ -1794,16 +1507,21 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_une_v4f32(<4 x float> %src, <4 x floa
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: vmovne.f32 s10, s6
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f32 s1, #0
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: vmovne.f32 s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: vmovne.f32 s9, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
+; CHECK-MVE-NEXT: it ne
+; CHECK-MVE-NEXT: vmovne.f32 s8, s4
+; CHECK-MVE-NEXT: vmov q0, q2
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_r_une_v4f32:
@@ -1820,26 +1538,23 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_ugt_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_ugt_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s3, #0
-; CHECK-MVE-NEXT: cset r0, lt
+; CHECK-MVE-NEXT: it lt
+; CHECK-MVE-NEXT: vmovlt.f32 s10, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, #0
-; CHECK-MVE-NEXT: cset r1, lt
+; CHECK-MVE-NEXT: it lt
+; CHECK-MVE-NEXT: vmovlt.f32 s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
-; CHECK-MVE-NEXT: cset r2, lt
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, lt
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: it lt
+; CHECK-MVE-NEXT: vmovlt.f32 s9, s5
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it lt
+; CHECK-MVE-NEXT: vmovlt.f32 s8, s4
+; CHECK-MVE-NEXT: vmov q0, q2
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_r_ugt_v4f32:
@@ -1856,26 +1571,23 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_uge_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_uge_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s3, #0
-; CHECK-MVE-NEXT: cset r0, le
+; CHECK-MVE-NEXT: it le
+; CHECK-MVE-NEXT: vmovle.f32 s10, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, #0
-; CHECK-MVE-NEXT: cset r1, le
+; CHECK-MVE-NEXT: it le
+; CHECK-MVE-NEXT: vmovle.f32 s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
-; CHECK-MVE-NEXT: cset r2, le
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, le
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: it le
+; CHECK-MVE-NEXT: vmovle.f32 s9, s5
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it le
+; CHECK-MVE-NEXT: vmovle.f32 s8, s4
+; CHECK-MVE-NEXT: vmov q0, q2
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_r_uge_v4f32:
@@ -1892,26 +1604,23 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_ult_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_ult_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s3, #0
-; CHECK-MVE-NEXT: cset r0, hi
+; CHECK-MVE-NEXT: it hi
+; CHECK-MVE-NEXT: vmovhi.f32 s10, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, #0
-; CHECK-MVE-NEXT: cset r1, hi
+; CHECK-MVE-NEXT: it hi
+; CHECK-MVE-NEXT: vmovhi.f32 s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
-; CHECK-MVE-NEXT: cset r2, hi
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, hi
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: it hi
+; CHECK-MVE-NEXT: vmovhi.f32 s9, s5
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it hi
+; CHECK-MVE-NEXT: vmovhi.f32 s8, s4
+; CHECK-MVE-NEXT: vmov q0, q2
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_r_ult_v4f32:
@@ -1928,26 +1637,23 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_ule_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_ule_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s3, #0
-; CHECK-MVE-NEXT: cset r0, pl
+; CHECK-MVE-NEXT: it pl
+; CHECK-MVE-NEXT: vmovpl.f32 s10, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, #0
-; CHECK-MVE-NEXT: cset r1, pl
+; CHECK-MVE-NEXT: it pl
+; CHECK-MVE-NEXT: vmovpl.f32 s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, #0
-; CHECK-MVE-NEXT: cset r2, pl
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, pl
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: it pl
+; CHECK-MVE-NEXT: vmovpl.f32 s9, s5
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it pl
+; CHECK-MVE-NEXT: vmovpl.f32 s8, s4
+; CHECK-MVE-NEXT: vmov q0, q2
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_r_ule_v4f32:
@@ -1964,26 +1670,18 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_ord_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_ord_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s0
+; CHECK-MVE-NEXT: vcmp.f32 s2, s2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f32 s1, s1
+; CHECK-MVE-NEXT: vselvs.f32 s2, s10, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s3, s3
-; CHECK-MVE-NEXT: cset r0, vc
+; CHECK-MVE-NEXT: vselvs.f32 s1, s9, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s1, s1
-; CHECK-MVE-NEXT: cset r1, vc
+; CHECK-MVE-NEXT: vcmp.f32 s0, s0
+; CHECK-MVE-NEXT: vselvs.f32 s3, s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, s2
-; CHECK-MVE-NEXT: cset r2, vc
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, vc
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
+; CHECK-MVE-NEXT: vselvs.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_r_ord_v4f32:
@@ -2001,26 +1699,18 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_uno_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_uno_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s0, s0
+; CHECK-MVE-NEXT: vcmp.f32 s2, s2
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f32 s1, s1
+; CHECK-MVE-NEXT: vselvs.f32 s2, s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s3, s3
-; CHECK-MVE-NEXT: cset r0, vs
+; CHECK-MVE-NEXT: vselvs.f32 s1, s5, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s1, s1
-; CHECK-MVE-NEXT: cset r1, vs
+; CHECK-MVE-NEXT: vcmp.f32 s0, s0
+; CHECK-MVE-NEXT: vselvs.f32 s3, s7, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s2, s2
-; CHECK-MVE-NEXT: cset r2, vs
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r3, vs
-; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
-; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
-; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
+; CHECK-MVE-NEXT: vselvs.f32 s0, s4, s8
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_r_uno_v4f32:
@@ -2041,60 +1731,44 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_oeq_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-LABEL: vcmp_r_oeq_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s12, s0
-; CHECK-MVE-NEXT: vmovx.f16 s14, s8
+; CHECK-MVE-NEXT: vmovx.f16 s14, s4
; CHECK-MVE-NEXT: vcmp.f16 s12, #0
-; CHECK-MVE-NEXT: vmovx.f16 s12, s4
+; CHECK-MVE-NEXT: vmovx.f16 s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
+; CHECK-MVE-NEXT: vseleq.f16 s0, s4, s8
; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: vmovx.f16 s4, s5
+; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s9
+; CHECK-MVE-NEXT: vmovx.f16 s8, s5
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s10
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
+; CHECK-MVE-NEXT: vmovx.f16 s8, s6
+; CHECK-MVE-NEXT: vseleq.f16 s1, s5, s9
; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: vmovx.f16 s4, s6
+; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
-; CHECK-MVE-NEXT: vmovx.f16 s6, s11
+; CHECK-MVE-NEXT: vseleq.f16 s2, s6, s10
+; CHECK-MVE-NEXT: vmovx.f16 s6, s7
; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: vmovx.f16 s4, s7
+; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
+; CHECK-MVE-NEXT: vseleq.f16 s3, s7, s11
; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -2118,47 +1792,41 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_one_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: csinc r0, r0, zr, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s14, s12
+; CHECK-MVE-NEXT: vselgt.f16 s12, s12, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: csinc r0, r0, zr, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s8, s4
+; CHECK-MVE-NEXT: vselgt.f16 s0, s4, s8
; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s8, s4
; CHECK-MVE-NEXT: vins.f16 s0, s12
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: csinc r0, r0, zr, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselgt.f16 s4, s4, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s9, s5
; CHECK-MVE-NEXT: vmovx.f16 s8, s10
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: csinc r0, r0, zr, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
+; CHECK-MVE-NEXT: vselgt.f16 s1, s5, s9
; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: csinc r0, r0, zr, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s8, s4
+; CHECK-MVE-NEXT: vselgt.f16 s4, s4, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: csinc r0, r0, zr, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s10, s6
+; CHECK-MVE-NEXT: vselgt.f16 s2, s6, s10
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3
@@ -2166,15 +1834,13 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_one_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: csinc r0, r0, zr, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s6, s4
+; CHECK-MVE-NEXT: vselgt.f16 s4, s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: csinc r0, r0, zr, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
+; CHECK-MVE-NEXT: it mi
+; CHECK-MVE-NEXT: vmovmi.f32 s11, s7
+; CHECK-MVE-NEXT: vselgt.f16 s3, s7, s11
; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -2193,63 +1859,52 @@ entry:
define arm_aapcs_vfpcc <8 x half> @vcmp_r_ogt_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_ogt_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vmovx.f16 s12, s0
+; CHECK-MVE-NEXT: vldr.16 s12, .LCPI44_0
+; CHECK-MVE-NEXT: vmovx.f16 s14, s0
+; CHECK-MVE-NEXT: vmovx.f16 s13, s4
+; CHECK-MVE-NEXT: vcmp.f16 s12, s14
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
-; CHECK-MVE-NEXT: vcmp.f16 s12, #0
-; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vcmp.f16 s12, s0
+; CHECK-MVE-NEXT: vselgt.f16 s14, s13, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
+; CHECK-MVE-NEXT: vselgt.f16 s0, s4, s8
; CHECK-MVE-NEXT: vmovx.f16 s4, s1
-; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: vmovx.f16 s4, s5
+; CHECK-MVE-NEXT: vcmp.f16 s12, s4
+; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s9
-; CHECK-MVE-NEXT: vcmp.f16 s1, #0
-; CHECK-MVE-NEXT: vins.f16 s0, s12
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vmovx.f16 s8, s5
+; CHECK-MVE-NEXT: vcmp.f16 s12, s1
+; CHECK-MVE-NEXT: vins.f16 s0, s14
+; CHECK-MVE-NEXT: vselgt.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s10
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
+; CHECK-MVE-NEXT: vmovx.f16 s8, s6
+; CHECK-MVE-NEXT: vselgt.f16 s1, s5, s9
; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2
-; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: vmovx.f16 s4, s6
+; CHECK-MVE-NEXT: vcmp.f16 s12, s4
+; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s2, #0
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vcmp.f16 s12, s2
+; CHECK-MVE-NEXT: vselgt.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
-; CHECK-MVE-NEXT: vmovx.f16 s6, s11
+; CHECK-MVE-NEXT: vselgt.f16 s2, s6, s10
+; CHECK-MVE-NEXT: vmovx.f16 s6, s7
; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3
-; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: vmovx.f16 s4, s7
+; CHECK-MVE-NEXT: vcmp.f16 s12, s4
+; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s3, #0
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
+; CHECK-MVE-NEXT: vcmp.f16 s12, s3
+; CHECK-MVE-NEXT: vselgt.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
+; CHECK-MVE-NEXT: vselgt.f16 s3, s7, s11
; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr
+; CHECK-MVE-NEXT: .p2align 1
+; CHECK-MVE-NEXT: @ %bb.1:
+; CHECK-MVE-NEXT: .LCPI44_0:
+; CHECK-MVE-NEXT: .short 0x0000 @ half 0
;
; CHECK-MVEFP-LABEL: vcmp_r_ogt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry
@@ -2265,63 +1920,52 @@ entry:
define arm_aapcs_vfpcc <8 x half> @vcmp_r_oge_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_oge_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vmovx.f16 s12, s0
+; CHECK-MVE-NEXT: vldr.16 s12, .LCPI45_0
+; CHECK-MVE-NEXT: vmovx.f16 s14, s0
+; CHECK-MVE-NEXT: vmovx.f16 s13, s4
+; CHECK-MVE-NEXT: vcmp.f16 s12, s14
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
-; CHECK-MVE-NEXT: vcmp.f16 s12, #0
-; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: cset r0, ls
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vcmp.f16 s12, s0
+; CHECK-MVE-NEXT: vselge.f16 s14, s13, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, ls
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
+; CHECK-MVE-NEXT: vselge.f16 s0, s4, s8
; CHECK-MVE-NEXT: vmovx.f16 s4, s1
-; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: vmovx.f16 s4, s5
+; CHECK-MVE-NEXT: vcmp.f16 s12, s4
+; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s9
-; CHECK-MVE-NEXT: vcmp.f16 s1, #0
-; CHECK-MVE-NEXT: vins.f16 s0, s12
-; CHECK-MVE-NEXT: cset r0, ls
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vmovx.f16 s8, s5
+; CHECK-MVE-NEXT: vcmp.f16 s12, s1
+; CHECK-MVE-NEXT: vins.f16 s0, s14
+; CHECK-MVE-NEXT: vselge.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s10
-; CHECK-MVE-NEXT: cset r0, ls
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
+; CHECK-MVE-NEXT: vmovx.f16 s8, s6
+; CHECK-MVE-NEXT: vselge.f16 s1, s5, s9
; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2
-; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: vmovx.f16 s4, s6
+; CHECK-MVE-NEXT: vcmp.f16 s12, s4
+; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s2, #0
-; CHECK-MVE-NEXT: cset r0, ls
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vcmp.f16 s12, s2
+; CHECK-MVE-NEXT: vselge.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, ls
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
-; CHECK-MVE-NEXT: vmovx.f16 s6, s11
+; CHECK-MVE-NEXT: vselge.f16 s2, s6, s10
+; CHECK-MVE-NEXT: vmovx.f16 s6, s7
; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3
-; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: vmovx.f16 s4, s7
+; CHECK-MVE-NEXT: vcmp.f16 s12, s4
+; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s3, #0
-; CHECK-MVE-NEXT: cset r0, ls
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
+; CHECK-MVE-NEXT: vcmp.f16 s12, s3
+; CHECK-MVE-NEXT: vselge.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, ls
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
+; CHECK-MVE-NEXT: vselge.f16 s3, s7, s11
; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr
+; CHECK-MVE-NEXT: .p2align 1
+; CHECK-MVE-NEXT: @ %bb.1:
+; CHECK-MVE-NEXT: .LCPI45_0:
+; CHECK-MVE-NEXT: .short 0x0000 @ half 0
;
; CHECK-MVEFP-LABEL: vcmp_r_oge_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry
@@ -2338,60 +1982,44 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_olt_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-LABEL: vcmp_r_olt_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s12, s0
-; CHECK-MVE-NEXT: vmovx.f16 s14, s8
+; CHECK-MVE-NEXT: vmovx.f16 s14, s4
; CHECK-MVE-NEXT: vcmp.f16 s12, #0
-; CHECK-MVE-NEXT: vmovx.f16 s12, s4
+; CHECK-MVE-NEXT: vmovx.f16 s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: cset r0, gt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vselgt.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, gt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
+; CHECK-MVE-NEXT: vselgt.f16 s0, s4, s8
; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: vmovx.f16 s4, s5
+; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s9
+; CHECK-MVE-NEXT: vmovx.f16 s8, s5
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
-; CHECK-MVE-NEXT: cset r0, gt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselgt.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s10
-; CHECK-MVE-NEXT: cset r0, gt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
+; CHECK-MVE-NEXT: vmovx.f16 s8, s6
+; CHECK-MVE-NEXT: vselgt.f16 s1, s5, s9
; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: vmovx.f16 s4, s6
+; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
-; CHECK-MVE-NEXT: cset r0, gt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselgt.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, gt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
-; CHECK-MVE-NEXT: vmovx.f16 s6, s11
+; CHECK-MVE-NEXT: vselgt.f16 s2, s6, s10
+; CHECK-MVE-NEXT: vmovx.f16 s6, s7
; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: vmovx.f16 s4, s7
+; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
-; CHECK-MVE-NEXT: cset r0, gt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
+; CHECK-MVE-NEXT: vselgt.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, gt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
+; CHECK-MVE-NEXT: vselgt.f16 s3, s7, s11
; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -2410,60 +2038,44 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ole_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-LABEL: vcmp_r_ole_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s12, s0
-; CHECK-MVE-NEXT: vmovx.f16 s14, s8
+; CHECK-MVE-NEXT: vmovx.f16 s14, s4
; CHECK-MVE-NEXT: vcmp.f16 s12, #0
-; CHECK-MVE-NEXT: vmovx.f16 s12, s4
+; CHECK-MVE-NEXT: vmovx.f16 s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: cset r0, ge
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vselge.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, ge
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
+; CHECK-MVE-NEXT: vselge.f16 s0, s4, s8
; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: vmovx.f16 s4, s5
+; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s9
+; CHECK-MVE-NEXT: vmovx.f16 s8, s5
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
-; CHECK-MVE-NEXT: cset r0, ge
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselge.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s10
-; CHECK-MVE-NEXT: cset r0, ge
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
+; CHECK-MVE-NEXT: vmovx.f16 s8, s6
+; CHECK-MVE-NEXT: vselge.f16 s1, s5, s9
; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: vmovx.f16 s4, s6
+; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
-; CHECK-MVE-NEXT: cset r0, ge
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselge.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, ge
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
-; CHECK-MVE-NEXT: vmovx.f16 s6, s11
+; CHECK-MVE-NEXT: vselge.f16 s2, s6, s10
+; CHECK-MVE-NEXT: vmovx.f16 s6, s7
; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: vmovx.f16 s4, s7
+; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
-; CHECK-MVE-NEXT: cset r0, ge
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
+; CHECK-MVE-NEXT: vselge.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, ge
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
+; CHECK-MVE-NEXT: vselge.f16 s3, s7, s11
; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -2482,68 +2094,52 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ueq_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-LABEL: vcmp_r_ueq_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s12, s0
-; CHECK-MVE-NEXT: vmovx.f16 s14, s8
+; CHECK-MVE-NEXT: vmovx.f16 s14, s4
; CHECK-MVE-NEXT: vcmp.f16 s12, #0
-; CHECK-MVE-NEXT: vmovx.f16 s12, s4
+; CHECK-MVE-NEXT: vmovx.f16 s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
-; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vselvs.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
+; CHECK-MVE-NEXT: vseleq.f16 s0, s4, s8
+; CHECK-MVE-NEXT: vmovx.f16 s8, s5
+; CHECK-MVE-NEXT: vselvs.f16 s0, s4, s0
; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: vmovx.f16 s4, s5
+; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
-; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselvs.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s10
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
+; CHECK-MVE-NEXT: vseleq.f16 s8, s5, s9
+; CHECK-MVE-NEXT: vselvs.f16 s1, s5, s8
+; CHECK-MVE-NEXT: vmovx.f16 s8, s6
; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: vmovx.f16 s4, s6
+; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
-; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselvs.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
-; CHECK-MVE-NEXT: vmovx.f16 s6, s11
+; CHECK-MVE-NEXT: vseleq.f16 s2, s6, s10
+; CHECK-MVE-NEXT: vselvs.f16 s2, s6, s2
+; CHECK-MVE-NEXT: vmovx.f16 s6, s7
; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: vmovx.f16 s4, s7
+; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
-; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
+; CHECK-MVE-NEXT: vselvs.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
+; CHECK-MVE-NEXT: vseleq.f16 s6, s7, s11
+; CHECK-MVE-NEXT: vselvs.f16 s3, s7, s6
; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -2624,13 +2220,9 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ugt_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: cset r0, lt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vselge.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, lt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
+; CHECK-MVE-NEXT: vselge.f16 s0, s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s5
@@ -2638,27 +2230,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ugt_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
-; CHECK-MVE-NEXT: cset r0, lt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselge.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s10
-; CHECK-MVE-NEXT: cset r0, lt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
+; CHECK-MVE-NEXT: vselge.f16 s1, s9, s5
; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
-; CHECK-MVE-NEXT: cset r0, lt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselge.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, lt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
+; CHECK-MVE-NEXT: vselge.f16 s2, s10, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3
@@ -2666,13 +2250,9 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ugt_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
-; CHECK-MVE-NEXT: cset r0, lt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
+; CHECK-MVE-NEXT: vselge.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, lt
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
+; CHECK-MVE-NEXT: vselge.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -2696,13 +2276,9 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_uge_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: cset r0, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vselgt.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
+; CHECK-MVE-NEXT: vselgt.f16 s0, s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s5
@@ -2710,27 +2286,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_uge_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
-; CHECK-MVE-NEXT: cset r0, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselgt.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s10
-; CHECK-MVE-NEXT: cset r0, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
+; CHECK-MVE-NEXT: vselgt.f16 s1, s9, s5
; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
-; CHECK-MVE-NEXT: cset r0, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselgt.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
+; CHECK-MVE-NEXT: vselgt.f16 s2, s10, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3
@@ -2738,13 +2306,9 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_uge_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
-; CHECK-MVE-NEXT: cset r0, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
+; CHECK-MVE-NEXT: vselgt.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, le
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
+; CHECK-MVE-NEXT: vselgt.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -2762,63 +2326,52 @@ entry:
define arm_aapcs_vfpcc <8 x half> @vcmp_r_ult_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_ult_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vmovx.f16 s12, s0
-; CHECK-MVE-NEXT: vmovx.f16 s14, s8
-; CHECK-MVE-NEXT: vcmp.f16 s12, #0
-; CHECK-MVE-NEXT: vmovx.f16 s12, s4
+; CHECK-MVE-NEXT: vldr.16 s12, .LCPI52_0
+; CHECK-MVE-NEXT: vmovx.f16 s14, s0
+; CHECK-MVE-NEXT: vmovx.f16 s13, s8
+; CHECK-MVE-NEXT: vcmp.f16 s12, s14
+; CHECK-MVE-NEXT: vmovx.f16 s14, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: cset r0, hi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vcmp.f16 s12, s0
+; CHECK-MVE-NEXT: vselge.f16 s14, s13, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, hi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
+; CHECK-MVE-NEXT: vselge.f16 s0, s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s1
-; CHECK-MVE-NEXT: vcmp.f16 s4, #0
+; CHECK-MVE-NEXT: vcmp.f16 s12, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s9
-; CHECK-MVE-NEXT: vcmp.f16 s1, #0
-; CHECK-MVE-NEXT: vins.f16 s0, s12
-; CHECK-MVE-NEXT: cset r0, hi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vcmp.f16 s12, s1
+; CHECK-MVE-NEXT: vins.f16 s0, s14
+; CHECK-MVE-NEXT: vselge.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s10
-; CHECK-MVE-NEXT: cset r0, hi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
+; CHECK-MVE-NEXT: vselge.f16 s1, s9, s5
; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2
-; CHECK-MVE-NEXT: vcmp.f16 s4, #0
+; CHECK-MVE-NEXT: vcmp.f16 s12, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s2, #0
-; CHECK-MVE-NEXT: cset r0, hi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vcmp.f16 s12, s2
+; CHECK-MVE-NEXT: vselge.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, hi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
+; CHECK-MVE-NEXT: vselge.f16 s2, s10, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3
-; CHECK-MVE-NEXT: vcmp.f16 s4, #0
+; CHECK-MVE-NEXT: vcmp.f16 s12, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s3, #0
-; CHECK-MVE-NEXT: cset r0, hi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
+; CHECK-MVE-NEXT: vcmp.f16 s12, s3
+; CHECK-MVE-NEXT: vselge.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, hi
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
+; CHECK-MVE-NEXT: vselge.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr
+; CHECK-MVE-NEXT: .p2align 1
+; CHECK-MVE-NEXT: @ %bb.1:
+; CHECK-MVE-NEXT: .LCPI52_0:
+; CHECK-MVE-NEXT: .short 0x0000 @ half 0
;
; CHECK-MVEFP-LABEL: vcmp_r_ult_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry
@@ -2834,63 +2387,52 @@ entry:
define arm_aapcs_vfpcc <8 x half> @vcmp_r_ule_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_ule_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vmovx.f16 s12, s0
-; CHECK-MVE-NEXT: vmovx.f16 s14, s8
-; CHECK-MVE-NEXT: vcmp.f16 s12, #0
-; CHECK-MVE-NEXT: vmovx.f16 s12, s4
+; CHECK-MVE-NEXT: vldr.16 s12, .LCPI53_0
+; CHECK-MVE-NEXT: vmovx.f16 s14, s0
+; CHECK-MVE-NEXT: vmovx.f16 s13, s8
+; CHECK-MVE-NEXT: vcmp.f16 s12, s14
+; CHECK-MVE-NEXT: vmovx.f16 s14, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: cset r0, pl
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vcmp.f16 s12, s0
+; CHECK-MVE-NEXT: vselgt.f16 s14, s13, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, pl
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
+; CHECK-MVE-NEXT: vselgt.f16 s0, s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s1
-; CHECK-MVE-NEXT: vcmp.f16 s4, #0
+; CHECK-MVE-NEXT: vcmp.f16 s12, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s9
-; CHECK-MVE-NEXT: vcmp.f16 s1, #0
-; CHECK-MVE-NEXT: vins.f16 s0, s12
-; CHECK-MVE-NEXT: cset r0, pl
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vcmp.f16 s12, s1
+; CHECK-MVE-NEXT: vins.f16 s0, s14
+; CHECK-MVE-NEXT: vselgt.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s10
-; CHECK-MVE-NEXT: cset r0, pl
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
+; CHECK-MVE-NEXT: vselgt.f16 s1, s9, s5
; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2
-; CHECK-MVE-NEXT: vcmp.f16 s4, #0
+; CHECK-MVE-NEXT: vcmp.f16 s12, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s2, #0
-; CHECK-MVE-NEXT: cset r0, pl
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vcmp.f16 s12, s2
+; CHECK-MVE-NEXT: vselgt.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, pl
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
+; CHECK-MVE-NEXT: vselgt.f16 s2, s10, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3
-; CHECK-MVE-NEXT: vcmp.f16 s4, #0
+; CHECK-MVE-NEXT: vcmp.f16 s12, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s3, #0
-; CHECK-MVE-NEXT: cset r0, pl
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
+; CHECK-MVE-NEXT: vcmp.f16 s12, s3
+; CHECK-MVE-NEXT: vselgt.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, pl
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
+; CHECK-MVE-NEXT: vselgt.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr
+; CHECK-MVE-NEXT: .p2align 1
+; CHECK-MVE-NEXT: @ %bb.1:
+; CHECK-MVE-NEXT: .LCPI53_0:
+; CHECK-MVE-NEXT: .short 0x0000 @ half 0
;
; CHECK-MVEFP-LABEL: vcmp_r_ule_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry
@@ -2912,13 +2454,9 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ord_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s0, s0
-; CHECK-MVE-NEXT: cset r0, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vselvs.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
+; CHECK-MVE-NEXT: vselvs.f16 s0, s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s5
@@ -2926,27 +2464,19 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ord_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, s1
; CHECK-MVE-NEXT: vins.f16 s0, s12
-; CHECK-MVE-NEXT: cset r0, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselvs.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s10
-; CHECK-MVE-NEXT: cset r0, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
+; CHECK-MVE-NEXT: vselvs.f16 s1, s9, s5
; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s2, s2
-; CHECK-MVE-NEXT: cset r0, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselvs.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
+; CHECK-MVE-NEXT: vselvs.f16 s2, s10, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3
@@ -2954,13 +2484,9 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_ord_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s3, s3
-; CHECK-MVE-NEXT: cset r0, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
+; CHECK-MVE-NEXT: vselvs.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, vc
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
+; CHECK-MVE-NEXT: vselvs.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -2980,60 +2506,44 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_uno_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-LABEL: vcmp_r_uno_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s12, s0
-; CHECK-MVE-NEXT: vmovx.f16 s14, s8
+; CHECK-MVE-NEXT: vmovx.f16 s14, s4
; CHECK-MVE-NEXT: vcmp.f16 s12, s12
-; CHECK-MVE-NEXT: vmovx.f16 s12, s4
+; CHECK-MVE-NEXT: vmovx.f16 s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s0, s0
-; CHECK-MVE-NEXT: cset r0, vs
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
+; CHECK-MVE-NEXT: vselvs.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, vs
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
+; CHECK-MVE-NEXT: vselvs.f16 s0, s4, s8
; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s4
-; CHECK-MVE-NEXT: vmovx.f16 s4, s5
+; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s9
+; CHECK-MVE-NEXT: vmovx.f16 s8, s5
; CHECK-MVE-NEXT: vcmp.f16 s1, s1
; CHECK-MVE-NEXT: vins.f16 s0, s12
-; CHECK-MVE-NEXT: cset r0, vs
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselvs.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s10
-; CHECK-MVE-NEXT: cset r0, vs
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
+; CHECK-MVE-NEXT: vmovx.f16 s8, s6
+; CHECK-MVE-NEXT: vselvs.f16 s1, s5, s9
; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s4
-; CHECK-MVE-NEXT: vmovx.f16 s4, s6
+; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s2, s2
-; CHECK-MVE-NEXT: cset r0, vs
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
+; CHECK-MVE-NEXT: vselvs.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, vs
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
-; CHECK-MVE-NEXT: vmovx.f16 s6, s11
+; CHECK-MVE-NEXT: vselvs.f16 s2, s6, s10
+; CHECK-MVE-NEXT: vmovx.f16 s6, s7
; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s4
-; CHECK-MVE-NEXT: vmovx.f16 s4, s7
+; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s3, s3
-; CHECK-MVE-NEXT: cset r0, vs
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
+; CHECK-MVE-NEXT: vselvs.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: cset r0, vs
-; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
+; CHECK-MVE-NEXT: vselvs.f16 s3, s7, s11
; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr
;
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