[llvm] [AArch64][ISel] Remove zero instruction for `rev` all true predicates (PR #192925)
Harry Ramsey via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 27 07:36:35 PDT 2026
https://github.com/Harry-Ramsey updated https://github.com/llvm/llvm-project/pull/192925
>From 270043271678567155f6ed8c2cf3f749f0ac076c Mon Sep 17 00:00:00 2001
From: Harry Ramsey <harry.ramsey at arm.com>
Date: Mon, 20 Apr 2026 08:39:01 +0000
Subject: [PATCH 1/3] [AArch64][ISel] Remove zero instruction for `rev` all
true predicates
This patch removes the redundant instruction to zero inactive lanes for
SVE2p1 `rev` intrinsics when all lanes are active.
---
.../Target/AArch64/AArch64ISelLowering.cpp | 28 ++++-
.../AArch64/sve2-intrinsics-rev-all-lanes.ll | 116 ++++++++++++++++++
2 files changed, 140 insertions(+), 4 deletions(-)
create mode 100644 llvm/test/CodeGen/AArch64/sve2-intrinsics-rev-all-lanes.ll
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 189347f9e07e8..5df91bbc6c31c 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -6827,18 +6827,38 @@ SDValue AArch64TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
return DAG.getNode(AArch64ISD::BITREVERSE_MERGE_PASSTHRU, DL,
Op.getValueType(), Op.getOperand(2), Op.getOperand(3),
Op.getOperand(1));
- case Intrinsic::aarch64_sve_revb:
+ case Intrinsic::aarch64_sve_revb: {
+ if (isAllActivePredicate(DAG, Op.getOperand(2)))
+ return DAG.getNode(AArch64ISD::BSWAP_MERGE_PASSTHRU, DL,
+ Op.getValueType(), Op.getOperand(2), Op.getOperand(3),
+ DAG.getUNDEF(Op.getValueType()));
return DAG.getNode(AArch64ISD::BSWAP_MERGE_PASSTHRU, DL, Op.getValueType(),
Op.getOperand(2), Op.getOperand(3), Op.getOperand(1));
- case Intrinsic::aarch64_sve_revh:
+ }
+ case Intrinsic::aarch64_sve_revh: {
+ if (isAllActivePredicate(DAG, Op.getOperand(2)))
+ return DAG.getNode(AArch64ISD::REVH_MERGE_PASSTHRU, DL, Op.getValueType(),
+ Op.getOperand(2), Op.getOperand(3),
+ DAG.getUNDEF(Op.getValueType()));
return DAG.getNode(AArch64ISD::REVH_MERGE_PASSTHRU, DL, Op.getValueType(),
Op.getOperand(2), Op.getOperand(3), Op.getOperand(1));
- case Intrinsic::aarch64_sve_revw:
+ }
+ case Intrinsic::aarch64_sve_revw: {
+ if (isAllActivePredicate(DAG, Op.getOperand(2)))
+ return DAG.getNode(AArch64ISD::REVW_MERGE_PASSTHRU, DL, Op.getValueType(),
+ Op.getOperand(2), Op.getOperand(3),
+ DAG.getUNDEF(Op.getValueType()));
return DAG.getNode(AArch64ISD::REVW_MERGE_PASSTHRU, DL, Op.getValueType(),
Op.getOperand(2), Op.getOperand(3), Op.getOperand(1));
- case Intrinsic::aarch64_sve_revd:
+ }
+ case Intrinsic::aarch64_sve_revd: {
+ if (isAllActivePredicate(DAG, Op.getOperand(2)))
+ return DAG.getNode(AArch64ISD::REVD_MERGE_PASSTHRU, DL, Op.getValueType(),
+ Op.getOperand(2), Op.getOperand(3),
+ DAG.getUNDEF(Op.getValueType()));
return DAG.getNode(AArch64ISD::REVD_MERGE_PASSTHRU, DL, Op.getValueType(),
Op.getOperand(2), Op.getOperand(3), Op.getOperand(1));
+ }
case Intrinsic::aarch64_sve_sxtb:
return DAG.getNode(
AArch64ISD::SIGN_EXTEND_INREG_MERGE_PASSTHRU, DL, Op.getValueType(),
diff --git a/llvm/test/CodeGen/AArch64/sve2-intrinsics-rev-all-lanes.ll b/llvm/test/CodeGen/AArch64/sve2-intrinsics-rev-all-lanes.ll
new file mode 100644
index 0000000000000..fb51aa6b05afc
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve2-intrinsics-rev-all-lanes.ll
@@ -0,0 +1,116 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p1 -verify-machineinstrs < %s | FileCheck %s
+
+define <vscale x 16 x i8> @test_revd_i8(<vscale x 16 x i8> %a) {
+; CHECK-LABEL: test_revd_i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: revd z0.q, p0/m, z0.q
+; CHECK-NEXT: ret
+ %res = call <vscale x 16 x i8> @llvm.aarch64.sve.revd.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> splat (i1 true), <vscale x 16 x i8> %a)
+ ret <vscale x 16 x i8> %res
+}
+
+define <vscale x 8 x i16> @test_revd_i16(<vscale x 8 x i16> %a) {
+; CHECK-LABEL: test_revd_i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: revd z0.q, p0/m, z0.q
+; CHECK-NEXT: ret
+ %res = call <vscale x 8 x i16> @llvm.aarch64.sve.revd.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> splat (i1 true), <vscale x 8 x i16> %a)
+ ret <vscale x 8 x i16> %res
+}
+
+define <vscale x 4 x i32> @test_revd_i32(<vscale x 4 x i32> %a) {
+; CHECK-LABEL: test_revd_i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: revd z0.q, p0/m, z0.q
+; CHECK-NEXT: ret
+ %res = call <vscale x 4 x i32> @llvm.aarch64.sve.revd.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> %a)
+ ret <vscale x 4 x i32> %res
+}
+
+define <vscale x 2 x i64> @test_revd_i64(<vscale x 2 x i64> %a) {
+; CHECK-LABEL: test_revd_i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: revd z0.q, p0/m, z0.q
+; CHECK-NEXT: ret
+ %res = call <vscale x 2 x i64> @llvm.aarch64.sve.revd.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> splat (i1 true), <vscale x 2 x i64> %a)
+ ret <vscale x 2 x i64> %res
+}
+
+define <vscale x 8 x i16> @test_revb_i16(<vscale x 8 x i16> %a) {
+; CHECK-LABEL: test_revb_i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: revb z0.h, p0/m, z0.h
+; CHECK-NEXT: ret
+ %res = call <vscale x 8 x i16> @llvm.aarch64.sve.revb.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> splat (i1 true), <vscale x 8 x i16> %a)
+ ret <vscale x 8 x i16> %res
+}
+
+define <vscale x 4 x i32> @test_revb_i32(<vscale x 4 x i32> %a) {
+; CHECK-LABEL: test_revb_i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: revb z0.s, p0/m, z0.s
+; CHECK-NEXT: ret
+ %res = call <vscale x 4 x i32> @llvm.aarch64.sve.revb.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> %a)
+ ret <vscale x 4 x i32> %res
+}
+
+define <vscale x 2 x i64> @test_revb_i64(<vscale x 2 x i64> %a) {
+; CHECK-LABEL: test_revb_i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: revb z0.d, p0/m, z0.d
+; CHECK-NEXT: ret
+ %res = call <vscale x 2 x i64> @llvm.aarch64.sve.revb.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> splat (i1 true), <vscale x 2 x i64> %a)
+ ret <vscale x 2 x i64> %res
+}
+
+define <vscale x 4 x i32> @test_revh_i32(<vscale x 4 x i32> %a) {
+; CHECK-LABEL: test_revh_i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: revh z0.s, p0/m, z0.s
+; CHECK-NEXT: ret
+ %res = call <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> %a)
+ ret <vscale x 4 x i32> %res
+}
+
+define <vscale x 2 x i64> @test_revh_i64(<vscale x 2 x i64> %a) {
+; CHECK-LABEL: test_revh_i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: revh z0.d, p0/m, z0.d
+; CHECK-NEXT: ret
+ %res = call <vscale x 2 x i64> @llvm.aarch64.sve.revh.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> splat (i1 true), <vscale x 2 x i64> %a)
+ ret <vscale x 2 x i64> %res
+}
+
+define <vscale x 2 x i64> @test_revw_i64(<vscale x 2 x i64> %a) {
+; CHECK-LABEL: test_revw_i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: revw z0.d, p0/m, z0.d
+; CHECK-NEXT: ret
+ %res = call <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> splat (i1 true), <vscale x 2 x i64> %a)
+ ret <vscale x 2 x i64> %res
+}
+
+declare <vscale x 16 x i8> @llvm.aarch64.sve.revd.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>)
+declare <vscale x 8 x i16> @llvm.aarch64.sve.revd.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>)
+declare <vscale x 4 x i32> @llvm.aarch64.sve.revd.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)
+declare <vscale x 2 x i64> @llvm.aarch64.sve.revd.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>)
+
+declare <vscale x 8 x i16> @llvm.aarch64.sve.revb.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>)
+declare <vscale x 4 x i32> @llvm.aarch64.sve.revb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)
+declare <vscale x 2 x i64> @llvm.aarch64.sve.revb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>)
+
+declare <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)
+declare <vscale x 2 x i64> @llvm.aarch64.sve.revh.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>)
+
+declare <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>)
>From 041b5abad50a1706b7e8c4e6ca58018d1f90e6d4 Mon Sep 17 00:00:00 2001
From: Harry Ramsey <harry.ramsey at arm.com>
Date: Mon, 20 Apr 2026 12:16:35 +0000
Subject: [PATCH 2/3] fixup! [AArch64][ISel] Remove zero instruction for `rev`
all true predicates
---
.../AArch64/sve2-intrinsics-rev-all-lanes.ll | 13 -------------
1 file changed, 13 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/sve2-intrinsics-rev-all-lanes.ll b/llvm/test/CodeGen/AArch64/sve2-intrinsics-rev-all-lanes.ll
index fb51aa6b05afc..9112524e34d76 100644
--- a/llvm/test/CodeGen/AArch64/sve2-intrinsics-rev-all-lanes.ll
+++ b/llvm/test/CodeGen/AArch64/sve2-intrinsics-rev-all-lanes.ll
@@ -101,16 +101,3 @@ define <vscale x 2 x i64> @test_revw_i64(<vscale x 2 x i64> %a) {
ret <vscale x 2 x i64> %res
}
-declare <vscale x 16 x i8> @llvm.aarch64.sve.revd.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>)
-declare <vscale x 8 x i16> @llvm.aarch64.sve.revd.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>)
-declare <vscale x 4 x i32> @llvm.aarch64.sve.revd.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)
-declare <vscale x 2 x i64> @llvm.aarch64.sve.revd.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>)
-
-declare <vscale x 8 x i16> @llvm.aarch64.sve.revb.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>)
-declare <vscale x 4 x i32> @llvm.aarch64.sve.revb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)
-declare <vscale x 2 x i64> @llvm.aarch64.sve.revb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>)
-
-declare <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)
-declare <vscale x 2 x i64> @llvm.aarch64.sve.revh.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>)
-
-declare <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>)
>From 2f5fa3be5937746d8f51bbea4b5c1e75aac37ea3 Mon Sep 17 00:00:00 2001
From: Harry Ramsey <harry.ramsey at arm.com>
Date: Thu, 23 Apr 2026 15:13:21 +0000
Subject: [PATCH 3/3] amend! [AArch64][ISel] Remove zero instruction for `rev`
all true predicates
[AArch64][Transform] Remove zero instruction for `rev` all true predicates
This patch removes the redundant instruction to zero inactive lanes for
SVE2p1 `rev` intrinsics when all lanes are active.
---
.../Target/AArch64/AArch64ISelLowering.cpp | 16 ---
.../AArch64/AArch64TargetTransformInfo.cpp | 4 +
.../AArch64/sve2-intrinsics-rev-all-lanes.ll | 103 ------------------
...sve-intrinsic-comb-all-active-lanes-cvt.ll | 100 +++++++++++++++++
.../sve-intrinsic-comb-no-active-lanes.ll | 12 +-
5 files changed, 108 insertions(+), 127 deletions(-)
delete mode 100644 llvm/test/CodeGen/AArch64/sve2-intrinsics-rev-all-lanes.ll
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 5df91bbc6c31c..0d5b174fbfa22 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -6828,34 +6828,18 @@ SDValue AArch64TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
Op.getValueType(), Op.getOperand(2), Op.getOperand(3),
Op.getOperand(1));
case Intrinsic::aarch64_sve_revb: {
- if (isAllActivePredicate(DAG, Op.getOperand(2)))
- return DAG.getNode(AArch64ISD::BSWAP_MERGE_PASSTHRU, DL,
- Op.getValueType(), Op.getOperand(2), Op.getOperand(3),
- DAG.getUNDEF(Op.getValueType()));
return DAG.getNode(AArch64ISD::BSWAP_MERGE_PASSTHRU, DL, Op.getValueType(),
Op.getOperand(2), Op.getOperand(3), Op.getOperand(1));
}
case Intrinsic::aarch64_sve_revh: {
- if (isAllActivePredicate(DAG, Op.getOperand(2)))
- return DAG.getNode(AArch64ISD::REVH_MERGE_PASSTHRU, DL, Op.getValueType(),
- Op.getOperand(2), Op.getOperand(3),
- DAG.getUNDEF(Op.getValueType()));
return DAG.getNode(AArch64ISD::REVH_MERGE_PASSTHRU, DL, Op.getValueType(),
Op.getOperand(2), Op.getOperand(3), Op.getOperand(1));
}
case Intrinsic::aarch64_sve_revw: {
- if (isAllActivePredicate(DAG, Op.getOperand(2)))
- return DAG.getNode(AArch64ISD::REVW_MERGE_PASSTHRU, DL, Op.getValueType(),
- Op.getOperand(2), Op.getOperand(3),
- DAG.getUNDEF(Op.getValueType()));
return DAG.getNode(AArch64ISD::REVW_MERGE_PASSTHRU, DL, Op.getValueType(),
Op.getOperand(2), Op.getOperand(3), Op.getOperand(1));
}
case Intrinsic::aarch64_sve_revd: {
- if (isAllActivePredicate(DAG, Op.getOperand(2)))
- return DAG.getNode(AArch64ISD::REVD_MERGE_PASSTHRU, DL, Op.getValueType(),
- Op.getOperand(2), Op.getOperand(3),
- DAG.getUNDEF(Op.getValueType()));
return DAG.getNode(AArch64ISD::REVD_MERGE_PASSTHRU, DL, Op.getValueType(),
Op.getOperand(2), Op.getOperand(3), Op.getOperand(1));
}
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
index 2947518f223f4..e945569ff9b3c 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -1461,6 +1461,10 @@ static SVEIntrinsicInfo constructSVEIntrinsicInfo(IntrinsicInst &II) {
case Intrinsic::aarch64_sve_fcvtzu_i32f64:
case Intrinsic::aarch64_sve_fcvtzu_i64f16:
case Intrinsic::aarch64_sve_fcvtzu_i64f32:
+ case Intrinsic::aarch64_sve_revb:
+ case Intrinsic::aarch64_sve_revh:
+ case Intrinsic::aarch64_sve_revw:
+ case Intrinsic::aarch64_sve_revd:
case Intrinsic::aarch64_sve_scvtf:
case Intrinsic::aarch64_sve_scvtf_f16i32:
case Intrinsic::aarch64_sve_scvtf_f16i64:
diff --git a/llvm/test/CodeGen/AArch64/sve2-intrinsics-rev-all-lanes.ll b/llvm/test/CodeGen/AArch64/sve2-intrinsics-rev-all-lanes.ll
deleted file mode 100644
index 9112524e34d76..0000000000000
--- a/llvm/test/CodeGen/AArch64/sve2-intrinsics-rev-all-lanes.ll
+++ /dev/null
@@ -1,103 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p1 -verify-machineinstrs < %s | FileCheck %s
-
-define <vscale x 16 x i8> @test_revd_i8(<vscale x 16 x i8> %a) {
-; CHECK-LABEL: test_revd_i8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ptrue p0.b
-; CHECK-NEXT: revd z0.q, p0/m, z0.q
-; CHECK-NEXT: ret
- %res = call <vscale x 16 x i8> @llvm.aarch64.sve.revd.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> splat (i1 true), <vscale x 16 x i8> %a)
- ret <vscale x 16 x i8> %res
-}
-
-define <vscale x 8 x i16> @test_revd_i16(<vscale x 8 x i16> %a) {
-; CHECK-LABEL: test_revd_i16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ptrue p0.h
-; CHECK-NEXT: revd z0.q, p0/m, z0.q
-; CHECK-NEXT: ret
- %res = call <vscale x 8 x i16> @llvm.aarch64.sve.revd.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> splat (i1 true), <vscale x 8 x i16> %a)
- ret <vscale x 8 x i16> %res
-}
-
-define <vscale x 4 x i32> @test_revd_i32(<vscale x 4 x i32> %a) {
-; CHECK-LABEL: test_revd_i32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: revd z0.q, p0/m, z0.q
-; CHECK-NEXT: ret
- %res = call <vscale x 4 x i32> @llvm.aarch64.sve.revd.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> %a)
- ret <vscale x 4 x i32> %res
-}
-
-define <vscale x 2 x i64> @test_revd_i64(<vscale x 2 x i64> %a) {
-; CHECK-LABEL: test_revd_i64:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: revd z0.q, p0/m, z0.q
-; CHECK-NEXT: ret
- %res = call <vscale x 2 x i64> @llvm.aarch64.sve.revd.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> splat (i1 true), <vscale x 2 x i64> %a)
- ret <vscale x 2 x i64> %res
-}
-
-define <vscale x 8 x i16> @test_revb_i16(<vscale x 8 x i16> %a) {
-; CHECK-LABEL: test_revb_i16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ptrue p0.h
-; CHECK-NEXT: revb z0.h, p0/m, z0.h
-; CHECK-NEXT: ret
- %res = call <vscale x 8 x i16> @llvm.aarch64.sve.revb.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> splat (i1 true), <vscale x 8 x i16> %a)
- ret <vscale x 8 x i16> %res
-}
-
-define <vscale x 4 x i32> @test_revb_i32(<vscale x 4 x i32> %a) {
-; CHECK-LABEL: test_revb_i32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: revb z0.s, p0/m, z0.s
-; CHECK-NEXT: ret
- %res = call <vscale x 4 x i32> @llvm.aarch64.sve.revb.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> %a)
- ret <vscale x 4 x i32> %res
-}
-
-define <vscale x 2 x i64> @test_revb_i64(<vscale x 2 x i64> %a) {
-; CHECK-LABEL: test_revb_i64:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: revb z0.d, p0/m, z0.d
-; CHECK-NEXT: ret
- %res = call <vscale x 2 x i64> @llvm.aarch64.sve.revb.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> splat (i1 true), <vscale x 2 x i64> %a)
- ret <vscale x 2 x i64> %res
-}
-
-define <vscale x 4 x i32> @test_revh_i32(<vscale x 4 x i32> %a) {
-; CHECK-LABEL: test_revh_i32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ptrue p0.s
-; CHECK-NEXT: revh z0.s, p0/m, z0.s
-; CHECK-NEXT: ret
- %res = call <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> %a)
- ret <vscale x 4 x i32> %res
-}
-
-define <vscale x 2 x i64> @test_revh_i64(<vscale x 2 x i64> %a) {
-; CHECK-LABEL: test_revh_i64:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: revh z0.d, p0/m, z0.d
-; CHECK-NEXT: ret
- %res = call <vscale x 2 x i64> @llvm.aarch64.sve.revh.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> splat (i1 true), <vscale x 2 x i64> %a)
- ret <vscale x 2 x i64> %res
-}
-
-define <vscale x 2 x i64> @test_revw_i64(<vscale x 2 x i64> %a) {
-; CHECK-LABEL: test_revw_i64:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: revw z0.d, p0/m, z0.d
-; CHECK-NEXT: ret
- %res = call <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> splat (i1 true), <vscale x 2 x i64> %a)
- ret <vscale x 2 x i64> %res
-}
-
diff --git a/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-comb-all-active-lanes-cvt.ll b/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-comb-all-active-lanes-cvt.ll
index 1c5f7464d858a..3662fbcb8e230 100644
--- a/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-comb-all-active-lanes-cvt.ll
+++ b/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-comb-all-active-lanes-cvt.ll
@@ -277,6 +277,106 @@ define <vscale x 2 x i64> @test_fcvtzu_i64_f32(<vscale x 2 x i64> %a, <vscale x
ret <vscale x 2 x i64> %out
}
+define <vscale x 16 x i8> @test_revd_i8(<vscale x 16 x i8> %a) {
+; CHECK-LABEL: define <vscale x 16 x i8> @test_revd_i8(
+; CHECK-SAME: <vscale x 16 x i8> [[A:%.*]]) {
+; CHECK-NEXT: [[RES:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.revd.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i1> splat (i1 true), <vscale x 16 x i8> [[A]])
+; CHECK-NEXT: ret <vscale x 16 x i8> [[RES]]
+;
+ %res = tail call <vscale x 16 x i8> @llvm.aarch64.sve.revd.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> splat (i1 true), <vscale x 16 x i8> %a)
+ ret <vscale x 16 x i8> %res
+}
+
+define <vscale x 8 x i16> @test_revd_i16(<vscale x 8 x i16> %a) {
+; CHECK-LABEL: define <vscale x 8 x i16> @test_revd_i16(
+; CHECK-SAME: <vscale x 8 x i16> [[A:%.*]]) {
+; CHECK-NEXT: [[RES:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.revd.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i1> splat (i1 true), <vscale x 8 x i16> [[A]])
+; CHECK-NEXT: ret <vscale x 8 x i16> [[RES]]
+;
+ %res = call <vscale x 8 x i16> @llvm.aarch64.sve.revd.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> splat (i1 true), <vscale x 8 x i16> %a)
+ ret <vscale x 8 x i16> %res
+}
+
+define <vscale x 4 x i32> @test_revd_i32(<vscale x 4 x i32> %a) {
+; CHECK-LABEL: define <vscale x 4 x i32> @test_revd_i32(
+; CHECK-SAME: <vscale x 4 x i32> [[A:%.*]]) {
+; CHECK-NEXT: [[RES:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.revd.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> [[A]])
+; CHECK-NEXT: ret <vscale x 4 x i32> [[RES]]
+;
+ %res = call <vscale x 4 x i32> @llvm.aarch64.sve.revd.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> %a)
+ ret <vscale x 4 x i32> %res
+}
+
+define <vscale x 2 x i64> @test_revd_i64(<vscale x 2 x i64> %a) {
+; CHECK-LABEL: define <vscale x 2 x i64> @test_revd_i64(
+; CHECK-SAME: <vscale x 2 x i64> [[A:%.*]]) {
+; CHECK-NEXT: [[RES:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.revd.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> splat (i1 true), <vscale x 2 x i64> [[A]])
+; CHECK-NEXT: ret <vscale x 2 x i64> [[RES]]
+;
+ %res = call <vscale x 2 x i64> @llvm.aarch64.sve.revd.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> splat (i1 true), <vscale x 2 x i64> %a)
+ ret <vscale x 2 x i64> %res
+}
+
+define <vscale x 8 x i16> @test_revb_i16(<vscale x 8 x i16> %a) {
+; CHECK-LABEL: define <vscale x 8 x i16> @test_revb_i16(
+; CHECK-SAME: <vscale x 8 x i16> [[A:%.*]]) {
+; CHECK-NEXT: [[RES:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.revb.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i1> splat (i1 true), <vscale x 8 x i16> [[A]])
+; CHECK-NEXT: ret <vscale x 8 x i16> [[RES]]
+;
+ %res = call <vscale x 8 x i16> @llvm.aarch64.sve.revb.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> splat (i1 true), <vscale x 8 x i16> %a)
+ ret <vscale x 8 x i16> %res
+}
+
+define <vscale x 4 x i32> @test_revb_i32(<vscale x 4 x i32> %a) {
+; CHECK-LABEL: define <vscale x 4 x i32> @test_revb_i32(
+; CHECK-SAME: <vscale x 4 x i32> [[A:%.*]]) {
+; CHECK-NEXT: [[RES:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.revb.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> [[A]])
+; CHECK-NEXT: ret <vscale x 4 x i32> [[RES]]
+;
+ %res = call <vscale x 4 x i32> @llvm.aarch64.sve.revb.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> %a)
+ ret <vscale x 4 x i32> %res
+}
+
+define <vscale x 2 x i64> @test_revb_i64(<vscale x 2 x i64> %a) {
+; CHECK-LABEL: define <vscale x 2 x i64> @test_revb_i64(
+; CHECK-SAME: <vscale x 2 x i64> [[A:%.*]]) {
+; CHECK-NEXT: [[RES:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.revb.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> splat (i1 true), <vscale x 2 x i64> [[A]])
+; CHECK-NEXT: ret <vscale x 2 x i64> [[RES]]
+;
+ %res = call <vscale x 2 x i64> @llvm.aarch64.sve.revb.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> splat (i1 true), <vscale x 2 x i64> %a)
+ ret <vscale x 2 x i64> %res
+}
+
+define <vscale x 4 x i32> @test_revh_i32(<vscale x 4 x i32> %a) {
+; CHECK-LABEL: define <vscale x 4 x i32> @test_revh_i32(
+; CHECK-SAME: <vscale x 4 x i32> [[A:%.*]]) {
+; CHECK-NEXT: [[RES:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> [[A]])
+; CHECK-NEXT: ret <vscale x 4 x i32> [[RES]]
+;
+ %res = call <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> %a)
+ ret <vscale x 4 x i32> %res
+}
+
+define <vscale x 2 x i64> @test_revh_i64(<vscale x 2 x i64> %a) {
+; CHECK-LABEL: define <vscale x 2 x i64> @test_revh_i64(
+; CHECK-SAME: <vscale x 2 x i64> [[A:%.*]]) {
+; CHECK-NEXT: [[RES:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.revh.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> splat (i1 true), <vscale x 2 x i64> [[A]])
+; CHECK-NEXT: ret <vscale x 2 x i64> [[RES]]
+;
+ %res = call <vscale x 2 x i64> @llvm.aarch64.sve.revh.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> splat (i1 true), <vscale x 2 x i64> %a)
+ ret <vscale x 2 x i64> %res
+}
+
+define <vscale x 2 x i64> @test_revw_i64(<vscale x 2 x i64> %a) {
+; CHECK-LABEL: define <vscale x 2 x i64> @test_revw_i64(
+; CHECK-SAME: <vscale x 2 x i64> [[A:%.*]]) {
+; CHECK-NEXT: [[RES:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> splat (i1 true), <vscale x 2 x i64> [[A]])
+; CHECK-NEXT: ret <vscale x 2 x i64> [[RES]]
+;
+ %res = call <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> splat (i1 true), <vscale x 2 x i64> %a)
+ ret <vscale x 2 x i64> %res
+}
+
define <vscale x 8 x half> @test_scvtf(<vscale x 8 x half> %a, <vscale x 8 x i16> %b) {
; CHECK-LABEL: define <vscale x 8 x half> @test_scvtf(
; CHECK-SAME: <vscale x 8 x half> [[A:%.*]], <vscale x 8 x i16> [[B:%.*]]) {
diff --git a/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-comb-no-active-lanes.ll b/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-comb-no-active-lanes.ll
index f082bddbf9fec..22500fcc37efc 100644
--- a/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-comb-no-active-lanes.ll
+++ b/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-comb-no-active-lanes.ll
@@ -655,8 +655,7 @@ declare <vscale x 4 x i32> @llvm.aarch64.sve.revb.nxv4i32(<vscale x 4 x i32>, <v
define <vscale x 4 x i32> @simplify_revb_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
; CHECK-LABEL: define <vscale x 4 x i32> @simplify_revb_intrinsic
; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) {
-; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.revb.nxv4i32(<vscale x 4 x i32> [[A]], <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[B]])
-; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]
+; CHECK-NEXT: ret <vscale x 4 x i32> [[A]]
;
%r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.revb.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %b)
ret <vscale x 4 x i32> %r
@@ -666,8 +665,7 @@ declare <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32>, <v
define <vscale x 4 x i32> @simplify_revh_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
; CHECK-LABEL: define <vscale x 4 x i32> @simplify_revh_intrinsic
; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) {
-; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32> [[A]], <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[B]])
-; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]
+; CHECK-NEXT: ret <vscale x 4 x i32> [[A]]
;
%r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %b)
ret <vscale x 4 x i32> %r
@@ -677,8 +675,7 @@ declare <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64>, <v
define <vscale x 2 x i64> @simplify_revw_intrinsic(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
; CHECK-LABEL: define <vscale x 2 x i64> @simplify_revw_intrinsic
; CHECK-SAME: (<vscale x 2 x i64> [[A:%.*]], <vscale x 2 x i64> [[B:%.*]]) {
-; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64> [[A]], <vscale x 2 x i1> zeroinitializer, <vscale x 2 x i64> [[B]])
-; CHECK-NEXT: ret <vscale x 2 x i64> [[R]]
+; CHECK-NEXT: ret <vscale x 2 x i64> [[A]]
;
%r = tail call <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> zeroinitializer, <vscale x 2 x i64> %b)
ret <vscale x 2 x i64> %r
@@ -688,8 +685,7 @@ declare <vscale x 4 x i32> @llvm.aarch64.sve.revd.nxv4i32(<vscale x 4 x i32>, <v
define <vscale x 4 x i32> @simplify_revd_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
; CHECK-LABEL: define <vscale x 4 x i32> @simplify_revd_intrinsic
; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) {
-; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.revd.nxv4i32(<vscale x 4 x i32> [[A]], <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[B]])
-; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]
+; CHECK-NEXT: ret <vscale x 4 x i32> [[A]]
;
%r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.revd.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %b)
ret <vscale x 4 x i32> %r
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