[llvm] [AMDGPU] Make `ds_atomic_barrier` operations atomic (PR #194351)

[Fabian Ritter via llvm-commits]

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@@ -1777,6 +1777,24 @@ The AMDGPU backend implements the following LLVM IR intrinsics.
                                                    * :ref:`Synchronization Scope<amdgpu-intrinsics-syncscope-metadata-operand>`.
                                                      Note that the scope used must ensure that the L2 cache will be hit.
 
+  llvm.amdgcn.ds.atomic.barrier.arrive.rtn.b64     Available starting GFX12.5.
+                                                   Corresponds to ``ds_atomic_barrier_arrive_rtn_b64``.
+
+                                                   For the purposes of the memory model, this is a relaxed atomic
+                                                   read-modify-write operation in the local address space.
+                                                   It remains in order with other operations that use ``DScnt``.
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ritter-x2a wrote:

Should we also specify what the operand is and what it returns?

https://github.com/llvm/llvm-project/pull/194351