[llvm] AMDGPU: Add baseline test for v_mac_f16 rounding mode (PR #194360)

[Matt Arsenault via llvm-commits]

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/194360

AMDGPU: Add baseline test for v_mac_f16 rounding mode

AMDGPU: Address fixme for v_mac_f16 rounding mode

This should use the f16/f64 rounding mode

>From 9e6a7bbbd72d9d902be7a0da0eee5d0638830951 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Mon, 27 Apr 2026 13:33:41 +0100
Subject: [PATCH 1/2] AMDGPU: Add baseline test for v_mac_f16 rounding mode

---
 .../AMDGPU/v_mac_f16-fpdp-rounding-mode.ll    | 27 +++++++++++++++++++
 1 file changed, 27 insertions(+)
 create mode 100644 llvm/test/CodeGen/AMDGPU/v_mac_f16-fpdp-rounding-mode.ll

diff --git a/llvm/test/CodeGen/AMDGPU/v_mac_f16-fpdp-rounding-mode.ll b/llvm/test/CodeGen/AMDGPU/v_mac_f16-fpdp-rounding-mode.ll
new file mode 100644
index 0000000000000..520cbe154dee3
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/v_mac_f16-fpdp-rounding-mode.ll
@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 < %s | FileCheck %s
+
+; Make sure the f16/f64 rounding mode is assumed for v_mac_f16
+
+define <2 x half> @v_mac_f16_fpdp_rounding(<2 x half> %a, <2 x half> %c, <2 x half> %b, float %x, ptr addrspace(1) %ptr) #0 {
+; CHECK-LABEL: v_mac_f16_fpdp_rounding:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_lshrrev_b32_e32 v6, 16, v1
+; CHECK-NEXT:    v_mac_f16_sdwa v6, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; CHECK-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
+; CHECK-NEXT:    v_mac_f16_e32 v1, v0, v2
+; CHECK-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1
+; CHECK-NEXT:    v_cvt_f16_f32_e32 v3, v3
+; CHECK-NEXT:    v_or_b32_e32 v0, v1, v6
+; CHECK-NEXT:    flat_store_short v[4:5], v3
+; CHECK-NEXT:    s_waitcnt vmcnt(0)
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %round.x = call half @llvm.fptrunc.round.f16.f32(float %x, metadata !"round.upward")
+  %mul = fmul <2 x half> %a, %b
+  %mac = fadd <2 x half> %mul, %c
+  store half %round.x, ptr addrspace(1) %ptr
+  ret <2 x half> %mac
+}
+
+attributes #0 = { nounwind denormal_fpenv(preservesign) }

>From bdae9e37c88670d98c2d6fc57351a9913ffcd1b5 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Mon, 27 Apr 2026 13:34:58 +0100
Subject: [PATCH 2/2] AMDGPU: Address fixme for v_mac_f16 rounding mode

This should use the f16/f64 rounding mode
---
 llvm/lib/Target/AMDGPU/VOP2Instructions.td               | 2 +-
 llvm/test/CodeGen/AMDGPU/v_mac_f16-fpdp-rounding-mode.ll | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
index deb531ae180d2..6cd23d394782b 100644
--- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
@@ -1217,8 +1217,8 @@ let SubtargetPredicate = isGFX8GFX9 in {
 } // End isCommutable = 1
 } // End isReMaterializable = 1
 
-// FIXME: Missing FPDPRounding
 let Constraints = "$vdst = $src2",
+    FPDPRounding = 1,
     isConvertibleToThreeAddress = 1, isCommutable = 1 in {
 defm V_MAC_F16 : VOP2Inst <"v_mac_f16", VOP_MAC_F16>;
 }
diff --git a/llvm/test/CodeGen/AMDGPU/v_mac_f16-fpdp-rounding-mode.ll b/llvm/test/CodeGen/AMDGPU/v_mac_f16-fpdp-rounding-mode.ll
index 520cbe154dee3..f32db0dd5f473 100644
--- a/llvm/test/CodeGen/AMDGPU/v_mac_f16-fpdp-rounding-mode.ll
+++ b/llvm/test/CodeGen/AMDGPU/v_mac_f16-fpdp-rounding-mode.ll
@@ -11,7 +11,7 @@ define <2 x half> @v_mac_f16_fpdp_rounding(<2 x half> %a, <2 x half> %c, <2 x ha
 ; CHECK-NEXT:    v_mac_f16_sdwa v6, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
 ; CHECK-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
 ; CHECK-NEXT:    v_mac_f16_e32 v1, v0, v2
-; CHECK-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1
+; CHECK-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 1
 ; CHECK-NEXT:    v_cvt_f16_f32_e32 v3, v3
 ; CHECK-NEXT:    v_or_b32_e32 v0, v1, v6
 ; CHECK-NEXT:    flat_store_short v[4:5], v3