[llvm] [AArch64] Add C1-Premium scheduling model (PR #185398)
Nashe Mncube via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 27 04:53:53 PDT 2026
================
@@ -0,0 +1,2280 @@
+//=- AArch64SchedC1Premium.td - C1 Premium Scheduling Defs --*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the scheduling model for the C1 Premium processors.
+// Information is taken from the C1 Premium Software Optimization Guide
+//
+// https://developer.arm.com/documentation/111080/3-0/
+//
+//===----------------------------------------------------------------------===//
+
+def C1PremiumModel : SchedMachineModel {
+ let IssueWidth = 10;
+ let MicroOpBufferSize = 320; // Entries in micro-op re-order buffer.
+ let LoadLatency = 4; // Optimistic load latency.
+ let MispredictPenalty = 10; // Extra cycles for mispredicted branch.
+ let LoopMicroOpBufferSize = 16;
+ let CompleteModel = 1;
+
+ list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F,
+ [HasSVE2p1, HasSVEB16B16,
+ HasCPA, HasCSSC]);
+}
+
+//===----------------------------------------------------------------------===//
+// Define each kind of processor resource and number available on C1 Premium.
+// Instructions are first fetched and then decoded into internal macro-ops
+// (MOPs). From there, the MOPs proceed through register renaming and dispatch
+// stages. A MOP can be split into two micro-ops further down the pipeline
+// after the decode stage.
+
+let SchedModel = C1PremiumModel in {
+
+// Define the issue ports.
+def C1PUnitB : ProcResource<3>; // Branch 0/1/2
+def C1PUnitS0 : ProcResource<1>; // Integer single-cycle 0
+def C1PUnitS1 : ProcResource<1>; // Integer single-cycle 1
+def C1PUnitS2 : ProcResource<1>; // Integer single-cycle 2
+def C1PUnitS3 : ProcResource<1>; // Integer single-cycle 3
+def C1PUnitS4 : ProcResource<1>; // Integer single-cycle 4
+def C1PUnitS5 : ProcResource<1>; // Integer single-cycle 5
+def C1PUnitM0 : ProcResource<1>; // Integer single/multicycle 0
+def C1PUnitM1 : ProcResource<1>; // Integer single/multicycle 1
+def C1PUnitV0 : ProcResource<1>; // FP/ASIMD 0
+def C1PUnitV1 : ProcResource<1>; // FP/ASIMD 1
+def C1PUnitLS0 : ProcResource<1>; // Load/Store 0
+def C1PUnitLS1 : ProcResource<1>; // Load/Store 1
+def C1PUnitL23 : ProcResource<2>; // Load 2/3
+def C1PUnitD : ProcResource<2>; // Store data 0/1
+def C1PUnitCME : ProcResource<1>; // CME operations block
+def C1PUnitFlg : ProcResource<4>; // Flags
+
+def C1PUnitS : ProcResGroup<[C1PUnitS0, C1PUnitS1, C1PUnitS2, C1PUnitS3,
+ C1PUnitS4, C1PUnitS5]>;
+def C1PUnitI : ProcResGroup<[C1PUnitS0, C1PUnitS1, C1PUnitS2, C1PUnitS3,
+ C1PUnitS4, C1PUnitS5, C1PUnitM0, C1PUnitM1]>;
+def C1PUnitI4 : ProcResGroup<[C1PUnitS0, C1PUnitS2, C1PUnitS4, C1PUnitM0]>;
+def C1PUnitM : ProcResGroup<[C1PUnitM0, C1PUnitM1]>;
+def C1PUnitL : ProcResGroup<[C1PUnitLS0, C1PUnitLS1, C1PUnitL23]>;
+def C1PUnitSA : ProcResGroup<[C1PUnitLS0, C1PUnitLS1]>;
+def C1PUnitV : ProcResGroup<[C1PUnitV0, C1PUnitV1]>;
+def C1PUnitV01 : ProcResGroup<[C1PUnitV0, C1PUnitV1]>;
+
+// Define commonly used read types.
+def : ReadAdvance<ReadI, 0>;
+def : ReadAdvance<ReadISReg, 0>;
+def : ReadAdvance<ReadIEReg, 0>;
+def : ReadAdvance<ReadIM, 0>;
+def : ReadAdvance<ReadIMA, 0>;
+def : ReadAdvance<ReadID, 0>;
+def : ReadAdvance<ReadExtrHi, 0>;
+def : ReadAdvance<ReadAdrBase, 0>;
+def : ReadAdvance<ReadST, 0>;
+def : ReadAdvance<ReadVLD, 0>;
+
+def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
+def : WriteRes<WriteBarrier, []> { let Latency = 1; }
+def : WriteRes<WriteHint, []> { let Latency = 1; }
+def : WriteRes<WriteLDHi, []> { let Latency = 4; }
+
+//===----------------------------------------------------------------------===//
+// Define customized scheduler read/write types specific to C1 Premium.
+//===----------------------------------------------------------------------===//
+
+// Define generic 0 micro-op types.
+def C1PWrite_0c : SchedWriteRes<[]> { let Latency = 0; }
+
+// Define a small set of generic 1 micro-op types as placeholders.
+def C1PWrite_1c_1B : SchedWriteRes<[C1PUnitB]> { let Latency = 1; }
+def C1PWrite_2c_1B : SchedWriteRes<[C1PUnitB]> { let Latency = 2; }
+def C1PWrite_1c_1I : SchedWriteRes<[C1PUnitI]> { let Latency = 1; }
+def C1PWrite_2c_1I : SchedWriteRes<[C1PUnitI]> { let Latency = 2; }
+def C1PWrite_3c_1I : SchedWriteRes<[C1PUnitI]> { let Latency = 3; }
+def C1PWrite_2c_1I4 : SchedWriteRes<[C1PUnitI4]> { let Latency = 2; }
+def C1PWrite_1c_1M : SchedWriteRes<[C1PUnitM]> { let Latency = 1; }
+def C1PWrite_1c_2M : SchedWriteRes<[C1PUnitM, C1PUnitM]> { let Latency = 1; }
+def C1PWrite_2c_1M : SchedWriteRes<[C1PUnitM]> { let Latency = 2; }
+def C1PWrite_2c_1M0 : SchedWriteRes<[C1PUnitM0]> { let Latency = 2; }
+def C1PWrite_3c_1M0 : SchedWriteRes<[C1PUnitM0]> { let Latency = 3; }
+def C1PWrite_4c_1M0 : SchedWriteRes<[C1PUnitM0]> { let Latency = 4; }
+def C1PWrite_5c_1M0 : SchedWriteRes<[C1PUnitM0]> { let Latency = 5; }
+def C1PWrite_5c_1M0_5rc : SchedWriteRes<[C1PUnitM0]> { let Latency = 5;
+ let ReleaseAtCycles = [5]; }
+def C1PWrite_12c_1M0 : SchedWriteRes<[C1PUnitM0]> { let Latency = 12;
+ let ReleaseAtCycles = [12]; }
+def C1PWrite_20c_1M0 : SchedWriteRes<[C1PUnitM0]> { let Latency = 20;
+ let ReleaseAtCycles = [20]; }
+def C1PWrite_1c_1V : SchedWriteRes<[C1PUnitV]> { let Latency = 1; }
+def C1PWrite_2c_1V : SchedWriteRes<[C1PUnitV]> { let Latency = 2; }
+def C1PWrite_2c_3V : SchedWriteRes<[C1PUnitV, C1PUnitV, C1PUnitV]> { let Latency = 2; }
+def C1PWrite_3c_1V : SchedWriteRes<[C1PUnitV]> { let Latency = 3; }
+def C1PWrite_4c_1V : SchedWriteRes<[C1PUnitV]> { let Latency = 4; }
+def C1PWrite_6c_1V : SchedWriteRes<[C1PUnitV]> { let Latency = 6; }
+def C1PWrite_6c_5V : SchedWriteRes<[
+ C1PUnitV, C1PUnitV, C1PUnitV,
+ C1PUnitV, C1PUnitV,
+ ]> {
+ let Latency = 6;
+}
+
+def C1PWrite_8c_1V : SchedWriteRes<[C1PUnitV]> { let Latency = 8; }
+def C1PWrite_1c_1V0 : SchedWriteRes<[C1PUnitV0]> { let Latency = 1; }
+def C1PWrite_2c_1V0 : SchedWriteRes<[C1PUnitV0]> { let Latency = 2; }
+def C1PWrite_4c_1V0 : SchedWriteRes<[C1PUnitV0]> { let Latency = 4; }
+def C1PWrite_6c_1V0_6rc : SchedWriteRes<[C1PUnitV0]> { let Latency = 6; let ReleaseAtCycles = [6]; }
+def C1PWrite_10c_1V0_10rc : SchedWriteRes<[C1PUnitV0]> { let Latency = 10; let ReleaseAtCycles = [10]; }
+def C1PWrite_12c_1V0_12rc : SchedWriteRes<[C1PUnitV0]> { let Latency = 12; let ReleaseAtCycles = [12];}
+def C1PWrite_20c_1V0_20rc : SchedWriteRes<[C1PUnitV0]> { let Latency = 20; let ReleaseAtCycles = [20];}
+def C1PWrite_3c_1V0_1M : SchedWriteRes<[C1PUnitV0, C1PUnitM]> { let Latency = 3; }
+def C1PWrite_3c_1V1 : SchedWriteRes<[C1PUnitV1]> { let Latency = 3; }
+def C1PWrite_5c_1V1 : SchedWriteRes<[C1PUnitV1]> { let Latency = 5; }
+def C1PWrite_5c_1V1_8rc : SchedWriteRes<[C1PUnitV1]> {
+ let Latency = 5;
+ let ReleaseAtCycles = [8];
+}
+def C1PWrite_8c_1V1 : SchedWriteRes<[C1PUnitV1]> { let Latency = 8; }
+def C1PWrite_8c_1V1_4rc : SchedWriteRes<[C1PUnitV1]> {
+ let Latency = 8;
+ let ReleaseAtCycles = [4];
+}
+def C1PWrite_12c_1V1 : SchedWriteRes<[C1PUnitV1]> { let Latency = 12; }
+def C1PWrite_12c_1V1_2rc : SchedWriteRes<[C1PUnitV1]> {
+ let Latency = 12;
+ let ReleaseAtCycles = [2];
+}
+def C1PWrite_2c_1V01 : SchedWriteRes<[C1PUnitV01]> { let Latency = 2; }
+def C1PWrite_3c_1V01 : SchedWriteRes<[C1PUnitV01]> { let Latency = 3; }
+def C1PWrite_1c_1L : SchedWriteRes<[C1PUnitL]> { let Latency = 1; }
+def C1PWrite_4c_1L : SchedWriteRes<[C1PUnitL]> { let Latency = 4; }
+def C1PWrite_4c_1L_1I : SchedWriteRes<[C1PUnitL, C1PUnitI]> { let Latency = 4; }
+def C1PWrite_6c_1L : SchedWriteRes<[C1PUnitL]> { let Latency = 6; }
+def C1PWrite_1c_1SA : SchedWriteRes<[C1PUnitSA]> { let Latency = 1; }
+
+def C1PWrite_1c_1SA_1D : SchedWriteRes<[C1PUnitSA, C1PUnitD]> { let Latency = 1; }
+def C1PWrite_1c_1SA_1D_1I : SchedWriteRes<[C1PUnitSA, C1PUnitD, C1PUnitI]> { let Latency = 1; }
+def C1PWrite_2c_1B_1I : SchedWriteRes<[C1PUnitB, C1PUnitI]> { let Latency = 2; }
+def C1PWrite_5c_1L_1I : SchedWriteRes<[C1PUnitL, C1PUnitI]> { let Latency = 5; }
+def C1PWrite_5c_2L_1I : SchedWriteRes<[C1PUnitL, C1PUnitL, C1PUnitI]> { let Latency = 5; }
+def C1PWrite_5c_2L_2I : SchedWriteRes<[C1PUnitL, C1PUnitL, C1PUnitI, C1PUnitI]> { let Latency = 5; }
+def C1PWrite_6c_1L_1I : SchedWriteRes<[C1PUnitL, C1PUnitI]> { let Latency = 6; }
+def C1PWrite_6c_2L_1I : SchedWriteRes<[C1PUnitL, C1PUnitL, C1PUnitI]> { let Latency = 6; }
+def C1PWrite_7c_1L_1I : SchedWriteRes<[C1PUnitL, C1PUnitI]> { let Latency = 7; }
+def C1PWrite_5c_1M0_1V : SchedWriteRes<[C1PUnitM0, C1PUnitV]> { let Latency = 5; }
+def C1PWrite_6c_1M0_1B : SchedWriteRes<[C1PUnitM0, C1PUnitB]> { let Latency = 6; }
+def C1PWrite_6c_1M0_1B_1I : SchedWriteRes<[C1PUnitM0, C1PUnitB, C1PUnitI]> { let Latency = 6; }
+def C1PWrite_9c_1M0_1L : SchedWriteRes<[C1PUnitM0, C1PUnitL]> { let Latency = 9; }
+def C1PWrite_2c_1SA_1V01 : SchedWriteRes<[C1PUnitSA, C1PUnitV01]> { let Latency = 2; }
+
+def C1PWrite_2c_2SA_2V01 : SchedWriteRes<[
+ C1PUnitSA, C1PUnitSA,
+ C1PUnitV01, C1PUnitV01]> {
+ let Latency = 2;
+}
+
+def C1PWrite_2c_3SA_3V01 : SchedWriteRes<[
+ C1PUnitSA, C1PUnitSA, C1PUnitSA,
+ C1PUnitV01, C1PUnitV01, C1PUnitV01]> {
+ let Latency = 2;
+}
+
+def C1PWrite_2c_4SA_4V01 : SchedWriteRes<[
+ C1PUnitSA, C1PUnitSA,
+ C1PUnitSA, C1PUnitSA,
+ C1PUnitV01, C1PUnitV01,
+ C1PUnitV01, C1PUnitV01]> {
+ let Latency = 2;
+}
+
+def C1PWrite_2c_1SA_1V01_1I : SchedWriteRes<[C1PUnitSA, C1PUnitV01, C1PUnitI]> { let Latency = 2; }
+def C1PWrite_2c_2SA_2V01_2I : SchedWriteRes<[
+ C1PUnitSA, C1PUnitSA,
+ C1PUnitV01, C1PUnitV01,
+ C1PUnitI, C1PUnitI]> {
+ let Latency = 2;
+}
+
+def C1PWrite_8c_1L_1V : SchedWriteRes<[C1PUnitL, C1PUnitV]> { let Latency = 8; }
+def C1PWrite_7c_1M0_1V : SchedWriteRes<[C1PUnitM0, C1PUnitV]> { let Latency = 7; }
+def C1PWrite_5c_1V_1M0 : SchedWriteRes<[C1PUnitM0, C1PUnitV]> { let Latency = 5; }
+def C1PWrite_2c_1SA_1V : SchedWriteRes<[C1PUnitSA, C1PUnitV]> { let Latency = 2; }
+def C1PWrite_2c_1SA_2V : SchedWriteRes<[C1PUnitSA, C1PUnitV, C1PUnitV]> { let Latency = 2; }
+def C1PWrite_4c_1SA_2V : SchedWriteRes<[C1PUnitSA, C1PUnitV, C1PUnitV]> { let Latency = 4; }
+def C1PWrite_4c_1SA_1V : SchedWriteRes<[C1PUnitSA, C1PUnitV]> { let Latency = 4; }
+def C1PWrite_4c_1I_1SA_2V : SchedWriteRes<[C1PUnitI, C1PUnitSA, C1PUnitV, C1PUnitV]> { let Latency = 4; }
+def C1PWrite_4c_1I_1SA_1V : SchedWriteRes<[C1PUnitI, C1PUnitSA, C1PUnitV]> { let Latency = 4; }
+def C1PWrite_5c_1SA_2V : SchedWriteRes<[C1PUnitSA, C1PUnitV, C1PUnitV]> { let Latency = 5; }
+def C1PWrite_5c_1SA_1V : SchedWriteRes<[C1PUnitSA, C1PUnitV]> { let Latency = 5; }
+def C1PWrite_5c_3SA_6V : SchedWriteRes<[C1PUnitSA, C1PUnitSA, C1PUnitSA,
+ C1PUnitV, C1PUnitV, C1PUnitV,
+ C1PUnitV, C1PUnitV, C1PUnitV]> { let Latency = 5; }
+def C1PWrite_5c_1I_1SA_2V : SchedWriteRes<[C1PUnitI, C1PUnitSA, C1PUnitV, C1PUnitV]> { let Latency = 5; }
+def C1PWrite_5c_1I_1SA_1V : SchedWriteRes<[C1PUnitI, C1PUnitSA, C1PUnitV]> { let Latency = 5; }
+def C1PWrite_7c_1SA_2V : SchedWriteRes<[C1PUnitSA, C1PUnitV, C1PUnitV]> { let Latency = 7; }
+def C1PWrite_7c_1SA_1V : SchedWriteRes<[C1PUnitSA, C1PUnitV]> { let Latency = 7; }
+def C1PWrite_7c_1I_1SA_2V : SchedWriteRes<[C1PUnitI, C1PUnitSA, C1PUnitV, C1PUnitV]> { let Latency = 7; }
+def C1PWrite_7c_1I_1SA_1V : SchedWriteRes<[C1PUnitI, C1PUnitSA, C1PUnitV]> { let Latency = 7; }
+def C1PWrite_4c_1SA_1V01_1V : SchedWriteRes<[C1PUnitSA, C1PUnitV01, C1PUnitV]> { let Latency = 4; }
+def C1PWrite_4c_1SA_2V01_1V : SchedWriteRes<[C1PUnitSA, C1PUnitV01, C1PUnitV01, C1PUnitV]> { let Latency = 4; }
+def C1PWrite_4c_2SA_2V01_2V : SchedWriteRes<[C1PUnitSA, C1PUnitSA,
+ C1PUnitV01, C1PUnitV01,
+ C1PUnitV, C1PUnitV]> { let Latency = 4; }
+def C1PWrite_6c_1SA_1V01_1V : SchedWriteRes<[C1PUnitSA, C1PUnitV01, C1PUnitV]> { let Latency = 6; }
+def C1PWrite_6c_2SA_2V01_2V : SchedWriteRes<[C1PUnitSA, C1PUnitSA,
+ C1PUnitV01, C1PUnitV01,
+ C1PUnitV, C1PUnitV]> { let Latency = 6; }
+def C1PWrite_6c_2SA_3V01_2V : SchedWriteRes<[C1PUnitSA, C1PUnitSA,
+ C1PUnitV01, C1PUnitV01, C1PUnitV01,
+ C1PUnitV, C1PUnitV]> { let Latency = 6; }
+def C1PWrite_6c_3SA_3V01_3V : SchedWriteRes<[C1PUnitSA, C1PUnitSA, C1PUnitSA,
+ C1PUnitV01, C1PUnitV01, C1PUnitV01,
+ C1PUnitV, C1PUnitV, C1PUnitV]> { let Latency = 6; }
+def C1PWrite_6c_1SA_1V01_2V : SchedWriteRes<[C1PUnitSA, C1PUnitV01,
+ C1PUnitV, C1PUnitV]> { let Latency = 6; }
+def C1PWrite_7c_1SA_1V01_1V : SchedWriteRes<[C1PUnitSA, C1PUnitV01, C1PUnitV]> { let Latency = 7; }
+def C1PWrite_7c_3SA_3V01_3V : SchedWriteRes<[C1PUnitSA, C1PUnitSA, C1PUnitSA,
+ C1PUnitV01, C1PUnitV01, C1PUnitV01,
+ C1PUnitV, C1PUnitV, C1PUnitV]> { let Latency = 7; }
+
+def C1PWrite_7c_2SA_2V01_8V : SchedWriteRes<[
+ C1PUnitSA, C1PUnitSA,
+ C1PUnitV01, C1PUnitV01,
+ C1PUnitV, C1PUnitV, C1PUnitV, C1PUnitV,
+ C1PUnitV, C1PUnitV, C1PUnitV, C1PUnitV]> {
+ let Latency = 7;
+}
+
+def C1PWrite_7c_6SA_6V01_6V : SchedWriteRes<[
+ C1PUnitSA, C1PUnitSA, C1PUnitSA,
+ C1PUnitSA, C1PUnitSA, C1PUnitSA,
+ C1PUnitV01, C1PUnitV01, C1PUnitV01,
+ C1PUnitV01, C1PUnitV01, C1PUnitV01,
+ C1PUnitV, C1PUnitV, C1PUnitV,
+ C1PUnitV, C1PUnitV, C1PUnitV]> {
+ let Latency = 7;
+}
+
+def C1PWrite_7c_1M_1M0_1V : SchedWriteRes<[C1PUnitM, C1PUnitM0, C1PUnitV]> { let Latency = 7; }
+def C1PWrite_8c_1M0_1V1_1V : SchedWriteRes<[C1PUnitM0, C1PUnitV1, C1PUnitV]> { let Latency = 8; }
+def C1PWrite_5c_1V1_1V : SchedWriteRes<[C1PUnitV1, C1PUnitV]> { let Latency = 5; }
+def C1PWrite_4c_2V : SchedWriteRes<[C1PUnitV, C1PUnitV]> { let Latency = 4; }
+def C1PWrite_4c_3V : SchedWriteRes<[C1PUnitV, C1PUnitV, C1PUnitV]> { let Latency = 4; }
+def C1PWrite_6c_1L_1M : SchedWriteRes<[C1PUnitL, C1PUnitM]> { let Latency = 6; }
+def C1PWrite_9c_1V_1L : SchedWriteRes<[C1PUnitV, C1PUnitL]> { let Latency = 9; }
+def C1PWrite_9c_1I_1L_1V : SchedWriteRes<[C1PUnitI, C1PUnitL, C1PUnitV]> { let Latency = 9; }
+def C1PWrite_9c_2I_2L_2V : SchedWriteRes<[C1PUnitI, C1PUnitI,
+ C1PUnitL, C1PUnitL,
+ C1PUnitV, C1PUnitV]> { let Latency = 9; }
+def C1PWrite_9c_3I_3L_3V : SchedWriteRes<[C1PUnitI, C1PUnitI, C1PUnitI,
+ C1PUnitL, C1PUnitL, C1PUnitL,
+ C1PUnitV, C1PUnitV, C1PUnitV]> { let Latency = 9; }
+def C1PWrite_4c_2L : SchedWriteRes<[C1PUnitL, C1PUnitL]> { let Latency = 4; }
+def C1PWrite_4c_2L_1I : SchedWriteRes<[C1PUnitL, C1PUnitL, C1PUnitI]> { let Latency = 4; }
+def C1PWrite_10c_1L_1V : SchedWriteRes<[
+ C1PUnitL, C1PUnitV,
+C1PUnitL, C1PUnitV,
+C1PUnitL, C1PUnitV,
+C1PUnitL, C1PUnitV,
+C1PUnitL, C1PUnitV,
+C1PUnitL, C1PUnitV,
+C1PUnitL, C1PUnitV,
+C1PUnitL, C1PUnitV ]> { let Latency = 10; }
+
+def C1PWrite_11c_8I_8L_8V : SchedWriteRes<[
+ C1PUnitI, C1PUnitL, C1PUnitV,
+ C1PUnitI, C1PUnitL, C1PUnitV,
+ C1PUnitI, C1PUnitL, C1PUnitV,
+ C1PUnitI, C1PUnitL, C1PUnitV,
+ C1PUnitI, C1PUnitL, C1PUnitV,
+ C1PUnitI, C1PUnitL, C1PUnitV,
+ C1PUnitI, C1PUnitL, C1PUnitV,
+ C1PUnitI, C1PUnitL, C1PUnitV,
+ ]> { let Latency = 11; }
+
+def C1PWrite_3c_1M0_1M : SchedWriteRes<[C1PUnitM0, C1PUnitM]> { let Latency = 3; }
+
+def C1PWrite_8c_V1_4rc : SchedWriteRes<[C1PUnitV1]> {
+ let Latency = 8;
+ let ReleaseAtCycles = [4];
+}
+
+def C1PWrite_9c_V1_2rc : SchedWriteRes<[C1PUnitV1]> {
+ let Latency = 9;
+ let ReleaseAtCycles = [2];
+}
+
+def C1PWrite_12c_V1_8rc : SchedWriteRes<[C1PUnitV1]> {
+ let Latency = 12;
+ let ReleaseAtCycles = [8];
+}
+
+
+def C1PWrite_11c_V1_4rc : SchedWriteRes<[C1PUnitV1]> {
+ let Latency = 11;
+ let ReleaseAtCycles = [4];
+}
+
+def C1PWrite_13c_V1_2rc : SchedWriteRes<[C1PUnitV1]> {
+ let Latency = 13;
+ let ReleaseAtCycles = [2];
+}
+
+def C1PWrite_6c_4V : SchedWriteRes<[C1PUnitV, C1PUnitV, C1PUnitV, C1PUnitV]> {
+ let Latency = 6;
+}
+
+def C1PWrite_6c_2L : SchedWriteRes<[C1PUnitL, C1PUnitL]> { let Latency = 6; }
+
+def C1PWrite_6c_3L : SchedWriteRes<[C1PUnitL, C1PUnitL, C1PUnitL]> { let Latency = 6; }
+
+def C1PWrite_7c_2L : SchedWriteRes<[C1PUnitL, C1PUnitL]> { let Latency = 7; }
+def C1PWrite_7c_4L : SchedWriteRes<[C1PUnitL, C1PUnitL, C1PUnitL, C1PUnitL]> { let Latency = 7; }
+
+def C1PWrite_8c_1L_2V : SchedWriteRes<[C1PUnitL, C1PUnitV, C1PUnitV]> { let Latency = 8; }
+
+def C1PWrite_8c_2L_2V : SchedWriteRes<[C1PUnitL, C1PUnitL, C1PUnitV, C1PUnitV]> { let Latency = 8; }
+def C1PWrite_8c_3L_3V : SchedWriteRes<[C1PUnitL, C1PUnitL, C1PUnitL,
+ C1PUnitV, C1PUnitV, C1PUnitV]> { let Latency = 8; }
+
+def C1PWrite_9c_2L_3V : SchedWriteRes<[C1PUnitL, C1PUnitL, C1PUnitV, C1PUnitV, C1PUnitV]> { let Latency = 9; }
+
+def C1PWrite_10c_3L_3V : SchedWriteRes<[C1PUnitL, C1PUnitL, C1PUnitL, C1PUnitV, C1PUnitV, C1PUnitV]> { let Latency = 10; }
+
+def C1PWrite_9c_3L_3V : SchedWriteRes<[C1PUnitL, C1PUnitL, C1PUnitL, C1PUnitV, C1PUnitV, C1PUnitV]> { let Latency = 9; }
+
+def C1PWrite_9c_3L_4V : SchedWriteRes<[C1PUnitL, C1PUnitL, C1PUnitL, C1PUnitV, C1PUnitV, C1PUnitV, C1PUnitV]> { let Latency = 9; }
+
+def C1PWrite_11c_6L_8V : SchedWriteRes<[
+ C1PUnitL, C1PUnitL, C1PUnitL,
+ C1PUnitL, C1PUnitL, C1PUnitL,
+ C1PUnitV, C1PUnitV, C1PUnitV, C1PUnitV,
+ C1PUnitV, C1PUnitV, C1PUnitV, C1PUnitV
+ ]> { let Latency = 11; }
+
+def C1PWrite_9c_4L_4V : SchedWriteRes<[C1PUnitL, C1PUnitL, C1PUnitL, C1PUnitL, C1PUnitV, C1PUnitV, C1PUnitV, C1PUnitV]> { let Latency = 9; }
+
+def C1PWrite_6c_1V1 : SchedWriteRes<[C1PUnitV1, C1PUnitV1]> { let Latency = 6; }
+
+def C1PWrite_8c_4V : SchedWriteRes<[C1PUnitV, C1PUnitV, C1PUnitV, C1PUnitV]> { let Latency = 8; }
+
+def C1PWrite_6c_3V : SchedWriteRes<[C1PUnitV, C1PUnitV, C1PUnitV]> { let Latency = 6; }
+
+def C1PWrite_12c_1V0_8rc : SchedWriteRes<[C1PUnitV0]> {
+ let Latency = 12;
+ let ReleaseAtCycles = [8];
+}
+
+def C1PWrite_11c_1V0_4rc : SchedWriteRes<[C1PUnitV0]> {
+ let Latency = 11;
+ let ReleaseAtCycles = [4];
+}
+
+def C1PWrite_13c_1V0_2rc : SchedWriteRes<[C1PUnitV0]> {
+ let Latency = 13;
+ let ReleaseAtCycles = [2];
+}
+
+
+def C1PWrite_12c_1V1_8rc : SchedWriteRes<[C1PUnitV1]> {
+ let Latency = 12;
+ let ReleaseAtCycles = [8];
+}
+
+def C1PWrite_11c_1V1_4rc : SchedWriteRes<[C1PUnitV1]> {
+ let Latency = 11;
+ let ReleaseAtCycles = [4];
+}
+
+def C1PWrite_13c_1V1_2rc : SchedWriteRes<[C1PUnitV1]> {
+ let Latency = 13;
+ let ReleaseAtCycles = [2];
+}
+
+
+// Predicate Controlled types
+def C1PWrite_Extr: SchedWriteVariant<[
+ SchedVar<IsRORImmIdiomPred, [C1PWrite_1c_1I]>,
+ SchedVar<NoSchedPred, [C1PWrite_3c_1I]>]>;
+def C1PWrite_1c_1I_1Flg : SchedWriteRes<[C1PUnitI, C1PUnitFlg]> { let Latency = 1; }
+def C1PWrite_2c_1I_1Flg : SchedWriteRes<[C1PUnitI, C1PUnitFlg]> { let Latency = 2; }
+def C1PWrite_ArithI : SchedWriteVariant<[
+ SchedVar<IsCheapLSL, [C1PWrite_1c_1I]>,
+ SchedVar<NoSchedPred, [C1PWrite_2c_1I]>]>;
+def C1PWrite_ArithI_1Flg : SchedWriteVariant<[
+ SchedVar<IsCheapLSL, [C1PWrite_1c_1I_1Flg]>,
+ SchedVar<NoSchedPred, [C1PWrite_2c_1I_1Flg]>]>;
+def C1PWrite_ArithIE : SchedWriteVariant<[
+ SchedVar<IsExtWorXPred, [C1PWrite_1c_1I]>,
+ SchedVar<NoSchedPred, [C1PWrite_2c_1I]>]>;
+
+def C1PWrite_LdrQ : SchedWriteVariant<[
+ SchedVar<FPIsQForm, [C1PWrite_7c_1L_1I]>,
+ SchedVar<NoSchedPred, [C1PWrite_6c_1L]>]>;
+def C1PWrite_StrQ : SchedWriteVariant<[
+ SchedVar<FPIsQForm, [C1PWrite_2c_1SA_1V01_1I]>,
+ SchedVar<NoSchedPred, [C1PWrite_2c_1SA_1V01]>]>;
+def C1PWrite_PredCmp : SchedWriteVariant<[
+ SchedVar<IsPredDestSameAsPgPred, [C1PWrite_3c_1V0_1M]>,
+ SchedVar<NoSchedPred, [C1PWrite_2c_1V0]>]>;
+
+def C1PWrite_1or2c_1I : SchedWriteVariant<[
+ SchedVar<IsXOrWDest, [C1PWrite_1c_1I]>,
+ SchedVar<NoSchedPred, [C1PWrite_2c_1I]>]>;
+
+def C1PWrite_1or2c_1I_1Flg : SchedWriteVariant<[
+ SchedVar<IsXOrWDest, [C1PWrite_1c_1I_1Flg]>,
+ SchedVar<NoSchedPred, [C1PWrite_2c_1I_1Flg]>]>;
+
+//===----------------------------------------------------------------------===//
+// Define forwarded types
+
+def C1PWr_FMA : SchedWriteRes<[C1PUnitV]> { let Latency = 4; }
+def C1PRd_FMA : SchedReadAdvance<2, [WriteFMul, C1PWr_FMA]>;
+
+def C1PWr_VA : SchedWriteRes<[C1PUnitV]> { let Latency = 4; }
+def C1PRd_VA : SchedReadAdvance<3, [C1PWr_VA]>;
+
+def C1PWr_VDOT : SchedWriteRes<[C1PUnitV]> { let Latency = 3; }
+def C1PRd_VDOT : SchedReadAdvance<2, [C1PWr_VDOT]>;
+
+def C1PWr_VMMA : SchedWriteRes<[C1PUnitV]> { let Latency = 3; }
+def C1PRd_VMMA : SchedReadAdvance<2, [C1PWr_VMMA]>;
+
+def C1PWr_VMA : SchedWriteRes<[C1PUnitV]> { let Latency = 4; }
+def C1PRd_VMA : SchedReadAdvance<3, [C1PWr_VMA]>;
+
+def C1PWr_MA : SchedWriteRes<[C1PUnitI4]> { let Latency = 3; }
+def C1PRd_MA : SchedReadAdvance<2, [C1PWr_MA]>;
+def C1PWrite_MAOrMul : SchedWriteVariant<[
+ SchedVar<IsReg3ZeroPred, [C1PWrite_2c_1I4]>,
+ SchedVar<NoSchedPred, [C1PWr_MA]>]>;
+
+def C1PWr_Pred : SchedWriteRes<[C1PUnitM, C1PUnitM]> { let Latency = 2; }
+def C1PRd_Pred : SchedReadAdvance<1, [C1PWr_Pred]>;
+
+def C1PWr_VMAH : SchedWriteRes<[C1PUnitV]> { let Latency = 4; }
+def C1PRd_VMAH : SchedReadAdvance<2, [C1PWr_VMAH]>;
+
+def C1PWr_VPA : SchedWriteRes<[C1PUnitV]> { let Latency = 4; }
+def C1PRd_VPA : SchedReadAdvance<3, [C1PWr_VPA]>;
+
+def C1PWr_VSA : SchedWriteRes<[C1PUnitV]> { let Latency = 4; }
+def C1PRd_VSA : SchedReadAdvance<3, [C1PWr_VSA]>;
+
+def C1PWr_VFCMA : SchedWriteRes<[C1PUnitV]> { let Latency = 5; }
+def C1PRd_VFCMA : SchedReadAdvance<3, [C1PWr_VFCMA]>;
+
+def C1PWr_VFMA : SchedWriteRes<[C1PUnitV]> { let Latency = 4; }
+def C1PRd_VFMA : SchedReadAdvance<2, [C1PWr_VFMA]>;
+
+def C1PWr_VBFDOT : SchedWriteRes<[C1PUnitV]> { let Latency = 4; }
+def C1PRd_VBFDOT : SchedReadAdvance<2, [C1PWr_VBFDOT]>;
+
+def C1PWr_VBFMMA : SchedWriteRes<[C1PUnitV]> { let Latency = 5; }
+def C1PRd_VBFMMA : SchedReadAdvance<1, [C1PWr_VBFMMA]>;
+
+def C1PWr_VBFMAL : SchedWriteRes<[C1PUnitV]> { let Latency = 5; }
+def C1PRd_VBFMAL : SchedReadAdvance<3, [C1PWr_VBFMAL]>;
+
+def C1PWr_ZA : SchedWriteRes<[C1PUnitV]> { let Latency = 4; }
+def C1PRd_ZA : SchedReadAdvance<3, [C1PWr_ZA]>;
+
+def C1PWr_ZPA : SchedWriteRes<[C1PUnitV]> { let Latency = 4; }
+def C1PRd_ZPA : SchedReadAdvance<3, [C1PWr_ZPA]>;
+
+def C1PWr_ZSA : SchedWriteRes<[C1PUnitV]> { let Latency = 4; }
+def C1PRd_ZSA : SchedReadAdvance<3, [C1PWr_ZSA]>;
+
+def C1PWr_ZDOTB : SchedWriteRes<[C1PUnitV]> { let Latency = 3; }
+def C1PRd_ZDOTB : SchedReadAdvance<2, [C1PWr_ZDOTB]>;
+
+def C1PWr_ZDOTH : SchedWriteRes<[C1PUnitV]> { let Latency = 3; }
+def C1PRd_ZDOTH : SchedReadAdvance<2, [C1PWr_ZDOTH]>;
+
+def C1PWr_ZCMABHS : SchedWriteRes<[C1PUnitV]> { let Latency = 4; }
+def C1PRd_ZCMABHS : SchedReadAdvance<3, [C1PWr_ZCMABHS]>;
+
+def C1PWr_ZMMA : SchedWriteRes<[C1PUnitV]> { let Latency = 3; }
+def C1PRd_ZMMA : SchedReadAdvance<2, [C1PWr_ZMMA]>;
+
+def C1PWr_ZMA : SchedWriteRes<[C1PUnitV]> { let Latency = 4; }
+def C1PRd_ZMA : SchedReadAdvance<3, [C1PWr_ZMA]>;
+
+def C1PWr_ZMASQL : SchedWriteRes<[C1PUnitV]> { let Latency = 4; }
+def C1PRd_ZMASQL : SchedReadAdvance<2, [C1PWr_ZMASQL]>;
+
+def C1PWr_ZFCMA : SchedWriteRes<[C1PUnitV]> { let Latency = 5; }
+def C1PRd_ZFCMA : SchedReadAdvance<3, [C1PWr_ZFCMA]>;
+
+def C1PWr_ZFMA : SchedWriteRes<[C1PUnitV]> { let Latency = 4; }
+def C1PRd_ZFMA : SchedReadAdvance<2, [C1PWr_ZFMA]>;
+
+def C1PWr_ZFMAL : SchedWriteRes<[C1PUnitV]> { let Latency = 5; }
+def C1PRd_ZFMAL : SchedReadAdvance<3, [C1PWr_ZFMAL]>;
+
+def C1PWr_ZBFDOT : SchedWriteRes<[C1PUnitV]> { let Latency = 4; }
+def C1PRd_ZBFDOT : SchedReadAdvance<2, [C1PWr_ZBFDOT]>;
+def C1PWr_ZBFMMA : SchedWriteRes<[C1PUnitV]> { let Latency = 5; }
+def C1PRd_ZBFMMA : SchedReadAdvance<2, [C1PWr_ZBFMMA]>;
+def C1PWr_ZBFMAL : SchedWriteRes<[C1PUnitV]> { let Latency = 5; }
+def C1PRd_ZBFMAL : SchedReadAdvance<3, [C1PWr_ZBFMAL]>;
+
+def C1PWr_CRC : SchedWriteRes<[C1PUnitM]> { let Latency = 2; }
+def C1PRd_CRC : SchedReadAdvance<1, [C1PWr_CRC]>;
+
+// Miscellaneous
+// -----------------------------------------------------------------------------
+
+def : InstRW<[WriteI], (instrs COPY)>;
+
+
+//===----------------------------------------------------------------------===//
+// Instruction scheduling classes.
+//===----------------------------------------------------------------------===//
+
+// Branch instructions
+// -----------------------------------------------------------------------------
+
+// Branch, immed
+// Compare and branch
+def : SchedAlias<WriteBr, C1PWrite_2c_1B>;
+
+// Branch, register
+def : SchedAlias<WriteBrReg, C1PWrite_2c_1B>;
+
+// Branch and link, immed
+// Branch and link, register
+def : InstRW<[C1PWrite_2c_1B_1I], (instrs BL, BLR)>;
+
+
+// Arithmetic and logical operations
+// -----------------------------------------------------------------------------
+
+// ALU, basic
+def : SchedAlias<WriteI, C1PWrite_1c_1I>;
+
+// ALU, basic, flagset
+def : InstRW<[C1PWrite_1c_1I_1Flg],
+ (instregex "^(ADC|SBC)S[WX]r$",
+ "^ANDS[WX]ri$",
+ "^(AND|BIC)S[WX]rr$")>;
+
+// ALU, extend and shift
+def : SchedAlias<WriteIEReg, C1PWrite_1or2c_1I>;
+
+// ALU, extend and shift, flagset
+def : InstRW<[C1PWrite_1or2c_1I_1Flg],
+ (instregex "^(ADD|SUB)S[WX]r[irx]$",
+ "^(ADD|SUB)SXrx64$")>;
+def : InstRW<[C1PWrite_2c_1I_1Flg],
+ (instregex "^(ADD|SUB)S[WX]rs$")>;
+
+// Arithmetic, LSL shift, shift <= 4
+// Arithmetic, flagset, LSL shift, shift <= 4
+// Arithmetic, LSR/ASR/ROR shift or LSL shift > 4
+def : SchedAlias<WriteISReg, C1PWrite_ArithI>;
+
+// Arithmetic, immediate to logical address tag
+def : InstRW<[C1PWrite_2c_1I], (instrs ADDG, SUBG)>;
+
+// Conditional compare
+def : InstRW<[C1PWrite_1c_1I_1Flg], (instregex "^CCM[NP][WX][ir]")>;
+
+// Conditional select
+def : InstRW<[C1PWrite_1c_1I],
+ (instregex "(CSEL|CSINC|CSINV|CSNEG)(X|W)[ir]")>;
+
+// Convert floating-point condition flags
+// Flag manipulation instructions
+def : WriteRes<WriteSys, []> { let Latency = 1; }
+def : InstRW<[C1PWrite_1c_1I], (instrs AXFLAG, XAFLAG)>;
+
+// Insert Random Tags
+// NOTE: SOG reports 2c on M (RRND=1) and 3c on M0 (RRND=0); model 2c on M.
+def : InstRW<[C1PWrite_2c_1M], (instrs IRG, IRGstack)>;
+
+// Insert Tag Mask
+// Subtract Pointer
+def : InstRW<[C1PWrite_1c_1I], (instrs GMI, SUBP)>;
+
+// Subtract Pointer, flagset
+def : InstRW<[C1PWrite_1c_1I_1Flg], (instrs SUBPS)>;
+
+// Logical, shift, no flagset
+def : InstRW<[C1PWrite_1c_1I],
+ (instregex "^(AND|BIC|EON|EOR|ORN)[WX]rs",
+ "^ORR[WX]rs$")>;
+
+// Logical, shift, flagset
+def : InstRW<[C1PWrite_1c_1I_1Flg], (instregex "^(AND|BIC)S[WX]rs$")>;
+
+// Move and shift instructions
+// -----------------------------------------------------------------------------
+
+def : SchedAlias<WriteImm, C1PWrite_1c_1I>;
+
+// Divide and multiply instructions
+// -----------------------------------------------------------------------------
+
+// SDIV, UDIV
+def : SchedAlias<WriteID32, C1PWrite_12c_1M0>;
+def : SchedAlias<WriteID64, C1PWrite_20c_1M0>;
+
+def : SchedAlias<WriteIM32, C1PWrite_2c_1I4>;
+def : SchedAlias<WriteIM64, C1PWrite_2c_1I4>;
+
+// Multiply accumulate, W-form
+// Multiply accumulate, X-form
+def : InstRW<[C1PWrite_MAOrMul, ReadIM, ReadIM, C1PRd_MA],
+ (instregex "^M(ADD|SUB)[WX]rrr$")>;
+
+// Multiply accumulate long
+def : InstRW<[C1PWrite_MAOrMul, ReadIM, ReadIM, C1PRd_MA],
+ (instregex "^(S|U)M(ADD|SUB)Lrrr$")>;
+
+// Multiply high
+def : InstRW<[C1PWrite_2c_1I4], (instrs SMULHrr, UMULHrr)>;
+
+// Pointer Authentication Instructions (v8.3 PAC)
+// -----------------------------------------------------------------------------
+
+// Authenticate data address
+// Authenticate instruction address
+// Compute pointer authentication code for data address
+// Compute pointer authentication code, using generic key
+// Compute pointer authentication code for instruction address
+def : InstRW<[C1PWrite_4c_1M0], (instregex "^AUT", "^PAC")>;
+
+// Branch and link, register, with pointer authentication
+def : InstRW<[C1PWrite_6c_1M0_1B_1I], (instrs BLRAA, BLRAAZ, BLRAB, BLRABZ)>;
+
+// Branch, register, with pointer authentication
+// Branch, return, with pointer authentication
+def : InstRW<[C1PWrite_6c_1M0_1B], (instrs BRAA, BRAAZ, BRAB, BRABZ,
+ RETAA, RETAB, ERETAA, ERETAB)>;
+
+
+// Load register, with pointer authentication
+def : InstRW<[C1PWrite_9c_1M0_1L], (instregex "^LDRA[AB](indexed|writeback)")>;
+
+// Strip pointer authentication code
+def : InstRW<[C1PWrite_2c_1M0], (instrs XPACD, XPACI, XPACLRI)>;
+
+// Miscellaneous data-processing instructions
+// -----------------------------------------------------------------------------
+
+// Address generation
+def : InstRW<[C1PWrite_1c_1I], (instrs ADR, ADRP)>;
+
+// Bitfield extract, one reg
+// Bitfield extract, two regs
+def : SchedAlias<WriteExtr, C1PWrite_Extr>;
+def : InstRW<[C1PWrite_Extr], (instrs EXTRWrri, EXTRXrri)>;
+
+// Bitfield move, basic
+def : SchedAlias<WriteIS, C1PWrite_1c_1I>;
+
+// Bitfield move, insert
+def : InstRW<[C1PWrite_2c_1I], (instregex "^BFM[WX]ri$")>;
+
+// Count leading
+// Move immed
+// Reverse bits/bytes
+// Variable shift
+def : InstRW<[C1PWrite_1c_1I],
+ (instregex "^(CLS|CLZ)(W|X)r",
+ "^(MOVN|MOVK|MOVZ)(W|X)i",
+ "^(RBIT|REV(16|32)?)(W|X)r",
+ "^(ASRV|LSLV|LSRV|RORV)(W|X)r")>;
+// Load instructions
+// -----------------------------------------------------------------------------
+
+def : SchedAlias<WriteLD, C1PWrite_4c_1L>;
+def : SchedAlias<WriteLDIdx, C1PWrite_4c_1L_1I>;
+
+// Load register, literal
+def : InstRW<[C1PWrite_5c_1L_1I], (instrs LDRWl, LDRXl, LDRSWl, PRFMl)>;
+
+// Load pair, signed immed offset, normal X form
+// Load pair, signed immed post-index or immed pre-index, normal X form
+def : InstRW<[C1PWrite_4c_2L], (instrs LDPXi, LDNPXi)>;
+def : InstRW<[C1PWrite_4c_2L_1I], (instrs LDPXpre, LDPXpost)>;
+
+
+// Load pair, signed immed offset, signed words
+def : InstRW<[C1PWrite_5c_2L_1I, WriteLDHi], (instrs LDPSWi)>;
+
+// Load pair, immed post-index or immed pre-index, signed words
+def : InstRW<[WriteAdr, C1PWrite_5c_2L_2I, WriteLDHi],
+ (instregex "^LDPSW(post|pre)$")>;
+
+// Store instructions
+// -----------------------------------------------------------------------------
+
+def : SchedAlias<WriteST, C1PWrite_1c_1SA_1D>;
+def : SchedAlias<WriteSTIdx, C1PWrite_1c_1SA_1D_1I>;
+def : SchedAlias<WriteSTP, C1PWrite_1c_1SA_1D>;
+def : SchedAlias<WriteAdr, C1PWrite_1c_1I>;
+
+// Tag load instructions
+// -----------------------------------------------------------------------------
+
+// Load allocation tag
+// Load multiple allocation tags
+def : InstRW<[C1PWrite_4c_1L], (instrs LDG, LDGM)>;
+
+// Tag store instructions
+// -----------------------------------------------------------------------------
+
+// Store allocation tags to one or two granules, post-index
+// Store allocation tags to one or two granules, pre-index
+// Store allocation tag to one or two granules, zeroing, post-index
+// Store Allocation Tag to one or two granules, zeroing, pre-index
+// Store allocation tag and reg pair to memory, post-Index
+// Store allocation tag and reg pair to memory, pre-Index
+def : InstRW<[C1PWrite_1c_1SA_1D_1I], (instrs STGPreIndex, STGPostIndex,
+ ST2GPreIndex, ST2GPostIndex,
+ STZGPreIndex, STZGPostIndex,
+ STZ2GPreIndex, STZ2GPostIndex,
+ STGPpre, STGPpost)>;
+
+// Store allocation tags to one or two granules, signed offset
+// Store allocation tag to two granules, zeroing, signed offset
+// Store allocation tag and reg pair to memory, signed offset
+// Store multiple allocation tags
+def : InstRW<[C1PWrite_1c_1SA_1D], (instrs STGi, ST2Gi, STZGi,
+ STZ2Gi, STGPi, STGM, STZGM)>;
+
+// FP data processing instructions
+// -----------------------------------------------------------------------------
+
+// FP absolute value
+// FP arithmetic
+// FP min/max
+// FP negate
+// FP select
+def : SchedAlias<WriteF, C1PWrite_2c_1V>;
+
+// FP compare
+def : SchedAlias<WriteFCmp, C1PWrite_2c_1V01>;
+
+// FP divide, square root
+def : SchedAlias<WriteFDiv, C1PWrite_5c_1V1_8rc>;
+
+// FP divide, H-form
+def : InstRW<[C1PWrite_5c_1V1], (instrs FDIVHrr)>;
+// FP divide, S-form
+def : InstRW<[C1PWrite_8c_1V1], (instrs FDIVSrr)>;
+// FP divide, D-form
+def : InstRW<[C1PWrite_12c_1V1], (instrs FDIVDrr)>;
+
+// FP square root, H-form
+def : InstRW<[C1PWrite_5c_1V1], (instrs FSQRTHr)>;
+// FP square root, S-form
+def : InstRW<[C1PWrite_8c_1V1], (instrs FSQRTSr)>;
+// FP square root, D-form
+def : InstRW<[C1PWrite_12c_1V1], (instrs FSQRTDr)>;
+
+// FP multiply
+def : SchedAlias<WriteFMul, C1PWrite_3c_1V>;
+
+// FP multiply accumulate
+def : InstRW<[C1PWr_FMA, ReadDefault, ReadDefault, C1PRd_FMA],
+ (instregex "^FN?M(ADD|SUB)[HSD]rrr$")>;
+
+// FP round to integral
+def : InstRW<[C1PWrite_2c_1V], (instregex "^FRINT[AIMNPXZ][HSD]r$",
+ "^FRINT(32|64)[XZ][SD]r$")>;
+
+
+// FP miscellaneous instructions
+// -----------------------------------------------------------------------------
+
+// FP convert, from gen to vec reg
+def : InstRW<[C1PWrite_3c_1M0], (instregex "^[SU]CVTF[SU][WX][HSD]ri$")>;
+
+// FP convert, from vec to gen reg
+def : InstRW<[C1PWrite_3c_1V01],
+ (instregex "^FCVT[AMNPZ][SU][SU][WX][HSD]ri?$")>;
+
+// FP convert, Javascript from vec to gen reg
+def : SchedAlias<WriteFCvt, C1PWrite_3c_1V>;
+
+// FP convert, from vec to vec reg
+def : InstRW<[C1PWrite_3c_1V], (instrs FCVTSHr, FCVTDHr, FCVTHSr, FCVTDSr,
+ FCVTHDr, FCVTSDr, FCVTXNv1i64)>;
+
+// FP move, immed
+// FP move, register
+def : SchedAlias<WriteFImm, C1PWrite_2c_1V>;
+
+//FP transfer, from gen to low half of vec reg
----------------
nasherm wrote:
Done
https://github.com/llvm/llvm-project/pull/185398
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