[llvm] 31ea083 - Handle IMPLICIT_DEF in TripleMBB for WindowScheduler (#179190)
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Mon Apr 27 03:27:27 PDT 2026
Author: Chandana Mudda
Date: 2026-04-27T15:57:22+05:30
New Revision: 31ea083c6b70a79706ba88dfea393d3834f65370
URL: https://github.com/llvm/llvm-project/commit/31ea083c6b70a79706ba88dfea393d3834f65370
DIFF: https://github.com/llvm/llvm-project/commit/31ea083c6b70a79706ba88dfea393d3834f65370.diff
LOG: Handle IMPLICIT_DEF in TripleMBB for WindowScheduler (#179190)
Previously, IMPLICIT_DEF instructions were not copied into the
triple-MBB region used by the WindowScheduler. This left the
machine-level liveness inconsistent with the triplicated code and could
trigger a LiveIntervals assertion:
LiveIntervals::HMEditor::updateRange: Assertion `LR.verify()' failed.
Copy IMPLICIT_DEF into the triple region so that the triplicated block
has a consistent set of defs and LiveIntervals can update ranges
correctly.
---------
Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
Added:
llvm/test/CodeGen/Hexagon/win-sched-implicit-def.mir
Modified:
llvm/lib/CodeGen/WindowScheduler.cpp
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/WindowScheduler.cpp b/llvm/lib/CodeGen/WindowScheduler.cpp
index 2492dfc3ca553..3849a2c2caddf 100644
--- a/llvm/lib/CodeGen/WindowScheduler.cpp
+++ b/llvm/lib/CodeGen/WindowScheduler.cpp
@@ -211,7 +211,7 @@ bool WindowScheduler::initialize() {
};
auto PLI = TII->analyzeLoopForPipelining(MBB);
for (auto &MI : *MBB) {
- if (MI.isMetaInstruction() || MI.isTerminator())
+ if (MI.isDebugOrPseudoInstr() || MI.isTerminator())
continue;
if (MI.isPHI()) {
if (IsLoopCarried(MI)) {
@@ -297,7 +297,7 @@ void WindowScheduler::generateTripleMBB() {
// DefPairs hold the old and new define register pairs.
DenseMap<Register, Register> DefPairs;
for (auto *MI : OriMIs) {
- if (MI->isMetaInstruction() || MI->isTerminator())
+ if (MI->isDebugOrPseudoInstr() || MI->isTerminator())
continue;
if (MI->isPHI())
if (Register AntiReg = getAntiRegister(MI))
@@ -312,7 +312,7 @@ void WindowScheduler::generateTripleMBB() {
// are updated accordingly.
for (size_t Cnt = 1; Cnt < DuplicateNum; ++Cnt) {
for (auto *MI : OriMIs) {
- if (MI->isPHI() || MI->isMetaInstruction() ||
+ if (MI->isPHI() || MI->isDebugOrPseudoInstr() ||
(MI->isTerminator() && Cnt < DuplicateNum - 1))
continue;
auto *NewMI = MF->CloneMachineInstr(MI);
@@ -687,7 +687,7 @@ unsigned WindowScheduler::getOriStage(MachineInstr *OriMI, unsigned Offset) {
// while the rest are set to 1.
unsigned Id = 0;
for (auto *MI : OriMIs) {
- if (MI->isMetaInstruction())
+ if (MI->isDebugOrPseudoInstr())
continue;
if (MI == OriMI)
break;
diff --git a/llvm/test/CodeGen/Hexagon/win-sched-implicit-def.mir b/llvm/test/CodeGen/Hexagon/win-sched-implicit-def.mir
new file mode 100644
index 0000000000000..cfc2a7788f0cb
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/win-sched-implicit-def.mir
@@ -0,0 +1,89 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=hexagon -run-pass=pipeliner -window-sched=force %s -o - | FileCheck %s
+# Ensure WindowScheduler copies IMPLICIT_DEF into the triple-MBB region
+# so LiveIntervals no longer hits LR.verify()
+
+--- |
+ define void @foo() {
+ ret void
+ }
+...
+---
+name: foo
+tracksRegLiveness: true
+
+body: |
+ ; CHECK-LABEL: name: foo
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x60000000), %bb.2(0x20000000)
+ ; CHECK-NEXT: liveins: $r0, $r1, $r2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:intregs = IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:predregs = IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF2:%[0-9]+]]:intregslow8 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF3:%[0-9]+]]:hvxqr = IMPLICIT_DEF
+ ; CHECK-NEXT: J2_jumpf [[DEF1]], %bb.2, implicit-def dead $pc
+ ; CHECK-NEXT: J2_jump %bb.1, implicit-def dead $pc
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.4(0x55555555), %bb.2(0x2aaaaaab)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: J2_jumpt [[DEF1]], %bb.4, implicit-def dead $pc
+ ; CHECK-NEXT: J2_jump %bb.2, implicit-def dead $pc
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: J2_loop0r %bb.3, [[DEF]], implicit-def $lc0, implicit-def $sa0, implicit-def $usr
+ ; CHECK-NEXT: J2_jump %bb.3, implicit-def $pc
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3 (machine-block-address-taken):
+ ; CHECK-NEXT: successors: %bb.4(0x04000000), %bb.3(0x7c000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[V6_vL32Ub_ai:%[0-9]+]]:hvxvr = V6_vL32Ub_ai [[DEF]], 0 :: (load (s1024), align 8)
+ ; CHECK-NEXT: [[DEF4:%[0-9]+]]:hvxwr = IMPLICIT_DEF
+ ; CHECK-NEXT: dead [[V6_vlalignb:%[0-9]+]]:hvxvr = V6_vlalignb [[DEF4]].vsub_lo, [[V6_vL32Ub_ai]], [[DEF2]]
+ ; CHECK-NEXT: [[V6_vlalignb1:%[0-9]+]]:hvxvr = V6_vlalignb [[DEF4]].vsub_lo, [[DEF4]].vsub_hi, [[DEF2]]
+ ; CHECK-NEXT: V6_vS32b_qpred_ai [[DEF3]], [[DEF]], 0, [[V6_vlalignb1]] :: (store (s1024))
+ ; CHECK-NEXT: ENDLOOP0 %bb.3, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0
+ ; CHECK-NEXT: J2_jump %bb.4, implicit-def dead $pc
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4:
+ ; CHECK-NEXT: PS_jmpret $r31, implicit-def dead $pc
+ bb.0:
+ successors: %bb.1(0x60000000), %bb.2(0x20000000)
+ liveins: $r0, $r1, $r2
+
+ %0:intregs = IMPLICIT_DEF
+ %1:predregs = IMPLICIT_DEF
+ %2:intregslow8 = IMPLICIT_DEF
+ %3:hvxqr = IMPLICIT_DEF
+ J2_jumpf %1, %bb.2, implicit-def dead $pc
+ J2_jump %bb.1, implicit-def dead $pc
+
+ bb.1:
+ successors: %bb.4(0x55555555), %bb.2(0x2aaaaaab)
+
+ J2_jumpt %1, %bb.4, implicit-def dead $pc
+ J2_jump %bb.2, implicit-def dead $pc
+
+ bb.2:
+ successors: %bb.3(0x80000000)
+
+ J2_loop0r %bb.3, %0, implicit-def $lc0, implicit-def $sa0, implicit-def $usr
+ J2_jump %bb.3, implicit-def $pc
+
+ bb.3 (machine-block-address-taken):
+ successors: %bb.4(0x04000000), %bb.3(0x7c000000)
+
+ %4:hvxvr = V6_vL32Ub_ai %0, 0 :: (load (s1024), align 8)
+ %5:hvxwr = IMPLICIT_DEF
+ %6:hvxvr = V6_vlalignb %5.vsub_lo, %4, %2
+ %7:hvxvr = V6_vlalignb %5.vsub_lo, %5.vsub_hi, %2
+ V6_vS32b_qpred_ai %3, %0, 0, %7 :: (store (s1024))
+ ENDLOOP0 %bb.3, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0
+ J2_jump %bb.4, implicit-def dead $pc
+
+ bb.4:
+ PS_jmpret $r31, implicit-def dead $pc
+...
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