[llvm] [RISCV] Further improved exact VLEN lowering for mul reductions (PR #192688)

[Pengcheng Wang via llvm-commits]

================
@@ -288,25 +288,46 @@ bool RISCVCodeGenPrepare::expandMulReduction(IntrinsicInst &II) {
     return false;
 
   IRBuilder<> Builder(&II);
+  auto *M1Ty = FixedVectorType::get(VecTy->getElementType(), M1VF);
 
-  // Shuffle-reduce at the original vector width.  This just duplicates the
-  // default lowering down to m1.
-  SmallVector<int, 32> ShuffleMask(VF);
-  for (unsigned LiveElts = VF; LiveElts > M1VF; LiveElts /= 2) {
-    unsigned Half = LiveElts / 2;
-    std::iota(ShuffleMask.begin(), ShuffleMask.begin() + Half, Half);
-    std::fill(ShuffleMask.begin() + Half, ShuffleMask.end(), -1);
-    Value *Shuf = Builder.CreateShuffleVector(TmpVec, ShuffleMask, "rdx.shuf");
-    TmpVec = Builder.CreateMul(TmpVec, Shuf, "bin.rdx");
+  // When VLEN is exactly known, extract m1 pieces and build a mul tree.
+  // This greatly reduces register pressure during the reduction, and
+  // avoids all but one vsetvli (the one from original LMUL to m1).
+  if (MinVLen == ST->getRealMaxVLen()) {
+    unsigned NumM1 = VF / M1VF;
+    assert(isPowerOf2_32(NumM1) && NumM1 <= 8);
----------------
wangpc-pp wrote:

Should we just return false for `NumM1 > 8`? It is possible we may assert here when the type is too large?

https://github.com/llvm/llvm-project/pull/192688