[llvm] b6a4fdb - [LSR] Autogenerate some tests
via llvm-commits
llvm-commits at lists.llvm.org
Sun Apr 19 11:49:07 PDT 2026
Author: Aiden Grossman
Date: 2026-04-19T11:49:03-07:00
New Revision: b6a4fdb8035d78934f98e823f67a5adb8c333828
URL: https://github.com/llvm/llvm-project/commit/b6a4fdb8035d78934f98e823f67a5adb8c333828
DIFF: https://github.com/llvm/llvm-project/commit/b6a4fdb8035d78934f98e823f67a5adb8c333828.diff
LOG: [LSR] Autogenerate some tests
pr25541.ll - Was a regression test for a crash. Make a note and
autogenerate the tests.
bin_power.ll - Was essentially doing what UTC would do already, minus
one test where the assembly output is somewhat large, but the large
assembly output shouldn't be an issue with an autoupdate script and
isn't big enough to justify not including in my opinion.
This makes updating some tests easier for planned changes to LCSSA
preservation.
Reviewers: fhahn, nikic
Pull Request: https://github.com/llvm/llvm-project/pull/191664
Added:
Modified:
llvm/test/Transforms/LoopStrengthReduce/X86/2011-12-04-loserreg.ll
llvm/test/Transforms/LoopStrengthReduce/X86/bin_power.ll
llvm/test/Transforms/LoopStrengthReduce/pr25541.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/LoopStrengthReduce/X86/2011-12-04-loserreg.ll b/llvm/test/Transforms/LoopStrengthReduce/X86/2011-12-04-loserreg.ll
index f1a75f9615a59..76faad105ee7e 100644
--- a/llvm/test/Transforms/LoopStrengthReduce/X86/2011-12-04-loserreg.ll
+++ b/llvm/test/Transforms/LoopStrengthReduce/X86/2011-12-04-loserreg.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt < %s -loop-reduce -S | FileCheck %s
;
; Test LSR's ability to prune formulae that refer to nonexistent
@@ -14,12 +15,87 @@
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
target triple = "x86_64-apple-darwin"
-; CHECK-LABEL: @test(
-; CHECK: for.body:
-; CHECK: %lsr.iv
-; CHECK-NOT: %dummyout
-; CHECK: ret
define i64 @test(i64 %count, ptr nocapture %srcrow, ptr nocapture %destrow) nounwind uwtable ssp {
+; CHECK-LABEL: define i64 @test(
+; CHECK-SAME: i64 [[COUNT:%.*]], ptr captures(none) [[SRCROW:%.*]], ptr captures(none) [[DESTROW:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[CMP34:%.*]] = icmp eq i64 [[COUNT]], 0
+; CHECK-NEXT: br i1 [[CMP34]], label %[[FOR_END29:.*]], label %[[FOR_BODY_PREHEADER:.*]]
+; CHECK: [[FOR_BODY_PREHEADER]]:
+; CHECK-NEXT: [[SCEVGEP4:%.*]] = getelementptr i8, ptr [[SRCROW]], i64 4
+; CHECK-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK: [[FOR_BODY]]:
+; CHECK-NEXT: [[LSR_IV:%.*]] = phi ptr [ [[SCEVGEP4]], %[[FOR_BODY_PREHEADER]] ], [ [[SCEVGEP5:%.*]], %[[FOR_BODY]] ]
+; CHECK-NEXT: [[DUMMYIV:%.*]] = phi i64 [ [[DUMMYCNT:%.*]], %[[FOR_BODY]] ], [ 0, %[[FOR_BODY_PREHEADER]] ]
+; CHECK-NEXT: [[INDVARS_IV39:%.*]] = phi i64 [ [[INDVARS_IV_NEXT40:%.*]], %[[FOR_BODY]] ], [ 0, %[[FOR_BODY_PREHEADER]] ]
+; CHECK-NEXT: [[DP_036:%.*]] = phi ptr [ [[SCEVGEP16:%.*]], %[[FOR_BODY]] ], [ [[DESTROW]], %[[FOR_BODY_PREHEADER]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[LSR_IV]], align 4
+; CHECK-NEXT: [[SCEVGEP9:%.*]] = getelementptr i8, ptr [[LSR_IV]], i64 4
+; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[SCEVGEP9]], align 4
+; CHECK-NEXT: [[SCEVGEP8:%.*]] = getelementptr i8, ptr [[LSR_IV]], i64 8
+; CHECK-NEXT: [[TMP2:%.*]] = load float, ptr [[SCEVGEP8]], align 4
+; CHECK-NEXT: [[SCEVGEP7:%.*]] = getelementptr i8, ptr [[LSR_IV]], i64 12
+; CHECK-NEXT: [[TMP3:%.*]] = load float, ptr [[SCEVGEP7]], align 4
+; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DP_036]], align 4
+; CHECK-NEXT: [[CONV5:%.*]] = fptoui float [[TMP0]] to i32
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[TMP4]], [[CONV5]]
+; CHECK-NEXT: [[SCEVGEP10:%.*]] = getelementptr i8, ptr [[DP_036]], i64 4
+; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[SCEVGEP10]], align 4
+; CHECK-NEXT: [[CONV7:%.*]] = fptoui float [[TMP1]] to i32
+; CHECK-NEXT: [[OR8:%.*]] = or i32 [[TMP5]], [[CONV7]]
+; CHECK-NEXT: [[SCEVGEP11:%.*]] = getelementptr i8, ptr [[DP_036]], i64 8
+; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[SCEVGEP11]], align 4
+; CHECK-NEXT: [[CONV10:%.*]] = fptoui float [[TMP2]] to i32
+; CHECK-NEXT: [[OR11:%.*]] = or i32 [[TMP6]], [[CONV10]]
+; CHECK-NEXT: [[SCEVGEP12:%.*]] = getelementptr i8, ptr [[DP_036]], i64 12
+; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[SCEVGEP12]], align 4
+; CHECK-NEXT: [[CONV13:%.*]] = fptoui float [[TMP3]] to i32
+; CHECK-NEXT: [[OR14:%.*]] = or i32 [[TMP7]], [[CONV13]]
+; CHECK-NEXT: store i32 [[OR]], ptr [[DP_036]], align 4
+; CHECK-NEXT: [[SCEVGEP13:%.*]] = getelementptr i8, ptr [[DP_036]], i64 4
+; CHECK-NEXT: store i32 [[OR8]], ptr [[SCEVGEP13]], align 4
+; CHECK-NEXT: [[SCEVGEP14:%.*]] = getelementptr i8, ptr [[DP_036]], i64 8
+; CHECK-NEXT: store i32 [[OR11]], ptr [[SCEVGEP14]], align 4
+; CHECK-NEXT: [[SCEVGEP15:%.*]] = getelementptr i8, ptr [[DP_036]], i64 12
+; CHECK-NEXT: store i32 [[OR14]], ptr [[SCEVGEP15]], align 4
+; CHECK-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, ptr [[DP_036]], i64 4
+; CHECK-NEXT: [[INDVARS_IV_NEXT40]] = add i64 [[INDVARS_IV39]], 4
+; CHECK-NEXT: [[DUMMYCNT]] = add i64 [[DUMMYIV]], 1
+; CHECK-NEXT: [[SCEVGEP5]] = getelementptr i8, ptr [[LSR_IV]], i64 16
+; CHECK-NEXT: [[CMP:%.*]] = icmp ult i64 [[INDVARS_IV_NEXT40]], [[COUNT]]
+; CHECK-NEXT: [[SCEVGEP16]] = getelementptr i8, ptr [[DP_036]], i64 16
+; CHECK-NEXT: br i1 [[CMP]], label %[[FOR_BODY]], label %[[FOR_COND19_PREHEADER:.*]]
+; CHECK: [[FOR_COND19_PREHEADER]]:
+; CHECK-NEXT: [[DUMMYCNT_LCSSA:%.*]] = phi i64 [ [[DUMMYCNT]], %[[FOR_BODY]] ]
+; CHECK-NEXT: [[REM:%.*]] = and i64 [[COUNT]], 3
+; CHECK-NEXT: [[CMP2130:%.*]] = icmp eq i64 [[REM]], 0
+; CHECK-NEXT: br i1 [[CMP2130]], label %[[FOR_COND19_PREHEADER_FOR_END29_CRIT_EDGE:.*]], label %[[FOR_BODY23_LR_PH:.*]]
+; CHECK: [[FOR_COND19_PREHEADER_FOR_END29_CRIT_EDGE]]:
+; CHECK-NEXT: br label %[[FOR_END29]]
+; CHECK: [[FOR_BODY23_LR_PH]]:
+; CHECK-NEXT: [[TMP8:%.*]] = and i64 [[COUNT]], 3
+; CHECK-NEXT: br label %[[FOR_BODY23:.*]]
+; CHECK: [[FOR_BODY23]]:
+; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, %[[FOR_BODY23_LR_PH]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[FOR_BODY23]] ]
+; CHECK-NEXT: [[TMP9:%.*]] = shl nuw nsw i64 [[INDVARS_IV]], 2
+; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[ADD_PTR]], i64 [[TMP9]]
+; CHECK-NEXT: [[TMP10:%.*]] = shl nuw nsw i64 [[INDVARS_IV]], 2
+; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[ADD_PTR]], i64 [[TMP10]]
+; CHECK-NEXT: [[SCEVGEP6:%.*]] = getelementptr i8, ptr [[SCEVGEP5]], i64 [[TMP10]]
+; CHECK-NEXT: [[TMP11:%.*]] = load float, ptr [[SCEVGEP6]], align 4
+; CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[SCEVGEP1]], align 4
+; CHECK-NEXT: [[CONV25:%.*]] = fptoui float [[TMP11]] to i32
+; CHECK-NEXT: [[OR26:%.*]] = or i32 [[TMP12]], [[CONV25]]
+; CHECK-NEXT: store i32 [[OR26]], ptr [[SCEVGEP]], align 4
+; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add i64 [[INDVARS_IV]], 1
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[TMP8]], [[INDVARS_IV_NEXT]]
+; CHECK-NEXT: br i1 [[EXITCOND]], label %[[FOR_END29_LOOPEXIT:.*]], label %[[FOR_BODY23]]
+; CHECK: [[FOR_END29_LOOPEXIT]]:
+; CHECK-NEXT: br label %[[FOR_END29]]
+; CHECK: [[FOR_END29]]:
+; CHECK-NEXT: [[RESULT:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[DUMMYCNT_LCSSA]], %[[FOR_COND19_PREHEADER_FOR_END29_CRIT_EDGE]] ], [ [[DUMMYCNT_LCSSA]], %[[FOR_END29_LOOPEXIT]] ]
+; CHECK-NEXT: ret i64 [[RESULT]]
+;
entry:
%cmp34 = icmp eq i64 %count, 0
br i1 %cmp34, label %for.end29, label %for.body
diff --git a/llvm/test/Transforms/LoopStrengthReduce/X86/bin_power.ll b/llvm/test/Transforms/LoopStrengthReduce/X86/bin_power.ll
index c9781241c9699..26681c33a6607 100644
--- a/llvm/test/Transforms/LoopStrengthReduce/X86/bin_power.ll
+++ b/llvm/test/Transforms/LoopStrengthReduce/X86/bin_power.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt < %s -scalar-evolution-huge-expr-threshold=1000000 -loop-reduce -S | FileCheck %s
target datalayout = "e-m:e-i32:64-f80:128-n8:16:32:64-S128"
@@ -5,20 +6,22 @@ target triple = "x86_64-unknown-linux-gnu"
; Show that the b^2 is expanded correctly.
define i32 @test_01(i32 %a) {
-; CHECK-LABEL: @test_01
-; CHECK: entry:
-; CHECK-NEXT: br label %loop
-; CHECK: loop:
-; CHECK-NEXT: [[IV:[^ ]+]] = phi i32 [ [[IV_INC:[^ ]+]], %loop ], [ 0, %entry ]
-; CHECK-NEXT: [[IV_INC]] = add nsw i32 [[IV]], -1
-; CHECK-NEXT: [[EXITCOND:[^ ]+]] = icmp eq i32 [[IV_INC]], -80
-; CHECK-NEXT: br i1 [[EXITCOND]], label %exit, label %loop
-; CHECK: exit:
-; CHECK-NEXT: [[B:[^ ]+]] = add i32 %a, 1
-; CHECK-NEXT: [[B2:[^ ]+]] = mul i32 [[B]], [[B]]
-; CHECK-NEXT: [[R1:[^ ]+]] = add i32 [[B2]], -1
-; CHECK-NEXT: [[R2:[^ ]+]] = sub i32 [[R1]], [[IV_INC]]
-; CHECK-NEXT: ret i32 [[R2]]
+; CHECK-LABEL: define i32 @test_01(
+; CHECK-SAME: i32 [[A:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], %[[LOOP]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT: [[LSR_IV_NEXT]] = add nsw i32 [[LSR_IV]], -1
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[LSR_IV_NEXT]], -80
+; CHECK-NEXT: br i1 [[EXITCOND]], label %[[EXIT:.*]], label %[[LOOP]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[A]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[TMP0]], [[TMP0]]
+; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], -1
+; CHECK-NEXT: [[TMP3:%.*]] = sub i32 [[TMP2]], [[LSR_IV_NEXT]]
+; CHECK-NEXT: ret i32 [[TMP3]]
+;
entry:
br label %loop
@@ -38,22 +41,24 @@ exit: ; preds = %loop
; Show that b^8 is expanded correctly.
define i32 @test_02(i32 %a) {
-; CHECK-LABEL: @test_02
-; CHECK: entry:
-; CHECK-NEXT: br label %loop
-; CHECK: loop:
-; CHECK-NEXT: [[IV:[^ ]+]] = phi i32 [ [[IV_INC:[^ ]+]], %loop ], [ 0, %entry ]
-; CHECK-NEXT: [[IV_INC]] = add nsw i32 [[IV]], -1
-; CHECK-NEXT: [[EXITCOND:[^ ]+]] = icmp eq i32 [[IV_INC]], -80
-; CHECK-NEXT: br i1 [[EXITCOND]], label %exit, label %loop
-; CHECK: exit:
-; CHECK-NEXT: [[B:[^ ]+]] = add i32 %a, 1
-; CHECK-NEXT: [[B2:[^ ]+]] = mul i32 [[B]], [[B]]
-; CHECK-NEXT: [[B4:[^ ]+]] = mul i32 [[B2]], [[B2]]
-; CHECK-NEXT: [[B8:[^ ]+]] = mul i32 [[B4]], [[B4]]
-; CHECK-NEXT: [[R1:[^ ]+]] = add i32 [[B8]], -1
-; CHECK-NEXT: [[R2:[^ ]+]] = sub i32 [[R1]], [[IV_INC]]
-; CHECK-NEXT: ret i32 [[R2]]
+; CHECK-LABEL: define i32 @test_02(
+; CHECK-SAME: i32 [[A:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], %[[LOOP]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT: [[LSR_IV_NEXT]] = add nsw i32 [[LSR_IV]], -1
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[LSR_IV_NEXT]], -80
+; CHECK-NEXT: br i1 [[EXITCOND]], label %[[EXIT:.*]], label %[[LOOP]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[A]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[TMP0]], [[TMP0]]
+; CHECK-NEXT: [[TMP2:%.*]] = mul i32 [[TMP1]], [[TMP1]]
+; CHECK-NEXT: [[TMP3:%.*]] = mul i32 [[TMP2]], [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[TMP3]], -1
+; CHECK-NEXT: [[TMP5:%.*]] = sub i32 [[TMP4]], [[LSR_IV_NEXT]]
+; CHECK-NEXT: ret i32 [[TMP5]]
+;
entry:
br label %loop
@@ -74,26 +79,28 @@ exit: ; preds = %loop
; Show that b^27 (27 = 1 + 2 + 8 + 16) is expanded correctly.
define i32 @test_03(i32 %a) {
-; CHECK-LABEL: @test_03
-; CHECK: entry:
-; CHECK-NEXT: br label %loop
-; CHECK: loop:
-; CHECK-NEXT: [[IV:[^ ]+]] = phi i32 [ [[IV_INC:[^ ]+]], %loop ], [ 0, %entry ]
-; CHECK-NEXT: [[IV_INC]] = add nsw i32 [[IV]], -1
-; CHECK-NEXT: [[EXITCOND:[^ ]+]] = icmp eq i32 [[IV_INC]], -80
-; CHECK-NEXT: br i1 [[EXITCOND]], label %exit, label %loop
-; CHECK: exit:
-; CHECK-NEXT: [[B:[^ ]+]] = add i32 %a, 1
-; CHECK-NEXT: [[B2:[^ ]+]] = mul i32 [[B]], [[B]]
-; CHECK-NEXT: [[B3:[^ ]+]] = mul i32 [[B]], [[B2]]
-; CHECK-NEXT: [[B4:[^ ]+]] = mul i32 [[B2]], [[B2]]
-; CHECK-NEXT: [[B8:[^ ]+]] = mul i32 [[B4]], [[B4]]
-; CHECK-NEXT: [[B11:[^ ]+]] = mul i32 [[B3]], [[B8]]
-; CHECK-NEXT: [[B16:[^ ]+]] = mul i32 [[B8]], [[B8]]
-; CHECK-NEXT: [[B27:[^ ]+]] = mul i32 [[B11]], [[B16]]
-; CHECK-NEXT: [[R1:[^ ]+]] = add i32 [[B27]], -1
-; CHECK-NEXT: [[R2:[^ ]+]] = sub i32 [[R1]], [[IV_INC]]
-; CHECK-NEXT: ret i32 [[R2]]
+; CHECK-LABEL: define i32 @test_03(
+; CHECK-SAME: i32 [[A:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], %[[LOOP]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT: [[LSR_IV_NEXT]] = add nsw i32 [[LSR_IV]], -1
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[LSR_IV_NEXT]], -80
+; CHECK-NEXT: br i1 [[EXITCOND]], label %[[EXIT:.*]], label %[[LOOP]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[A]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[TMP0]], [[TMP0]]
+; CHECK-NEXT: [[TMP2:%.*]] = mul i32 [[TMP0]], [[TMP1]]
+; CHECK-NEXT: [[TMP3:%.*]] = mul i32 [[TMP1]], [[TMP1]]
+; CHECK-NEXT: [[TMP4:%.*]] = mul i32 [[TMP3]], [[TMP3]]
+; CHECK-NEXT: [[TMP5:%.*]] = mul i32 [[TMP2]], [[TMP4]]
+; CHECK-NEXT: [[TMP6:%.*]] = mul i32 [[TMP4]], [[TMP4]]
+; CHECK-NEXT: [[TMP7:%.*]] = mul i32 [[TMP5]], [[TMP6]]
+; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP7]], -1
+; CHECK-NEXT: [[TMP9:%.*]] = sub i32 [[TMP8]], [[LSR_IV_NEXT]]
+; CHECK-NEXT: ret i32 [[TMP9]]
+;
entry:
br label %loop
@@ -119,23 +126,25 @@ exit: ; preds = %loop
; Show how linear calculation of b^16 is turned into logarithmic.
define i32 @test_04(i32 %a) {
-; CHECK-LABEL: @test_04
-; CHECK: entry:
-; CHECK-NEXT: br label %loop
-; CHECK: loop:
-; CHECK-NEXT: [[IV:[^ ]+]] = phi i32 [ [[IV_INC:[^ ]+]], %loop ], [ 0, %entry ]
-; CHECK-NEXT: [[IV_INC]] = add nsw i32 [[IV]], -1
-; CHECK-NEXT: [[EXITCOND:[^ ]+]] = icmp eq i32 [[IV_INC]], -80
-; CHECK-NEXT: br i1 [[EXITCOND]], label %exit, label %loop
-; CHECK: exit:
-; CHECK-NEXT: [[B:[^ ]+]] = add i32 %a, 1
-; CHECK-NEXT: [[B2:[^ ]+]] = mul i32 [[B]], [[B]]
-; CHECK-NEXT: [[B4:[^ ]+]] = mul i32 [[B2]], [[B2]]
-; CHECK-NEXT: [[B8:[^ ]+]] = mul i32 [[B4]], [[B4]]
-; CHECK-NEXT: [[B16:[^ ]+]] = mul i32 [[B8]], [[B8]]
-; CHECK-NEXT: [[R1:[^ ]+]] = add i32 [[B16]], -1
-; CHECK-NEXT: [[R2:[^ ]+]] = sub i32 [[R1]], [[IV_INC]]
-; CHECK-NEXT: ret i32 [[R2]]
+; CHECK-LABEL: define i32 @test_04(
+; CHECK-SAME: i32 [[A:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], %[[LOOP]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT: [[LSR_IV_NEXT]] = add nsw i32 [[LSR_IV]], -1
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[LSR_IV_NEXT]], -80
+; CHECK-NEXT: br i1 [[EXITCOND]], label %[[EXIT:.*]], label %[[LOOP]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[A]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[TMP0]], [[TMP0]]
+; CHECK-NEXT: [[TMP2:%.*]] = mul i32 [[TMP1]], [[TMP1]]
+; CHECK-NEXT: [[TMP3:%.*]] = mul i32 [[TMP2]], [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = mul i32 [[TMP3]], [[TMP3]]
+; CHECK-NEXT: [[TMP5:%.*]] = add i32 [[TMP4]], -1
+; CHECK-NEXT: [[TMP6:%.*]] = sub i32 [[TMP5]], [[LSR_IV_NEXT]]
+; CHECK-NEXT: ret i32 [[TMP6]]
+;
entry:
br label %loop
@@ -166,20 +175,160 @@ exit: ; preds = %loop
ret i32 %result
}
-; The output here is reasonably big, we just check that the amount of expanded
-; instructions is sane.
define i32 @test_05(i32 %a) {
-; CHECK-LABEL: @test_05
-; CHECK: entry:
-; CHECK-NEXT: br label %loop
-; CHECK: loop:
-; CHECK-NEXT: [[IV:[^ ]+]] = phi i32 [ [[IV_INC:[^ ]+]], %loop ], [ 0, %entry ]
-; CHECK-NEXT: [[IV_INC]] = add nsw i32 [[IV]], -1
-; CHECK-NEXT: [[EXITCOND:[^ ]+]] = icmp eq i32 [[IV_INC]], -80
-; CHECK-NEXT: br i1 [[EXITCOND]], label %exit, label %loop
-; CHECK: exit:
-; CHECK: %100
-; CHECK-NOT: %150
+; CHECK-LABEL: define i32 @test_05(
+; CHECK-SAME: i32 [[A:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], %[[LOOP]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT: [[LSR_IV_NEXT]] = add nsw i32 [[LSR_IV]], -1
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[LSR_IV_NEXT]], -80
+; CHECK-NEXT: br i1 [[EXITCOND]], label %[[EXIT:.*]], label %[[LOOP]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[A]], 1
+; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[TMP0]], [[TMP0]]
+; CHECK-NEXT: [[TMP2:%.*]] = mul i32 [[TMP1]], [[TMP1]]
+; CHECK-NEXT: [[TMP3:%.*]] = mul i32 [[TMP2]], [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = mul i32 [[TMP3]], [[TMP3]]
+; CHECK-NEXT: [[TMP5:%.*]] = mul i32 [[TMP4]], [[TMP4]]
+; CHECK-NEXT: [[TMP6:%.*]] = mul i32 [[TMP5]], [[TMP5]]
+; CHECK-NEXT: [[TMP7:%.*]] = mul i32 [[TMP6]], [[TMP5]]
+; CHECK-NEXT: [[TMP8:%.*]] = mul i32 [[TMP0]], [[TMP0]]
+; CHECK-NEXT: [[TMP9:%.*]] = mul i32 [[TMP8]], [[TMP8]]
+; CHECK-NEXT: [[TMP10:%.*]] = mul i32 [[TMP9]], [[TMP9]]
+; CHECK-NEXT: [[TMP11:%.*]] = mul i32 [[TMP10]], [[TMP10]]
+; CHECK-NEXT: [[TMP12:%.*]] = mul i32 [[TMP11]], [[TMP11]]
+; CHECK-NEXT: [[TMP13:%.*]] = mul i32 [[TMP7]], [[TMP12]]
+; CHECK-NEXT: [[TMP14:%.*]] = mul i32 [[TMP13]], [[TMP6]]
+; CHECK-NEXT: [[TMP15:%.*]] = mul i32 [[TMP14]], [[TMP5]]
+; CHECK-NEXT: [[TMP16:%.*]] = mul i32 [[TMP0]], [[TMP0]]
+; CHECK-NEXT: [[TMP17:%.*]] = mul i32 [[TMP16]], [[TMP16]]
+; CHECK-NEXT: [[TMP18:%.*]] = mul i32 [[TMP17]], [[TMP17]]
+; CHECK-NEXT: [[TMP19:%.*]] = mul i32 [[TMP18]], [[TMP18]]
+; CHECK-NEXT: [[TMP20:%.*]] = mul i32 [[TMP19]], [[TMP19]]
+; CHECK-NEXT: [[TMP21:%.*]] = mul i32 [[TMP15]], [[TMP20]]
+; CHECK-NEXT: [[TMP22:%.*]] = mul i32 [[TMP21]], [[TMP13]]
+; CHECK-NEXT: [[TMP23:%.*]] = mul i32 [[TMP22]], [[TMP6]]
+; CHECK-NEXT: [[TMP24:%.*]] = mul i32 [[TMP23]], [[TMP5]]
+; CHECK-NEXT: [[TMP25:%.*]] = mul i32 [[TMP0]], [[TMP0]]
+; CHECK-NEXT: [[TMP26:%.*]] = mul i32 [[TMP25]], [[TMP25]]
+; CHECK-NEXT: [[TMP27:%.*]] = mul i32 [[TMP26]], [[TMP26]]
+; CHECK-NEXT: [[TMP28:%.*]] = mul i32 [[TMP27]], [[TMP27]]
+; CHECK-NEXT: [[TMP29:%.*]] = mul i32 [[TMP28]], [[TMP28]]
+; CHECK-NEXT: [[TMP30:%.*]] = mul i32 [[TMP24]], [[TMP29]]
+; CHECK-NEXT: [[TMP31:%.*]] = mul i32 [[TMP30]], [[TMP21]]
+; CHECK-NEXT: [[TMP32:%.*]] = mul i32 [[TMP31]], [[TMP13]]
+; CHECK-NEXT: [[TMP33:%.*]] = mul i32 [[TMP32]], [[TMP6]]
+; CHECK-NEXT: [[TMP34:%.*]] = mul i32 [[TMP33]], [[TMP5]]
+; CHECK-NEXT: [[TMP35:%.*]] = mul i32 [[TMP0]], [[TMP0]]
+; CHECK-NEXT: [[TMP36:%.*]] = mul i32 [[TMP35]], [[TMP35]]
+; CHECK-NEXT: [[TMP37:%.*]] = mul i32 [[TMP36]], [[TMP36]]
+; CHECK-NEXT: [[TMP38:%.*]] = mul i32 [[TMP37]], [[TMP37]]
+; CHECK-NEXT: [[TMP39:%.*]] = mul i32 [[TMP38]], [[TMP38]]
+; CHECK-NEXT: [[TMP40:%.*]] = mul i32 [[TMP34]], [[TMP39]]
+; CHECK-NEXT: [[TMP41:%.*]] = mul i32 [[TMP40]], [[TMP30]]
+; CHECK-NEXT: [[TMP42:%.*]] = mul i32 [[TMP41]], [[TMP21]]
+; CHECK-NEXT: [[TMP43:%.*]] = mul i32 [[TMP42]], [[TMP13]]
+; CHECK-NEXT: [[TMP44:%.*]] = mul i32 [[TMP43]], [[TMP6]]
+; CHECK-NEXT: [[TMP45:%.*]] = mul i32 [[TMP44]], [[TMP5]]
+; CHECK-NEXT: [[TMP46:%.*]] = mul i32 [[TMP0]], [[TMP0]]
+; CHECK-NEXT: [[TMP47:%.*]] = mul i32 [[TMP46]], [[TMP46]]
+; CHECK-NEXT: [[TMP48:%.*]] = mul i32 [[TMP47]], [[TMP47]]
+; CHECK-NEXT: [[TMP49:%.*]] = mul i32 [[TMP48]], [[TMP48]]
+; CHECK-NEXT: [[TMP50:%.*]] = mul i32 [[TMP49]], [[TMP49]]
+; CHECK-NEXT: [[TMP51:%.*]] = mul i32 [[TMP45]], [[TMP50]]
+; CHECK-NEXT: [[TMP52:%.*]] = mul i32 [[TMP51]], [[TMP40]]
+; CHECK-NEXT: [[TMP53:%.*]] = mul i32 [[TMP52]], [[TMP30]]
+; CHECK-NEXT: [[TMP54:%.*]] = mul i32 [[TMP53]], [[TMP21]]
+; CHECK-NEXT: [[TMP55:%.*]] = mul i32 [[TMP54]], [[TMP13]]
+; CHECK-NEXT: [[TMP56:%.*]] = mul i32 [[TMP55]], [[TMP6]]
+; CHECK-NEXT: [[TMP57:%.*]] = mul i32 [[TMP56]], [[TMP5]]
+; CHECK-NEXT: [[TMP58:%.*]] = mul i32 [[TMP0]], [[TMP0]]
+; CHECK-NEXT: [[TMP59:%.*]] = mul i32 [[TMP58]], [[TMP58]]
+; CHECK-NEXT: [[TMP60:%.*]] = mul i32 [[TMP59]], [[TMP59]]
+; CHECK-NEXT: [[TMP61:%.*]] = mul i32 [[TMP60]], [[TMP60]]
+; CHECK-NEXT: [[TMP62:%.*]] = mul i32 [[TMP61]], [[TMP61]]
+; CHECK-NEXT: [[TMP63:%.*]] = mul i32 [[TMP57]], [[TMP62]]
+; CHECK-NEXT: [[TMP64:%.*]] = mul i32 [[TMP63]], [[TMP51]]
+; CHECK-NEXT: [[TMP65:%.*]] = mul i32 [[TMP64]], [[TMP40]]
+; CHECK-NEXT: [[TMP66:%.*]] = mul i32 [[TMP65]], [[TMP30]]
+; CHECK-NEXT: [[TMP67:%.*]] = mul i32 [[TMP66]], [[TMP21]]
+; CHECK-NEXT: [[TMP68:%.*]] = mul i32 [[TMP67]], [[TMP13]]
+; CHECK-NEXT: [[TMP69:%.*]] = mul i32 [[TMP68]], [[TMP6]]
+; CHECK-NEXT: [[TMP70:%.*]] = mul i32 [[TMP69]], [[TMP5]]
+; CHECK-NEXT: [[TMP71:%.*]] = mul i32 [[TMP0]], [[TMP0]]
+; CHECK-NEXT: [[TMP72:%.*]] = mul i32 [[TMP71]], [[TMP71]]
+; CHECK-NEXT: [[TMP73:%.*]] = mul i32 [[TMP72]], [[TMP72]]
+; CHECK-NEXT: [[TMP74:%.*]] = mul i32 [[TMP73]], [[TMP73]]
+; CHECK-NEXT: [[TMP75:%.*]] = mul i32 [[TMP74]], [[TMP74]]
+; CHECK-NEXT: [[TMP76:%.*]] = mul i32 [[TMP70]], [[TMP75]]
+; CHECK-NEXT: [[TMP77:%.*]] = mul i32 [[TMP76]], [[TMP63]]
+; CHECK-NEXT: [[TMP78:%.*]] = mul i32 [[TMP77]], [[TMP51]]
+; CHECK-NEXT: [[TMP79:%.*]] = mul i32 [[TMP78]], [[TMP40]]
+; CHECK-NEXT: [[TMP80:%.*]] = mul i32 [[TMP79]], [[TMP30]]
+; CHECK-NEXT: [[TMP81:%.*]] = mul i32 [[TMP80]], [[TMP21]]
+; CHECK-NEXT: [[TMP82:%.*]] = mul i32 [[TMP81]], [[TMP13]]
+; CHECK-NEXT: [[TMP83:%.*]] = mul i32 [[TMP82]], [[TMP6]]
+; CHECK-NEXT: [[TMP84:%.*]] = mul i32 [[TMP83]], [[TMP5]]
+; CHECK-NEXT: [[TMP85:%.*]] = mul i32 [[TMP0]], [[TMP0]]
+; CHECK-NEXT: [[TMP86:%.*]] = mul i32 [[TMP85]], [[TMP85]]
+; CHECK-NEXT: [[TMP87:%.*]] = mul i32 [[TMP86]], [[TMP86]]
+; CHECK-NEXT: [[TMP88:%.*]] = mul i32 [[TMP87]], [[TMP87]]
+; CHECK-NEXT: [[TMP89:%.*]] = mul i32 [[TMP88]], [[TMP88]]
+; CHECK-NEXT: [[TMP90:%.*]] = mul i32 [[TMP84]], [[TMP89]]
+; CHECK-NEXT: [[TMP91:%.*]] = mul i32 [[TMP90]], [[TMP76]]
+; CHECK-NEXT: [[TMP92:%.*]] = mul i32 [[TMP91]], [[TMP63]]
+; CHECK-NEXT: [[TMP93:%.*]] = mul i32 [[TMP92]], [[TMP51]]
+; CHECK-NEXT: [[TMP94:%.*]] = mul i32 [[TMP93]], [[TMP40]]
+; CHECK-NEXT: [[TMP95:%.*]] = mul i32 [[TMP94]], [[TMP30]]
+; CHECK-NEXT: [[TMP96:%.*]] = mul i32 [[TMP95]], [[TMP21]]
+; CHECK-NEXT: [[TMP97:%.*]] = mul i32 [[TMP96]], [[TMP13]]
+; CHECK-NEXT: [[TMP98:%.*]] = mul i32 [[TMP97]], [[TMP6]]
+; CHECK-NEXT: [[TMP99:%.*]] = mul i32 [[TMP98]], [[TMP5]]
+; CHECK-NEXT: [[TMP100:%.*]] = mul i32 [[TMP0]], [[TMP0]]
+; CHECK-NEXT: [[TMP101:%.*]] = mul i32 [[TMP100]], [[TMP100]]
+; CHECK-NEXT: [[TMP102:%.*]] = mul i32 [[TMP101]], [[TMP101]]
+; CHECK-NEXT: [[TMP103:%.*]] = mul i32 [[TMP102]], [[TMP102]]
+; CHECK-NEXT: [[TMP104:%.*]] = mul i32 [[TMP103]], [[TMP103]]
+; CHECK-NEXT: [[TMP105:%.*]] = mul i32 [[TMP99]], [[TMP104]]
+; CHECK-NEXT: [[TMP106:%.*]] = mul i32 [[TMP105]], [[TMP90]]
+; CHECK-NEXT: [[TMP107:%.*]] = mul i32 [[TMP106]], [[TMP76]]
+; CHECK-NEXT: [[TMP108:%.*]] = mul i32 [[TMP107]], [[TMP63]]
+; CHECK-NEXT: [[TMP109:%.*]] = mul i32 [[TMP108]], [[TMP51]]
+; CHECK-NEXT: [[TMP110:%.*]] = mul i32 [[TMP109]], [[TMP40]]
+; CHECK-NEXT: [[TMP111:%.*]] = mul i32 [[TMP110]], [[TMP30]]
+; CHECK-NEXT: [[TMP112:%.*]] = mul i32 [[TMP111]], [[TMP21]]
+; CHECK-NEXT: [[TMP113:%.*]] = mul i32 [[TMP112]], [[TMP13]]
+; CHECK-NEXT: [[TMP114:%.*]] = mul i32 [[TMP113]], [[TMP6]]
+; CHECK-NEXT: [[TMP115:%.*]] = mul i32 [[TMP114]], [[TMP5]]
+; CHECK-NEXT: [[TMP116:%.*]] = mul i32 [[TMP0]], [[TMP0]]
+; CHECK-NEXT: [[TMP117:%.*]] = mul i32 [[TMP116]], [[TMP116]]
+; CHECK-NEXT: [[TMP118:%.*]] = mul i32 [[TMP117]], [[TMP117]]
+; CHECK-NEXT: [[TMP119:%.*]] = mul i32 [[TMP118]], [[TMP118]]
+; CHECK-NEXT: [[TMP120:%.*]] = mul i32 [[TMP119]], [[TMP119]]
+; CHECK-NEXT: [[TMP121:%.*]] = mul i32 [[TMP115]], [[TMP120]]
+; CHECK-NEXT: [[TMP122:%.*]] = mul i32 [[TMP121]], [[TMP105]]
+; CHECK-NEXT: [[TMP123:%.*]] = mul i32 [[TMP122]], [[TMP90]]
+; CHECK-NEXT: [[TMP124:%.*]] = mul i32 [[TMP123]], [[TMP76]]
+; CHECK-NEXT: [[TMP125:%.*]] = mul i32 [[TMP124]], [[TMP63]]
+; CHECK-NEXT: [[TMP126:%.*]] = mul i32 [[TMP125]], [[TMP51]]
+; CHECK-NEXT: [[TMP127:%.*]] = mul i32 [[TMP126]], [[TMP40]]
+; CHECK-NEXT: [[TMP128:%.*]] = mul i32 [[TMP127]], [[TMP30]]
+; CHECK-NEXT: [[TMP129:%.*]] = mul i32 [[TMP128]], [[TMP21]]
+; CHECK-NEXT: [[TMP130:%.*]] = mul i32 [[TMP129]], [[TMP13]]
+; CHECK-NEXT: [[TMP131:%.*]] = mul i32 [[TMP130]], [[TMP6]]
+; CHECK-NEXT: [[TMP132:%.*]] = mul i32 [[TMP131]], [[TMP5]]
+; CHECK-NEXT: [[TMP133:%.*]] = mul i32 [[TMP0]], [[TMP0]]
+; CHECK-NEXT: [[TMP134:%.*]] = mul i32 [[TMP133]], [[TMP133]]
+; CHECK-NEXT: [[TMP135:%.*]] = mul i32 [[TMP134]], [[TMP134]]
+; CHECK-NEXT: [[TMP136:%.*]] = mul i32 [[TMP135]], [[TMP135]]
+; CHECK-NEXT: [[TMP137:%.*]] = mul i32 [[TMP136]], [[TMP136]]
+; CHECK-NEXT: [[TMP138:%.*]] = mul i32 [[TMP132]], [[TMP137]]
+; CHECK-NEXT: [[TMP139:%.*]] = add i32 [[TMP138]], -1
+; CHECK-NEXT: [[TMP140:%.*]] = sub i32 [[TMP139]], [[LSR_IV_NEXT]]
+; CHECK-NEXT: ret i32 [[TMP140]]
+;
entry:
br label %loop
@@ -216,20 +365,28 @@ exit: ; preds = %loop
; Show that the transformation works even if the calculation involves
diff erent
; values inside.
define i32 @test_06(i32 %a, i32 %c) {
-; CHECK-LABEL: @test_06
-; CHECK: entry:
-; CHECK-NEXT: br label %loop
-; CHECK: loop:
-; CHECK-NEXT: [[IV:[^ ]+]] = phi i32 [ [[IV_INC:[^ ]+]], %loop ], [ 0, %entry ]
-; CHECK-NEXT: [[IV_INC]] = add nsw i32 [[IV]], -1
-; CHECK-NEXT: [[EXITCOND:[^ ]+]] = icmp eq i32 [[IV_INC]], -80
-; CHECK-NEXT: br i1 [[EXITCOND]], label %exit, label %loop
-; CHECK: exit:
-; CHECK: [[B:[^ ]+]] = add i32 %a, 1
-; CHECK-NEXT: [[B2:[^ ]+]] = mul i32 [[B]], [[B]]
-; CHECK-NEXT: [[B4:[^ ]+]] = mul i32 [[B2]], [[B2]]
-; CHECK-NEXT: [[B8:[^ ]+]] = mul i32 [[B4]], [[B4]]
-; CHECK-NEXT: [[B16:[^ ]+]] = mul i32 [[B8]], [[B8]]
+; CHECK-LABEL: define i32 @test_06(
+; CHECK-SAME: i32 [[A:%.*]], i32 [[C:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], %[[LOOP]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT: [[LSR_IV_NEXT]] = add nsw i32 [[LSR_IV]], -1
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[LSR_IV_NEXT]], -80
+; CHECK-NEXT: br i1 [[EXITCOND]], label %[[EXIT:.*]], label %[[LOOP]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: [[TMP0:%.*]] = mul i32 [[C]], [[C]]
+; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[C]], [[TMP0]]
+; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[A]], 1
+; CHECK-NEXT: [[TMP3:%.*]] = mul i32 [[TMP2]], [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = mul i32 [[TMP3]], [[TMP3]]
+; CHECK-NEXT: [[TMP5:%.*]] = mul i32 [[TMP4]], [[TMP4]]
+; CHECK-NEXT: [[TMP6:%.*]] = mul i32 [[TMP5]], [[TMP5]]
+; CHECK-NEXT: [[TMP7:%.*]] = mul i32 [[TMP1]], [[TMP6]]
+; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP7]], -1
+; CHECK-NEXT: [[TMP9:%.*]] = sub i32 [[TMP8]], [[LSR_IV_NEXT]]
+; CHECK-NEXT: ret i32 [[TMP9]]
+;
entry:
br label %loop
diff --git a/llvm/test/Transforms/LoopStrengthReduce/pr25541.ll b/llvm/test/Transforms/LoopStrengthReduce/pr25541.ll
index 85ed6f56310f7..1995b8be179ae 100644
--- a/llvm/test/Transforms/LoopStrengthReduce/pr25541.ll
+++ b/llvm/test/Transforms/LoopStrengthReduce/pr25541.ll
@@ -1,15 +1,46 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt < %s -loop-reduce -S | FileCheck %s
target datalayout = "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-pc-windows-msvc"
+; Check that we do not segfault by moving an iterator past the end of a basic
+; block.
+
define void @f() personality ptr @__CxxFrameHandler3 {
+; CHECK-LABEL: define void @f() personality ptr @__CxxFrameHandler3 {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: br label %[[FOR_COND_I:.*]]
+; CHECK: [[FOR_COND_I]]:
+; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], %[[FOR_INC_I:.*]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT: [[LSR_IV_LCSSA1:%.*]] = inttoptr i64 [[LSR_IV]] to ptr
+; CHECK-NEXT: invoke void @g()
+; CHECK-NEXT: to label %[[FOR_INC_I]] unwind label %[[CATCH_DISPATCH_I:.*]]
+; CHECK: [[CATCH_DISPATCH_I]]:
+; CHECK-NEXT: [[CS:%.*]] = catchswitch within none [label %[[FOR_COND_1_PREHEADER_I:.*]]] unwind to caller
+; CHECK: [[FOR_COND_1_PREHEADER_I]]:
+; CHECK-NEXT: [[TMP0:%.*]] = catchpad within [[CS]] [ptr null, i32 64, ptr null]
+; CHECK-NEXT: [[CMP_I:%.*]] = icmp eq ptr [[LSR_IV_LCSSA1]], null
+; CHECK-NEXT: br label %[[FOR_COND_1_I:.*]]
+; CHECK: [[FOR_COND_1_I]]:
+; CHECK-NEXT: br i1 [[CMP_I]], label %[[FOR_END_I:.*]], label %[[FOR_BODY_I:.*]]
+; CHECK: [[FOR_BODY_I]]:
+; CHECK-NEXT: call void @g()
+; CHECK-NEXT: br label %[[FOR_COND_1_I]]
+; CHECK: [[FOR_INC_I]]:
+; CHECK-NEXT: [[LSR_IV_NEXT]] = add i64 [[LSR_IV]], -4
+; CHECK-NEXT: br label %[[FOR_COND_I]]
+; CHECK: [[FOR_END_I]]:
+; CHECK-NEXT: catchret from [[TMP0]] to label %[[LEAVE:.*]]
+; CHECK: [[LEAVE]]:
+; CHECK-NEXT: ret void
+;
entry:
br label %for.cond.i
for.cond.i: ; preds = %for.inc.i, %entry
%_First.addr.0.i = phi ptr [ null, %entry ], [ %incdec.ptr.i, %for.inc.i ]
invoke void @g()
- to label %for.inc.i unwind label %catch.dispatch.i
+ to label %for.inc.i unwind label %catch.dispatch.i
catch.dispatch.i: ; preds = %for.cond.i
%cs = catchswitch within none [label %for.cond.1.preheader.i] unwind to caller
@@ -37,11 +68,6 @@ leave: ; preds = %for.end.i
ret void
}
-; CHECK-LABEL: define void @f(
-; CHECK: %[[PHI:.*]] = phi i64 [ %[[IV_NEXT:.*]], {{.*}} ], [ 0, {{.*}} ]
-; CHECK: %[[ITOP:.*]] = inttoptr i64 %[[PHI]] to ptr
-; CHECK: %[[CMP:.*]] = icmp eq ptr %[[ITOP]], null
-; CHECK: %[[IV_NEXT]] = add i64 %[[PHI]], -4
declare void @g()
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