[llvm] [WIP] AMDGPU: VGPR bank conflict avoidance hints (PR #192140)

[Shilei Tian via llvm-commits]

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@@ -274,6 +274,10 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
     return RC->TSFlags & SIRCFlags::HasSGPR;
   }
 
+  /// Returns true if MI is a 3-operand VALU instruction that may cause
+  /// bank conflicts if operands are from the same bank.
+  bool is3OperandVALU(const MachineInstr &MI) const;
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shiltian wrote:

Also, this is to check if it is a three VGPR operand VALU, not just three operand.

https://github.com/llvm/llvm-project/pull/192140