[llvm] [AArch64] Optimize lowering of i1 vector reduction (PR #187912)

[Cheng Lingfei via llvm-commits]

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@@ -147,9 +147,11 @@ define i1 @combine_setcc_eq_vecreduce_and_v16i1(<16 x i8> %a) {
 ; CHECK-LABEL: combine_setcc_eq_vecreduce_and_v16i1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmeq v0.16b, v0.16b, #0
-; CHECK-NEXT:    uminv b0, v0.16b
-; CHECK-NEXT:    fmov w8, s0
-; CHECK-NEXT:    and w0, w8, #0x1
+; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
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clingfei wrote:

Sorry for the late reply, I was busy with my paper these days :).

It does work, and I have updated for it.

https://github.com/llvm/llvm-project/pull/187912