[llvm] [NVPTX] Scalarize contract FMUL v2f32 to enable FMA fusion (PR #192815)

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git-clang-format --diff origin/main HEAD --extensions cpp,h -- llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp llvm/lib/Target/NVPTX/NVPTXISelLowering.h --diff_from_common_commit
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``````````diff
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
index 537508532..b403524da 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
@@ -6133,7 +6133,7 @@ static bool isNonCoalescableBuildVector(const SDValue &BV) {
 /// Return true if FMUL v2f32 node \p N may be scalarized to fold each lane's
 /// product into a scalar FMA.
 bool NVPTXTargetLowering::MayFoldFMULIntoFMA(SDNode *N, MachineFunction &MF,
-                                              CodeGenOptLevel OptLevel) const {
+                                             CodeGenOptLevel OptLevel) const {
   if (N->getOpcode() != ISD::FMUL || N->getValueType(0) != MVT::v2f32)
     return false;
   const bool GlobalFMA = allowFMA(MF, OptLevel);
@@ -6216,9 +6216,10 @@ SDValue NVPTXTargetLowering::PerformScalarizeV2F32Op(
 }
 
 /// Target-specific dag combine xforms for ISD::FADD.
-SDValue NVPTXTargetLowering::PerformFADDCombine(
-    SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
-    CodeGenOptLevel OptLevel) const {
+SDValue
+NVPTXTargetLowering::PerformFADDCombine(SDNode *N,
+                                        TargetLowering::DAGCombinerInfo &DCI,
+                                        CodeGenOptLevel OptLevel) const {
   if (SDValue Result = PerformScalarizeV2F32Op(N, DCI, OptLevel))
     return Result;
 

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https://github.com/llvm/llvm-project/pull/192815