[llvm] [RISCV][GlobalISel] Call `tryEmitMemcpyInline` for G_MEMCPY_INLINE (PR #192671)
Gábor Spaits via llvm-commits
llvm-commits at lists.llvm.org
Sat Apr 18 03:22:48 PDT 2026
https://github.com/spaits updated https://github.com/llvm/llvm-project/pull/192671
>From bb70b0b66c396a4b40ba96aaa87349c301728386 Mon Sep 17 00:00:00 2001
From: Gabor Spaits <gaborspaits1 at gmail.com>
Date: Fri, 17 Apr 2026 16:35:00 +0200
Subject: [PATCH 1/3] [RISCV][GlobalISel] Call `tryEmitMemcpyInline` for
G_MEMCPY_INLINE
Before this, MIR that contained G_MEMCPY_INLINE has failed in the
lagalization stage.
---
.../RISCV/GISel/RISCVPreLegalizerCombiner.cpp | 14 +++++
llvm/lib/Target/RISCV/RISCVCombine.td | 1 +
.../prelegalizer-combiner/inline-memcpy.mir | 63 +++++++++++++++++++
3 files changed, 78 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/prelegalizer-combiner/inline-memcpy.mir
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVPreLegalizerCombiner.cpp b/llvm/lib/Target/RISCV/GISel/RISCVPreLegalizerCombiner.cpp
index f652f74c8bdc7..b1ae7f0e3caeb 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVPreLegalizerCombiner.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVPreLegalizerCombiner.cpp
@@ -55,6 +55,7 @@ class RISCVPreLegalizerCombinerImpl : public Combiner {
static const char *getName() { return "RISCV00PreLegalizerCombiner"; }
bool tryCombineAll(MachineInstr &I) const override;
+ bool tryCombineAllImpl(MachineInstr &I) const;
private:
#define GET_GICOMBINER_CLASS_MEMBERS
@@ -154,6 +155,19 @@ bool RISCVPreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
return Impl.combineMachineInstrs();
}
+bool RISCVPreLegalizerCombinerImpl::tryCombineAll(MachineInstr &MI) const {
+ if (tryCombineAllImpl(MI))
+ return true;
+
+ unsigned Opc = MI.getOpcode();
+ switch (Opc) {
+ case TargetOpcode::G_MEMCPY_INLINE:
+ return Helper.tryEmitMemcpyInline(MI);
+ }
+
+ return false;
+}
+
char RISCVPreLegalizerCombiner::ID = 0;
INITIALIZE_PASS_BEGIN(RISCVPreLegalizerCombiner, DEBUG_TYPE,
"Combine RISC-V machine instrs before legalization", false,
diff --git a/llvm/lib/Target/RISCV/RISCVCombine.td b/llvm/lib/Target/RISCV/RISCVCombine.td
index a06b60d8cce07..1083558e8c163 100644
--- a/llvm/lib/Target/RISCV/RISCVCombine.td
+++ b/llvm/lib/Target/RISCV/RISCVCombine.td
@@ -13,6 +13,7 @@ include "llvm/Target/GlobalISel/Combine.td"
def RISCVPreLegalizerCombiner: GICombiner<
"RISCVPreLegalizerCombinerImpl", [all_combines]> {
+ let CombineAllMethodName = "tryCombineAllImpl";
}
def RISCVO0PreLegalizerCombiner: GICombiner<
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/prelegalizer-combiner/inline-memcpy.mir b/llvm/test/CodeGen/RISCV/GlobalISel/prelegalizer-combiner/inline-memcpy.mir
new file mode 100644
index 0000000000000..66575c71a9f7b
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/prelegalizer-combiner/inline-memcpy.mir
@@ -0,0 +1,63 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -O0 -mtriple=riscv32 -run-pass=riscv-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=RISCV32
+# RUN: llc -O0 -mtriple=riscv64 -run-pass=riscv-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=RISCV64
+
+--- |
+ declare void @llvm.memcpy.inline.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64 immarg, i1 immarg) #0
+
+ define void @test_memcpy_inline(ptr nocapture %dst, ptr nocapture readonly %src) local_unnamed_addr {
+ entry:
+ %0 = bitcast ptr %dst to ptr
+ %1 = bitcast ptr %src to ptr
+ tail call void @llvm.memcpy.inline.p0.p0.i64(ptr align 4 %0, ptr align 4 %1, i64 2, i1 false)
+ ret void
+ }
+
+ attributes #0 = { argmemonly nofree nounwind willreturn }
+...
+
+---
+name: test_memcpy_inline
+alignment: 4
+liveins:
+ - { reg: '$x10', virtual-reg: '' }
+ - { reg: '$x11', virtual-reg: '' }
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11
+
+ ; RISCV32-LABEL: name: test_memcpy_inline
+ ; RISCV32: liveins: $x10, $x11
+ ; RISCV32-NEXT: {{ $}}
+ ; RISCV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RISCV32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11
+ ; RISCV32-NEXT: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[COPY1]](p0) :: (load (s8) from %ir.1, align 4)
+ ; RISCV32-NEXT: G_STORE [[LOAD]](s8), [[COPY]](p0) :: (store (s8) into %ir.0, align 4)
+ ; RISCV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; RISCV32-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](s32)
+ ; RISCV32-NEXT: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[PTR_ADD]](p0) :: (load (s8) from %ir.1 + 1, basealign 4)
+ ; RISCV32-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s32)
+ ; RISCV32-NEXT: G_STORE [[LOAD1]](s8), [[PTR_ADD1]](p0) :: (store (s8) into %ir.0 + 1, basealign 4)
+ ; RISCV32-NEXT: PseudoRET
+ ;
+ ; RISCV64-LABEL: name: test_memcpy_inline
+ ; RISCV64: liveins: $x10, $x11
+ ; RISCV64-NEXT: {{ $}}
+ ; RISCV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RISCV64-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11
+ ; RISCV64-NEXT: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[COPY1]](p0) :: (load (s8) from %ir.1, align 4)
+ ; RISCV64-NEXT: G_STORE [[LOAD]](s8), [[COPY]](p0) :: (store (s8) into %ir.0, align 4)
+ ; RISCV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; RISCV64-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](s64)
+ ; RISCV64-NEXT: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[PTR_ADD]](p0) :: (load (s8) from %ir.1 + 1, basealign 4)
+ ; RISCV64-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
+ ; RISCV64-NEXT: G_STORE [[LOAD1]](s8), [[PTR_ADD1]](p0) :: (store (s8) into %ir.0 + 1, basealign 4)
+ ; RISCV64-NEXT: PseudoRET
+ %0:_(p0) = COPY $x10
+ %1:_(p0) = COPY $x11
+ %2:_(s64) = G_CONSTANT i64 2
+ %3:_(s32) = G_TRUNC %2(s64)
+ G_MEMCPY_INLINE %0(p0), %1(p0), %3(s32) :: (store (s8) into %ir.0, align 4), (load (s8) from %ir.1, align 4)
+ PseudoRET
+
+...
>From 28452dbbcc8338952b5ac0eb7fcff19a6702213e Mon Sep 17 00:00:00 2001
From: Gabor Spaits <gaborspaits1 at gmail.com>
Date: Sat, 18 Apr 2026 12:13:47 +0200
Subject: [PATCH 2/3] Revert "[RISCV][GlobalISel] Call `tryEmitMemcpyInline`
for G_MEMCPY_INLINE"
This reverts commit bb70b0b66c396a4b40ba96aaa87349c301728386.
---
.../RISCV/GISel/RISCVPreLegalizerCombiner.cpp | 14 -----
llvm/lib/Target/RISCV/RISCVCombine.td | 1 -
.../prelegalizer-combiner/inline-memcpy.mir | 63 -------------------
3 files changed, 78 deletions(-)
delete mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/prelegalizer-combiner/inline-memcpy.mir
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVPreLegalizerCombiner.cpp b/llvm/lib/Target/RISCV/GISel/RISCVPreLegalizerCombiner.cpp
index b1ae7f0e3caeb..f652f74c8bdc7 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVPreLegalizerCombiner.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVPreLegalizerCombiner.cpp
@@ -55,7 +55,6 @@ class RISCVPreLegalizerCombinerImpl : public Combiner {
static const char *getName() { return "RISCV00PreLegalizerCombiner"; }
bool tryCombineAll(MachineInstr &I) const override;
- bool tryCombineAllImpl(MachineInstr &I) const;
private:
#define GET_GICOMBINER_CLASS_MEMBERS
@@ -155,19 +154,6 @@ bool RISCVPreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
return Impl.combineMachineInstrs();
}
-bool RISCVPreLegalizerCombinerImpl::tryCombineAll(MachineInstr &MI) const {
- if (tryCombineAllImpl(MI))
- return true;
-
- unsigned Opc = MI.getOpcode();
- switch (Opc) {
- case TargetOpcode::G_MEMCPY_INLINE:
- return Helper.tryEmitMemcpyInline(MI);
- }
-
- return false;
-}
-
char RISCVPreLegalizerCombiner::ID = 0;
INITIALIZE_PASS_BEGIN(RISCVPreLegalizerCombiner, DEBUG_TYPE,
"Combine RISC-V machine instrs before legalization", false,
diff --git a/llvm/lib/Target/RISCV/RISCVCombine.td b/llvm/lib/Target/RISCV/RISCVCombine.td
index 1083558e8c163..a06b60d8cce07 100644
--- a/llvm/lib/Target/RISCV/RISCVCombine.td
+++ b/llvm/lib/Target/RISCV/RISCVCombine.td
@@ -13,7 +13,6 @@ include "llvm/Target/GlobalISel/Combine.td"
def RISCVPreLegalizerCombiner: GICombiner<
"RISCVPreLegalizerCombinerImpl", [all_combines]> {
- let CombineAllMethodName = "tryCombineAllImpl";
}
def RISCVO0PreLegalizerCombiner: GICombiner<
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/prelegalizer-combiner/inline-memcpy.mir b/llvm/test/CodeGen/RISCV/GlobalISel/prelegalizer-combiner/inline-memcpy.mir
deleted file mode 100644
index 66575c71a9f7b..0000000000000
--- a/llvm/test/CodeGen/RISCV/GlobalISel/prelegalizer-combiner/inline-memcpy.mir
+++ /dev/null
@@ -1,63 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -O0 -mtriple=riscv32 -run-pass=riscv-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=RISCV32
-# RUN: llc -O0 -mtriple=riscv64 -run-pass=riscv-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=RISCV64
-
---- |
- declare void @llvm.memcpy.inline.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64 immarg, i1 immarg) #0
-
- define void @test_memcpy_inline(ptr nocapture %dst, ptr nocapture readonly %src) local_unnamed_addr {
- entry:
- %0 = bitcast ptr %dst to ptr
- %1 = bitcast ptr %src to ptr
- tail call void @llvm.memcpy.inline.p0.p0.i64(ptr align 4 %0, ptr align 4 %1, i64 2, i1 false)
- ret void
- }
-
- attributes #0 = { argmemonly nofree nounwind willreturn }
-...
-
----
-name: test_memcpy_inline
-alignment: 4
-liveins:
- - { reg: '$x10', virtual-reg: '' }
- - { reg: '$x11', virtual-reg: '' }
-body: |
- bb.0.entry:
- liveins: $x10, $x11
-
- ; RISCV32-LABEL: name: test_memcpy_inline
- ; RISCV32: liveins: $x10, $x11
- ; RISCV32-NEXT: {{ $}}
- ; RISCV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
- ; RISCV32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11
- ; RISCV32-NEXT: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[COPY1]](p0) :: (load (s8) from %ir.1, align 4)
- ; RISCV32-NEXT: G_STORE [[LOAD]](s8), [[COPY]](p0) :: (store (s8) into %ir.0, align 4)
- ; RISCV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; RISCV32-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](s32)
- ; RISCV32-NEXT: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[PTR_ADD]](p0) :: (load (s8) from %ir.1 + 1, basealign 4)
- ; RISCV32-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s32)
- ; RISCV32-NEXT: G_STORE [[LOAD1]](s8), [[PTR_ADD1]](p0) :: (store (s8) into %ir.0 + 1, basealign 4)
- ; RISCV32-NEXT: PseudoRET
- ;
- ; RISCV64-LABEL: name: test_memcpy_inline
- ; RISCV64: liveins: $x10, $x11
- ; RISCV64-NEXT: {{ $}}
- ; RISCV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
- ; RISCV64-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11
- ; RISCV64-NEXT: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[COPY1]](p0) :: (load (s8) from %ir.1, align 4)
- ; RISCV64-NEXT: G_STORE [[LOAD]](s8), [[COPY]](p0) :: (store (s8) into %ir.0, align 4)
- ; RISCV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; RISCV64-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](s64)
- ; RISCV64-NEXT: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[PTR_ADD]](p0) :: (load (s8) from %ir.1 + 1, basealign 4)
- ; RISCV64-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
- ; RISCV64-NEXT: G_STORE [[LOAD1]](s8), [[PTR_ADD1]](p0) :: (store (s8) into %ir.0 + 1, basealign 4)
- ; RISCV64-NEXT: PseudoRET
- %0:_(p0) = COPY $x10
- %1:_(p0) = COPY $x11
- %2:_(s64) = G_CONSTANT i64 2
- %3:_(s32) = G_TRUNC %2(s64)
- G_MEMCPY_INLINE %0(p0), %1(p0), %3(s32) :: (store (s8) into %ir.0, align 4), (load (s8) from %ir.1, align 4)
- PseudoRET
-
-...
>From f4be01e78213d3b631bf31eecddf49799880635a Mon Sep 17 00:00:00 2001
From: Gabor Spaits <gaborspaits1 at gmail.com>
Date: Sat, 18 Apr 2026 12:21:52 +0200
Subject: [PATCH 3/3] Use lower call in legalizer instead
---
.../Target/RISCV/GISel/RISCVLegalizerInfo.cpp | 2 +
.../legalizer/legalize-memcpy-inline.mir | 62 +++++++++++++++++++
2 files changed, 64 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-memcpy-inline.mir
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index 7766a4540f2d4..52fa1cf9fa3cc 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -520,6 +520,8 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
getActionDefinitionsBuilder({G_MEMCPY, G_MEMMOVE, G_MEMSET}).libcall();
+ getActionDefinitionsBuilder(G_MEMCPY_INLINE).lower();
+
getActionDefinitionsBuilder({G_DYN_STACKALLOC, G_STACKSAVE, G_STACKRESTORE})
.lower();
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-memcpy-inline.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-memcpy-inline.mir
new file mode 100644
index 0000000000000..cc6e817409f94
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-memcpy-inline.mir
@@ -0,0 +1,62 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=riscv32 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=RISCV32
+# RUN: llc -mtriple=riscv64 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=RISCV64
+
+--- |
+ declare void @llvm.memcpy.inline.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64 immarg, i1 immarg) #0
+
+ define void @test_memcpy_inline(ptr nocapture %dst, ptr nocapture readonly %src) local_unnamed_addr {
+ entry:
+ %0 = bitcast ptr %dst to ptr
+ %1 = bitcast ptr %src to ptr
+ tail call void @llvm.memcpy.inline.p0.p0.i64(ptr align 4 %0, ptr align 4 %1, i64 2, i1 false)
+ ret void
+ }
+
+ attributes #0 = { argmemonly nofree nounwind willreturn }
+...
+
+---
+name: test_memcpy_inline
+alignment: 4
+liveins:
+ - { reg: '$x10', virtual-reg: '' }
+ - { reg: '$x11', virtual-reg: '' }
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11
+ ; RISCV32-LABEL: name: test_memcpy_inline
+ ; RISCV32: liveins: $x10, $x11
+ ; RISCV32-NEXT: {{ $}}
+ ; RISCV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RISCV32-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11
+ ; RISCV32-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY1]](p0) :: (load (s8) from %ir.1, align 4)
+ ; RISCV32-NEXT: G_STORE [[LOAD]](s16), [[COPY]](p0) :: (store (s8) into %ir.0, align 4)
+ ; RISCV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; RISCV32-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](s32)
+ ; RISCV32-NEXT: [[LOAD1:%[0-9]+]]:_(s16) = G_LOAD [[PTR_ADD]](p0) :: (load (s8) from %ir.1 + 1, basealign 4)
+ ; RISCV32-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s32)
+ ; RISCV32-NEXT: G_STORE [[LOAD1]](s16), [[PTR_ADD1]](p0) :: (store (s8) into %ir.0 + 1, basealign 4)
+ ; RISCV32-NEXT: PseudoRET
+ ;
+ ; RISCV64-LABEL: name: test_memcpy_inline
+ ; RISCV64: liveins: $x10, $x11
+ ; RISCV64-NEXT: {{ $}}
+ ; RISCV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
+ ; RISCV64-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11
+ ; RISCV64-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY1]](p0) :: (load (s8) from %ir.1, align 4)
+ ; RISCV64-NEXT: G_STORE [[LOAD]](s16), [[COPY]](p0) :: (store (s8) into %ir.0, align 4)
+ ; RISCV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; RISCV64-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY1]], [[C]](s64)
+ ; RISCV64-NEXT: [[LOAD1:%[0-9]+]]:_(s16) = G_LOAD [[PTR_ADD]](p0) :: (load (s8) from %ir.1 + 1, basealign 4)
+ ; RISCV64-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)
+ ; RISCV64-NEXT: G_STORE [[LOAD1]](s16), [[PTR_ADD1]](p0) :: (store (s8) into %ir.0 + 1, basealign 4)
+ ; RISCV64-NEXT: PseudoRET
+ %0:_(p0) = COPY $x10
+ %1:_(p0) = COPY $x11
+ %2:_(s64) = G_CONSTANT i64 2
+ %3:_(s32) = G_TRUNC %2(s64)
+ G_MEMCPY_INLINE %0(p0), %1(p0), %3(s32) :: (store (s8) into %ir.0, align 4), (load (s8) from %ir.1, align 4)
+ PseudoRET
+
+...
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