[llvm] [DAG] Precommit tests for computeKnownFPClass - ISD::EXTRACT_SUBVECTOR and ISD::INSERT_SUBVECTOR. (PR #190694)

[via llvm-commits]

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@@ -52,43 +52,115 @@ define <vscale x 2 x i1> @splat_constant_f64_isinf_false() {
   ret <vscale x 2 x i1> %res
 }
 
-define <4 x i1> @fneg_vec_not_negative(<4 x i32> %vecbits) nounwind {
-; CHECK-LABEL: fneg_vec_not_negative:
+define <vscale x 4 x i1> @extract_subvec_scalable(<vscale x 8 x float> %a0) {
+; CHECK-LABEL: extract_subvec_scalable:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
-; CHECK-NEXT:    vmclr.m v0
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT:    vfabs.v v8, v8
+; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
+; CHECK-NEXT:    vfclass.v v8, v8
+; CHECK-NEXT:    vand.vi v8, v8, 15
+; CHECK-NEXT:    vmsne.vi v0, v8, 0
 ; CHECK-NEXT:    ret
-  %masked = or <4 x i32> %vecbits, splat(i32 u0x80000000) ; set sign bits
-  %fvec = bitcast <4 x i32> %masked to <4 x float>
-  %neg = fneg <4 x float> %fvec
-  %res = call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> %neg, i32 60) ; any negative
-  ret <4 x i1> %res
+  %abs = call <vscale x 8 x float> @llvm.fabs.nxv8f32(<vscale x 8 x float> %a0)
+  %sub = call <vscale x 4 x float> @llvm.vector.extract.nxv4f32.nxv8f32(<vscale x 8 x float> %abs, i64 0)
+  %res = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f32(<vscale x 4 x float> %sub, i32 60)
+  ret <vscale x 4 x i1> %res
 }
 
-define <4 x i1> @fneg_vec_not_positive(<4 x i32> %vecbits) nounwind {
-; CHECK-LABEL: fneg_vec_not_positive:
+define <vscale x 4 x i1> @insert_subvec_scalable_both(<vscale x 4 x float> %base, <vscale x 2 x float> %sub) {
+; CHECK-LABEL: insert_subvec_scalable_both:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
-; CHECK-NEXT:    vmclr.m v0
+; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
+; CHECK-NEXT:    vfabs.v v8, v8
+; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
+; CHECK-NEXT:    vfabs.v v8, v10
+; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
+; CHECK-NEXT:    vfclass.v v8, v8
+; CHECK-NEXT:    vand.vi v8, v8, 15
+; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    ret
+  %absbase = call <vscale x 4 x float> @llvm.fabs.nxv4f32(<vscale x 4 x float> %base)
+  %abssub  = call <vscale x 2 x float> @llvm.fabs.nxv2f32(<vscale x 2 x float> %sub)
+  %ins = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float> %absbase, <vscale x 2 x float> %abssub, i64 0)
+  %res = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f32(<vscale x 4 x float> %ins, i32 60)
+  ret <vscale x 4 x i1> %res
+}
+
+define <2 x i1> @extract_subvec_mixed_to_pos(<4 x float> %a) {
+; CHECK-LABEL: extract_subvec_mixed_to_pos:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT:    vfabs.v v8, v8
+; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT:    vfclass.v v8, v8
+; CHECK-NEXT:    vand.vi v8, v8, 15
+; CHECK-NEXT:    vmsne.vi v0, v8, 0
 ; CHECK-NEXT:    ret
-  %masked = and <4 x i32> %vecbits, splat(i32 u0x7fffffff) ; clear sign bit
-  %fvec = bitcast <4 x i32> %masked to <4 x float>
-  %neg = fneg <4 x float> %fvec
-  %res = call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> %neg, i32 960) ; any positive
+  %abs = call <4 x float> @llvm.fabs.v4f32(<4 x float> %a)
+  %neg = fneg <4 x float> %abs
+  %mixed = shufflevector <4 x float> %abs, <4 x float> %neg, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
+  %sub = call <2 x float> @llvm.vector.extract.v2f32.v4f32(<4 x float> %mixed, i64 0)
+  %res = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> %sub, i32 60)
+  ret <2 x i1> %res
+}
+
+define <2 x i1> @extract_subvec_straddle(<4 x float> %a) {
----------------
Xylecrack wrote:

In this case the lanes are interleaved ([+, -, +, -]), so the extract produces mixed FP classes.

https://github.com/llvm/llvm-project/pull/190694