[llvm] [X86][APX] Update live internals of physical registers too (PR #192595)
Phoebe Wang via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 17 23:00:42 PDT 2026
https://github.com/phoebewang updated https://github.com/llvm/llvm-project/pull/192595
>From c7a3852516c479c217a52eeb3bd872fb792886a1 Mon Sep 17 00:00:00 2001
From: Phoebe Wang <phoebe.wang at intel.com>
Date: Fri, 17 Apr 2026 13:50:07 +0800
Subject: [PATCH 1/2] [X86][APX] Update live internals of physical registers
too
---
llvm/lib/CodeGen/InlineSpiller.cpp | 2 +
llvm/lib/CodeGen/LiveRangeEdit.cpp | 2 +
llvm/test/CodeGen/X86/apx/foldmemory.mir | 190 +++++++++++++++++++++++
3 files changed, 194 insertions(+)
create mode 100644 llvm/test/CodeGen/X86/apx/foldmemory.mir
diff --git a/llvm/lib/CodeGen/InlineSpiller.cpp b/llvm/lib/CodeGen/InlineSpiller.cpp
index ea062282b97b2..5f4dd2f04a610 100644
--- a/llvm/lib/CodeGen/InlineSpiller.cpp
+++ b/llvm/lib/CodeGen/InlineSpiller.cpp
@@ -1110,6 +1110,8 @@ foldMemoryOperand(ArrayRef<std::pair<MachineInstr *, unsigned>> Ops,
if (R.isVirtual()) {
LiveInterval &LI = LIS.getInterval(R);
LIS.shrinkToUses(&LI);
+ } else {
+ LIS.removeAllRegUnitsForPhysReg(R.asMCReg());
}
}
diff --git a/llvm/lib/CodeGen/LiveRangeEdit.cpp b/llvm/lib/CodeGen/LiveRangeEdit.cpp
index edff8c8600188..f986fcde205d0 100644
--- a/llvm/lib/CodeGen/LiveRangeEdit.cpp
+++ b/llvm/lib/CodeGen/LiveRangeEdit.cpp
@@ -174,6 +174,8 @@ bool LiveRangeEdit::foldAsLoad(LiveInterval *LI,
if (R.isVirtual()) {
LiveInterval &SrcLI = LIS.getInterval(R);
LIS.shrinkToUses(&SrcLI);
+ } else {
+ LIS.removeAllRegUnitsForPhysReg(R.asMCReg());
}
}
return true;
diff --git a/llvm/test/CodeGen/X86/apx/foldmemory.mir b/llvm/test/CodeGen/X86/apx/foldmemory.mir
new file mode 100644
index 0000000000000..b3f665c741b98
--- /dev/null
+++ b/llvm/test/CodeGen/X86/apx/foldmemory.mir
@@ -0,0 +1,190 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=x86_64-- -run-pass=greedy %s -o - | FileCheck %s
+--- |
+ define fastcc void @fold_with_physical_reg(ptr %arg0, i64 %arg1, ptr %arg2, i1 %arg3) #0 {
+ entry:
+ br label %bb1
+
+ bb1: ; preds = %bb2, %entry
+ %alloc = alloca i8, i64 %arg1, align 16
+ br label %bb2
+
+ bb2: ; preds = %bb2, %bb1
+ %phi = phi i64 [ 0, %bb1 ], [ %arg1, %bb2 ]
+ %call = call fastcc ptr null(ptr %arg0, ptr null, ptr null, ptr null, float 0.000000e+00)
+ %gep = getelementptr ptr, ptr %alloc, i64 %phi
+ store ptr null, ptr %gep, align 8
+ store ptr null, ptr %arg2, align 8
+ br i1 %arg3, label %bb1, label %bb2
+ }
+
+ attributes #0 = { nounwind "target-features"="+ndd" }
+...
+---
+name: fold_with_physical_reg
+alignment: 1
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+hasWinCFI: false
+noPhis: true
+isSSA: false
+noVRegs: false
+hasFakeUses: false
+callsEHReturn: false
+callsUnwindInit: false
+hasEHContTarget: false
+hasEHScopes: false
+hasEHFunclets: false
+isOutlined: false
+debugInstrRef: true
+failsVerification: false
+tracksDebugUserValues: false
+registers:
+ - { id: 0, class: gr64, preferred-register: '', flags: [ ] }
+ - { id: 1, class: gr64_nosp, preferred-register: '', flags: [ ] }
+ - { id: 2, class: gr64, preferred-register: '', flags: [ ] }
+ - { id: 3, class: gr64, preferred-register: '', flags: [ ] }
+ - { id: 4, class: gr64, preferred-register: '', flags: [ ] }
+ - { id: 5, class: gr32, preferred-register: '', flags: [ ] }
+ - { id: 6, class: gr8, preferred-register: '', flags: [ ] }
+ - { id: 7, class: gr64_with_sub_8bit, preferred-register: '', flags: [ ] }
+ - { id: 8, class: gr64, preferred-register: '', flags: [ ] }
+ - { id: 9, class: gr64, preferred-register: '', flags: [ ] }
+ - { id: 10, class: gr64, preferred-register: '', flags: [ ] }
+ - { id: 11, class: gr32, preferred-register: '', flags: [ ] }
+ - { id: 12, class: gr32, preferred-register: '', flags: [ ] }
+ - { id: 13, class: gr64_with_sub_8bit, preferred-register: '', flags: [ ] }
+ - { id: 14, class: fr32, preferred-register: '', flags: [ ] }
+ - { id: 15, class: gr64, preferred-register: '', flags: [ ] }
+ - { id: 16, class: gr64_nosp, preferred-register: '', flags: [ ] }
+liveins:
+ - { reg: '$rdi', virtual-reg: '%2' }
+ - { reg: '$rsi', virtual-reg: '%3' }
+ - { reg: '$rdx', virtual-reg: '%4' }
+ - { reg: '$ecx', virtual-reg: '%5' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: true
+ hasCalls: true
+ stackProtector: ''
+ functionContext: ''
+ maxCallFrameSize: 4294967295
+ cvBytesOfCalleeSavedRegisters: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ hasTailCall: false
+ isCalleeSavedInfoValid: false
+ localFrameSize: 0
+fixedStack: []
+stack:
+ - { id: 0, name: alloc, type: variable-sized, offset: 0, alignment: 1,
+ stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+entry_values: []
+callSites: []
+debugValueSubstitutions: []
+constants: []
+machineFunctionInfo:
+ amxProgModel: None
+body: |
+ ; CHECK-LABEL: name: fold_with_physical_reg
+ ; CHECK: bb.0.entry:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: liveins: $rdi, $rsi, $rdx, $ecx
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $ecx
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdx
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY $rsi
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gr64 = COPY $rdi
+ ; CHECK-NEXT: [[LEA64r:%[0-9]+]]:gr64 = LEA64r [[COPY2]], 1, $noreg, 15, $noreg
+ ; CHECK-NEXT: [[AND64ri32_ND:%[0-9]+]]:gr64 = AND64ri32_ND [[LEA64r]], -16, implicit-def dead $eflags
+ ; CHECK-NEXT: MOV64mr %stack.1, 1, $noreg, 0, $noreg, [[AND64ri32_ND]] :: (store (s64) into %stack.1)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1.bb1:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gr64 = COPY $rsp
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gr64 = SUB64rm [[COPY4]], %stack.1, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load (s64) from %stack.1)
+ ; CHECK-NEXT: MOV64mr %stack.2, 1, $noreg, 0, $noreg, [[COPY4]] :: (store (s64) into %stack.2)
+ ; CHECK-NEXT: $rsp = COPY [[COPY4]]
+ ; CHECK-NEXT: ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
+ ; CHECK-NEXT: undef [[MOV32r0_:%[0-9]+]].sub_32bit:gr64_nosp = MOV32r0 implicit-def dead $eflags
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.bb2:
+ ; CHECK-NEXT: successors: %bb.1(0x04000000), %bb.2(0x7c000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
+ ; CHECK-NEXT: $xmm0 = FsFLD0SS
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gr64 = COPY [[COPY3]]
+ ; CHECK-NEXT: $rdi = COPY [[COPY5]]
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:gr64 = COPY [[COPY2]]
+ ; CHECK-NEXT: dead $esi = MOV32r0 implicit-def dead $eflags, implicit-def $rsi
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:gr64 = COPY [[COPY1]]
+ ; CHECK-NEXT: dead $edx = MOV32r0 implicit-def dead $eflags, implicit-def $rdx
+ ; CHECK-NEXT: [[COPY8:%[0-9]+]]:gr32 = COPY [[COPY]]
+ ; CHECK-NEXT: dead $ecx = MOV32r0 implicit-def dead $eflags, implicit-def $rcx
+ ; CHECK-NEXT: undef [[MOV32r0_1:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = MOV32r0 implicit-def dead $eflags
+ ; CHECK-NEXT: CALL64r [[MOV32r0_1]], csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $rdx, implicit $rcx, implicit killed $xmm0, implicit-def $rsp, implicit-def $ssp, implicit-def dead $rax
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gr64 = COPY [[COPY5]]
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY [[COPY6]]
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY [[COPY7]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY [[COPY8]]
+ ; CHECK-NEXT: ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
+ ; CHECK-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm %stack.2, 1, $noreg, 0, $noreg :: (load (s64) from %stack.2)
+ ; CHECK-NEXT: MOV64mi32 [[MOV64rm]], 8, [[MOV32r0_]], 0, $noreg, 0 :: (store (s64) into %ir.gep)
+ ; CHECK-NEXT: MOV64mi32 [[COPY1]], 1, $noreg, 0, $noreg, 0 :: (store (s64) into %ir.arg2)
+ ; CHECK-NEXT: TEST8ri [[COPY]].sub_8bit, 1, implicit-def $eflags
+ ; CHECK-NEXT: [[MOV32r0_:%[0-9]+]]:gr64_nosp = COPY [[COPY2]]
+ ; CHECK-NEXT: JCC_1 %bb.1, 5, implicit $eflags
+ ; CHECK-NEXT: JMP_1 %bb.2
+ bb.0.entry:
+ successors: %bb.1(0x80000000)
+ liveins: $rdi, $rsi, $rdx, $ecx
+
+ %5:gr32 = COPY $ecx
+ %4:gr64 = COPY $rdx
+ %3:gr64 = COPY $rsi
+ %2:gr64 = COPY $rdi
+ %8:gr64 = LEA64r %3, 1, $noreg, 15, $noreg
+ %9:gr64 = AND64ri32_ND %8, -16, implicit-def dead $eflags
+ undef %7.sub_32bit:gr64_with_sub_8bit = MOV32r0 implicit-def dead $eflags
+
+ bb.1.bb1:
+ successors: %bb.2(0x80000000)
+
+ ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
+ %0:gr64 = SUB64rr_ND $rsp, %9, implicit-def dead $eflags
+ $rsp = COPY %0
+ ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
+ undef %16.sub_32bit:gr64_nosp = MOV32r0 implicit-def dead $eflags
+
+ bb.2.bb2:
+ successors: %bb.1(0x04000000), %bb.2(0x7c000000)
+
+ ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
+ $xmm0 = FsFLD0SS
+ $rdi = COPY %2
+ dead $esi = MOV32r0 implicit-def dead $eflags, implicit-def $rsi
+ dead $edx = MOV32r0 implicit-def dead $eflags, implicit-def $rdx
+ dead $ecx = MOV32r0 implicit-def dead $eflags, implicit-def $rcx
+ CALL64r %7, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $rdx, implicit $rcx, implicit killed $xmm0, implicit-def $rsp, implicit-def $ssp, implicit-def dead $rax
+ ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
+ MOV64mi32 %0, 8, %16, 0, $noreg, 0 :: (store (s64) into %ir.gep)
+ MOV64mi32 %4, 1, $noreg, 0, $noreg, 0 :: (store (s64) into %ir.arg2)
+ TEST8ri %5.sub_8bit, 1, implicit-def $eflags
+ %16:gr64_nosp = COPY %3
+ JCC_1 %bb.1, 5, implicit $eflags
+ JMP_1 %bb.2
+...
>From e38601b8685f210c6ec3ea83b8c578187b402b21 Mon Sep 17 00:00:00 2001
From: Phoebe Wang <phoebe.wang at intel.com>
Date: Sat, 18 Apr 2026 14:00:16 +0800
Subject: [PATCH 2/2] Address review comments
---
llvm/lib/CodeGen/InlineSpiller.cpp | 2 +-
llvm/lib/CodeGen/LiveRangeEdit.cpp | 2 +-
llvm/test/CodeGen/X86/apx/foldmemory.mir | 102 +++--------------------
3 files changed, 14 insertions(+), 92 deletions(-)
diff --git a/llvm/lib/CodeGen/InlineSpiller.cpp b/llvm/lib/CodeGen/InlineSpiller.cpp
index 5f4dd2f04a610..a9341a3c3253c 100644
--- a/llvm/lib/CodeGen/InlineSpiller.cpp
+++ b/llvm/lib/CodeGen/InlineSpiller.cpp
@@ -1111,7 +1111,7 @@ foldMemoryOperand(ArrayRef<std::pair<MachineInstr *, unsigned>> Ops,
LiveInterval &LI = LIS.getInterval(R);
LIS.shrinkToUses(&LI);
} else {
- LIS.removeAllRegUnitsForPhysReg(R.asMCReg());
+ assert(MRI.isReserved(R) && "Unexpected PhysReg in source operand!");
}
}
diff --git a/llvm/lib/CodeGen/LiveRangeEdit.cpp b/llvm/lib/CodeGen/LiveRangeEdit.cpp
index f986fcde205d0..10b23819c1de0 100644
--- a/llvm/lib/CodeGen/LiveRangeEdit.cpp
+++ b/llvm/lib/CodeGen/LiveRangeEdit.cpp
@@ -175,7 +175,7 @@ bool LiveRangeEdit::foldAsLoad(LiveInterval *LI,
LiveInterval &SrcLI = LIS.getInterval(R);
LIS.shrinkToUses(&SrcLI);
} else {
- LIS.removeAllRegUnitsForPhysReg(R.asMCReg());
+ assert(MRI.isReserved(R) && "Unexpected PhysReg in source operand!");
}
}
return true;
diff --git a/llvm/test/CodeGen/X86/apx/foldmemory.mir b/llvm/test/CodeGen/X86/apx/foldmemory.mir
index b3f665c741b98..3cdaf613e9431 100644
--- a/llvm/test/CodeGen/X86/apx/foldmemory.mir
+++ b/llvm/test/CodeGen/X86/apx/foldmemory.mir
@@ -1,105 +1,27 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=x86_64-- -run-pass=greedy %s -o - | FileCheck %s
--- |
- define fastcc void @fold_with_physical_reg(ptr %arg0, i64 %arg1, ptr %arg2, i1 %arg3) #0 {
- entry:
- br label %bb1
-
- bb1: ; preds = %bb2, %entry
+ define fastcc void @fold_with_physical_reg(i64 %arg1) "target-features"="+ndd" {
%alloc = alloca i8, i64 %arg1, align 16
- br label %bb2
-
- bb2: ; preds = %bb2, %bb1
- %phi = phi i64 [ 0, %bb1 ], [ %arg1, %bb2 ]
- %call = call fastcc ptr null(ptr %arg0, ptr null, ptr null, ptr null, float 0.000000e+00)
- %gep = getelementptr ptr, ptr %alloc, i64 %phi
- store ptr null, ptr %gep, align 8
- store ptr null, ptr %arg2, align 8
- br i1 %arg3, label %bb1, label %bb2
+ ret void
}
-
- attributes #0 = { nounwind "target-features"="+ndd" }
...
---
name: fold_with_physical_reg
alignment: 1
-exposesReturnsTwice: false
-legalized: false
-regBankSelected: false
-selected: false
-failedISel: false
tracksRegLiveness: true
-hasWinCFI: false
noPhis: true
isSSA: false
-noVRegs: false
-hasFakeUses: false
-callsEHReturn: false
-callsUnwindInit: false
-hasEHContTarget: false
-hasEHScopes: false
-hasEHFunclets: false
-isOutlined: false
-debugInstrRef: true
-failsVerification: false
-tracksDebugUserValues: false
-registers:
- - { id: 0, class: gr64, preferred-register: '', flags: [ ] }
- - { id: 1, class: gr64_nosp, preferred-register: '', flags: [ ] }
- - { id: 2, class: gr64, preferred-register: '', flags: [ ] }
- - { id: 3, class: gr64, preferred-register: '', flags: [ ] }
- - { id: 4, class: gr64, preferred-register: '', flags: [ ] }
- - { id: 5, class: gr32, preferred-register: '', flags: [ ] }
- - { id: 6, class: gr8, preferred-register: '', flags: [ ] }
- - { id: 7, class: gr64_with_sub_8bit, preferred-register: '', flags: [ ] }
- - { id: 8, class: gr64, preferred-register: '', flags: [ ] }
- - { id: 9, class: gr64, preferred-register: '', flags: [ ] }
- - { id: 10, class: gr64, preferred-register: '', flags: [ ] }
- - { id: 11, class: gr32, preferred-register: '', flags: [ ] }
- - { id: 12, class: gr32, preferred-register: '', flags: [ ] }
- - { id: 13, class: gr64_with_sub_8bit, preferred-register: '', flags: [ ] }
- - { id: 14, class: fr32, preferred-register: '', flags: [ ] }
- - { id: 15, class: gr64, preferred-register: '', flags: [ ] }
- - { id: 16, class: gr64_nosp, preferred-register: '', flags: [ ] }
-liveins:
- - { reg: '$rdi', virtual-reg: '%2' }
- - { reg: '$rsi', virtual-reg: '%3' }
- - { reg: '$rdx', virtual-reg: '%4' }
- - { reg: '$ecx', virtual-reg: '%5' }
frameInfo:
- isFrameAddressTaken: false
- isReturnAddressTaken: false
- hasStackMap: false
- hasPatchPoint: false
- stackSize: 0
- offsetAdjustment: 0
- maxAlignment: 1
adjustsStack: true
hasCalls: true
- stackProtector: ''
- functionContext: ''
- maxCallFrameSize: 4294967295
- cvBytesOfCalleeSavedRegisters: 0
- hasOpaqueSPAdjustment: false
- hasVAStart: false
- hasMustTailInVarArgFunc: false
- hasTailCall: false
- isCalleeSavedInfoValid: false
- localFrameSize: 0
-fixedStack: []
stack:
- { id: 0, name: alloc, type: variable-sized, offset: 0, alignment: 1,
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
-entry_values: []
-callSites: []
-debugValueSubstitutions: []
-constants: []
-machineFunctionInfo:
- amxProgModel: None
body: |
; CHECK-LABEL: name: fold_with_physical_reg
- ; CHECK: bb.0.entry:
+ ; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: liveins: $rdi, $rsi, $rdx, $ecx
; CHECK-NEXT: {{ $}}
@@ -111,7 +33,7 @@ body: |
; CHECK-NEXT: [[AND64ri32_ND:%[0-9]+]]:gr64 = AND64ri32_ND [[LEA64r]], -16, implicit-def dead $eflags
; CHECK-NEXT: MOV64mr %stack.1, 1, $noreg, 0, $noreg, [[AND64ri32_ND]] :: (store (s64) into %stack.1)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.1.bb1:
+ ; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
@@ -122,7 +44,7 @@ body: |
; CHECK-NEXT: ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
; CHECK-NEXT: undef [[MOV32r0_:%[0-9]+]].sub_32bit:gr64_nosp = MOV32r0 implicit-def dead $eflags
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.2.bb2:
+ ; CHECK-NEXT: bb.2:
; CHECK-NEXT: successors: %bb.1(0x04000000), %bb.2(0x7c000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
@@ -143,13 +65,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY [[COPY8]]
; CHECK-NEXT: ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
; CHECK-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm %stack.2, 1, $noreg, 0, $noreg :: (load (s64) from %stack.2)
- ; CHECK-NEXT: MOV64mi32 [[MOV64rm]], 8, [[MOV32r0_]], 0, $noreg, 0 :: (store (s64) into %ir.gep)
- ; CHECK-NEXT: MOV64mi32 [[COPY1]], 1, $noreg, 0, $noreg, 0 :: (store (s64) into %ir.arg2)
+ ; CHECK-NEXT: MOV64mi32 [[MOV64rm]], 8, [[MOV32r0_]], 0, $noreg, 0 :: (store (s64))
+ ; CHECK-NEXT: MOV64mi32 [[COPY1]], 1, $noreg, 0, $noreg, 0 :: (store (s64))
; CHECK-NEXT: TEST8ri [[COPY]].sub_8bit, 1, implicit-def $eflags
; CHECK-NEXT: [[MOV32r0_:%[0-9]+]]:gr64_nosp = COPY [[COPY2]]
; CHECK-NEXT: JCC_1 %bb.1, 5, implicit $eflags
; CHECK-NEXT: JMP_1 %bb.2
- bb.0.entry:
+ bb.0:
successors: %bb.1(0x80000000)
liveins: $rdi, $rsi, $rdx, $ecx
@@ -161,7 +83,7 @@ body: |
%9:gr64 = AND64ri32_ND %8, -16, implicit-def dead $eflags
undef %7.sub_32bit:gr64_with_sub_8bit = MOV32r0 implicit-def dead $eflags
- bb.1.bb1:
+ bb.1:
successors: %bb.2(0x80000000)
ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
@@ -170,7 +92,7 @@ body: |
ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
undef %16.sub_32bit:gr64_nosp = MOV32r0 implicit-def dead $eflags
- bb.2.bb2:
+ bb.2:
successors: %bb.1(0x04000000), %bb.2(0x7c000000)
ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
@@ -181,8 +103,8 @@ body: |
dead $ecx = MOV32r0 implicit-def dead $eflags, implicit-def $rcx
CALL64r %7, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $rdx, implicit $rcx, implicit killed $xmm0, implicit-def $rsp, implicit-def $ssp, implicit-def dead $rax
ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
- MOV64mi32 %0, 8, %16, 0, $noreg, 0 :: (store (s64) into %ir.gep)
- MOV64mi32 %4, 1, $noreg, 0, $noreg, 0 :: (store (s64) into %ir.arg2)
+ MOV64mi32 %0, 8, %16, 0, $noreg, 0 :: (store (s64))
+ MOV64mi32 %4, 1, $noreg, 0, $noreg, 0 :: (store (s64))
TEST8ri %5.sub_8bit, 1, implicit-def $eflags
%16:gr64_nosp = COPY %3
JCC_1 %bb.1, 5, implicit $eflags
More information about the llvm-commits
mailing list