[llvm] [AArch64][GISel] Regbank G_BITCAST using src regbank. (PR #191522)

[David Green via llvm-commits]

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@@ -897,6 +906,19 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
                                    &ValMappings[Shift64Imm], 3);
     return getSameKindOfOperandsMapping(MI);
   }
+  case TargetOpcode::G_BITCAST: {
+    Register SrcReg = MI.getOperand(1).getReg();
+    const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI);
+    if (SrcRB) {
+      TypeSize Size = getSizeInBits(SrcReg, MRI, TRI);
+      return getInstructionMapping(
+          DefaultMappingID, 0,
+          getCopyMapping(SrcRB->getID(), SrcRB->getID(), Size),
+          // We only care about the mapping of the destination.
+          /*NumOperands*/ 2);
+    }
+    [[fallthrough]];
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davemgreen wrote:

Yeah it's intended. (It would probably be missing a [[fallthrough]] or break if it wasn't).

https://github.com/llvm/llvm-project/pull/191522