[llvm] AMDGPU/GlobalISel: RegBankLegalize rules for flat/global prefetch (PR #192764)

via llvm-commits llvm-commits at lists.llvm.org
Fri Apr 17 20:08:35 PDT 2026


https://github.com/vangthao95 created https://github.com/llvm/llvm-project/pull/192764

None

>From 1c5825fc429ceab3b4bb75c31a3fa9ad13fe3164 Mon Sep 17 00:00:00 2001
From: Vang Thao <Vang.Thao at amd.com>
Date: Fri, 17 Apr 2026 22:47:54 -0400
Subject: [PATCH] AMDGPU/GlobalISel: RegBankLegalize rules for flat/global
 prefetch

---
 llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp   | 4 ++++
 llvm/test/CodeGen/AMDGPU/llvm.amdgcn.flat.prefetch.ll   | 2 +-
 llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.prefetch.ll | 2 +-
 3 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 03b9ea9397650..5afbfb7427f31 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -1565,6 +1565,10 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
       {amdgcn_s_get_named_barrier_state, amdgcn_s_get_barrier_state}, Standard)
       .Uni(S32, {{Sgpr32}, {IntrId, SgprB32_M0}});
 
+  addRulesForIOpcs({amdgcn_flat_prefetch}).Any({{}, {{}, {IntrId, VgprP0}}});
+
+  addRulesForIOpcs({amdgcn_global_prefetch}).Any({{}, {{}, {IntrId, VgprP1}}});
+
   addRulesForIOpcs({amdgcn_s_prefetch_data})
       .Any({{}, {{}, {IntrId, SgprB64_ReadFirstLane, SgprB32_ReadFirstLane}}});
 
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.flat.prefetch.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.flat.prefetch.ll
index 041c67255b2a9..bace9a1d8a7d1 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.flat.prefetch.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.flat.prefetch.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck --check-prefix=GCN %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck --check-prefix=GCN %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck --check-prefix=GCN %s
 
 declare void @llvm.amdgcn.flat.prefetch(ptr %ptr, i32 %col)
 
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.prefetch.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.prefetch.ll
index 2da2da9a35683..2c5ad1e36cc9e 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.prefetch.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.prefetch.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck --check-prefix=GCN %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck --check-prefix=GCN %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck --check-prefix=GCN %s
 
 declare void @llvm.amdgcn.global.prefetch(ptr addrspace(1) %ptr, i32 %col)
 



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