[llvm] [AMDGPU] Post-RA Peephole for latency-hiding and hazard-avoidance bet… (PR #191319)

[Zeng Wu via llvm-commits]

zwu-2025 wrote:

> > > This seems like a scheduling problem - why doesn't PostRA scheduler do it?
> > > My main concern is that this is not always beneficial - for example, if we want to schedule the mfma after the buffer_load to hide the buffer_load latency.
> > > I'm also unclear on why we're limiting to just mfma - why not any valu for example?
> > 
> > 
> > The scheduler pre/post RA will consider many elements and trade-offs in a much bigger scope and if our scheduler can handle this case well for now, we can ignore the changes here.
> 
> Sure - so I guess my question is why doesn't the post RA scheduler do it? Do you have a complete end-to-end case which demonstrates why the post RA scheduler can't do it?

Ideally, we should analyze why scheduler does not do it. However, the patch here is to port the the [changes](https://github.com/ROCm/triton/blob/4837e77a8faac4fd3dd88ac3c6958bf1b5e96130/python/triton/tools/amdgcnas.py#L2888) and before the changes, there are several other transformations on the assembly code. In other words, there is no such pattern exposed to the llvm schduler.

https://github.com/llvm/llvm-project/pull/191319