[llvm] [AMDGPU][GlobalIsel] Add regbank support for cvt_scalef32_sr_pk_f6_f116/32 intrinsics (PR #192745)
Syadus Sefat via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 17 14:58:15 PDT 2026
https://github.com/mssefat updated https://github.com/llvm/llvm-project/pull/192745
>From 26407066c2439ebdc2fbe21a42b67064c68023ff Mon Sep 17 00:00:00 2001
From: mssefat <syadus.sefat at gmail.com>
Date: Fri, 17 Apr 2026 12:05:35 -0500
Subject: [PATCH] [AMDGPU][GlobalIsel] Add regbank support for cvt scalef32
intrinsics
---
.../AMDGPU/AMDGPURegBankLegalizeHelper.cpp | 17 +-
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 14 +
.../AMDGPU/AMDGPURegBankLegalizeRules.h | 5 +
.../AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.ll | 510 +++++++-----------
4 files changed, 218 insertions(+), 328 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
index 63a940ab5d29b..3423a9fc55960 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
@@ -1450,6 +1450,12 @@ LLT RegBankLegalizeHelper::getTyFromID(RegBankLLTMappingApplyID ID) {
case VgprV2S64:
case UniInVgprV2S64:
return LLT::fixed_vector(2, 64);
+ case VgprV6S32:
+ return LLT::fixed_vector(6, 32);
+ case VgprV32S16:
+ return LLT::fixed_vector(32, 16);
+ case VgprV32S32:
+ return LLT::fixed_vector(32, 32);
default:
return LLT();
}
@@ -1611,7 +1617,9 @@ RegBankLegalizeHelper::getRegBankFromID(RegBankLLTMappingApplyID ID) {
case VgprV3S32:
case VgprV4S16:
case VgprV4S32:
+ case VgprV6S32:
case VgprV8S32:
+ case VgprV32S16:
case VgprB32:
case VgprB64:
case VgprB96:
@@ -1675,7 +1683,9 @@ bool RegBankLegalizeHelper::applyMappingDst(
case VgprV3S32:
case VgprV4S16:
case VgprV4S32:
- case VgprV8S32: {
+ case VgprV6S32:
+ case VgprV8S32:
+ case VgprV32S16: {
assert(Ty == getTyFromID(MethodIDs[OpIdx]));
assert(RB == getRegBankFromID(MethodIDs[OpIdx]));
break;
@@ -1868,7 +1878,10 @@ bool RegBankLegalizeHelper::applyMappingSrc(
case VgprV3S32:
case VgprV4S16:
case VgprV4S32:
- case VgprV8S32: {
+ case VgprV6S32:
+ case VgprV8S32:
+ case VgprV32S16:
+ case VgprV32S32: {
assert(Ty == getTyFromID(MethodIDs[i]));
if (RB != VgprRB) {
auto CopyToVgpr = B.buildCopy({VgprRB, Ty}, Reg);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 03b9ea9397650..ade44c0e06cda 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -193,6 +193,8 @@ bool matchUniformityAndLLT(Register Reg, UniformityLLTOpPredicateID UniID,
return MRI.getType(Reg) == LLT::fixed_vector(3, 32) && MUI.isDivergent(Reg);
case DivV4S16:
return MRI.getType(Reg) == LLT::fixed_vector(4, 16) && MUI.isDivergent(Reg);
+ case DivV6S32:
+ return MRI.getType(Reg) == LLT::fixed_vector(6, 32) && MUI.isDivergent(Reg);
case DivB32:
return MRI.getType(Reg).getSizeInBits() == 32 && MUI.isDivergent(Reg);
case DivB64:
@@ -1708,6 +1710,18 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Uni(V2S16, {{UniInVgprV2S16}, {IntrId, Vgpr32, Vgpr32}})
.Div(V2S16, {{VgprV2S16}, {IntrId, Vgpr32, Vgpr32}});
+ addRulesForIOpcs({amdgcn_cvt_scalef32_sr_pk32_bf6_f16,
+ amdgcn_cvt_scalef32_sr_pk32_fp6_f16,
+ amdgcn_cvt_scalef32_sr_pk32_bf6_bf16,
+ amdgcn_cvt_scalef32_sr_pk32_fp6_bf16},
+ Standard)
+ .Any({{DivV6S32}, {{VgprV6S32}, {IntrId, VgprV32S16, Vgpr32, Vgpr32}}});
+
+ addRulesForIOpcs({amdgcn_cvt_scalef32_sr_pk32_bf6_f32,
+ amdgcn_cvt_scalef32_sr_pk32_fp6_f32},
+ Standard)
+ .Any({{DivV6S32}, {{VgprV6S32}, {IntrId, VgprV32S32, Vgpr32, Vgpr32}}});
+
addRulesForIOpcs({amdgcn_global_load_tr_b64})
.Any({{DivB64}, {{VgprB64}, {IntrId, SgprP1}}})
.Any({{DivB32}, {{VgprB32}, {IntrId, SgprP1}}});
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
index 3d282220d8611..9bed18d16cc61 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
@@ -107,6 +107,7 @@ enum UniformityLLTOpPredicateID {
DivV2S64,
DivV3S32,
DivV4S16,
+ DivV6S32,
// B types
B32,
@@ -255,6 +256,10 @@ enum RegBankLLTMappingApplyID {
Vgpr32AExt,
Vgpr32SExt,
Vgpr32ZExt,
+
+ VgprV6S32,
+ VgprV32S16,
+ VgprV32S32,
};
// Instruction needs to be replaced with sequence of instructions. Lowering was
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.ll
index 854708a281f1b..bcd4d03056077 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck -check-prefix=GFX950-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck -check-prefix=GFX950-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck -check-prefix=GCN,GFX950-SDAG %s
+; RUN: llc -global-isel=1 -global-isel-abort=2 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck -check-prefix=GCN,GFX950-GISEL %s
declare <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.bf6.bf16(<32 x bfloat> %src, i32 %sr, float %scale)
declare <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.bf6.f16(<32 x half> %src, i32 %sr, float %scale)
@@ -10,72 +10,41 @@ declare <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.fp6.f16(<32 x half> %src, i3
declare <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.fp6.f32(<32 x float> %src, i32 %sr, float %scale)
define amdgpu_ps void @test_scalef32_sr_pk32_bf6_bf16_vv(<32 x bfloat> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {
-; GFX950-SDAG-LABEL: test_scalef32_sr_pk32_bf6_bf16_vv:
-; GFX950-SDAG: ; %bb.0:
-; GFX950-SDAG-NEXT: v_cvt_scalef32_sr_pk32_bf6_bf16 v[20:25], v[0:15], v16, v17
-; GFX950-SDAG-NEXT: global_store_dwordx2 v[18:19], v[24:25], off offset:16
-; GFX950-SDAG-NEXT: global_store_dwordx4 v[18:19], v[20:23], off
-; GFX950-SDAG-NEXT: s_endpgm
-;
-; GFX950-GISEL-LABEL: test_scalef32_sr_pk32_bf6_bf16_vv:
-; GFX950-GISEL: ; %bb.0:
-; GFX950-GISEL-NEXT: v_cvt_scalef32_sr_pk32_bf6_bf16 v[20:25], v[0:15], v16, v17
-; GFX950-GISEL-NEXT: global_store_dwordx2 v[18:19], v[24:25], off offset:16
-; GFX950-GISEL-NEXT: global_store_dwordx4 v[18:19], v[20:23], off
-; GFX950-GISEL-NEXT: s_endpgm
+; GCN-LABEL: test_scalef32_sr_pk32_bf6_bf16_vv:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_cvt_scalef32_sr_pk32_bf6_bf16 v[20:25], v[0:15], v16, v17
+; GCN-NEXT: global_store_dwordx2 v[18:19], v[24:25], off offset:16
+; GCN-NEXT: global_store_dwordx4 v[18:19], v[20:23], off
+; GCN-NEXT: s_endpgm
%cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.bf6.bf16(<32 x bfloat> %src, i32 %sr, float %scale)
store <6 x i32> %cvt, ptr addrspace(1) %out, align 8
ret void
}
define amdgpu_ps void @test_scalef32_sr_pk32_bf6_bf16_sl(<32 x bfloat> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {
-; GFX950-SDAG-LABEL: test_scalef32_sr_pk32_bf6_bf16_sl:
-; GFX950-SDAG: ; %bb.0:
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, s0
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, s1
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v4, s2
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v5, s3
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v6, s4
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v7, s5
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v8, s6
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v9, s7
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v10, s8
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v11, s9
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v12, s10
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v13, s11
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v14, s12
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v15, s13
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v16, s14
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v17, s15
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v24, 0x42c80000
-; GFX950-SDAG-NEXT: v_cvt_scalef32_sr_pk32_bf6_bf16 v[18:23], v[2:17], s16, v24
-; GFX950-SDAG-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16
-; GFX950-SDAG-NEXT: global_store_dwordx4 v[0:1], v[18:21], off
-; GFX950-SDAG-NEXT: s_endpgm
-;
-; GFX950-GISEL-LABEL: test_scalef32_sr_pk32_bf6_bf16_sl:
-; GFX950-GISEL: ; %bb.0:
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, s2
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, s3
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v6, s4
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v7, s5
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v8, s6
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v9, s7
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v10, s8
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v11, s9
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v12, s10
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v13, s11
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v14, s12
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v15, s13
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v16, s14
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v17, s15
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v24, 0x42c80000
-; GFX950-GISEL-NEXT: v_cvt_scalef32_sr_pk32_bf6_bf16 v[18:23], v[2:17], s16, v24
-; GFX950-GISEL-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16
-; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[18:21], off
-; GFX950-GISEL-NEXT: s_endpgm
+; GCN-LABEL: test_scalef32_sr_pk32_bf6_bf16_sl:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_mov_b32_e32 v2, s0
+; GCN-NEXT: v_mov_b32_e32 v3, s1
+; GCN-NEXT: v_mov_b32_e32 v4, s2
+; GCN-NEXT: v_mov_b32_e32 v5, s3
+; GCN-NEXT: v_mov_b32_e32 v6, s4
+; GCN-NEXT: v_mov_b32_e32 v7, s5
+; GCN-NEXT: v_mov_b32_e32 v8, s6
+; GCN-NEXT: v_mov_b32_e32 v9, s7
+; GCN-NEXT: v_mov_b32_e32 v10, s8
+; GCN-NEXT: v_mov_b32_e32 v11, s9
+; GCN-NEXT: v_mov_b32_e32 v12, s10
+; GCN-NEXT: v_mov_b32_e32 v13, s11
+; GCN-NEXT: v_mov_b32_e32 v14, s12
+; GCN-NEXT: v_mov_b32_e32 v15, s13
+; GCN-NEXT: v_mov_b32_e32 v16, s14
+; GCN-NEXT: v_mov_b32_e32 v17, s15
+; GCN-NEXT: v_mov_b32_e32 v24, 0x42c80000
+; GCN-NEXT: v_cvt_scalef32_sr_pk32_bf6_bf16 v[18:23], v[2:17], s16, v24
+; GCN-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16
+; GCN-NEXT: global_store_dwordx4 v[0:1], v[18:21], off
+; GCN-NEXT: s_endpgm
%cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.bf6.bf16(<32 x bfloat> %src, i32 %sr, float 100.0)
store <6 x i32> %cvt, ptr addrspace(1) %out, align 8
ret void
@@ -101,117 +70,70 @@ define amdgpu_ps void @test_scalef32_sr_pk32_bf6_f16_vv(<32 x half> %src, i32 %s
}
define amdgpu_ps void @test_scalef32_sr_pk32_bf6_f16_sl(<32 x half> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {
-; GFX950-SDAG-LABEL: test_scalef32_sr_pk32_bf6_f16_sl:
-; GFX950-SDAG: ; %bb.0:
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, s0
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, s1
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v4, s2
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v5, s3
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v6, s4
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v7, s5
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v8, s6
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v9, s7
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v10, s8
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v11, s9
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v12, s10
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v13, s11
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v14, s12
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v15, s13
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v16, s14
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v17, s15
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v24, 0x42c80000
-; GFX950-SDAG-NEXT: v_cvt_scalef32_sr_pk32_bf6_f16 v[18:23], v[2:17], s16, v24
-; GFX950-SDAG-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16
-; GFX950-SDAG-NEXT: global_store_dwordx4 v[0:1], v[18:21], off
-; GFX950-SDAG-NEXT: s_endpgm
-;
-; GFX950-GISEL-LABEL: test_scalef32_sr_pk32_bf6_f16_sl:
-; GFX950-GISEL: ; %bb.0:
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[14:15]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[12:13]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[10:11]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[8:9]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v24, 0x42c80000
-; GFX950-GISEL-NEXT: v_cvt_scalef32_sr_pk32_bf6_f16 v[18:23], v[2:17], s16, v24
-; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[18:21], off
-; GFX950-GISEL-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16
-; GFX950-GISEL-NEXT: s_endpgm
+; GCN-LABEL: test_scalef32_sr_pk32_bf6_f16_sl:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_mov_b32_e32 v2, s0
+; GCN-NEXT: v_mov_b32_e32 v3, s1
+; GCN-NEXT: v_mov_b32_e32 v4, s2
+; GCN-NEXT: v_mov_b32_e32 v5, s3
+; GCN-NEXT: v_mov_b32_e32 v6, s4
+; GCN-NEXT: v_mov_b32_e32 v7, s5
+; GCN-NEXT: v_mov_b32_e32 v8, s6
+; GCN-NEXT: v_mov_b32_e32 v9, s7
+; GCN-NEXT: v_mov_b32_e32 v10, s8
+; GCN-NEXT: v_mov_b32_e32 v11, s9
+; GCN-NEXT: v_mov_b32_e32 v12, s10
+; GCN-NEXT: v_mov_b32_e32 v13, s11
+; GCN-NEXT: v_mov_b32_e32 v14, s12
+; GCN-NEXT: v_mov_b32_e32 v15, s13
+; GCN-NEXT: v_mov_b32_e32 v16, s14
+; GCN-NEXT: v_mov_b32_e32 v17, s15
+; GCN-NEXT: v_mov_b32_e32 v24, 0x42c80000
+; GCN-NEXT: v_cvt_scalef32_sr_pk32_bf6_f16 v[18:23], v[2:17], s16, v24
+; GCN-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16
+; GCN-NEXT: global_store_dwordx4 v[0:1], v[18:21], off
+; GCN-NEXT: s_endpgm
%cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.bf6.f16(<32 x half> %src, i32 %sr, float 100.0)
store <6 x i32> %cvt, ptr addrspace(1) %out, align 8
ret void
}
define amdgpu_ps void @test_scalef32_sr_pk32_fp6_bf16_vv(<32 x bfloat> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {
-; GFX950-SDAG-LABEL: test_scalef32_sr_pk32_fp6_bf16_vv:
-; GFX950-SDAG: ; %bb.0:
-; GFX950-SDAG-NEXT: v_cvt_scalef32_sr_pk32_fp6_bf16 v[20:25], v[0:15], v16, v17
-; GFX950-SDAG-NEXT: global_store_dwordx2 v[18:19], v[24:25], off offset:16
-; GFX950-SDAG-NEXT: global_store_dwordx4 v[18:19], v[20:23], off
-; GFX950-SDAG-NEXT: s_endpgm
-;
-; GFX950-GISEL-LABEL: test_scalef32_sr_pk32_fp6_bf16_vv:
-; GFX950-GISEL: ; %bb.0:
-; GFX950-GISEL-NEXT: v_cvt_scalef32_sr_pk32_fp6_bf16 v[20:25], v[0:15], v16, v17
-; GFX950-GISEL-NEXT: global_store_dwordx2 v[18:19], v[24:25], off offset:16
-; GFX950-GISEL-NEXT: global_store_dwordx4 v[18:19], v[20:23], off
-; GFX950-GISEL-NEXT: s_endpgm
+; GCN-LABEL: test_scalef32_sr_pk32_fp6_bf16_vv:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_cvt_scalef32_sr_pk32_fp6_bf16 v[20:25], v[0:15], v16, v17
+; GCN-NEXT: global_store_dwordx2 v[18:19], v[24:25], off offset:16
+; GCN-NEXT: global_store_dwordx4 v[18:19], v[20:23], off
+; GCN-NEXT: s_endpgm
%cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.fp6.bf16(<32 x bfloat> %src, i32 %sr, float %scale)
store <6 x i32> %cvt, ptr addrspace(1) %out, align 8
ret void
}
define amdgpu_ps void @test_scalef32_sr_pk32_fp6_bf16_sl(<32 x bfloat> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {
-; GFX950-SDAG-LABEL: test_scalef32_sr_pk32_fp6_bf16_sl:
-; GFX950-SDAG: ; %bb.0:
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, s0
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, s1
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v4, s2
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v5, s3
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v6, s4
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v7, s5
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v8, s6
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v9, s7
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v10, s8
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v11, s9
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v12, s10
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v13, s11
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v14, s12
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v15, s13
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v16, s14
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v17, s15
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v24, 0x42c80000
-; GFX950-SDAG-NEXT: v_cvt_scalef32_sr_pk32_fp6_bf16 v[18:23], v[2:17], s16, v24
-; GFX950-SDAG-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16
-; GFX950-SDAG-NEXT: global_store_dwordx4 v[0:1], v[18:21], off
-; GFX950-SDAG-NEXT: s_endpgm
-;
-; GFX950-GISEL-LABEL: test_scalef32_sr_pk32_fp6_bf16_sl:
-; GFX950-GISEL: ; %bb.0:
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v3, s1
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, s2
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, s3
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v6, s4
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v7, s5
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v8, s6
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v9, s7
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v10, s8
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v11, s9
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v12, s10
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v13, s11
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v14, s12
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v15, s13
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v16, s14
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v17, s15
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v24, 0x42c80000
-; GFX950-GISEL-NEXT: v_cvt_scalef32_sr_pk32_fp6_bf16 v[18:23], v[2:17], s16, v24
-; GFX950-GISEL-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16
-; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[18:21], off
-; GFX950-GISEL-NEXT: s_endpgm
+; GCN-LABEL: test_scalef32_sr_pk32_fp6_bf16_sl:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_mov_b32_e32 v2, s0
+; GCN-NEXT: v_mov_b32_e32 v3, s1
+; GCN-NEXT: v_mov_b32_e32 v4, s2
+; GCN-NEXT: v_mov_b32_e32 v5, s3
+; GCN-NEXT: v_mov_b32_e32 v6, s4
+; GCN-NEXT: v_mov_b32_e32 v7, s5
+; GCN-NEXT: v_mov_b32_e32 v8, s6
+; GCN-NEXT: v_mov_b32_e32 v9, s7
+; GCN-NEXT: v_mov_b32_e32 v10, s8
+; GCN-NEXT: v_mov_b32_e32 v11, s9
+; GCN-NEXT: v_mov_b32_e32 v12, s10
+; GCN-NEXT: v_mov_b32_e32 v13, s11
+; GCN-NEXT: v_mov_b32_e32 v14, s12
+; GCN-NEXT: v_mov_b32_e32 v15, s13
+; GCN-NEXT: v_mov_b32_e32 v16, s14
+; GCN-NEXT: v_mov_b32_e32 v17, s15
+; GCN-NEXT: v_mov_b32_e32 v24, 0x42c80000
+; GCN-NEXT: v_cvt_scalef32_sr_pk32_fp6_bf16 v[18:23], v[2:17], s16, v24
+; GCN-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16
+; GCN-NEXT: global_store_dwordx4 v[0:1], v[18:21], off
+; GCN-NEXT: s_endpgm
%cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.fp6.bf16(<32 x bfloat> %src, i32 %sr, float 100.0)
store <6 x i32> %cvt, ptr addrspace(1) %out, align 8
ret void
@@ -237,45 +159,29 @@ define amdgpu_ps void @test_scalef32_sr_pk32_fp6_f16_vv(<32 x half> %src, i32 %s
}
define amdgpu_ps void @test_scalef32_sr_pk32_fp6_f16_sl(<32 x half> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {
-; GFX950-SDAG-LABEL: test_scalef32_sr_pk32_fp6_f16_sl:
-; GFX950-SDAG: ; %bb.0:
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, s0
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, s1
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v4, s2
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v5, s3
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v6, s4
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v7, s5
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v8, s6
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v9, s7
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v10, s8
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v11, s9
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v12, s10
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v13, s11
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v14, s12
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v15, s13
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v16, s14
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v17, s15
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v24, 0x42c80000
-; GFX950-SDAG-NEXT: v_cvt_scalef32_sr_pk32_fp6_f16 v[18:23], v[2:17], s16, v24
-; GFX950-SDAG-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16
-; GFX950-SDAG-NEXT: global_store_dwordx4 v[0:1], v[18:21], off
-; GFX950-SDAG-NEXT: s_endpgm
-;
-; GFX950-GISEL-LABEL: test_scalef32_sr_pk32_fp6_f16_sl:
-; GFX950-GISEL: ; %bb.0:
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[14:15]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[12:13]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[10:11]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[8:9]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v24, 0x42c80000
-; GFX950-GISEL-NEXT: v_cvt_scalef32_sr_pk32_fp6_f16 v[18:23], v[2:17], s16, v24
-; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[18:21], off
-; GFX950-GISEL-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16
-; GFX950-GISEL-NEXT: s_endpgm
+; GCN-LABEL: test_scalef32_sr_pk32_fp6_f16_sl:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_mov_b32_e32 v2, s0
+; GCN-NEXT: v_mov_b32_e32 v3, s1
+; GCN-NEXT: v_mov_b32_e32 v4, s2
+; GCN-NEXT: v_mov_b32_e32 v5, s3
+; GCN-NEXT: v_mov_b32_e32 v6, s4
+; GCN-NEXT: v_mov_b32_e32 v7, s5
+; GCN-NEXT: v_mov_b32_e32 v8, s6
+; GCN-NEXT: v_mov_b32_e32 v9, s7
+; GCN-NEXT: v_mov_b32_e32 v10, s8
+; GCN-NEXT: v_mov_b32_e32 v11, s9
+; GCN-NEXT: v_mov_b32_e32 v12, s10
+; GCN-NEXT: v_mov_b32_e32 v13, s11
+; GCN-NEXT: v_mov_b32_e32 v14, s12
+; GCN-NEXT: v_mov_b32_e32 v15, s13
+; GCN-NEXT: v_mov_b32_e32 v16, s14
+; GCN-NEXT: v_mov_b32_e32 v17, s15
+; GCN-NEXT: v_mov_b32_e32 v24, 0x42c80000
+; GCN-NEXT: v_cvt_scalef32_sr_pk32_fp6_f16 v[18:23], v[2:17], s16, v24
+; GCN-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16
+; GCN-NEXT: global_store_dwordx4 v[0:1], v[18:21], off
+; GCN-NEXT: s_endpgm
%cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.fp6.f16(<32 x half> %src, i32 %sr, float 100.0)
store <6 x i32> %cvt, ptr addrspace(1) %out, align 8
ret void
@@ -301,69 +207,45 @@ define amdgpu_ps void @test_scalef32_sr_pk32_bf6_f32_vv(<32 x float> %src, i32 %
}
define amdgpu_ps void @test_scalef32_sr_pk32_bf6_f32_sl(<32 x float> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {
-; GFX950-SDAG-LABEL: test_scalef32_sr_pk32_bf6_f32_sl:
-; GFX950-SDAG: ; %bb.0:
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, s0
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, s1
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v4, s2
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v5, s3
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v6, s4
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v7, s5
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v8, s6
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v9, s7
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v10, s8
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v11, s9
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v12, s10
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v13, s11
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v14, s12
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v15, s13
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v16, s14
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v17, s15
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v18, s16
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v19, s17
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v20, s18
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v21, s19
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v22, s20
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v23, s21
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v24, s22
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v25, s23
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v26, s24
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v27, s25
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v28, s26
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v29, s27
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v30, s28
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v31, s29
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v32, s30
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v33, s31
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v40, 0x42c80000
-; GFX950-SDAG-NEXT: v_cvt_scalef32_sr_pk32_bf6_f32 v[34:39], v[2:33], s32, v40
-; GFX950-SDAG-NEXT: global_store_dwordx2 v[0:1], v[38:39], off offset:16
-; GFX950-SDAG-NEXT: global_store_dwordx4 v[0:1], v[34:37], off
-; GFX950-SDAG-NEXT: s_endpgm
-;
-; GFX950-GISEL-LABEL: test_scalef32_sr_pk32_bf6_f32_sl:
-; GFX950-GISEL: ; %bb.0:
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[32:33], s[30:31]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[30:31], s[28:29]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[28:29], s[26:27]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[26:27], s[24:25]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[24:25], s[22:23]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[22:23], s[20:21]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[20:21], s[18:19]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[16:17]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[14:15]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[12:13]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[10:11]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[8:9]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v40, 0x42c80000
-; GFX950-GISEL-NEXT: v_cvt_scalef32_sr_pk32_bf6_f32 v[34:39], v[2:33], s32, v40
-; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[34:37], off
-; GFX950-GISEL-NEXT: global_store_dwordx2 v[0:1], v[38:39], off offset:16
-; GFX950-GISEL-NEXT: s_endpgm
+; GCN-LABEL: test_scalef32_sr_pk32_bf6_f32_sl:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_mov_b32_e32 v2, s0
+; GCN-NEXT: v_mov_b32_e32 v3, s1
+; GCN-NEXT: v_mov_b32_e32 v4, s2
+; GCN-NEXT: v_mov_b32_e32 v5, s3
+; GCN-NEXT: v_mov_b32_e32 v6, s4
+; GCN-NEXT: v_mov_b32_e32 v7, s5
+; GCN-NEXT: v_mov_b32_e32 v8, s6
+; GCN-NEXT: v_mov_b32_e32 v9, s7
+; GCN-NEXT: v_mov_b32_e32 v10, s8
+; GCN-NEXT: v_mov_b32_e32 v11, s9
+; GCN-NEXT: v_mov_b32_e32 v12, s10
+; GCN-NEXT: v_mov_b32_e32 v13, s11
+; GCN-NEXT: v_mov_b32_e32 v14, s12
+; GCN-NEXT: v_mov_b32_e32 v15, s13
+; GCN-NEXT: v_mov_b32_e32 v16, s14
+; GCN-NEXT: v_mov_b32_e32 v17, s15
+; GCN-NEXT: v_mov_b32_e32 v18, s16
+; GCN-NEXT: v_mov_b32_e32 v19, s17
+; GCN-NEXT: v_mov_b32_e32 v20, s18
+; GCN-NEXT: v_mov_b32_e32 v21, s19
+; GCN-NEXT: v_mov_b32_e32 v22, s20
+; GCN-NEXT: v_mov_b32_e32 v23, s21
+; GCN-NEXT: v_mov_b32_e32 v24, s22
+; GCN-NEXT: v_mov_b32_e32 v25, s23
+; GCN-NEXT: v_mov_b32_e32 v26, s24
+; GCN-NEXT: v_mov_b32_e32 v27, s25
+; GCN-NEXT: v_mov_b32_e32 v28, s26
+; GCN-NEXT: v_mov_b32_e32 v29, s27
+; GCN-NEXT: v_mov_b32_e32 v30, s28
+; GCN-NEXT: v_mov_b32_e32 v31, s29
+; GCN-NEXT: v_mov_b32_e32 v32, s30
+; GCN-NEXT: v_mov_b32_e32 v33, s31
+; GCN-NEXT: v_mov_b32_e32 v40, 0x42c80000
+; GCN-NEXT: v_cvt_scalef32_sr_pk32_bf6_f32 v[34:39], v[2:33], s32, v40
+; GCN-NEXT: global_store_dwordx2 v[0:1], v[38:39], off offset:16
+; GCN-NEXT: global_store_dwordx4 v[0:1], v[34:37], off
+; GCN-NEXT: s_endpgm
%cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.bf6.f32(<32 x float> %src, i32 %sr, float 100.0)
store <6 x i32> %cvt, ptr addrspace(1) %out, align 8
ret void
@@ -389,69 +271,45 @@ define amdgpu_ps void @test_scalef32_sr_pk32_fp6_f32_vv(<32 x float> %src, i32 %
}
define amdgpu_ps void @test_scalef32_sr_pk32_fp6_f32_sl(<32 x float> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {
-; GFX950-SDAG-LABEL: test_scalef32_sr_pk32_fp6_f32_sl:
-; GFX950-SDAG: ; %bb.0:
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, s0
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, s1
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v4, s2
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v5, s3
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v6, s4
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v7, s5
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v8, s6
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v9, s7
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v10, s8
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v11, s9
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v12, s10
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v13, s11
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v14, s12
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v15, s13
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v16, s14
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v17, s15
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v18, s16
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v19, s17
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v20, s18
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v21, s19
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v22, s20
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v23, s21
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v24, s22
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v25, s23
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v26, s24
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v27, s25
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v28, s26
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v29, s27
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v30, s28
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v31, s29
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v32, s30
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v33, s31
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v40, 0x42c80000
-; GFX950-SDAG-NEXT: v_cvt_scalef32_sr_pk32_fp6_f32 v[34:39], v[2:33], s32, v40
-; GFX950-SDAG-NEXT: global_store_dwordx2 v[0:1], v[38:39], off offset:16
-; GFX950-SDAG-NEXT: global_store_dwordx4 v[0:1], v[34:37], off
-; GFX950-SDAG-NEXT: s_endpgm
-;
-; GFX950-GISEL-LABEL: test_scalef32_sr_pk32_fp6_f32_sl:
-; GFX950-GISEL: ; %bb.0:
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[32:33], s[30:31]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[30:31], s[28:29]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[28:29], s[26:27]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[26:27], s[24:25]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[24:25], s[22:23]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[22:23], s[20:21]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[20:21], s[18:19]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[16:17]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[14:15]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[12:13]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[10:11]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[8:9]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v40, 0x42c80000
-; GFX950-GISEL-NEXT: v_cvt_scalef32_sr_pk32_fp6_f32 v[34:39], v[2:33], s32, v40
-; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[34:37], off
-; GFX950-GISEL-NEXT: global_store_dwordx2 v[0:1], v[38:39], off offset:16
-; GFX950-GISEL-NEXT: s_endpgm
+; GCN-LABEL: test_scalef32_sr_pk32_fp6_f32_sl:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_mov_b32_e32 v2, s0
+; GCN-NEXT: v_mov_b32_e32 v3, s1
+; GCN-NEXT: v_mov_b32_e32 v4, s2
+; GCN-NEXT: v_mov_b32_e32 v5, s3
+; GCN-NEXT: v_mov_b32_e32 v6, s4
+; GCN-NEXT: v_mov_b32_e32 v7, s5
+; GCN-NEXT: v_mov_b32_e32 v8, s6
+; GCN-NEXT: v_mov_b32_e32 v9, s7
+; GCN-NEXT: v_mov_b32_e32 v10, s8
+; GCN-NEXT: v_mov_b32_e32 v11, s9
+; GCN-NEXT: v_mov_b32_e32 v12, s10
+; GCN-NEXT: v_mov_b32_e32 v13, s11
+; GCN-NEXT: v_mov_b32_e32 v14, s12
+; GCN-NEXT: v_mov_b32_e32 v15, s13
+; GCN-NEXT: v_mov_b32_e32 v16, s14
+; GCN-NEXT: v_mov_b32_e32 v17, s15
+; GCN-NEXT: v_mov_b32_e32 v18, s16
+; GCN-NEXT: v_mov_b32_e32 v19, s17
+; GCN-NEXT: v_mov_b32_e32 v20, s18
+; GCN-NEXT: v_mov_b32_e32 v21, s19
+; GCN-NEXT: v_mov_b32_e32 v22, s20
+; GCN-NEXT: v_mov_b32_e32 v23, s21
+; GCN-NEXT: v_mov_b32_e32 v24, s22
+; GCN-NEXT: v_mov_b32_e32 v25, s23
+; GCN-NEXT: v_mov_b32_e32 v26, s24
+; GCN-NEXT: v_mov_b32_e32 v27, s25
+; GCN-NEXT: v_mov_b32_e32 v28, s26
+; GCN-NEXT: v_mov_b32_e32 v29, s27
+; GCN-NEXT: v_mov_b32_e32 v30, s28
+; GCN-NEXT: v_mov_b32_e32 v31, s29
+; GCN-NEXT: v_mov_b32_e32 v32, s30
+; GCN-NEXT: v_mov_b32_e32 v33, s31
+; GCN-NEXT: v_mov_b32_e32 v40, 0x42c80000
+; GCN-NEXT: v_cvt_scalef32_sr_pk32_fp6_f32 v[34:39], v[2:33], s32, v40
+; GCN-NEXT: global_store_dwordx2 v[0:1], v[38:39], off offset:16
+; GCN-NEXT: global_store_dwordx4 v[0:1], v[34:37], off
+; GCN-NEXT: s_endpgm
%cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.fp6.f32(<32 x float> %src, i32 %sr, float 100.0)
store <6 x i32> %cvt, ptr addrspace(1) %out, align 8
ret void
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