[llvm] 8e424e3 - [RISCV] Support emitting plui.h for i32 constants on RV64. (#192534)

[via llvm-commits]

Author: Craig Topper
Date: 2026-04-17T12:54:00-07:00
New Revision: 8e424e318de2f7b51b0fea27915601c4a38cdb13

URL: https://github.com/llvm/llvm-project/commit/8e424e318de2f7b51b0fea27915601c4a38cdb13
DIFF: https://github.com/llvm/llvm-project/commit/8e424e318de2f7b51b0fea27915601c4a38cdb13.diff

LOG: [RISCV] Support emitting plui.h for i32 constants on RV64. (#192534)

If the constant was originally i32, it will be sign or zero
extended to i64 during type legalization. If we can prove the
upper bits aren't used we can duplicate the lower bits to allow
RISCVMatInt to select plui.h.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    llvm/test/CodeGen/RISCV/rv64p.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 5f459f016faa4..359ba913589a6 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -1082,7 +1082,7 @@ static unsigned getSegInstNF(unsigned Intrinsic) {
   }
 }
 
-static bool isApplicableToPLI(int Val) {
+static bool isApplicableToPLIOrPLUI(int Val) {
   // Check if the immediate is packed i8 or i10
   int16_t Bit31To16 = Val >> 16;
   int16_t Bit15To0 = Val;
@@ -1091,7 +1091,8 @@ static bool isApplicableToPLI(int Val) {
   if (Bit31To16 != Bit15To0)
     return false;
 
-  return isInt<10>(Bit31To16) || Bit15To8 == Bit7To0;
+  return isInt<10>(Bit15To0) || isShiftedInt<10, 6>(Bit15To0) ||
+         Bit15To8 == Bit7To0;
 }
 
 void RISCVDAGToDAGISel::Select(SDNode *Node) {
@@ -1151,8 +1152,9 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
       if (!isInt<32>(Imm) && isUInt<32>(Imm) && hasAllWUsers(Node))
         Imm = SignExtend64<32>(Imm);
 
-      if (VT == MVT::i64 && !isInt<12>(Imm) && Subtarget->hasStdExtP() &&
-          isApplicableToPLI(Imm) && hasAllWUsers(Node)) {
+      if (VT == MVT::i64 && !isInt<12>(Imm) && !isShiftedInt<20, 12>(Imm) &&
+          Subtarget->hasStdExtP() && isApplicableToPLIOrPLUI(Imm) &&
+          hasAllWUsers(Node)) {
         // If it's 4 packed 8-bit integers or 2 packed signed 16-bit integers,
         // we can simply copy lower 32 bits to higher 32 bits to make it able to
         // rematerialize to PLI_B or PLI_H

diff  --git a/llvm/test/CodeGen/RISCV/rv64p.ll b/llvm/test/CodeGen/RISCV/rv64p.ll
index 21630c8dbb37f..4948e7ba50816 100644
--- a/llvm/test/CodeGen/RISCV/rv64p.ll
+++ b/llvm/test/CodeGen/RISCV/rv64p.ll
@@ -191,6 +191,27 @@ define i64 @plui_h_i64() {
   ret i64 u0xfdc0fdc0fdc0fdc0
 }
 
+define void @plui_h_i32(ptr %p) {
+; CHECK-LABEL: plui_h_i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    plui.h a1, -9
+; CHECK-NEXT:    sw a1, 0(a0)
+; CHECK-NEXT:    ret
+  store i32 u0xfdc0fdc0, ptr %p
+  ret void
+}
+
+; Make sure we use lui instead of plui.h.
+define void @lui_i32(ptr %p) {
+; CHECK-LABEL: lui_i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a1, 524296
+; CHECK-NEXT:    sw a1, 0(a0)
+; CHECK-NEXT:    ret
+  store i32 u0x80008000, ptr %p
+  ret void
+}
+
 define i64 @plui_w_i64() {
 ; CHECK-LABEL: plui_w_i64:
 ; CHECK:       # %bb.0: