[llvm] [RISCV] Add zero-store merging and load-from-store promotion (PR #192662)

[Alexander Richardson via llvm-commits]

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@@ -0,0 +1,137 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+Xmipslsp -use-riscv-mips-load-store-pairs=1 -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s --check-prefix=RV32
+; RUN: llc -mtriple=riscv64 -mattr=+Xmipslsp -use-riscv-mips-load-store-pairs=1 -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s --check-prefix=RV64
+
+; Test zero store merging optimization: sb + sb -> sh
+define void @test_zero_store_merge_byte(ptr %ptr) {
+; RV32-LABEL: test_zero_store_merge_byte:
+; RV32:       # %bb.0:
+; RV32-NEXT:    sh zero, 0(a0)
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: test_zero_store_merge_byte:
+; RV64:       # %bb.0:
+; RV64-NEXT:    sh zero, 0(a0)
+; RV64-NEXT:    ret
+  store i8 0, ptr %ptr, align 1
+  %ptr1 = getelementptr inbounds i8, ptr %ptr, i64 1
+  store i8 0, ptr %ptr1, align 1
+  ret void
+}
+
+; Test zero store merging optimization: sh + sh -> sw
+define void @test_zero_store_merge_half(ptr %ptr) {
+; RV32-LABEL: test_zero_store_merge_half:
+; RV32:       # %bb.0:
+; RV32-NEXT:    sw zero, 0(a0)
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arichardson wrote:

This is now potentially an unaligned access. We need to check that unaligned stores are permitted before doing this merging right?

https://github.com/llvm/llvm-project/pull/192662