[llvm] [WIP] AMDGPU: VGPR bank conflict avoidance hints (PR #192140)

[Matt Arsenault via llvm-commits]

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@@ -3853,6 +3859,26 @@ const int *SIRegisterInfo::getRegUnitPressureSets(MCRegUnit RegUnit) const {
   return AMDGPUGenRegisterInfo::getRegUnitPressureSets(RegUnit);
 }
 
+bool SIRegisterInfo::is3OperandVALU(const MachineInstr &MI) const {
+  if (!SIInstrInfo::isVALU(MI))
+    return false;
+
+  const MCInstrDesc &Desc = MI.getDesc();
+  const SIInstrInfo *TII = ST.getInstrInfo();
+  const MachineFunction &MF = *MI.getMF();
+  unsigned NumVGPRSrcs = 0;
+
+  // Count explicit source operands whose register class can hold VGPRs.
+  // Skip defs (operands 0..NumDefs-1); only inspect use slots.
+  for (unsigned i = Desc.getNumDefs(), e = Desc.getNumOperands(); i < e; ++i) {
+    const TargetRegisterClass *OpRC = TII->getRegClass(Desc, i);
+    if (OpRC && hasVGPRs(OpRC))
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arsenm wrote:

This is just looking at the static instruction definition; should it be ignoring VS operands that are dynamically known to be SGPR or constants? 

https://github.com/llvm/llvm-project/pull/192140