[llvm] [RISCV] Cost UDIV/UREM by a constant power of 2 as a SHL/AND in getArithmeticInstrCost() (PR #179570)
Ryan Buchner via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 17 10:07:37 PDT 2026
https://github.com/bababuck updated https://github.com/llvm/llvm-project/pull/179570
>From eba0ed38d2f8174a13fefec48c9e4d8af7bec6d3 Mon Sep 17 00:00:00 2001
From: bababuck <buchner.ryan at gmail.com>
Date: Mon, 2 Feb 2026 10:07:27 -0800
Subject: [PATCH 01/19] [RISCV] Add tests for UDIV/UREM by power of 2 costing
---
.../Analysis/CostModel/RISCV/arith-int.ll | 22 +++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/llvm/test/Analysis/CostModel/RISCV/arith-int.ll b/llvm/test/Analysis/CostModel/RISCV/arith-int.ll
index 7e9a190966fb4..8863bb0962fcf 100644
--- a/llvm/test/Analysis/CostModel/RISCV/arith-int.ll
+++ b/llvm/test/Analysis/CostModel/RISCV/arith-int.ll
@@ -705,6 +705,9 @@ define i32 @udiv() {
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = udiv i16 undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = udiv i32 undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = udiv i64 undef, undef
+; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64_C2 = udiv i64 undef, 2
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2I64_C2 = udiv <2 x i64> undef, <i64 2, i64 4>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64_C2C = udiv <2 x i64> undef, splat (i64 2)
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1I16 = udiv <1 x i16> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I16 = udiv <2 x i16> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4I16 = udiv <4 x i16> undef, undef
@@ -741,6 +744,9 @@ define i32 @udiv() {
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I16 = udiv i16 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I32 = udiv i32 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I64 = udiv i64 undef, undef
+; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I64_C2 = udiv i64 undef, 2
+; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2I64_C2 = udiv <2 x i64> undef, <i64 2, i64 4>
+; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64_C2C = udiv <2 x i64> undef, splat (i64 2)
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1I16 = udiv <1 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I16 = udiv <2 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4I16 = udiv <4 x i16> undef, undef
@@ -777,6 +783,11 @@ define i32 @udiv() {
%I32 = udiv i32 undef, undef
%I64 = udiv i64 undef, undef
+ ; UDIV by power of 2 constant
+ %I64_C2 = udiv i64 undef, 2
+ %V2I64_C2 = udiv <2 x i64> undef, <i64 2, i64 4>
+ %V2I64_C2C = udiv <2 x i64> undef, <i64 2, i64 2>
+
%V1I16 = udiv <1 x i16> undef, undef
%V2I16 = udiv <2 x i16> undef, undef
%V4I16 = udiv <4 x i16> undef, undef
@@ -821,6 +832,9 @@ define i32 @urem() {
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = urem i16 undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = urem i32 undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = urem i64 undef, undef
+; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64_C2 = udiv i64 undef, 2
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2I64_C2 = udiv <2 x i64> undef, <i64 2, i64 4>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64_C2C = udiv <2 x i64> undef, splat (i64 2)
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1I16 = urem <1 x i16> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I16 = urem <2 x i16> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4I16 = urem <4 x i16> undef, undef
@@ -857,6 +871,9 @@ define i32 @urem() {
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I16 = urem i16 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I32 = urem i32 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I64 = urem i64 undef, undef
+; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I64_C2 = udiv i64 undef, 2
+; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2I64_C2 = udiv <2 x i64> undef, <i64 2, i64 4>
+; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64_C2C = udiv <2 x i64> undef, splat (i64 2)
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1I16 = urem <1 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I16 = urem <2 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4I16 = urem <4 x i16> undef, undef
@@ -893,6 +910,11 @@ define i32 @urem() {
%I32 = urem i32 undef, undef
%I64 = urem i64 undef, undef
+ ; UDIV by power of 2 constant
+ %I64_C2 = udiv i64 undef, 2
+ %V2I64_C2 = udiv <2 x i64> undef, <i64 2, i64 4>
+ %V2I64_C2C = udiv <2 x i64> undef, <i64 2, i64 2>
+
%V1I16 = urem <1 x i16> undef, undef
%V2I16 = urem <2 x i16> undef, undef
%V4I16 = urem <4 x i16> undef, undef
>From 921ebff68536a92aa14a99214d2c0dbe607fd195 Mon Sep 17 00:00:00 2001
From: bababuck <buchner.ryan at gmail.com>
Date: Fri, 30 Jan 2026 16:53:31 -0800
Subject: [PATCH 02/19] [RISCV] Cost UDIV/UREM by a constant power of 2 as a
SHL/AND
Assume these instructions will be lowered to SHL/AND instructions.
---
.../Target/RISCV/RISCVTargetTransformInfo.cpp | 11 ++++++++++
.../Analysis/CostModel/RISCV/arith-int.ll | 20 +++++++++----------
2 files changed, 21 insertions(+), 10 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index dc4bf0784e2d1..d895988527a8c 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2617,6 +2617,17 @@ InstructionCost RISCVTTIImpl::getArithmeticInstrCost(
std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(Ty);
unsigned ISDOpcode = TLI->InstructionOpcodeToISD(Opcode);
+ // Vector unsigned division/remainder will be simplified to shifts/masks.
+ if ((ISDOpcode == ISD::UDIV || ISDOpcode == ISD::UREM) &&
+ Op2Info.isConstant() && Op2Info.isPowerOf2()) {
+ if (ISDOpcode == ISD::UDIV)
+ return getArithmeticInstrCost(Instruction::LShr, Ty, CostKind,
+ Op1Info.getNoProps(), Op2Info.getNoProps());
+ // UREM
+ return getArithmeticInstrCost(Instruction::And, Ty, CostKind,
+ Op1Info.getNoProps(), Op2Info.getNoProps());
+ }
+
// TODO: Handle scalar type.
if (!LT.second.isVector()) {
static const CostTblEntry DivTbl[]{
diff --git a/llvm/test/Analysis/CostModel/RISCV/arith-int.ll b/llvm/test/Analysis/CostModel/RISCV/arith-int.ll
index 8863bb0962fcf..296a8f9d7da95 100644
--- a/llvm/test/Analysis/CostModel/RISCV/arith-int.ll
+++ b/llvm/test/Analysis/CostModel/RISCV/arith-int.ll
@@ -706,8 +706,8 @@ define i32 @udiv() {
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = udiv i32 undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = udiv i64 undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64_C2 = udiv i64 undef, 2
-; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2I64_C2 = udiv <2 x i64> undef, <i64 2, i64 4>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64_C2C = udiv <2 x i64> undef, splat (i64 2)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64_C2 = udiv <2 x i64> undef, <i64 2, i64 4>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64_C2C = udiv <2 x i64> undef, splat (i64 2)
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1I16 = udiv <1 x i16> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I16 = udiv <2 x i16> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4I16 = udiv <4 x i16> undef, undef
@@ -744,9 +744,9 @@ define i32 @udiv() {
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I16 = udiv i16 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I32 = udiv i32 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I64 = udiv i64 undef, undef
-; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I64_C2 = udiv i64 undef, 2
-; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2I64_C2 = udiv <2 x i64> undef, <i64 2, i64 4>
-; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64_C2C = udiv <2 x i64> undef, splat (i64 2)
+; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64_C2 = udiv i64 undef, 2
+; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64_C2 = udiv <2 x i64> undef, <i64 2, i64 4>
+; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64_C2C = udiv <2 x i64> undef, splat (i64 2)
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1I16 = udiv <1 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I16 = udiv <2 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4I16 = udiv <4 x i16> undef, undef
@@ -833,8 +833,8 @@ define i32 @urem() {
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = urem i32 undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = urem i64 undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64_C2 = udiv i64 undef, 2
-; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2I64_C2 = udiv <2 x i64> undef, <i64 2, i64 4>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64_C2C = udiv <2 x i64> undef, splat (i64 2)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64_C2 = udiv <2 x i64> undef, <i64 2, i64 4>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64_C2C = udiv <2 x i64> undef, splat (i64 2)
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1I16 = urem <1 x i16> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I16 = urem <2 x i16> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4I16 = urem <4 x i16> undef, undef
@@ -871,9 +871,9 @@ define i32 @urem() {
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I16 = urem i16 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I32 = urem i32 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I64 = urem i64 undef, undef
-; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I64_C2 = udiv i64 undef, 2
-; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2I64_C2 = udiv <2 x i64> undef, <i64 2, i64 4>
-; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64_C2C = udiv <2 x i64> undef, splat (i64 2)
+; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64_C2 = udiv i64 undef, 2
+; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64_C2 = udiv <2 x i64> undef, <i64 2, i64 4>
+; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64_C2C = udiv <2 x i64> undef, splat (i64 2)
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1I16 = urem <1 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I16 = urem <2 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4I16 = urem <4 x i16> undef, undef
>From ae93493415c5d04ea473d308910e7d4aa6b2d86e Mon Sep 17 00:00:00 2001
From: bababuck <buchner.ryan at gmail.com>
Date: Mon, 2 Feb 2026 08:54:01 -0800
Subject: [PATCH 03/19] [TTI][RISCV][AArch64][NFC] Pull out common costing
logic into getConvertedArtihmeticInstructionCost()
For certain instruction-arguments, we try to more accurately cost by predicting how these instructions
will be lowered. Many of these cases are common across all backends and ought to be pull out into
a common location.
---
llvm/include/llvm/CodeGen/BasicTTIImpl.h | 24 +++++++++++++++++++
.../AArch64/AArch64TargetTransformInfo.cpp | 15 ++++--------
.../Target/RISCV/RISCVTargetTransformInfo.cpp | 14 ++++-------
3 files changed, 33 insertions(+), 20 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/BasicTTIImpl.h b/llvm/include/llvm/CodeGen/BasicTTIImpl.h
index 21afcbefdf719..c807b06a292b4 100644
--- a/llvm/include/llvm/CodeGen/BasicTTIImpl.h
+++ b/llvm/include/llvm/CodeGen/BasicTTIImpl.h
@@ -1048,6 +1048,30 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
unsigned getMaxInterleaveFactor(ElementCount VF) const override { return 1; }
+ bool getConvertedArithmeticInstructionCost(unsigned ISDOpcode, Type *Ty,
+ TTI::TargetCostKind CostKind,
+ TTI::OperandValueInfo Opd1Info,
+ TTI::OperandValueInfo Opd2Info,
+ ArrayRef<const Value *> Args,
+ const Instruction *CxtI,
+ InstructionCost &Cost) const {
+ // Vector unsigned division/remainder will be simplified to shifts/masks.
+ if ((ISDOpcode == ISD::UDIV || ISDOpcode == ISD::UREM) &&
+ Opd2Info.isConstant() && Opd2Info.isPowerOf2()) {
+ if (ISDOpcode == ISD::UDIV)
+ Cost = getArithmeticInstrCost(Instruction::LShr, Ty, CostKind,
+ Opd1Info.getNoProps(),
+ Opd2Info.getNoProps());
+ // UREM
+ else
+ Cost = getArithmeticInstrCost(Instruction::And, Ty, CostKind,
+ Opd1Info.getNoProps(),
+ Opd2Info.getNoProps());
+ return true;
+ }
+ return false;
+ }
+
InstructionCost getArithmeticInstrCost(
unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
TTI::OperandValueInfo Opd1Info = {TTI::OK_AnyValue, TTI::OP_None},
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
index bdf06e39d7367..fa473342fd6a7 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -4290,6 +4290,11 @@ InstructionCost AArch64TTIImpl::getArithmeticInstrCost(
return LT.first;
}
+ InstructionCost ConvertedCost;
+ if (getConvertedArithmeticInstructionCost(ISD, Ty, CostKind, Op1Info, Op2Info,
+ Args, CxtI, ConvertedCost))
+ return ConvertedCost;
+
switch (ISD) {
default:
return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info,
@@ -4413,16 +4418,6 @@ InstructionCost AArch64TTIImpl::getArithmeticInstrCost(
case ISD::UREM: {
auto VT = TLI->getValueType(DL, Ty);
if (Op2Info.isConstant()) {
- // If the operand is a power of 2 we can use the shift or and cost.
- if (ISD == ISD::UDIV && Op2Info.isPowerOf2())
- return getArithmeticInstrCost(Instruction::LShr, Ty, CostKind,
- Op1Info.getNoProps(),
- Op2Info.getNoProps());
- if (ISD == ISD::UREM && Op2Info.isPowerOf2())
- return getArithmeticInstrCost(Instruction::And, Ty, CostKind,
- Op1Info.getNoProps(),
- Op2Info.getNoProps());
-
if (ISD == ISD::UDIV || ISD == ISD::UREM) {
// Divides by a constant are expanded to MULHU + SUB + SRL + ADD + SRL.
// The MULHU will be expanded to UMULL for the types not listed below,
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index d895988527a8c..1f68d708ec1cb 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2617,16 +2617,10 @@ InstructionCost RISCVTTIImpl::getArithmeticInstrCost(
std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(Ty);
unsigned ISDOpcode = TLI->InstructionOpcodeToISD(Opcode);
- // Vector unsigned division/remainder will be simplified to shifts/masks.
- if ((ISDOpcode == ISD::UDIV || ISDOpcode == ISD::UREM) &&
- Op2Info.isConstant() && Op2Info.isPowerOf2()) {
- if (ISDOpcode == ISD::UDIV)
- return getArithmeticInstrCost(Instruction::LShr, Ty, CostKind,
- Op1Info.getNoProps(), Op2Info.getNoProps());
- // UREM
- return getArithmeticInstrCost(Instruction::And, Ty, CostKind,
- Op1Info.getNoProps(), Op2Info.getNoProps());
- }
+ InstructionCost ConvertedCost;
+ if (getConvertedArithmeticInstructionCost(ISDOpcode, Ty, CostKind, Op1Info,
+ Op2Info, Args, CxtI, ConvertedCost))
+ return ConvertedCost;
// TODO: Handle scalar type.
if (!LT.second.isVector()) {
>From d3d9a09835e241f23e3658080d24fcf6df039f68 Mon Sep 17 00:00:00 2001
From: bababuck <buchner.ryan at gmail.com>
Date: Tue, 3 Feb 2026 15:31:31 -0800
Subject: [PATCH 04/19] [RISCV] Fix costing test
---
.../Analysis/CostModel/RISCV/arith-int.ll | 36 +++++++++----------
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/llvm/test/Analysis/CostModel/RISCV/arith-int.ll b/llvm/test/Analysis/CostModel/RISCV/arith-int.ll
index 296a8f9d7da95..5a9efbb317fa4 100644
--- a/llvm/test/Analysis/CostModel/RISCV/arith-int.ll
+++ b/llvm/test/Analysis/CostModel/RISCV/arith-int.ll
@@ -705,9 +705,9 @@ define i32 @udiv() {
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = udiv i16 undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = udiv i32 undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = udiv i64 undef, undef
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64_C2 = udiv i64 undef, 2
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64_C2 = udiv <2 x i64> undef, <i64 2, i64 4>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64_C2C = udiv <2 x i64> undef, splat (i64 2)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64_C2 = udiv i64 poison, 2
+; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64_C2 = udiv <2 x i64> poison, <i64 2, i64 4>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64_C2C = udiv <2 x i64> poison, splat (i64 2)
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1I16 = udiv <1 x i16> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I16 = udiv <2 x i16> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4I16 = udiv <4 x i16> undef, undef
@@ -744,9 +744,9 @@ define i32 @udiv() {
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I16 = udiv i16 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I32 = udiv i32 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I64 = udiv i64 undef, undef
-; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64_C2 = udiv i64 undef, 2
-; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64_C2 = udiv <2 x i64> undef, <i64 2, i64 4>
-; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64_C2C = udiv <2 x i64> undef, splat (i64 2)
+; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64_C2 = udiv i64 poison, 2
+; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64_C2 = udiv <2 x i64> poison, <i64 2, i64 4>
+; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64_C2C = udiv <2 x i64> poison, splat (i64 2)
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1I16 = udiv <1 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I16 = udiv <2 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4I16 = udiv <4 x i16> undef, undef
@@ -784,9 +784,9 @@ define i32 @udiv() {
%I64 = udiv i64 undef, undef
; UDIV by power of 2 constant
- %I64_C2 = udiv i64 undef, 2
- %V2I64_C2 = udiv <2 x i64> undef, <i64 2, i64 4>
- %V2I64_C2C = udiv <2 x i64> undef, <i64 2, i64 2>
+ %I64_C2 = udiv i64 poison, 2
+ %V2I64_C2 = udiv <2 x i64> poison, <i64 2, i64 4>
+ %V2I64_C2C = udiv <2 x i64> poison, <i64 2, i64 2>
%V1I16 = udiv <1 x i16> undef, undef
%V2I16 = udiv <2 x i16> undef, undef
@@ -832,9 +832,9 @@ define i32 @urem() {
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = urem i16 undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = urem i32 undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = urem i64 undef, undef
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64_C2 = udiv i64 undef, 2
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64_C2 = udiv <2 x i64> undef, <i64 2, i64 4>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64_C2C = udiv <2 x i64> undef, splat (i64 2)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64_C2 = urem i64 poison, 2
+; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64_C2 = urem <2 x i64> poison, <i64 2, i64 4>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64_C2C = urem <2 x i64> poison, splat (i64 2)
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1I16 = urem <1 x i16> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I16 = urem <2 x i16> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4I16 = urem <4 x i16> undef, undef
@@ -871,9 +871,9 @@ define i32 @urem() {
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I16 = urem i16 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I32 = urem i32 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I64 = urem i64 undef, undef
-; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64_C2 = udiv i64 undef, 2
-; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64_C2 = udiv <2 x i64> undef, <i64 2, i64 4>
-; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64_C2C = udiv <2 x i64> undef, splat (i64 2)
+; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64_C2 = urem i64 poison, 2
+; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64_C2 = urem <2 x i64> poison, <i64 2, i64 4>
+; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64_C2C = urem <2 x i64> poison, splat (i64 2)
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1I16 = urem <1 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I16 = urem <2 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4I16 = urem <4 x i16> undef, undef
@@ -911,9 +911,9 @@ define i32 @urem() {
%I64 = urem i64 undef, undef
; UDIV by power of 2 constant
- %I64_C2 = udiv i64 undef, 2
- %V2I64_C2 = udiv <2 x i64> undef, <i64 2, i64 4>
- %V2I64_C2C = udiv <2 x i64> undef, <i64 2, i64 2>
+ %I64_C2 = urem i64 poison, 2
+ %V2I64_C2 = urem <2 x i64> poison, <i64 2, i64 4>
+ %V2I64_C2C = urem <2 x i64> poison, <i64 2, i64 2>
%V1I16 = urem <1 x i16> undef, undef
%V2I16 = urem <2 x i16> undef, undef
>From 552b095e48e97bd08dc78068a5ea6eef4a413503 Mon Sep 17 00:00:00 2001
From: bababuck <buchner.ryan at gmail.com>
Date: Tue, 3 Feb 2026 17:52:16 -0800
Subject: [PATCH 05/19] [NFC][X86] Use getConvertedArithmeticInstrCost() for
X86
---
llvm/lib/Target/X86/X86TargetTransformInfo.cpp | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
index e4ef221e53b12..9e642b9dff6a9 100644
--- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -276,6 +276,11 @@ InstructionCost X86TTIImpl::getArithmeticInstrCost(
int ISD = TLI->InstructionOpcodeToISD(Opcode);
assert(ISD && "Invalid opcode");
+ InstructionCost ConvertedCost;
+ if (getConvertedArithmeticInstructionCost(ISD, Ty, CostKind, Op1Info, Op2Info,
+ Args, CxtI, ConvertedCost))
+ return ConvertedCost;
+
if (ISD == ISD::MUL && Args.size() == 2 && LT.second.isVector() &&
(LT.second.getScalarType() == MVT::i32 ||
LT.second.getScalarType() == MVT::i64)) {
>From 319433531289a49416df25e9698d69bc87a0e473 Mon Sep 17 00:00:00 2001
From: bababuck <buchner.ryan at gmail.com>
Date: Wed, 4 Feb 2026 09:46:40 -0800
Subject: [PATCH 06/19] [TTI] Simplify UDiv/URem directly in
TargetTransformInfo::getArithmeticInstructionCost()
---
llvm/include/llvm/CodeGen/BasicTTIImpl.h | 24 -------------------
llvm/lib/Analysis/TargetTransformInfo.cpp | 7 ++++++
.../AArch64/AArch64TargetTransformInfo.cpp | 5 ----
.../Target/RISCV/RISCVTargetTransformInfo.cpp | 5 ----
.../lib/Target/X86/X86TargetTransformInfo.cpp | 16 -------------
.../Analysis/CostModel/RISCV/arith-int.ll | 20 ++++++++--------
6 files changed, 17 insertions(+), 60 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/BasicTTIImpl.h b/llvm/include/llvm/CodeGen/BasicTTIImpl.h
index c807b06a292b4..21afcbefdf719 100644
--- a/llvm/include/llvm/CodeGen/BasicTTIImpl.h
+++ b/llvm/include/llvm/CodeGen/BasicTTIImpl.h
@@ -1048,30 +1048,6 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
unsigned getMaxInterleaveFactor(ElementCount VF) const override { return 1; }
- bool getConvertedArithmeticInstructionCost(unsigned ISDOpcode, Type *Ty,
- TTI::TargetCostKind CostKind,
- TTI::OperandValueInfo Opd1Info,
- TTI::OperandValueInfo Opd2Info,
- ArrayRef<const Value *> Args,
- const Instruction *CxtI,
- InstructionCost &Cost) const {
- // Vector unsigned division/remainder will be simplified to shifts/masks.
- if ((ISDOpcode == ISD::UDIV || ISDOpcode == ISD::UREM) &&
- Opd2Info.isConstant() && Opd2Info.isPowerOf2()) {
- if (ISDOpcode == ISD::UDIV)
- Cost = getArithmeticInstrCost(Instruction::LShr, Ty, CostKind,
- Opd1Info.getNoProps(),
- Opd2Info.getNoProps());
- // UREM
- else
- Cost = getArithmeticInstrCost(Instruction::And, Ty, CostKind,
- Opd1Info.getNoProps(),
- Opd2Info.getNoProps());
- return true;
- }
- return false;
- }
-
InstructionCost getArithmeticInstrCost(
unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
TTI::OperandValueInfo Opd1Info = {TTI::OK_AnyValue, TTI::OP_None},
diff --git a/llvm/lib/Analysis/TargetTransformInfo.cpp b/llvm/lib/Analysis/TargetTransformInfo.cpp
index 19785204ed2b3..e7d494a471889 100644
--- a/llvm/lib/Analysis/TargetTransformInfo.cpp
+++ b/llvm/lib/Analysis/TargetTransformInfo.cpp
@@ -1012,6 +1012,13 @@ InstructionCost TargetTransformInfo::getArithmeticInstrCost(
return getCallInstrCost(nullptr, VecTy, {VecTy, VecTy}, CostKind);
}
+ // Vector unsigned division/remainder will be simplified to shifts/masks.
+ if ((Opcode == Instruction::UDiv || Opcode == Instruction::URem) &&
+ Op2Info.isConstant() && Op2Info.isPowerOf2())
+ return getArithmeticInstrCost(
+ Opcode == Instruction::UDiv ? Instruction::LShr : Instruction::And, Ty,
+ CostKind, Op1Info.getNoProps(), Op2Info.getNoProps());
+
InstructionCost Cost = TTIImpl->getArithmeticInstrCost(
Opcode, Ty, CostKind, Op1Info, Op2Info, Args, CxtI);
assert(Cost >= 0 && "TTI should not produce negative costs!");
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
index fa473342fd6a7..f82327fb2edf3 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -4290,11 +4290,6 @@ InstructionCost AArch64TTIImpl::getArithmeticInstrCost(
return LT.first;
}
- InstructionCost ConvertedCost;
- if (getConvertedArithmeticInstructionCost(ISD, Ty, CostKind, Op1Info, Op2Info,
- Args, CxtI, ConvertedCost))
- return ConvertedCost;
-
switch (ISD) {
default:
return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info,
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 1f68d708ec1cb..dc4bf0784e2d1 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2617,11 +2617,6 @@ InstructionCost RISCVTTIImpl::getArithmeticInstrCost(
std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(Ty);
unsigned ISDOpcode = TLI->InstructionOpcodeToISD(Opcode);
- InstructionCost ConvertedCost;
- if (getConvertedArithmeticInstructionCost(ISDOpcode, Ty, CostKind, Op1Info,
- Op2Info, Args, CxtI, ConvertedCost))
- return ConvertedCost;
-
// TODO: Handle scalar type.
if (!LT.second.isVector()) {
static const CostTblEntry DivTbl[]{
diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
index 9e642b9dff6a9..af6b6153b7925 100644
--- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -276,11 +276,6 @@ InstructionCost X86TTIImpl::getArithmeticInstrCost(
int ISD = TLI->InstructionOpcodeToISD(Opcode);
assert(ISD && "Invalid opcode");
- InstructionCost ConvertedCost;
- if (getConvertedArithmeticInstructionCost(ISD, Ty, CostKind, Op1Info, Op2Info,
- Args, CxtI, ConvertedCost))
- return ConvertedCost;
-
if (ISD == ISD::MUL && Args.size() == 2 && LT.second.isVector() &&
(LT.second.getScalarType() == MVT::i32 ||
LT.second.getScalarType() == MVT::i64)) {
@@ -371,17 +366,6 @@ InstructionCost X86TTIImpl::getArithmeticInstrCost(
return Cost;
}
- // Vector unsigned division/remainder will be simplified to shifts/masks.
- if ((ISD == ISD::UDIV || ISD == ISD::UREM) &&
- Op2Info.isConstant() && Op2Info.isPowerOf2()) {
- if (ISD == ISD::UDIV)
- return getArithmeticInstrCost(Instruction::LShr, Ty, CostKind,
- Op1Info.getNoProps(), Op2Info.getNoProps());
- // UREM
- return getArithmeticInstrCost(Instruction::And, Ty, CostKind,
- Op1Info.getNoProps(), Op2Info.getNoProps());
- }
-
static const CostKindTblEntry GFNIUniformConstCostTable[] = {
{ ISD::SHL, MVT::v16i8, { 1, 6, 1, 2 } }, // gf2p8affineqb
{ ISD::SRL, MVT::v16i8, { 1, 6, 1, 2 } }, // gf2p8affineqb
diff --git a/llvm/test/Analysis/CostModel/RISCV/arith-int.ll b/llvm/test/Analysis/CostModel/RISCV/arith-int.ll
index 5a9efbb317fa4..4aef4664f5a01 100644
--- a/llvm/test/Analysis/CostModel/RISCV/arith-int.ll
+++ b/llvm/test/Analysis/CostModel/RISCV/arith-int.ll
@@ -706,8 +706,8 @@ define i32 @udiv() {
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = udiv i32 undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = udiv i64 undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64_C2 = udiv i64 poison, 2
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64_C2 = udiv <2 x i64> poison, <i64 2, i64 4>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64_C2C = udiv <2 x i64> poison, splat (i64 2)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2I64_C2 = udiv <2 x i64> poison, <i64 2, i64 4>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64_C2C = udiv <2 x i64> poison, splat (i64 2)
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1I16 = udiv <1 x i16> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I16 = udiv <2 x i16> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4I16 = udiv <4 x i16> undef, undef
@@ -744,9 +744,9 @@ define i32 @udiv() {
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I16 = udiv i16 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I32 = udiv i32 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I64 = udiv i64 undef, undef
-; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64_C2 = udiv i64 poison, 2
-; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64_C2 = udiv <2 x i64> poison, <i64 2, i64 4>
-; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64_C2C = udiv <2 x i64> poison, splat (i64 2)
+; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I64_C2 = udiv i64 poison, 2
+; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2I64_C2 = udiv <2 x i64> poison, <i64 2, i64 4>
+; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64_C2C = udiv <2 x i64> poison, splat (i64 2)
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1I16 = udiv <1 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I16 = udiv <2 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4I16 = udiv <4 x i16> undef, undef
@@ -833,8 +833,8 @@ define i32 @urem() {
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = urem i32 undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = urem i64 undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64_C2 = urem i64 poison, 2
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64_C2 = urem <2 x i64> poison, <i64 2, i64 4>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64_C2C = urem <2 x i64> poison, splat (i64 2)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2I64_C2 = urem <2 x i64> poison, <i64 2, i64 4>
+; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64_C2C = urem <2 x i64> poison, splat (i64 2)
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1I16 = urem <1 x i16> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I16 = urem <2 x i16> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4I16 = urem <4 x i16> undef, undef
@@ -871,9 +871,9 @@ define i32 @urem() {
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I16 = urem i16 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I32 = urem i32 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I64 = urem i64 undef, undef
-; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64_C2 = urem i64 poison, 2
-; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64_C2 = urem <2 x i64> poison, <i64 2, i64 4>
-; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64_C2C = urem <2 x i64> poison, splat (i64 2)
+; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I64_C2 = urem i64 poison, 2
+; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2I64_C2 = urem <2 x i64> poison, <i64 2, i64 4>
+; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64_C2C = urem <2 x i64> poison, splat (i64 2)
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1I16 = urem <1 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I16 = urem <2 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4I16 = urem <4 x i16> undef, undef
>From 40620b29d22dac0c87cf7095217426ba3a589316 Mon Sep 17 00:00:00 2001
From: bababuck <buchner.ryan at gmail.com>
Date: Wed, 4 Feb 2026 09:56:38 -0800
Subject: [PATCH 07/19] [RISCV] Replace UDiv/URem power of 2 cost test since
old test not functional after refactor
---
.../Analysis/CostModel/RISCV/arith-int.ll | 22 -------------------
1 file changed, 22 deletions(-)
diff --git a/llvm/test/Analysis/CostModel/RISCV/arith-int.ll b/llvm/test/Analysis/CostModel/RISCV/arith-int.ll
index 4aef4664f5a01..7e9a190966fb4 100644
--- a/llvm/test/Analysis/CostModel/RISCV/arith-int.ll
+++ b/llvm/test/Analysis/CostModel/RISCV/arith-int.ll
@@ -705,9 +705,6 @@ define i32 @udiv() {
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = udiv i16 undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = udiv i32 undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = udiv i64 undef, undef
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64_C2 = udiv i64 poison, 2
-; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2I64_C2 = udiv <2 x i64> poison, <i64 2, i64 4>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64_C2C = udiv <2 x i64> poison, splat (i64 2)
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1I16 = udiv <1 x i16> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I16 = udiv <2 x i16> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4I16 = udiv <4 x i16> undef, undef
@@ -744,9 +741,6 @@ define i32 @udiv() {
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I16 = udiv i16 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I32 = udiv i32 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I64 = udiv i64 undef, undef
-; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I64_C2 = udiv i64 poison, 2
-; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2I64_C2 = udiv <2 x i64> poison, <i64 2, i64 4>
-; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64_C2C = udiv <2 x i64> poison, splat (i64 2)
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1I16 = udiv <1 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I16 = udiv <2 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4I16 = udiv <4 x i16> undef, undef
@@ -783,11 +777,6 @@ define i32 @udiv() {
%I32 = udiv i32 undef, undef
%I64 = udiv i64 undef, undef
- ; UDIV by power of 2 constant
- %I64_C2 = udiv i64 poison, 2
- %V2I64_C2 = udiv <2 x i64> poison, <i64 2, i64 4>
- %V2I64_C2C = udiv <2 x i64> poison, <i64 2, i64 2>
-
%V1I16 = udiv <1 x i16> undef, undef
%V2I16 = udiv <2 x i16> undef, undef
%V4I16 = udiv <4 x i16> undef, undef
@@ -832,9 +821,6 @@ define i32 @urem() {
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = urem i16 undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = urem i32 undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = urem i64 undef, undef
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64_C2 = urem i64 poison, 2
-; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2I64_C2 = urem <2 x i64> poison, <i64 2, i64 4>
-; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64_C2C = urem <2 x i64> poison, splat (i64 2)
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1I16 = urem <1 x i16> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I16 = urem <2 x i16> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4I16 = urem <4 x i16> undef, undef
@@ -871,9 +857,6 @@ define i32 @urem() {
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I16 = urem i16 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I32 = urem i32 undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I64 = urem i64 undef, undef
-; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I64_C2 = urem i64 poison, 2
-; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2I64_C2 = urem <2 x i64> poison, <i64 2, i64 4>
-; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64_C2C = urem <2 x i64> poison, splat (i64 2)
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1I16 = urem <1 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I16 = urem <2 x i16> undef, undef
; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4I16 = urem <4 x i16> undef, undef
@@ -910,11 +893,6 @@ define i32 @urem() {
%I32 = urem i32 undef, undef
%I64 = urem i64 undef, undef
- ; UDIV by power of 2 constant
- %I64_C2 = urem i64 poison, 2
- %V2I64_C2 = urem <2 x i64> poison, <i64 2, i64 4>
- %V2I64_C2C = urem <2 x i64> poison, <i64 2, i64 2>
-
%V1I16 = urem <1 x i16> undef, undef
%V2I16 = urem <2 x i16> undef, undef
%V4I16 = urem <4 x i16> undef, undef
>From 57f3426dfeecffedbf5092c26a1b8dcc7cb0c36f Mon Sep 17 00:00:00 2001
From: bababuck <buchner.ryan at gmail.com>
Date: Wed, 4 Feb 2026 10:14:05 -0800
Subject: [PATCH 08/19] [RISCV] Precommit UDiv power of two test
---
.../SLPVectorizer/RISCV/load-binop-store.ll | 87 +++++++++++++++++++
1 file changed, 87 insertions(+)
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/load-binop-store.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/load-binop-store.ll
index 8c82c6ec8e7cb..7ba929ff3bd6d 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/load-binop-store.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/load-binop-store.ll
@@ -324,3 +324,90 @@ entry:
store i16 %a1, ptr %inc2, align 2
ret void
}
+
+define void @udiv_pow2(ptr %d, ptr %s) {
+; CHECK-LABEL: @udiv_pow2(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr [[S:%.*]], align 2
+; CHECK-NEXT: [[TMP1:%.*]] = udiv <2 x i16> [[TMP0]], <i16 2, i16 9>
+; CHECK-NEXT: store <2 x i16> [[TMP1]], ptr [[D:%.*]], align 2
+; CHECK-NEXT: ret void
+;
+; DEFAULT-LABEL: @udiv_pow2(
+; DEFAULT-NEXT: entry:
+; DEFAULT-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr [[S:%.*]], align 2
+; DEFAULT-NEXT: [[TMP1:%.*]] = udiv <2 x i16> [[TMP0]], <i16 2, i16 9>
+; DEFAULT-NEXT: store <2 x i16> [[TMP1]], ptr [[D:%.*]], align 2
+; DEFAULT-NEXT: ret void
+;
+entry:
+ %l0 = load i16, ptr %s
+ %s1 = getelementptr i16, ptr %s, i64 1
+ %l1 = load i16, ptr %s1
+
+ %a0 = udiv i16 %l0, 2
+ %a1 = udiv i16 %l1, 9
+
+ store i16 %a0, ptr %d
+ %d1 = getelementptr i16, ptr %d, i64 1
+ store i16 %a1, ptr %d1
+ ret void
+}
+
+define void @udiv_pow2_all_same(ptr %d, ptr %s) {
+; CHECK-LABEL: @udiv_pow2_all_same(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr [[S:%.*]], align 2
+; CHECK-NEXT: [[TMP2:%.*]] = udiv <2 x i16> [[TMP1]], splat (i16 2)
+; CHECK-NEXT: store <2 x i16> [[TMP2]], ptr [[D:%.*]], align 2
+; CHECK-NEXT: ret void
+;
+; DEFAULT-LABEL: @udiv_pow2_all_same(
+; DEFAULT-NEXT: entry:
+; DEFAULT-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr [[S:%.*]], align 2
+; DEFAULT-NEXT: [[TMP2:%.*]] = udiv <2 x i16> [[TMP1]], splat (i16 2)
+; DEFAULT-NEXT: store <2 x i16> [[TMP2]], ptr [[D:%.*]], align 2
+; DEFAULT-NEXT: ret void
+;
+entry:
+ %l0 = load i16, ptr %s
+ %s1 = getelementptr i16, ptr %s, i64 1
+ %l1 = load i16, ptr %s1
+
+ %a0 = udiv i16 %l0, 2
+ %a1 = udiv i16 %l1, 2
+
+ store i16 %a0, ptr %d
+ %d1 = getelementptr i16, ptr %d, i64 1
+ store i16 %a1, ptr %d1
+ ret void
+}
+
+define void @udiv_all_pow2(ptr %d, ptr %s) {
+; CHECK-LABEL: @udiv_all_pow2(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr [[S:%.*]], align 2
+; CHECK-NEXT: [[TMP1:%.*]] = udiv <2 x i16> [[TMP0]], <i16 2, i16 4>
+; CHECK-NEXT: store <2 x i16> [[TMP1]], ptr [[D:%.*]], align 2
+; CHECK-NEXT: ret void
+;
+; DEFAULT-LABEL: @udiv_all_pow2(
+; DEFAULT-NEXT: entry:
+; DEFAULT-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr [[S:%.*]], align 2
+; DEFAULT-NEXT: [[TMP1:%.*]] = udiv <2 x i16> [[TMP0]], <i16 2, i16 4>
+; DEFAULT-NEXT: store <2 x i16> [[TMP1]], ptr [[D:%.*]], align 2
+; DEFAULT-NEXT: ret void
+;
+entry:
+ %l0 = load i16, ptr %s
+ %s1 = getelementptr i16, ptr %s, i64 1
+ %l1 = load i16, ptr %s1
+
+ %a0 = udiv i16 %l0, 2
+ %a1 = udiv i16 %l1, 4
+
+ store i16 %a0, ptr %d
+ %d1 = getelementptr i16, ptr %d, i64 1
+ store i16 %a1, ptr %d1
+ ret void
+}
>From f0e56eab3c03dc207590aff52c71f3075b03e854 Mon Sep 17 00:00:00 2001
From: bababuck <buchner.ryan at gmail.com>
Date: Wed, 4 Feb 2026 10:18:29 -0800
Subject: [PATCH 09/19] [RISCV] Update tests
---
.../SLPVectorizer/RISCV/load-binop-store.ll | 50 ++++++++++++++-----
1 file changed, 38 insertions(+), 12 deletions(-)
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/load-binop-store.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/load-binop-store.ll
index 7ba929ff3bd6d..0c71c8cab439e 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/load-binop-store.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/load-binop-store.ll
@@ -325,19 +325,31 @@ entry:
ret void
}
+; Vector UDiv costs 7 (4 for the division, 3 to load constants)
+; Scalar UDiv costs 5, (4 for the div by 9, 1 for the div by 2
define void @udiv_pow2(ptr %d, ptr %s) {
; CHECK-LABEL: @udiv_pow2(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr [[S:%.*]], align 2
-; CHECK-NEXT: [[TMP1:%.*]] = udiv <2 x i16> [[TMP0]], <i16 2, i16 9>
-; CHECK-NEXT: store <2 x i16> [[TMP1]], ptr [[D:%.*]], align 2
+; CHECK-NEXT: [[L0:%.*]] = load i16, ptr [[S:%.*]], align 2
+; CHECK-NEXT: [[S1:%.*]] = getelementptr i16, ptr [[S]], i64 1
+; CHECK-NEXT: [[L1:%.*]] = load i16, ptr [[S1]], align 2
+; CHECK-NEXT: [[A0:%.*]] = udiv i16 [[L0]], 2
+; CHECK-NEXT: [[A1:%.*]] = udiv i16 [[L1]], 9
+; CHECK-NEXT: store i16 [[A0]], ptr [[D:%.*]], align 2
+; CHECK-NEXT: [[D1:%.*]] = getelementptr i16, ptr [[D]], i64 1
+; CHECK-NEXT: store i16 [[A1]], ptr [[D1]], align 2
; CHECK-NEXT: ret void
;
; DEFAULT-LABEL: @udiv_pow2(
; DEFAULT-NEXT: entry:
-; DEFAULT-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr [[S:%.*]], align 2
-; DEFAULT-NEXT: [[TMP1:%.*]] = udiv <2 x i16> [[TMP0]], <i16 2, i16 9>
-; DEFAULT-NEXT: store <2 x i16> [[TMP1]], ptr [[D:%.*]], align 2
+; DEFAULT-NEXT: [[L0:%.*]] = load i16, ptr [[S:%.*]], align 2
+; DEFAULT-NEXT: [[S1:%.*]] = getelementptr i16, ptr [[S]], i64 1
+; DEFAULT-NEXT: [[L1:%.*]] = load i16, ptr [[S1]], align 2
+; DEFAULT-NEXT: [[A0:%.*]] = udiv i16 [[L0]], 2
+; DEFAULT-NEXT: [[A1:%.*]] = udiv i16 [[L1]], 9
+; DEFAULT-NEXT: store i16 [[A0]], ptr [[D:%.*]], align 2
+; DEFAULT-NEXT: [[D1:%.*]] = getelementptr i16, ptr [[D]], i64 1
+; DEFAULT-NEXT: store i16 [[A1]], ptr [[D1]], align 2
; DEFAULT-NEXT: ret void
;
entry:
@@ -354,6 +366,8 @@ entry:
ret void
}
+; Vector UDiv costs 1 since shift by single constant
+; Scalar UDiv costs 2 since can be implemented as 2 shifts
define void @udiv_pow2_all_same(ptr %d, ptr %s) {
; CHECK-LABEL: @udiv_pow2_all_same(
; CHECK-NEXT: entry:
@@ -383,19 +397,31 @@ entry:
ret void
}
+; Vector UDiv costs 4 (1 for the shift, 3 to load constants)
+; Scalar UDiv cost 2 since can be implemented as 2 shifts
define void @udiv_all_pow2(ptr %d, ptr %s) {
; CHECK-LABEL: @udiv_all_pow2(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr [[S:%.*]], align 2
-; CHECK-NEXT: [[TMP1:%.*]] = udiv <2 x i16> [[TMP0]], <i16 2, i16 4>
-; CHECK-NEXT: store <2 x i16> [[TMP1]], ptr [[D:%.*]], align 2
+; CHECK-NEXT: [[L0:%.*]] = load i16, ptr [[S:%.*]], align 2
+; CHECK-NEXT: [[S1:%.*]] = getelementptr i16, ptr [[S]], i64 1
+; CHECK-NEXT: [[L1:%.*]] = load i16, ptr [[S1]], align 2
+; CHECK-NEXT: [[A0:%.*]] = udiv i16 [[L0]], 2
+; CHECK-NEXT: [[A1:%.*]] = udiv i16 [[L1]], 4
+; CHECK-NEXT: store i16 [[A0]], ptr [[D:%.*]], align 2
+; CHECK-NEXT: [[D1:%.*]] = getelementptr i16, ptr [[D]], i64 1
+; CHECK-NEXT: store i16 [[A1]], ptr [[D1]], align 2
; CHECK-NEXT: ret void
;
; DEFAULT-LABEL: @udiv_all_pow2(
; DEFAULT-NEXT: entry:
-; DEFAULT-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr [[S:%.*]], align 2
-; DEFAULT-NEXT: [[TMP1:%.*]] = udiv <2 x i16> [[TMP0]], <i16 2, i16 4>
-; DEFAULT-NEXT: store <2 x i16> [[TMP1]], ptr [[D:%.*]], align 2
+; DEFAULT-NEXT: [[L0:%.*]] = load i16, ptr [[S:%.*]], align 2
+; DEFAULT-NEXT: [[S1:%.*]] = getelementptr i16, ptr [[S]], i64 1
+; DEFAULT-NEXT: [[L1:%.*]] = load i16, ptr [[S1]], align 2
+; DEFAULT-NEXT: [[A0:%.*]] = udiv i16 [[L0]], 2
+; DEFAULT-NEXT: [[A1:%.*]] = udiv i16 [[L1]], 4
+; DEFAULT-NEXT: store i16 [[A0]], ptr [[D:%.*]], align 2
+; DEFAULT-NEXT: [[D1:%.*]] = getelementptr i16, ptr [[D]], i64 1
+; DEFAULT-NEXT: store i16 [[A1]], ptr [[D1]], align 2
; DEFAULT-NEXT: ret void
;
entry:
>From dd1bdf73cd164749ec8cd12db621ad2bae94611c Mon Sep 17 00:00:00 2001
From: bababuck <buchner.ryan at gmail.com>
Date: Wed, 4 Feb 2026 10:21:35 -0800
Subject: [PATCH 10/19] [AArch64] Update tests
---
llvm/test/Analysis/CostModel/AArch64/div.ll | 92 +++++++++----------
llvm/test/Analysis/CostModel/AArch64/rem.ll | 92 +++++++++----------
.../Analysis/CostModel/AArch64/sve-div.ll | 72 +++++++--------
.../Analysis/CostModel/AArch64/sve-rem.ll | 72 +++++++--------
4 files changed, 164 insertions(+), 164 deletions(-)
diff --git a/llvm/test/Analysis/CostModel/AArch64/div.ll b/llvm/test/Analysis/CostModel/AArch64/div.ll
index 3a2358dba51b2..10d0c82842bbf 100644
--- a/llvm/test/Analysis/CostModel/AArch64/div.ll
+++ b/llvm/test/Analysis/CostModel/AArch64/div.ll
@@ -578,29 +578,29 @@ define void @sdiv_constpow2() {
define void @udiv_constpow2() {
; CHECK-LABEL: 'udiv_constpow2'
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %I128 = udiv i128 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = udiv i64 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = udiv <2 x i64> undef, <i64 8, i64 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = udiv <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V8i64 = udiv <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = udiv i32 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i32 = udiv <2 x i32> undef, <i32 2, i32 4>
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = udiv <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = udiv <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V16i32 = udiv <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I16 = udiv i16 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i16 = udiv <2 x i16> undef, <i16 2, i16 4>
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i16 = udiv <4 x i16> undef, <i16 2, i16 4, i16 8, i16 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = udiv <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = udiv <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V32i16 = udiv <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = udiv i8 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i8 = udiv <2 x i8> undef, <i8 2, i8 4>
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i8 = udiv <4 x i8> undef, <i8 2, i8 4, i8 8, i8 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i8 = udiv <8 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = udiv <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = udiv <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V64i8 = udiv <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:10 CodeSize:4 Lat:4 SizeLat:4 for: %I128 = udiv i128 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %I64 = udiv i64 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = udiv <2 x i64> undef, <i64 8, i64 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:64 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = udiv <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:128 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = udiv <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
+; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = udiv i32 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V2i32 = udiv <2 x i32> undef, <i32 2, i32 4>
+; CHECK-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = udiv <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:12 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = udiv <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; CHECK-NEXT: Cost Model: Found costs of RThru:24 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = udiv <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %I16 = udiv i16 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V2i16 = udiv <2 x i16> undef, <i16 2, i16 4>
+; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V4i16 = udiv <4 x i16> undef, <i16 2, i16 4, i16 8, i16 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = udiv <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; CHECK-NEXT: Cost Model: Found costs of RThru:12 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = udiv <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; CHECK-NEXT: Cost Model: Found costs of RThru:24 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = udiv <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = udiv i8 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V2i8 = udiv <2 x i8> undef, <i8 2, i8 4>
+; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V4i8 = udiv <4 x i8> undef, <i8 2, i8 4, i8 8, i8 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V8i8 = udiv <8 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = udiv <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:12 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = udiv <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:24 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = udiv <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
%I128 = udiv i128 undef, 16
@@ -694,29 +694,29 @@ define void @sdiv_uniformconstpow2() {
define void @udiv_uniformconstpow2() {
; CHECK-LABEL: 'udiv_uniformconstpow2'
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %I128 = udiv i128 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = udiv i64 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = udiv <2 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = udiv <4 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V8i64 = udiv <8 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = udiv i32 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i32 = udiv <2 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = udiv <4 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = udiv <8 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V16i32 = udiv <16 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I16 = udiv i16 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i16 = udiv <2 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i16 = udiv <4 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = udiv <8 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = udiv <16 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V32i16 = udiv <32 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = udiv i8 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i8 = udiv <2 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i8 = udiv <4 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i8 = udiv <8 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = udiv <16 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = udiv <32 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V64i8 = udiv <64 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:10 CodeSize:4 Lat:4 SizeLat:4 for: %I128 = udiv i128 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %I64 = udiv i64 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = udiv <2 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:64 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = udiv <4 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:128 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = udiv <8 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = udiv i32 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V2i32 = udiv <2 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = udiv <4 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:12 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = udiv <8 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:24 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = udiv <16 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %I16 = udiv i16 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V2i16 = udiv <2 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V4i16 = udiv <4 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = udiv <8 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:12 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = udiv <16 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:24 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = udiv <32 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = udiv i8 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V2i8 = udiv <2 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V4i8 = udiv <4 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V8i8 = udiv <8 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = udiv <16 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:12 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = udiv <32 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:24 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = udiv <64 x i8> undef, splat (i8 16)
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
%I128 = udiv i128 undef, 16
diff --git a/llvm/test/Analysis/CostModel/AArch64/rem.ll b/llvm/test/Analysis/CostModel/AArch64/rem.ll
index 2fa62f1705911..288cf9e4b2602 100644
--- a/llvm/test/Analysis/CostModel/AArch64/rem.ll
+++ b/llvm/test/Analysis/CostModel/AArch64/rem.ll
@@ -578,29 +578,29 @@ define void @srem_constpow2() {
define void @urem_constpow2() {
; CHECK-LABEL: 'urem_constpow2'
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %I128 = urem i128 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = urem i64 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = urem <2 x i64> undef, <i64 8, i64 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = urem <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V8i64 = urem <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = urem i32 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i32 = urem <2 x i32> undef, <i32 2, i32 4>
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = urem <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = urem <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V16i32 = urem <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I16 = urem i16 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i16 = urem <2 x i16> undef, <i16 2, i16 4>
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i16 = urem <4 x i16> undef, <i16 2, i16 4, i16 8, i16 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = urem <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = urem <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V32i16 = urem <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = urem i8 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i8 = urem <2 x i8> undef, <i8 2, i8 4>
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i8 = urem <4 x i8> undef, <i8 2, i8 4, i8 8, i8 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i8 = urem <8 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = urem <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = urem <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V64i8 = urem <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %I128 = urem i128 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = urem i64 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:47 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = urem <2 x i64> undef, <i64 8, i64 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:94 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = urem <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:188 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = urem <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
+; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = urem i32 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V2i32 = urem <2 x i32> undef, <i32 2, i32 4>
+; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = urem <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = urem <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; CHECK-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = urem <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %I16 = urem i16 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V2i16 = urem <2 x i16> undef, <i16 2, i16 4>
+; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V4i16 = urem <4 x i16> undef, <i16 2, i16 4, i16 8, i16 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = urem <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = urem <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; CHECK-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = urem <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = urem i8 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V2i8 = urem <2 x i8> undef, <i8 2, i8 4>
+; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V4i8 = urem <4 x i8> undef, <i8 2, i8 4, i8 8, i8 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V8i8 = urem <8 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = urem <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = urem <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = urem <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
%I128 = urem i128 undef, 16
@@ -694,29 +694,29 @@ define void @srem_uniformconstpow2() {
define void @urem_uniformconstpow2() {
; CHECK-LABEL: 'urem_uniformconstpow2'
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %I128 = urem i128 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = urem i64 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = urem <2 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = urem <4 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V8i64 = urem <8 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = urem i32 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i32 = urem <2 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = urem <4 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = urem <8 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V16i32 = urem <16 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I16 = urem i16 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i16 = urem <2 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i16 = urem <4 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = urem <8 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = urem <16 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V32i16 = urem <32 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = urem i8 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i8 = urem <2 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i8 = urem <4 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i8 = urem <8 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = urem <16 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = urem <32 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V64i8 = urem <64 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %I128 = urem i128 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = urem i64 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:47 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = urem <2 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:94 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = urem <4 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:188 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = urem <8 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = urem i32 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V2i32 = urem <2 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = urem <4 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = urem <8 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = urem <16 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %I16 = urem i16 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V2i16 = urem <2 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V4i16 = urem <4 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = urem <8 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = urem <16 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = urem <32 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = urem i8 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V2i8 = urem <2 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V4i8 = urem <4 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V8i8 = urem <8 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = urem <16 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = urem <32 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = urem <64 x i8> undef, splat (i8 16)
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
%I128 = urem i128 undef, 16
diff --git a/llvm/test/Analysis/CostModel/AArch64/sve-div.ll b/llvm/test/Analysis/CostModel/AArch64/sve-div.ll
index 84a9ca0fab6d8..6341a697f0755 100644
--- a/llvm/test/Analysis/CostModel/AArch64/sve-div.ll
+++ b/llvm/test/Analysis/CostModel/AArch64/sve-div.ll
@@ -408,42 +408,42 @@ define void @sdiv_uniformconstpow2() {
define void @udiv_uniformconstpow2() {
; CHECK-LABEL: 'udiv_uniformconstpow2'
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = udiv <2 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = udiv <4 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V8i64 = udiv <8 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i32 = udiv <2 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = udiv <4 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = udiv <8 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V16i32 = udiv <16 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i16 = udiv <2 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i16 = udiv <4 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = udiv <8 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = udiv <16 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V32i16 = udiv <32 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i8 = udiv <2 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i8 = udiv <4 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i8 = udiv <8 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = udiv <16 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = udiv <32 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V64i8 = udiv <64 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV2i64 = udiv <vscale x 2 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %NV4i64 = udiv <vscale x 4 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV8i64 = udiv <vscale x 8 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV2i32 = udiv <vscale x 2 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV4i32 = udiv <vscale x 4 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %NV8i32 = udiv <vscale x 8 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV16i32 = udiv <vscale x 16 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV2i16 = udiv <vscale x 2 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV4i16 = udiv <vscale x 4 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV8i16 = udiv <vscale x 8 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %NV16i16 = udiv <vscale x 16 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV32i16 = udiv <vscale x 32 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV2i8 = udiv <vscale x 2 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV4i8 = udiv <vscale x 4 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV8i8 = udiv <vscale x 8 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV16i8 = udiv <vscale x 16 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %NV32i8 = udiv <vscale x 32 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV64i8 = udiv <vscale x 64 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = udiv <2 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:12 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = udiv <4 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:24 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = udiv <8 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V2i32 = udiv <2 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = udiv <4 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:12 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = udiv <8 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:24 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = udiv <16 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V2i16 = udiv <2 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V4i16 = udiv <4 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = udiv <8 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:12 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = udiv <16 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:24 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = udiv <32 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V2i8 = udiv <2 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V4i8 = udiv <4 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V8i8 = udiv <8 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = udiv <16 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:12 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = udiv <32 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:24 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = udiv <64 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV2i64 = udiv <vscale x 2 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %NV4i64 = udiv <vscale x 4 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %NV8i64 = udiv <vscale x 8 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV2i32 = udiv <vscale x 2 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV4i32 = udiv <vscale x 4 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %NV8i32 = udiv <vscale x 8 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %NV16i32 = udiv <vscale x 16 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV2i16 = udiv <vscale x 2 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV4i16 = udiv <vscale x 4 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV8i16 = udiv <vscale x 8 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %NV16i16 = udiv <vscale x 16 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %NV32i16 = udiv <vscale x 32 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV2i8 = udiv <vscale x 2 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV4i8 = udiv <vscale x 4 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV8i8 = udiv <vscale x 8 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV16i8 = udiv <vscale x 16 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %NV32i8 = udiv <vscale x 32 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %NV64i8 = udiv <vscale x 64 x i8> undef, splat (i8 16)
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
%V2i64 = udiv <2 x i64> undef, splat (i64 16)
diff --git a/llvm/test/Analysis/CostModel/AArch64/sve-rem.ll b/llvm/test/Analysis/CostModel/AArch64/sve-rem.ll
index eac8b66bcd216..0f1915c9f2128 100644
--- a/llvm/test/Analysis/CostModel/AArch64/sve-rem.ll
+++ b/llvm/test/Analysis/CostModel/AArch64/sve-rem.ll
@@ -410,43 +410,43 @@ define void @srem_uniformconstpow2() {
define void @urem_uniformconstpow2() {
; CHECK-LABEL: 'urem_uniformconstpow2'
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = urem <2 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = urem <4 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V8i64 = urem <8 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i32 = urem <2 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = urem <4 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = urem <8 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V16i32 = urem <16 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i16 = urem <2 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i16 = urem <4 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = urem <8 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = urem <16 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V32i16 = urem <32 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i8 = urem <2 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i8 = urem <4 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i8 = urem <8 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = urem <16 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = urem <32 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V64i8 = urem <64 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = urem <2 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = urem <4 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = urem <8 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V2i32 = urem <2 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = urem <4 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = urem <8 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = urem <16 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V2i16 = urem <2 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V4i16 = urem <4 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = urem <8 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = urem <16 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = urem <32 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V2i8 = urem <2 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V4i8 = urem <4 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V8i8 = urem <8 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = urem <16 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = urem <32 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = urem <64 x i8> undef, splat (i8 16)
; CHECK-NEXT: Cost Model: Found costs of RThru:Invalid CodeSize:4 Lat:4 SizeLat:4 for: %NV2i128 = urem <vscale x 2 x i128> undef, splat (i128 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV2i64 = urem <vscale x 2 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %NV4i64 = urem <vscale x 4 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV8i64 = urem <vscale x 8 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV2i32 = urem <vscale x 2 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV4i32 = urem <vscale x 4 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %NV8i32 = urem <vscale x 8 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV16i32 = urem <vscale x 16 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV2i16 = urem <vscale x 2 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV4i16 = urem <vscale x 4 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV8i16 = urem <vscale x 8 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %NV16i16 = urem <vscale x 16 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV32i16 = urem <vscale x 32 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV2i8 = urem <vscale x 2 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV4i8 = urem <vscale x 4 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV8i8 = urem <vscale x 8 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV16i8 = urem <vscale x 16 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %NV32i8 = urem <vscale x 32 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV64i8 = urem <vscale x 64 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %NV2i64 = urem <vscale x 2 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:12 CodeSize:4 Lat:4 SizeLat:4 for: %NV4i64 = urem <vscale x 4 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:24 CodeSize:4 Lat:4 SizeLat:4 for: %NV8i64 = urem <vscale x 8 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %NV2i32 = urem <vscale x 2 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %NV4i32 = urem <vscale x 4 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:12 CodeSize:4 Lat:4 SizeLat:4 for: %NV8i32 = urem <vscale x 8 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:24 CodeSize:4 Lat:4 SizeLat:4 for: %NV16i32 = urem <vscale x 16 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %NV2i16 = urem <vscale x 2 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %NV4i16 = urem <vscale x 4 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %NV8i16 = urem <vscale x 8 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:12 CodeSize:4 Lat:4 SizeLat:4 for: %NV16i16 = urem <vscale x 16 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:24 CodeSize:4 Lat:4 SizeLat:4 for: %NV32i16 = urem <vscale x 32 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %NV2i8 = urem <vscale x 2 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %NV4i8 = urem <vscale x 4 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %NV8i8 = urem <vscale x 8 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %NV16i8 = urem <vscale x 16 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:12 CodeSize:4 Lat:4 SizeLat:4 for: %NV32i8 = urem <vscale x 32 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:24 CodeSize:4 Lat:4 SizeLat:4 for: %NV64i8 = urem <vscale x 64 x i8> undef, splat (i8 16)
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
%V2i64 = urem <2 x i64> undef, splat (i64 16)
>From 411ab79d3f6a1d9908063dabb3e8a9f4a5901f82 Mon Sep 17 00:00:00 2001
From: bababuck <buchner.ryan at gmail.com>
Date: Wed, 4 Feb 2026 10:24:23 -0800
Subject: [PATCH 11/19] [X86] Update tests
---
llvm/test/Analysis/CostModel/X86/div.ll | 362 +++++++++++-------------
llvm/test/Analysis/CostModel/X86/rem.ll | 284 ++++++++++++-------
2 files changed, 342 insertions(+), 304 deletions(-)
diff --git a/llvm/test/Analysis/CostModel/X86/div.ll b/llvm/test/Analysis/CostModel/X86/div.ll
index 3af5b2dd217da..c76398ecf9edc 100644
--- a/llvm/test/Analysis/CostModel/X86/div.ll
+++ b/llvm/test/Analysis/CostModel/X86/div.ll
@@ -769,138 +769,100 @@ define i32 @sdiv_constpow2() {
}
define i32 @udiv_constpow2() {
-; SSE2-LABEL: 'udiv_constpow2'
-; SSE2-NEXT: Cost Model: Found costs of 1 for: %I64 = udiv i64 undef, 16
-; SSE2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:5 Lat:6 SizeLat:7 for: %V2i64 = udiv <2 x i64> undef, <i64 8, i64 16>
-; SSE2-NEXT: Cost Model: Found costs of RThru:8 CodeSize:10 Lat:12 SizeLat:14 for: %V4i64 = udiv <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
-; SSE2-NEXT: Cost Model: Found costs of RThru:16 CodeSize:20 Lat:24 SizeLat:28 for: %V8i64 = udiv <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
-; SSE2-NEXT: Cost Model: Found costs of 1 for: %I32 = udiv i32 undef, 16
-; SSE2-NEXT: Cost Model: Found costs of RThru:12 CodeSize:15 Lat:12 SizeLat:19 for: %V4i32 = udiv <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
-; SSE2-NEXT: Cost Model: Found costs of RThru:24 CodeSize:30 Lat:24 SizeLat:38 for: %V8i32 = udiv <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; SSE2-NEXT: Cost Model: Found costs of RThru:48 CodeSize:60 Lat:48 SizeLat:76 for: %V16i32 = udiv <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; SSE2-NEXT: Cost Model: Found costs of 1 for: %I16 = udiv i16 undef, 16
-; SSE2-NEXT: Cost Model: Found costs of RThru:16 CodeSize:31 Lat:19 SizeLat:31 for: %V8i16 = udiv <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; SSE2-NEXT: Cost Model: Found costs of RThru:32 CodeSize:62 Lat:38 SizeLat:62 for: %V16i16 = udiv <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; SSE2-NEXT: Cost Model: Found costs of RThru:64 CodeSize:124 Lat:76 SizeLat:124 for: %V32i16 = udiv <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; SSE2-NEXT: Cost Model: Found costs of 1 for: %I8 = udiv i8 undef, 16
-; SSE2-NEXT: Cost Model: Found costs of RThru:14 CodeSize:27 Lat:28 SizeLat:30 for: %V16i8 = udiv <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; SSE2-NEXT: Cost Model: Found costs of RThru:28 CodeSize:54 Lat:56 SizeLat:60 for: %V32i8 = udiv <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; SSE2-NEXT: Cost Model: Found costs of RThru:56 CodeSize:108 Lat:112 SizeLat:120 for: %V64i8 = udiv <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; SSE2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
-;
-; SSE42-LABEL: 'udiv_constpow2'
-; SSE42-NEXT: Cost Model: Found costs of 1 for: %I64 = udiv i64 undef, 16
-; SSE42-NEXT: Cost Model: Found costs of RThru:4 CodeSize:5 Lat:6 SizeLat:7 for: %V2i64 = udiv <2 x i64> undef, <i64 8, i64 16>
-; SSE42-NEXT: Cost Model: Found costs of RThru:8 CodeSize:10 Lat:12 SizeLat:14 for: %V4i64 = udiv <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
-; SSE42-NEXT: Cost Model: Found costs of RThru:16 CodeSize:20 Lat:24 SizeLat:28 for: %V8i64 = udiv <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
-; SSE42-NEXT: Cost Model: Found costs of 1 for: %I32 = udiv i32 undef, 16
-; SSE42-NEXT: Cost Model: Found costs of RThru:16 CodeSize:15 Lat:17 SizeLat:19 for: %V4i32 = udiv <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
-; SSE42-NEXT: Cost Model: Found costs of RThru:32 CodeSize:30 Lat:34 SizeLat:38 for: %V8i32 = udiv <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; SSE42-NEXT: Cost Model: Found costs of RThru:64 CodeSize:60 Lat:68 SizeLat:76 for: %V16i32 = udiv <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; SSE42-NEXT: Cost Model: Found costs of 1 for: %I16 = udiv i16 undef, 16
-; SSE42-NEXT: Cost Model: Found costs of RThru:22 CodeSize:23 Lat:26 SizeLat:27 for: %V8i16 = udiv <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; SSE42-NEXT: Cost Model: Found costs of RThru:44 CodeSize:46 Lat:52 SizeLat:54 for: %V16i16 = udiv <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; SSE42-NEXT: Cost Model: Found costs of RThru:88 CodeSize:92 Lat:104 SizeLat:108 for: %V32i16 = udiv <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; SSE42-NEXT: Cost Model: Found costs of 1 for: %I8 = udiv i8 undef, 16
-; SSE42-NEXT: Cost Model: Found costs of RThru:16 CodeSize:18 Lat:27 SizeLat:24 for: %V16i8 = udiv <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; SSE42-NEXT: Cost Model: Found costs of RThru:32 CodeSize:36 Lat:54 SizeLat:48 for: %V32i8 = udiv <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; SSE42-NEXT: Cost Model: Found costs of RThru:64 CodeSize:72 Lat:108 SizeLat:96 for: %V64i8 = udiv <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; SSE42-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
+; SSE-LABEL: 'udiv_constpow2'
+; SSE-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = udiv i64 undef, 16
+; SSE-NEXT: Cost Model: Found costs of RThru:40 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = udiv <2 x i64> undef, <i64 8, i64 16>
+; SSE-NEXT: Cost Model: Found costs of RThru:80 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = udiv <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
+; SSE-NEXT: Cost Model: Found costs of RThru:160 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = udiv <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
+; SSE-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = udiv i32 undef, 16
+; SSE-NEXT: Cost Model: Found costs of RThru:15 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = udiv <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
+; SSE-NEXT: Cost Model: Found costs of RThru:30 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = udiv <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; SSE-NEXT: Cost Model: Found costs of RThru:60 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = udiv <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; SSE-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I16 = udiv i16 undef, 16
+; SSE-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = udiv <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; SSE-NEXT: Cost Model: Found costs of RThru:12 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = udiv <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; SSE-NEXT: Cost Model: Found costs of RThru:24 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = udiv <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; SSE-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = udiv i8 undef, 16
+; SSE-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = udiv <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; SSE-NEXT: Cost Model: Found costs of RThru:28 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = udiv <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; SSE-NEXT: Cost Model: Found costs of RThru:56 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = udiv <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; SSE-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX1-LABEL: 'udiv_constpow2'
-; AVX1-NEXT: Cost Model: Found costs of 1 for: %I64 = udiv i64 undef, 16
-; AVX1-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:6 for: %V2i64 = udiv <2 x i64> undef, <i64 8, i64 16>
-; AVX1-NEXT: Cost Model: Found costs of RThru:6 CodeSize:11 Lat:7 SizeLat:15 for: %V4i64 = udiv <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
-; AVX1-NEXT: Cost Model: Found costs of RThru:12 CodeSize:22 Lat:14 SizeLat:30 for: %V8i64 = udiv <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
-; AVX1-NEXT: Cost Model: Found costs of 1 for: %I32 = udiv i32 undef, 16
-; AVX1-NEXT: Cost Model: Found costs of RThru:6 CodeSize:12 Lat:7 SizeLat:16 for: %V4i32 = udiv <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
-; AVX1-NEXT: Cost Model: Found costs of RThru:14 CodeSize:26 Lat:14 SizeLat:34 for: %V8i32 = udiv <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; AVX1-NEXT: Cost Model: Found costs of RThru:28 CodeSize:52 Lat:28 SizeLat:68 for: %V16i32 = udiv <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; AVX1-NEXT: Cost Model: Found costs of 1 for: %I16 = udiv i16 undef, 16
-; AVX1-NEXT: Cost Model: Found costs of RThru:13 CodeSize:14 Lat:16 SizeLat:22 for: %V8i16 = udiv <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; AVX1-NEXT: Cost Model: Found costs of RThru:28 CodeSize:31 Lat:30 SizeLat:48 for: %V16i16 = udiv <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; AVX1-NEXT: Cost Model: Found costs of RThru:56 CodeSize:62 Lat:60 SizeLat:96 for: %V32i16 = udiv <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; AVX1-NEXT: Cost Model: Found costs of 1 for: %I8 = udiv i8 undef, 16
-; AVX1-NEXT: Cost Model: Found costs of RThru:11 CodeSize:12 Lat:27 SizeLat:18 for: %V16i8 = udiv <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; AVX1-NEXT: Cost Model: Found costs of RThru:23 CodeSize:30 Lat:23 SizeLat:43 for: %V32i8 = udiv <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; AVX1-NEXT: Cost Model: Found costs of RThru:46 CodeSize:60 Lat:46 SizeLat:86 for: %V64i8 = udiv <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; AVX1-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = udiv i64 undef, 16
+; AVX1-NEXT: Cost Model: Found costs of RThru:40 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = udiv <2 x i64> undef, <i64 8, i64 16>
+; AVX1-NEXT: Cost Model: Found costs of RThru:80 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = udiv <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
+; AVX1-NEXT: Cost Model: Found costs of RThru:160 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = udiv <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
+; AVX1-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = udiv i32 undef, 16
+; AVX1-NEXT: Cost Model: Found costs of RThru:15 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = udiv <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
+; AVX1-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = udiv <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; AVX1-NEXT: Cost Model: Found costs of RThru:64 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = udiv <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; AVX1-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I16 = udiv i16 undef, 16
+; AVX1-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = udiv <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; AVX1-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = udiv <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; AVX1-NEXT: Cost Model: Found costs of RThru:28 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = udiv <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; AVX1-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = udiv i8 undef, 16
+; AVX1-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = udiv <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; AVX1-NEXT: Cost Model: Found costs of RThru:30 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = udiv <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; AVX1-NEXT: Cost Model: Found costs of RThru:60 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = udiv <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
; AVX1-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX2-LABEL: 'udiv_constpow2'
-; AVX2-NEXT: Cost Model: Found costs of 1 for: %I64 = udiv i64 undef, 16
-; AVX2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:3 SizeLat:1 for: %V2i64 = udiv <2 x i64> undef, <i64 8, i64 16>
-; AVX2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:4 SizeLat:2 for: %V4i64 = udiv <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
-; AVX2-NEXT: Cost Model: Found costs of RThru:8 CodeSize:2 Lat:8 SizeLat:4 for: %V8i64 = udiv <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
-; AVX2-NEXT: Cost Model: Found costs of 1 for: %I32 = udiv i32 undef, 16
-; AVX2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:3 SizeLat:3 for: %V4i32 = udiv <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
-; AVX2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:4 SizeLat:3 for: %V8i32 = udiv <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; AVX2-NEXT: Cost Model: Found costs of RThru:8 CodeSize:2 Lat:8 SizeLat:6 for: %V16i32 = udiv <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; AVX2-NEXT: Cost Model: Found costs of 1 for: %I16 = udiv i16 undef, 16
-; AVX2-NEXT: Cost Model: Found costs of RThru:5 CodeSize:5 Lat:11 SizeLat:10 for: %V8i16 = udiv <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; AVX2-NEXT: Cost Model: Found costs of RThru:8 CodeSize:10 Lat:10 SizeLat:14 for: %V16i16 = udiv <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; AVX2-NEXT: Cost Model: Found costs of RThru:16 CodeSize:20 Lat:20 SizeLat:28 for: %V32i16 = udiv <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; AVX2-NEXT: Cost Model: Found costs of 1 for: %I8 = udiv i8 undef, 16
-; AVX2-NEXT: Cost Model: Found costs of RThru:6 CodeSize:12 Lat:27 SizeLat:18 for: %V16i8 = udiv <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; AVX2-NEXT: Cost Model: Found costs of RThru:8 CodeSize:12 Lat:30 SizeLat:24 for: %V32i8 = udiv <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; AVX2-NEXT: Cost Model: Found costs of RThru:16 CodeSize:24 Lat:60 SizeLat:48 for: %V64i8 = udiv <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; AVX2-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = udiv i64 undef, 16
+; AVX2-NEXT: Cost Model: Found costs of RThru:40 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = udiv <2 x i64> undef, <i64 8, i64 16>
+; AVX2-NEXT: Cost Model: Found costs of RThru:80 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = udiv <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
+; AVX2-NEXT: Cost Model: Found costs of RThru:160 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = udiv <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
+; AVX2-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = udiv i32 undef, 16
+; AVX2-NEXT: Cost Model: Found costs of RThru:15 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = udiv <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
+; AVX2-NEXT: Cost Model: Found costs of RThru:15 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = udiv <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; AVX2-NEXT: Cost Model: Found costs of RThru:30 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = udiv <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; AVX2-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I16 = udiv i16 undef, 16
+; AVX2-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = udiv <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; AVX2-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = udiv <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; AVX2-NEXT: Cost Model: Found costs of RThru:12 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = udiv <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; AVX2-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = udiv i8 undef, 16
+; AVX2-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = udiv <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; AVX2-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = udiv <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; AVX2-NEXT: Cost Model: Found costs of RThru:28 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = udiv <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
; AVX2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX512F-LABEL: 'udiv_constpow2'
-; AVX512F-NEXT: Cost Model: Found costs of 1 for: %I64 = udiv i64 undef, 16
-; AVX512F-NEXT: Cost Model: Found costs of 1 for: %V2i64 = udiv <2 x i64> undef, <i64 8, i64 16>
-; AVX512F-NEXT: Cost Model: Found costs of 1 for: %V4i64 = udiv <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
-; AVX512F-NEXT: Cost Model: Found costs of 1 for: %V8i64 = udiv <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
-; AVX512F-NEXT: Cost Model: Found costs of 1 for: %I32 = udiv i32 undef, 16
-; AVX512F-NEXT: Cost Model: Found costs of 1 for: %V4i32 = udiv <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
-; AVX512F-NEXT: Cost Model: Found costs of 1 for: %V8i32 = udiv <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; AVX512F-NEXT: Cost Model: Found costs of 1 for: %V16i32 = udiv <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; AVX512F-NEXT: Cost Model: Found costs of 1 for: %I16 = udiv i16 undef, 16
-; AVX512F-NEXT: Cost Model: Found costs of RThru:5 CodeSize:5 Lat:11 SizeLat:10 for: %V8i16 = udiv <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; AVX512F-NEXT: Cost Model: Found costs of RThru:8 CodeSize:10 Lat:10 SizeLat:14 for: %V16i16 = udiv <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; AVX512F-NEXT: Cost Model: Found costs of RThru:11 CodeSize:11 Lat:16 SizeLat:15 for: %V32i16 = udiv <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; AVX512F-NEXT: Cost Model: Found costs of 1 for: %I8 = udiv i8 undef, 16
-; AVX512F-NEXT: Cost Model: Found costs of RThru:6 CodeSize:12 Lat:27 SizeLat:18 for: %V16i8 = udiv <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; AVX512F-NEXT: Cost Model: Found costs of RThru:8 CodeSize:12 Lat:30 SizeLat:24 for: %V32i8 = udiv <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; AVX512F-NEXT: Cost Model: Found costs of RThru:15 CodeSize:30 Lat:19 SizeLat:36 for: %V64i8 = udiv <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; AVX512F-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = udiv i64 undef, 16
+; AVX512F-NEXT: Cost Model: Found costs of RThru:40 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = udiv <2 x i64> undef, <i64 8, i64 16>
+; AVX512F-NEXT: Cost Model: Found costs of RThru:80 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = udiv <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
+; AVX512F-NEXT: Cost Model: Found costs of RThru:160 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = udiv <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
+; AVX512F-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = udiv i32 undef, 16
+; AVX512F-NEXT: Cost Model: Found costs of RThru:15 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = udiv <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
+; AVX512F-NEXT: Cost Model: Found costs of RThru:15 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = udiv <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; AVX512F-NEXT: Cost Model: Found costs of RThru:15 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = udiv <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; AVX512F-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I16 = udiv i16 undef, 16
+; AVX512F-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = udiv <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; AVX512F-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = udiv <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; AVX512F-NEXT: Cost Model: Found costs of RThru:12 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = udiv <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; AVX512F-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = udiv i8 undef, 16
+; AVX512F-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = udiv <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; AVX512F-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = udiv <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; AVX512F-NEXT: Cost Model: Found costs of RThru:28 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = udiv <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
; AVX512F-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX512BW-LABEL: 'udiv_constpow2'
-; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %I64 = udiv i64 undef, 16
-; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %V2i64 = udiv <2 x i64> undef, <i64 8, i64 16>
-; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %V4i64 = udiv <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
-; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %V8i64 = udiv <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
-; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %I32 = udiv i32 undef, 16
-; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %V4i32 = udiv <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
-; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %V8i32 = udiv <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %V16i32 = udiv <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %I16 = udiv i16 undef, 16
-; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %V8i16 = udiv <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %V16i16 = udiv <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %V32i16 = udiv <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %I8 = udiv i8 undef, 16
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:4 CodeSize:4 Lat:8 SizeLat:5 for: %V16i8 = udiv <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:4 CodeSize:12 Lat:30 SizeLat:18 for: %V32i8 = udiv <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:7 CodeSize:15 Lat:27 SizeLat:18 for: %V64i8 = udiv <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = udiv i64 undef, 16
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:40 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = udiv <2 x i64> undef, <i64 8, i64 16>
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:80 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = udiv <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:160 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = udiv <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = udiv i32 undef, 16
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:15 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = udiv <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:15 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = udiv <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:15 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = udiv <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I16 = udiv i16 undef, 16
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = udiv <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = udiv <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = udiv <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = udiv i8 undef, 16
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = udiv <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = udiv <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = udiv <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
; AVX512BW-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
-;
-; SLM-LABEL: 'udiv_constpow2'
-; SLM-NEXT: Cost Model: Found costs of 1 for: %I64 = udiv i64 undef, 16
-; SLM-NEXT: Cost Model: Found costs of RThru:4 CodeSize:5 Lat:6 SizeLat:7 for: %V2i64 = udiv <2 x i64> undef, <i64 8, i64 16>
-; SLM-NEXT: Cost Model: Found costs of RThru:8 CodeSize:10 Lat:12 SizeLat:14 for: %V4i64 = udiv <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
-; SLM-NEXT: Cost Model: Found costs of RThru:16 CodeSize:20 Lat:24 SizeLat:28 for: %V8i64 = udiv <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
-; SLM-NEXT: Cost Model: Found costs of 1 for: %I32 = udiv i32 undef, 16
-; SLM-NEXT: Cost Model: Found costs of RThru:16 CodeSize:15 Lat:17 SizeLat:19 for: %V4i32 = udiv <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
-; SLM-NEXT: Cost Model: Found costs of RThru:32 CodeSize:30 Lat:34 SizeLat:38 for: %V8i32 = udiv <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; SLM-NEXT: Cost Model: Found costs of RThru:64 CodeSize:60 Lat:68 SizeLat:76 for: %V16i32 = udiv <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; SLM-NEXT: Cost Model: Found costs of 1 for: %I16 = udiv i16 undef, 16
-; SLM-NEXT: Cost Model: Found costs of RThru:22 CodeSize:23 Lat:26 SizeLat:27 for: %V8i16 = udiv <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; SLM-NEXT: Cost Model: Found costs of RThru:44 CodeSize:46 Lat:52 SizeLat:54 for: %V16i16 = udiv <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; SLM-NEXT: Cost Model: Found costs of RThru:88 CodeSize:92 Lat:104 SizeLat:108 for: %V32i16 = udiv <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; SLM-NEXT: Cost Model: Found costs of 1 for: %I8 = udiv i8 undef, 16
-; SLM-NEXT: Cost Model: Found costs of RThru:16 CodeSize:18 Lat:27 SizeLat:24 for: %V16i8 = udiv <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; SLM-NEXT: Cost Model: Found costs of RThru:32 CodeSize:36 Lat:54 SizeLat:48 for: %V32i8 = udiv <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; SLM-NEXT: Cost Model: Found costs of RThru:64 CodeSize:72 Lat:108 SizeLat:96 for: %V64i8 = udiv <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; SLM-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
%I64 = udiv i64 undef, 16
%V2i64 = udiv <2 x i64> undef, <i64 8, i64 16>
@@ -1084,98 +1046,98 @@ define i32 @sdiv_uniformconstpow2() {
define i32 @udiv_uniformconstpow2() {
; SSE-LABEL: 'udiv_uniformconstpow2'
-; SSE-NEXT: Cost Model: Found costs of 1 for: %I64 = udiv i64 undef, 16
-; SSE-NEXT: Cost Model: Found costs of 1 for: %V2i64 = udiv <2 x i64> undef, splat (i64 16)
-; SSE-NEXT: Cost Model: Found costs of 2 for: %V4i64 = udiv <4 x i64> undef, splat (i64 16)
-; SSE-NEXT: Cost Model: Found costs of 4 for: %V8i64 = udiv <8 x i64> undef, splat (i64 16)
-; SSE-NEXT: Cost Model: Found costs of 1 for: %I32 = udiv i32 undef, 16
-; SSE-NEXT: Cost Model: Found costs of 1 for: %V4i32 = udiv <4 x i32> undef, splat (i32 16)
-; SSE-NEXT: Cost Model: Found costs of 2 for: %V8i32 = udiv <8 x i32> undef, splat (i32 16)
-; SSE-NEXT: Cost Model: Found costs of 4 for: %V16i32 = udiv <16 x i32> undef, splat (i32 16)
-; SSE-NEXT: Cost Model: Found costs of 1 for: %I16 = udiv i16 undef, 16
-; SSE-NEXT: Cost Model: Found costs of 1 for: %V8i16 = udiv <8 x i16> undef, splat (i16 16)
-; SSE-NEXT: Cost Model: Found costs of 2 for: %V16i16 = udiv <16 x i16> undef, splat (i16 16)
-; SSE-NEXT: Cost Model: Found costs of 4 for: %V32i16 = udiv <32 x i16> undef, splat (i16 16)
-; SSE-NEXT: Cost Model: Found costs of 1 for: %I8 = udiv i8 undef, 16
-; SSE-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:7 SizeLat:3 for: %V16i8 = udiv <16 x i8> undef, splat (i8 16)
-; SSE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:14 SizeLat:6 for: %V32i8 = udiv <32 x i8> undef, splat (i8 16)
-; SSE-NEXT: Cost Model: Found costs of RThru:4 CodeSize:8 Lat:28 SizeLat:12 for: %V64i8 = udiv <64 x i8> undef, splat (i8 16)
+; SSE-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = udiv i64 undef, 16
+; SSE-NEXT: Cost Model: Found costs of RThru:40 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = udiv <2 x i64> undef, splat (i64 16)
+; SSE-NEXT: Cost Model: Found costs of RThru:80 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = udiv <4 x i64> undef, splat (i64 16)
+; SSE-NEXT: Cost Model: Found costs of RThru:160 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = udiv <8 x i64> undef, splat (i64 16)
+; SSE-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = udiv i32 undef, 16
+; SSE-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = udiv <4 x i32> undef, splat (i32 16)
+; SSE-NEXT: Cost Model: Found costs of RThru:10 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = udiv <8 x i32> undef, splat (i32 16)
+; SSE-NEXT: Cost Model: Found costs of RThru:20 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = udiv <16 x i32> undef, splat (i32 16)
+; SSE-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I16 = udiv i16 undef, 16
+; SSE-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = udiv <8 x i16> undef, splat (i16 16)
+; SSE-NEXT: Cost Model: Found costs of RThru:12 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = udiv <16 x i16> undef, splat (i16 16)
+; SSE-NEXT: Cost Model: Found costs of RThru:24 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = udiv <32 x i16> undef, splat (i16 16)
+; SSE-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = udiv i8 undef, 16
+; SSE-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = udiv <16 x i8> undef, splat (i8 16)
+; SSE-NEXT: Cost Model: Found costs of RThru:28 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = udiv <32 x i8> undef, splat (i8 16)
+; SSE-NEXT: Cost Model: Found costs of RThru:56 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = udiv <64 x i8> undef, splat (i8 16)
; SSE-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX1-LABEL: 'udiv_uniformconstpow2'
-; AVX1-NEXT: Cost Model: Found costs of 1 for: %I64 = udiv i64 undef, 16
-; AVX1-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:2 SizeLat:1 for: %V2i64 = udiv <2 x i64> undef, splat (i64 16)
-; AVX1-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:6 SizeLat:5 for: %V4i64 = udiv <4 x i64> undef, splat (i64 16)
-; AVX1-NEXT: Cost Model: Found costs of RThru:6 CodeSize:8 Lat:12 SizeLat:10 for: %V8i64 = udiv <8 x i64> undef, splat (i64 16)
-; AVX1-NEXT: Cost Model: Found costs of 1 for: %I32 = udiv i32 undef, 16
-; AVX1-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:2 SizeLat:1 for: %V4i32 = udiv <4 x i32> undef, splat (i32 16)
-; AVX1-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:6 SizeLat:5 for: %V8i32 = udiv <8 x i32> undef, splat (i32 16)
-; AVX1-NEXT: Cost Model: Found costs of RThru:6 CodeSize:8 Lat:12 SizeLat:10 for: %V16i32 = udiv <16 x i32> undef, splat (i32 16)
-; AVX1-NEXT: Cost Model: Found costs of 1 for: %I16 = udiv i16 undef, 16
-; AVX1-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:2 SizeLat:1 for: %V8i16 = udiv <8 x i16> undef, splat (i16 16)
-; AVX1-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:6 SizeLat:5 for: %V16i16 = udiv <16 x i16> undef, splat (i16 16)
-; AVX1-NEXT: Cost Model: Found costs of RThru:6 CodeSize:8 Lat:12 SizeLat:10 for: %V32i16 = udiv <32 x i16> undef, splat (i16 16)
-; AVX1-NEXT: Cost Model: Found costs of 1 for: %I8 = udiv i8 undef, 16
-; AVX1-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:7 SizeLat:3 for: %V16i8 = udiv <16 x i8> undef, splat (i8 16)
-; AVX1-NEXT: Cost Model: Found costs of RThru:4 CodeSize:7 Lat:7 SizeLat:8 for: %V32i8 = udiv <32 x i8> undef, splat (i8 16)
-; AVX1-NEXT: Cost Model: Found costs of RThru:8 CodeSize:14 Lat:14 SizeLat:16 for: %V64i8 = udiv <64 x i8> undef, splat (i8 16)
+; AVX1-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = udiv i64 undef, 16
+; AVX1-NEXT: Cost Model: Found costs of RThru:40 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = udiv <2 x i64> undef, splat (i64 16)
+; AVX1-NEXT: Cost Model: Found costs of RThru:80 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = udiv <4 x i64> undef, splat (i64 16)
+; AVX1-NEXT: Cost Model: Found costs of RThru:160 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = udiv <8 x i64> undef, splat (i64 16)
+; AVX1-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = udiv i32 undef, 16
+; AVX1-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = udiv <4 x i32> undef, splat (i32 16)
+; AVX1-NEXT: Cost Model: Found costs of RThru:12 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = udiv <8 x i32> undef, splat (i32 16)
+; AVX1-NEXT: Cost Model: Found costs of RThru:24 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = udiv <16 x i32> undef, splat (i32 16)
+; AVX1-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I16 = udiv i16 undef, 16
+; AVX1-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = udiv <8 x i16> undef, splat (i16 16)
+; AVX1-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = udiv <16 x i16> undef, splat (i16 16)
+; AVX1-NEXT: Cost Model: Found costs of RThru:28 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = udiv <32 x i16> undef, splat (i16 16)
+; AVX1-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = udiv i8 undef, 16
+; AVX1-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = udiv <16 x i8> undef, splat (i8 16)
+; AVX1-NEXT: Cost Model: Found costs of RThru:30 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = udiv <32 x i8> undef, splat (i8 16)
+; AVX1-NEXT: Cost Model: Found costs of RThru:60 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = udiv <64 x i8> undef, splat (i8 16)
; AVX1-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX2-LABEL: 'udiv_uniformconstpow2'
-; AVX2-NEXT: Cost Model: Found costs of 1 for: %I64 = udiv i64 undef, 16
-; AVX2-NEXT: Cost Model: Found costs of 1 for: %V2i64 = udiv <2 x i64> undef, splat (i64 16)
-; AVX2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %V4i64 = udiv <4 x i64> undef, splat (i64 16)
-; AVX2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:2 Lat:4 SizeLat:4 for: %V8i64 = udiv <8 x i64> undef, splat (i64 16)
-; AVX2-NEXT: Cost Model: Found costs of 1 for: %I32 = udiv i32 undef, 16
-; AVX2-NEXT: Cost Model: Found costs of 1 for: %V4i32 = udiv <4 x i32> undef, splat (i32 16)
-; AVX2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %V8i32 = udiv <8 x i32> undef, splat (i32 16)
-; AVX2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:2 Lat:4 SizeLat:4 for: %V16i32 = udiv <16 x i32> undef, splat (i32 16)
-; AVX2-NEXT: Cost Model: Found costs of 1 for: %I16 = udiv i16 undef, 16
-; AVX2-NEXT: Cost Model: Found costs of 1 for: %V8i16 = udiv <8 x i16> undef, splat (i16 16)
-; AVX2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %V16i16 = udiv <16 x i16> undef, splat (i16 16)
-; AVX2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:2 Lat:4 SizeLat:4 for: %V32i16 = udiv <32 x i16> undef, splat (i16 16)
-; AVX2-NEXT: Cost Model: Found costs of 1 for: %I8 = udiv i8 undef, 16
-; AVX2-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:8 SizeLat:3 for: %V16i8 = udiv <16 x i8> undef, splat (i8 16)
-; AVX2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:8 SizeLat:4 for: %V32i8 = udiv <32 x i8> undef, splat (i8 16)
-; AVX2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:4 Lat:16 SizeLat:8 for: %V64i8 = udiv <64 x i8> undef, splat (i8 16)
+; AVX2-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = udiv i64 undef, 16
+; AVX2-NEXT: Cost Model: Found costs of RThru:40 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = udiv <2 x i64> undef, splat (i64 16)
+; AVX2-NEXT: Cost Model: Found costs of RThru:80 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = udiv <4 x i64> undef, splat (i64 16)
+; AVX2-NEXT: Cost Model: Found costs of RThru:160 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = udiv <8 x i64> undef, splat (i64 16)
+; AVX2-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = udiv i32 undef, 16
+; AVX2-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = udiv <4 x i32> undef, splat (i32 16)
+; AVX2-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = udiv <8 x i32> undef, splat (i32 16)
+; AVX2-NEXT: Cost Model: Found costs of RThru:10 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = udiv <16 x i32> undef, splat (i32 16)
+; AVX2-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I16 = udiv i16 undef, 16
+; AVX2-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = udiv <8 x i16> undef, splat (i16 16)
+; AVX2-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = udiv <16 x i16> undef, splat (i16 16)
+; AVX2-NEXT: Cost Model: Found costs of RThru:12 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = udiv <32 x i16> undef, splat (i16 16)
+; AVX2-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = udiv i8 undef, 16
+; AVX2-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = udiv <16 x i8> undef, splat (i8 16)
+; AVX2-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = udiv <32 x i8> undef, splat (i8 16)
+; AVX2-NEXT: Cost Model: Found costs of RThru:28 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = udiv <64 x i8> undef, splat (i8 16)
; AVX2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX512F-LABEL: 'udiv_uniformconstpow2'
-; AVX512F-NEXT: Cost Model: Found costs of 1 for: %I64 = udiv i64 undef, 16
-; AVX512F-NEXT: Cost Model: Found costs of 1 for: %V2i64 = udiv <2 x i64> undef, splat (i64 16)
-; AVX512F-NEXT: Cost Model: Found costs of 1 for: %V4i64 = udiv <4 x i64> undef, splat (i64 16)
-; AVX512F-NEXT: Cost Model: Found costs of 1 for: %V8i64 = udiv <8 x i64> undef, splat (i64 16)
-; AVX512F-NEXT: Cost Model: Found costs of 1 for: %I32 = udiv i32 undef, 16
-; AVX512F-NEXT: Cost Model: Found costs of 1 for: %V4i32 = udiv <4 x i32> undef, splat (i32 16)
-; AVX512F-NEXT: Cost Model: Found costs of 1 for: %V8i32 = udiv <8 x i32> undef, splat (i32 16)
-; AVX512F-NEXT: Cost Model: Found costs of 1 for: %V16i32 = udiv <16 x i32> undef, splat (i32 16)
-; AVX512F-NEXT: Cost Model: Found costs of 1 for: %I16 = udiv i16 undef, 16
-; AVX512F-NEXT: Cost Model: Found costs of 1 for: %V8i16 = udiv <8 x i16> undef, splat (i16 16)
-; AVX512F-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:7 SizeLat:4 for: %V16i16 = udiv <16 x i16> undef, splat (i16 16)
-; AVX512F-NEXT: Cost Model: Found costs of RThru:5 CodeSize:5 Lat:10 SizeLat:7 for: %V32i16 = udiv <32 x i16> undef, splat (i16 16)
-; AVX512F-NEXT: Cost Model: Found costs of 1 for: %I8 = udiv i8 undef, 16
-; AVX512F-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:8 SizeLat:3 for: %V16i8 = udiv <16 x i8> undef, splat (i8 16)
-; AVX512F-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:8 SizeLat:4 for: %V32i8 = udiv <32 x i8> undef, splat (i8 16)
-; AVX512F-NEXT: Cost Model: Found costs of RThru:2 CodeSize:5 Lat:12 SizeLat:6 for: %V64i8 = udiv <64 x i8> undef, splat (i8 16)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = udiv i64 undef, 16
+; AVX512F-NEXT: Cost Model: Found costs of RThru:40 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = udiv <2 x i64> undef, splat (i64 16)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:80 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = udiv <4 x i64> undef, splat (i64 16)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:160 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = udiv <8 x i64> undef, splat (i64 16)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = udiv i32 undef, 16
+; AVX512F-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = udiv <4 x i32> undef, splat (i32 16)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = udiv <8 x i32> undef, splat (i32 16)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = udiv <16 x i32> undef, splat (i32 16)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I16 = udiv i16 undef, 16
+; AVX512F-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = udiv <8 x i16> undef, splat (i16 16)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = udiv <16 x i16> undef, splat (i16 16)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:12 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = udiv <32 x i16> undef, splat (i16 16)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = udiv i8 undef, 16
+; AVX512F-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = udiv <16 x i8> undef, splat (i8 16)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = udiv <32 x i8> undef, splat (i8 16)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:28 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = udiv <64 x i8> undef, splat (i8 16)
; AVX512F-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX512BW-LABEL: 'udiv_uniformconstpow2'
-; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %I64 = udiv i64 undef, 16
-; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %V2i64 = udiv <2 x i64> undef, splat (i64 16)
-; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %V4i64 = udiv <4 x i64> undef, splat (i64 16)
-; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %V8i64 = udiv <8 x i64> undef, splat (i64 16)
-; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %I32 = udiv i32 undef, 16
-; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %V4i32 = udiv <4 x i32> undef, splat (i32 16)
-; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %V8i32 = udiv <8 x i32> undef, splat (i32 16)
-; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %V16i32 = udiv <16 x i32> undef, splat (i32 16)
-; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %I16 = udiv i16 undef, 16
-; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %V8i16 = udiv <8 x i16> undef, splat (i16 16)
-; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %V16i16 = udiv <16 x i16> undef, splat (i16 16)
-; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %V32i16 = udiv <32 x i16> undef, splat (i16 16)
-; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %I8 = udiv i8 undef, 16
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:7 SizeLat:3 for: %V16i8 = udiv <16 x i8> undef, splat (i8 16)
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:8 SizeLat:3 for: %V32i8 = udiv <32 x i8> undef, splat (i8 16)
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:8 SizeLat:3 for: %V64i8 = udiv <64 x i8> undef, splat (i8 16)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = udiv i64 undef, 16
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:40 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = udiv <2 x i64> undef, splat (i64 16)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:80 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = udiv <4 x i64> undef, splat (i64 16)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:160 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = udiv <8 x i64> undef, splat (i64 16)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = udiv i32 undef, 16
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = udiv <4 x i32> undef, splat (i32 16)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = udiv <8 x i32> undef, splat (i32 16)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = udiv <16 x i32> undef, splat (i32 16)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I16 = udiv i16 undef, 16
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = udiv <8 x i16> undef, splat (i16 16)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = udiv <16 x i16> undef, splat (i16 16)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = udiv <32 x i16> undef, splat (i16 16)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = udiv i8 undef, 16
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = udiv <16 x i8> undef, splat (i8 16)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = udiv <32 x i8> undef, splat (i8 16)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = udiv <64 x i8> undef, splat (i8 16)
; AVX512BW-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
%I64 = udiv i64 undef, 16
diff --git a/llvm/test/Analysis/CostModel/X86/rem.ll b/llvm/test/Analysis/CostModel/X86/rem.ll
index 06b23c0cf6428..9dda1bcc6bb44 100644
--- a/llvm/test/Analysis/CostModel/X86/rem.ll
+++ b/llvm/test/Analysis/CostModel/X86/rem.ll
@@ -922,61 +922,99 @@ define i32 @srem_constpow2() {
define i32 @urem_constpow2() {
; SSE-LABEL: 'urem_constpow2'
-; SSE-NEXT: Cost Model: Found costs of 1 for: %I64 = urem i64 undef, 16
-; SSE-NEXT: Cost Model: Found costs of 1 for: %V2i64 = urem <2 x i64> undef, <i64 8, i64 16>
-; SSE-NEXT: Cost Model: Found costs of 2 for: %V4i64 = urem <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
-; SSE-NEXT: Cost Model: Found costs of 4 for: %V8i64 = urem <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
-; SSE-NEXT: Cost Model: Found costs of 1 for: %I32 = urem i32 undef, 16
-; SSE-NEXT: Cost Model: Found costs of 1 for: %V4i32 = urem <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
-; SSE-NEXT: Cost Model: Found costs of 2 for: %V8i32 = urem <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; SSE-NEXT: Cost Model: Found costs of 4 for: %V16i32 = urem <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; SSE-NEXT: Cost Model: Found costs of 1 for: %I16 = urem i16 undef, 16
-; SSE-NEXT: Cost Model: Found costs of 1 for: %V8i16 = urem <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; SSE-NEXT: Cost Model: Found costs of 2 for: %V16i16 = urem <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; SSE-NEXT: Cost Model: Found costs of 4 for: %V32i16 = urem <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; SSE-NEXT: Cost Model: Found costs of 1 for: %I8 = urem i8 undef, 16
-; SSE-NEXT: Cost Model: Found costs of 1 for: %V16i8 = urem <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; SSE-NEXT: Cost Model: Found costs of 2 for: %V32i8 = urem <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; SSE-NEXT: Cost Model: Found costs of 4 for: %V64i8 = urem <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; SSE-NEXT: Cost Model: Found costs of 4 for: %I64 = urem i64 undef, 16
+; SSE-NEXT: Cost Model: Found costs of RThru:160 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = urem <2 x i64> undef, <i64 8, i64 16>
+; SSE-NEXT: Cost Model: Found costs of RThru:320 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = urem <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
+; SSE-NEXT: Cost Model: Found costs of RThru:640 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = urem <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
+; SSE-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = urem i32 undef, 16
+; SSE-NEXT: Cost Model: Found costs of RThru:20 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = urem <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
+; SSE-NEXT: Cost Model: Found costs of RThru:40 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = urem <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; SSE-NEXT: Cost Model: Found costs of RThru:80 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = urem <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; SSE-NEXT: Cost Model: Found costs of 4 for: %I16 = urem i16 undef, 16
+; SSE-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = urem <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; SSE-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = urem <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; SSE-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = urem <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; SSE-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = urem i8 undef, 16
+; SSE-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = urem <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; SSE-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = urem <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; SSE-NEXT: Cost Model: Found costs of RThru:64 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = urem <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
; SSE-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
-; AVX-LABEL: 'urem_constpow2'
-; AVX-NEXT: Cost Model: Found costs of 1 for: %I64 = urem i64 undef, 16
-; AVX-NEXT: Cost Model: Found costs of 1 for: %V2i64 = urem <2 x i64> undef, <i64 8, i64 16>
-; AVX-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:1 SizeLat:2 for: %V4i64 = urem <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
-; AVX-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:2 SizeLat:4 for: %V8i64 = urem <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
-; AVX-NEXT: Cost Model: Found costs of 1 for: %I32 = urem i32 undef, 16
-; AVX-NEXT: Cost Model: Found costs of 1 for: %V4i32 = urem <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
-; AVX-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:1 SizeLat:2 for: %V8i32 = urem <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; AVX-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:2 SizeLat:4 for: %V16i32 = urem <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; AVX-NEXT: Cost Model: Found costs of 1 for: %I16 = urem i16 undef, 16
-; AVX-NEXT: Cost Model: Found costs of 1 for: %V8i16 = urem <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; AVX-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:1 SizeLat:2 for: %V16i16 = urem <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; AVX-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:2 SizeLat:4 for: %V32i16 = urem <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; AVX-NEXT: Cost Model: Found costs of 1 for: %I8 = urem i8 undef, 16
-; AVX-NEXT: Cost Model: Found costs of 1 for: %V16i8 = urem <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; AVX-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:1 SizeLat:2 for: %V32i8 = urem <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; AVX-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:2 SizeLat:4 for: %V64i8 = urem <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; AVX-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
+; AVX1-LABEL: 'urem_constpow2'
+; AVX1-NEXT: Cost Model: Found costs of 4 for: %I64 = urem i64 undef, 16
+; AVX1-NEXT: Cost Model: Found costs of RThru:160 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = urem <2 x i64> undef, <i64 8, i64 16>
+; AVX1-NEXT: Cost Model: Found costs of RThru:320 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = urem <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
+; AVX1-NEXT: Cost Model: Found costs of RThru:640 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = urem <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
+; AVX1-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = urem i32 undef, 16
+; AVX1-NEXT: Cost Model: Found costs of RThru:20 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = urem <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
+; AVX1-NEXT: Cost Model: Found costs of RThru:42 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = urem <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; AVX1-NEXT: Cost Model: Found costs of RThru:84 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = urem <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; AVX1-NEXT: Cost Model: Found costs of 4 for: %I16 = urem i16 undef, 16
+; AVX1-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = urem <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; AVX1-NEXT: Cost Model: Found costs of RThru:18 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = urem <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; AVX1-NEXT: Cost Model: Found costs of RThru:36 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = urem <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; AVX1-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = urem i8 undef, 16
+; AVX1-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = urem <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; AVX1-NEXT: Cost Model: Found costs of RThru:34 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = urem <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; AVX1-NEXT: Cost Model: Found costs of RThru:68 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = urem <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; AVX1-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
-; AVX512-LABEL: 'urem_constpow2'
-; AVX512-NEXT: Cost Model: Found costs of 1 for: %I64 = urem i64 undef, 16
-; AVX512-NEXT: Cost Model: Found costs of 1 for: %V2i64 = urem <2 x i64> undef, <i64 8, i64 16>
-; AVX512-NEXT: Cost Model: Found costs of 1 for: %V4i64 = urem <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
-; AVX512-NEXT: Cost Model: Found costs of 1 for: %V8i64 = urem <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
-; AVX512-NEXT: Cost Model: Found costs of 1 for: %I32 = urem i32 undef, 16
-; AVX512-NEXT: Cost Model: Found costs of 1 for: %V4i32 = urem <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
-; AVX512-NEXT: Cost Model: Found costs of 1 for: %V8i32 = urem <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; AVX512-NEXT: Cost Model: Found costs of 1 for: %V16i32 = urem <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; AVX512-NEXT: Cost Model: Found costs of 1 for: %I16 = urem i16 undef, 16
-; AVX512-NEXT: Cost Model: Found costs of 1 for: %V8i16 = urem <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; AVX512-NEXT: Cost Model: Found costs of 1 for: %V16i16 = urem <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; AVX512-NEXT: Cost Model: Found costs of 1 for: %V32i16 = urem <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; AVX512-NEXT: Cost Model: Found costs of 1 for: %I8 = urem i8 undef, 16
-; AVX512-NEXT: Cost Model: Found costs of 1 for: %V16i8 = urem <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; AVX512-NEXT: Cost Model: Found costs of 1 for: %V32i8 = urem <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; AVX512-NEXT: Cost Model: Found costs of 1 for: %V64i8 = urem <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; AVX512-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
+; AVX2-LABEL: 'urem_constpow2'
+; AVX2-NEXT: Cost Model: Found costs of 4 for: %I64 = urem i64 undef, 16
+; AVX2-NEXT: Cost Model: Found costs of RThru:160 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = urem <2 x i64> undef, <i64 8, i64 16>
+; AVX2-NEXT: Cost Model: Found costs of RThru:320 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = urem <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
+; AVX2-NEXT: Cost Model: Found costs of RThru:640 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = urem <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
+; AVX2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = urem i32 undef, 16
+; AVX2-NEXT: Cost Model: Found costs of RThru:20 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = urem <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
+; AVX2-NEXT: Cost Model: Found costs of RThru:19 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = urem <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; AVX2-NEXT: Cost Model: Found costs of RThru:38 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = urem <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; AVX2-NEXT: Cost Model: Found costs of 4 for: %I16 = urem i16 undef, 16
+; AVX2-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = urem <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; AVX2-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = urem <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; AVX2-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = urem <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; AVX2-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = urem i8 undef, 16
+; AVX2-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = urem <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; AVX2-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = urem <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; AVX2-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = urem <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; AVX2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
+;
+; AVX512F-LABEL: 'urem_constpow2'
+; AVX512F-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = urem i64 undef, 16
+; AVX512F-NEXT: Cost Model: Found costs of RThru:120 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = urem <2 x i64> undef, <i64 8, i64 16>
+; AVX512F-NEXT: Cost Model: Found costs of RThru:240 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = urem <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
+; AVX512F-NEXT: Cost Model: Found costs of RThru:480 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = urem <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
+; AVX512F-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = urem i32 undef, 16
+; AVX512F-NEXT: Cost Model: Found costs of RThru:20 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = urem <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
+; AVX512F-NEXT: Cost Model: Found costs of RThru:19 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = urem <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; AVX512F-NEXT: Cost Model: Found costs of RThru:17 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = urem <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; AVX512F-NEXT: Cost Model: Found costs of 4 for: %I16 = urem i16 undef, 16
+; AVX512F-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = urem <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; AVX512F-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = urem <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; AVX512F-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = urem <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; AVX512F-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = urem i8 undef, 16
+; AVX512F-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = urem <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; AVX512F-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = urem <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; AVX512F-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = urem <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; AVX512F-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
+;
+; AVX512BW-LABEL: 'urem_constpow2'
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = urem i64 undef, 16
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:120 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = urem <2 x i64> undef, <i64 8, i64 16>
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:240 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = urem <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:480 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = urem <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = urem i32 undef, 16
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:20 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = urem <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:19 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = urem <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:17 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = urem <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; AVX512BW-NEXT: Cost Model: Found costs of 4 for: %I16 = urem i16 undef, 16
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = urem <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = urem <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = urem <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = urem i8 undef, 16
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = urem <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = urem <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = urem <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
%I64 = urem i64 undef, 16
%V2i64 = urem <2 x i64> undef, <i64 8, i64 16>
@@ -1198,61 +1236,99 @@ define i32 @srem_uniformconstpow2() {
define i32 @urem_uniformconstpow2() {
; SSE-LABEL: 'urem_uniformconstpow2'
-; SSE-NEXT: Cost Model: Found costs of 1 for: %I64 = urem i64 undef, 16
-; SSE-NEXT: Cost Model: Found costs of 1 for: %V2i64 = urem <2 x i64> undef, splat (i64 16)
-; SSE-NEXT: Cost Model: Found costs of 2 for: %V4i64 = urem <4 x i64> undef, splat (i64 16)
-; SSE-NEXT: Cost Model: Found costs of 4 for: %V8i64 = urem <8 x i64> undef, splat (i64 16)
-; SSE-NEXT: Cost Model: Found costs of 1 for: %I32 = urem i32 undef, 16
-; SSE-NEXT: Cost Model: Found costs of 1 for: %V4i32 = urem <4 x i32> undef, splat (i32 16)
-; SSE-NEXT: Cost Model: Found costs of 2 for: %V8i32 = urem <8 x i32> undef, splat (i32 16)
-; SSE-NEXT: Cost Model: Found costs of 4 for: %V16i32 = urem <16 x i32> undef, splat (i32 16)
-; SSE-NEXT: Cost Model: Found costs of 1 for: %I16 = urem i16 undef, 16
-; SSE-NEXT: Cost Model: Found costs of 1 for: %V8i16 = urem <8 x i16> undef, splat (i16 16)
-; SSE-NEXT: Cost Model: Found costs of 2 for: %V16i16 = urem <16 x i16> undef, splat (i16 16)
-; SSE-NEXT: Cost Model: Found costs of 4 for: %V32i16 = urem <32 x i16> undef, splat (i16 16)
-; SSE-NEXT: Cost Model: Found costs of 1 for: %I8 = urem i8 undef, 16
-; SSE-NEXT: Cost Model: Found costs of 1 for: %V16i8 = urem <16 x i8> undef, splat (i8 16)
-; SSE-NEXT: Cost Model: Found costs of 2 for: %V32i8 = urem <32 x i8> undef, splat (i8 16)
-; SSE-NEXT: Cost Model: Found costs of 4 for: %V64i8 = urem <64 x i8> undef, splat (i8 16)
+; SSE-NEXT: Cost Model: Found costs of 4 for: %I64 = urem i64 undef, 16
+; SSE-NEXT: Cost Model: Found costs of RThru:160 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = urem <2 x i64> undef, splat (i64 16)
+; SSE-NEXT: Cost Model: Found costs of RThru:320 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = urem <4 x i64> undef, splat (i64 16)
+; SSE-NEXT: Cost Model: Found costs of RThru:640 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = urem <8 x i64> undef, splat (i64 16)
+; SSE-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = urem i32 undef, 16
+; SSE-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = urem <4 x i32> undef, splat (i32 16)
+; SSE-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = urem <8 x i32> undef, splat (i32 16)
+; SSE-NEXT: Cost Model: Found costs of RThru:28 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = urem <16 x i32> undef, splat (i32 16)
+; SSE-NEXT: Cost Model: Found costs of 4 for: %I16 = urem i16 undef, 16
+; SSE-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = urem <8 x i16> undef, splat (i16 16)
+; SSE-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = urem <16 x i16> undef, splat (i16 16)
+; SSE-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = urem <32 x i16> undef, splat (i16 16)
+; SSE-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = urem i8 undef, 16
+; SSE-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = urem <16 x i8> undef, splat (i8 16)
+; SSE-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = urem <32 x i8> undef, splat (i8 16)
+; SSE-NEXT: Cost Model: Found costs of RThru:64 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = urem <64 x i8> undef, splat (i8 16)
; SSE-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
-; AVX-LABEL: 'urem_uniformconstpow2'
-; AVX-NEXT: Cost Model: Found costs of 1 for: %I64 = urem i64 undef, 16
-; AVX-NEXT: Cost Model: Found costs of 1 for: %V2i64 = urem <2 x i64> undef, splat (i64 16)
-; AVX-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:1 SizeLat:2 for: %V4i64 = urem <4 x i64> undef, splat (i64 16)
-; AVX-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:2 SizeLat:4 for: %V8i64 = urem <8 x i64> undef, splat (i64 16)
-; AVX-NEXT: Cost Model: Found costs of 1 for: %I32 = urem i32 undef, 16
-; AVX-NEXT: Cost Model: Found costs of 1 for: %V4i32 = urem <4 x i32> undef, splat (i32 16)
-; AVX-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:1 SizeLat:2 for: %V8i32 = urem <8 x i32> undef, splat (i32 16)
-; AVX-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:2 SizeLat:4 for: %V16i32 = urem <16 x i32> undef, splat (i32 16)
-; AVX-NEXT: Cost Model: Found costs of 1 for: %I16 = urem i16 undef, 16
-; AVX-NEXT: Cost Model: Found costs of 1 for: %V8i16 = urem <8 x i16> undef, splat (i16 16)
-; AVX-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:1 SizeLat:2 for: %V16i16 = urem <16 x i16> undef, splat (i16 16)
-; AVX-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:2 SizeLat:4 for: %V32i16 = urem <32 x i16> undef, splat (i16 16)
-; AVX-NEXT: Cost Model: Found costs of 1 for: %I8 = urem i8 undef, 16
-; AVX-NEXT: Cost Model: Found costs of 1 for: %V16i8 = urem <16 x i8> undef, splat (i8 16)
-; AVX-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:1 SizeLat:2 for: %V32i8 = urem <32 x i8> undef, splat (i8 16)
-; AVX-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:2 SizeLat:4 for: %V64i8 = urem <64 x i8> undef, splat (i8 16)
-; AVX-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
+; AVX1-LABEL: 'urem_uniformconstpow2'
+; AVX1-NEXT: Cost Model: Found costs of 4 for: %I64 = urem i64 undef, 16
+; AVX1-NEXT: Cost Model: Found costs of RThru:160 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = urem <2 x i64> undef, splat (i64 16)
+; AVX1-NEXT: Cost Model: Found costs of RThru:320 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = urem <4 x i64> undef, splat (i64 16)
+; AVX1-NEXT: Cost Model: Found costs of RThru:640 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = urem <8 x i64> undef, splat (i64 16)
+; AVX1-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = urem i32 undef, 16
+; AVX1-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = urem <4 x i32> undef, splat (i32 16)
+; AVX1-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = urem <8 x i32> undef, splat (i32 16)
+; AVX1-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = urem <16 x i32> undef, splat (i32 16)
+; AVX1-NEXT: Cost Model: Found costs of 4 for: %I16 = urem i16 undef, 16
+; AVX1-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = urem <8 x i16> undef, splat (i16 16)
+; AVX1-NEXT: Cost Model: Found costs of RThru:18 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = urem <16 x i16> undef, splat (i16 16)
+; AVX1-NEXT: Cost Model: Found costs of RThru:36 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = urem <32 x i16> undef, splat (i16 16)
+; AVX1-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = urem i8 undef, 16
+; AVX1-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = urem <16 x i8> undef, splat (i8 16)
+; AVX1-NEXT: Cost Model: Found costs of RThru:34 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = urem <32 x i8> undef, splat (i8 16)
+; AVX1-NEXT: Cost Model: Found costs of RThru:68 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = urem <64 x i8> undef, splat (i8 16)
+; AVX1-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
-; AVX512-LABEL: 'urem_uniformconstpow2'
-; AVX512-NEXT: Cost Model: Found costs of 1 for: %I64 = urem i64 undef, 16
-; AVX512-NEXT: Cost Model: Found costs of 1 for: %V2i64 = urem <2 x i64> undef, splat (i64 16)
-; AVX512-NEXT: Cost Model: Found costs of 1 for: %V4i64 = urem <4 x i64> undef, splat (i64 16)
-; AVX512-NEXT: Cost Model: Found costs of 1 for: %V8i64 = urem <8 x i64> undef, splat (i64 16)
-; AVX512-NEXT: Cost Model: Found costs of 1 for: %I32 = urem i32 undef, 16
-; AVX512-NEXT: Cost Model: Found costs of 1 for: %V4i32 = urem <4 x i32> undef, splat (i32 16)
-; AVX512-NEXT: Cost Model: Found costs of 1 for: %V8i32 = urem <8 x i32> undef, splat (i32 16)
-; AVX512-NEXT: Cost Model: Found costs of 1 for: %V16i32 = urem <16 x i32> undef, splat (i32 16)
-; AVX512-NEXT: Cost Model: Found costs of 1 for: %I16 = urem i16 undef, 16
-; AVX512-NEXT: Cost Model: Found costs of 1 for: %V8i16 = urem <8 x i16> undef, splat (i16 16)
-; AVX512-NEXT: Cost Model: Found costs of 1 for: %V16i16 = urem <16 x i16> undef, splat (i16 16)
-; AVX512-NEXT: Cost Model: Found costs of 1 for: %V32i16 = urem <32 x i16> undef, splat (i16 16)
-; AVX512-NEXT: Cost Model: Found costs of 1 for: %I8 = urem i8 undef, 16
-; AVX512-NEXT: Cost Model: Found costs of 1 for: %V16i8 = urem <16 x i8> undef, splat (i8 16)
-; AVX512-NEXT: Cost Model: Found costs of 1 for: %V32i8 = urem <32 x i8> undef, splat (i8 16)
-; AVX512-NEXT: Cost Model: Found costs of 1 for: %V64i8 = urem <64 x i8> undef, splat (i8 16)
-; AVX512-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
+; AVX2-LABEL: 'urem_uniformconstpow2'
+; AVX2-NEXT: Cost Model: Found costs of 4 for: %I64 = urem i64 undef, 16
+; AVX2-NEXT: Cost Model: Found costs of RThru:160 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = urem <2 x i64> undef, splat (i64 16)
+; AVX2-NEXT: Cost Model: Found costs of RThru:320 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = urem <4 x i64> undef, splat (i64 16)
+; AVX2-NEXT: Cost Model: Found costs of RThru:640 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = urem <8 x i64> undef, splat (i64 16)
+; AVX2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = urem i32 undef, 16
+; AVX2-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = urem <4 x i32> undef, splat (i32 16)
+; AVX2-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = urem <8 x i32> undef, splat (i32 16)
+; AVX2-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = urem <16 x i32> undef, splat (i32 16)
+; AVX2-NEXT: Cost Model: Found costs of 4 for: %I16 = urem i16 undef, 16
+; AVX2-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = urem <8 x i16> undef, splat (i16 16)
+; AVX2-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = urem <16 x i16> undef, splat (i16 16)
+; AVX2-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = urem <32 x i16> undef, splat (i16 16)
+; AVX2-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = urem i8 undef, 16
+; AVX2-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = urem <16 x i8> undef, splat (i8 16)
+; AVX2-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = urem <32 x i8> undef, splat (i8 16)
+; AVX2-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = urem <64 x i8> undef, splat (i8 16)
+; AVX2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
+;
+; AVX512F-LABEL: 'urem_uniformconstpow2'
+; AVX512F-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = urem i64 undef, 16
+; AVX512F-NEXT: Cost Model: Found costs of RThru:120 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = urem <2 x i64> undef, splat (i64 16)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:240 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = urem <4 x i64> undef, splat (i64 16)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:480 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = urem <8 x i64> undef, splat (i64 16)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = urem i32 undef, 16
+; AVX512F-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = urem <4 x i32> undef, splat (i32 16)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = urem <8 x i32> undef, splat (i32 16)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = urem <16 x i32> undef, splat (i32 16)
+; AVX512F-NEXT: Cost Model: Found costs of 4 for: %I16 = urem i16 undef, 16
+; AVX512F-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = urem <8 x i16> undef, splat (i16 16)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = urem <16 x i16> undef, splat (i16 16)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = urem <32 x i16> undef, splat (i16 16)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = urem i8 undef, 16
+; AVX512F-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = urem <16 x i8> undef, splat (i8 16)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = urem <32 x i8> undef, splat (i8 16)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = urem <64 x i8> undef, splat (i8 16)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
+;
+; AVX512BW-LABEL: 'urem_uniformconstpow2'
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = urem i64 undef, 16
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:120 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = urem <2 x i64> undef, splat (i64 16)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:240 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = urem <4 x i64> undef, splat (i64 16)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:480 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = urem <8 x i64> undef, splat (i64 16)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = urem i32 undef, 16
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = urem <4 x i32> undef, splat (i32 16)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = urem <8 x i32> undef, splat (i32 16)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = urem <16 x i32> undef, splat (i32 16)
+; AVX512BW-NEXT: Cost Model: Found costs of 4 for: %I16 = urem i16 undef, 16
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = urem <8 x i16> undef, splat (i16 16)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = urem <16 x i16> undef, splat (i16 16)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = urem <32 x i16> undef, splat (i16 16)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = urem i8 undef, 16
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = urem <16 x i8> undef, splat (i8 16)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = urem <32 x i8> undef, splat (i8 16)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = urem <64 x i8> undef, splat (i8 16)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
%I64 = urem i64 undef, 16
%V2i64 = urem <2 x i64> undef, <i64 16, i64 16>
>From e241021280d8a7416785c59922983305c421e350 Mon Sep 17 00:00:00 2001
From: Ryan Buchner <rbuchner at hu-rbuchner-lv.qualcomm.com>
Date: Mon, 9 Feb 2026 17:07:41 -0800
Subject: [PATCH 12/19] [TTI] Revert prior implementation of moving logic to
TargetTransformInfo
---
llvm/include/llvm/CodeGen/BasicTTIImpl.h | 24 ++
llvm/lib/Analysis/TargetTransformInfo.cpp | 7 -
.../AArch64/AArch64TargetTransformInfo.cpp | 5 +
.../Target/RISCV/RISCVTargetTransformInfo.cpp | 5 +
.../lib/Target/X86/X86TargetTransformInfo.cpp | 16 +
llvm/test/Analysis/CostModel/AArch64/div.ll | 92 ++---
llvm/test/Analysis/CostModel/AArch64/rem.ll | 92 ++---
.../Analysis/CostModel/AArch64/sve-div.ll | 72 ++--
.../Analysis/CostModel/AArch64/sve-rem.ll | 72 ++--
llvm/test/Analysis/CostModel/X86/div.ll | 362 ++++++++++--------
llvm/test/Analysis/CostModel/X86/rem.ll | 284 +++++---------
.../SLPVectorizer/RISCV/load-binop-store.ll | 113 ------
12 files changed, 518 insertions(+), 626 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/BasicTTIImpl.h b/llvm/include/llvm/CodeGen/BasicTTIImpl.h
index 21afcbefdf719..c807b06a292b4 100644
--- a/llvm/include/llvm/CodeGen/BasicTTIImpl.h
+++ b/llvm/include/llvm/CodeGen/BasicTTIImpl.h
@@ -1048,6 +1048,30 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
unsigned getMaxInterleaveFactor(ElementCount VF) const override { return 1; }
+ bool getConvertedArithmeticInstructionCost(unsigned ISDOpcode, Type *Ty,
+ TTI::TargetCostKind CostKind,
+ TTI::OperandValueInfo Opd1Info,
+ TTI::OperandValueInfo Opd2Info,
+ ArrayRef<const Value *> Args,
+ const Instruction *CxtI,
+ InstructionCost &Cost) const {
+ // Vector unsigned division/remainder will be simplified to shifts/masks.
+ if ((ISDOpcode == ISD::UDIV || ISDOpcode == ISD::UREM) &&
+ Opd2Info.isConstant() && Opd2Info.isPowerOf2()) {
+ if (ISDOpcode == ISD::UDIV)
+ Cost = getArithmeticInstrCost(Instruction::LShr, Ty, CostKind,
+ Opd1Info.getNoProps(),
+ Opd2Info.getNoProps());
+ // UREM
+ else
+ Cost = getArithmeticInstrCost(Instruction::And, Ty, CostKind,
+ Opd1Info.getNoProps(),
+ Opd2Info.getNoProps());
+ return true;
+ }
+ return false;
+ }
+
InstructionCost getArithmeticInstrCost(
unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
TTI::OperandValueInfo Opd1Info = {TTI::OK_AnyValue, TTI::OP_None},
diff --git a/llvm/lib/Analysis/TargetTransformInfo.cpp b/llvm/lib/Analysis/TargetTransformInfo.cpp
index e7d494a471889..19785204ed2b3 100644
--- a/llvm/lib/Analysis/TargetTransformInfo.cpp
+++ b/llvm/lib/Analysis/TargetTransformInfo.cpp
@@ -1012,13 +1012,6 @@ InstructionCost TargetTransformInfo::getArithmeticInstrCost(
return getCallInstrCost(nullptr, VecTy, {VecTy, VecTy}, CostKind);
}
- // Vector unsigned division/remainder will be simplified to shifts/masks.
- if ((Opcode == Instruction::UDiv || Opcode == Instruction::URem) &&
- Op2Info.isConstant() && Op2Info.isPowerOf2())
- return getArithmeticInstrCost(
- Opcode == Instruction::UDiv ? Instruction::LShr : Instruction::And, Ty,
- CostKind, Op1Info.getNoProps(), Op2Info.getNoProps());
-
InstructionCost Cost = TTIImpl->getArithmeticInstrCost(
Opcode, Ty, CostKind, Op1Info, Op2Info, Args, CxtI);
assert(Cost >= 0 && "TTI should not produce negative costs!");
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
index f82327fb2edf3..fa473342fd6a7 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -4290,6 +4290,11 @@ InstructionCost AArch64TTIImpl::getArithmeticInstrCost(
return LT.first;
}
+ InstructionCost ConvertedCost;
+ if (getConvertedArithmeticInstructionCost(ISD, Ty, CostKind, Op1Info, Op2Info,
+ Args, CxtI, ConvertedCost))
+ return ConvertedCost;
+
switch (ISD) {
default:
return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info,
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index dc4bf0784e2d1..1f68d708ec1cb 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2617,6 +2617,11 @@ InstructionCost RISCVTTIImpl::getArithmeticInstrCost(
std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(Ty);
unsigned ISDOpcode = TLI->InstructionOpcodeToISD(Opcode);
+ InstructionCost ConvertedCost;
+ if (getConvertedArithmeticInstructionCost(ISDOpcode, Ty, CostKind, Op1Info,
+ Op2Info, Args, CxtI, ConvertedCost))
+ return ConvertedCost;
+
// TODO: Handle scalar type.
if (!LT.second.isVector()) {
static const CostTblEntry DivTbl[]{
diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
index af6b6153b7925..1401bbb1f64ef 100644
--- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -276,6 +276,11 @@ InstructionCost X86TTIImpl::getArithmeticInstrCost(
int ISD = TLI->InstructionOpcodeToISD(Opcode);
assert(ISD && "Invalid opcode");
+ InstructionCost ConvertedCost;
+ if (getConvertedArithmeticInstructionCost(ISD, Ty, CostKind, Op1Info, Op2Info,
+ Args, CxtI, ConvertedCost))
+ return ConvertedCost;
+
if (ISD == ISD::MUL && Args.size() == 2 && LT.second.isVector() &&
(LT.second.getScalarType() == MVT::i32 ||
LT.second.getScalarType() == MVT::i64)) {
@@ -366,6 +371,17 @@ InstructionCost X86TTIImpl::getArithmeticInstrCost(
return Cost;
}
+ // Vector unsigned division/remainder will be simplified to shifts/masks.
+ if ((ISD == ISD::UDIV || ISD == ISD::UREM) && Op2Info.isConstant() &&
+ Op2Info.isPowerOf2()) {
+ if (ISD == ISD::UDIV)
+ return getArithmeticInstrCost(Instruction::LShr, Ty, CostKind,
+ Op1Info.getNoProps(), Op2Info.getNoProps());
+ // UREM
+ return getArithmeticInstrCost(Instruction::And, Ty, CostKind,
+ Op1Info.getNoProps(), Op2Info.getNoProps());
+ }
+
static const CostKindTblEntry GFNIUniformConstCostTable[] = {
{ ISD::SHL, MVT::v16i8, { 1, 6, 1, 2 } }, // gf2p8affineqb
{ ISD::SRL, MVT::v16i8, { 1, 6, 1, 2 } }, // gf2p8affineqb
diff --git a/llvm/test/Analysis/CostModel/AArch64/div.ll b/llvm/test/Analysis/CostModel/AArch64/div.ll
index 10d0c82842bbf..3a2358dba51b2 100644
--- a/llvm/test/Analysis/CostModel/AArch64/div.ll
+++ b/llvm/test/Analysis/CostModel/AArch64/div.ll
@@ -578,29 +578,29 @@ define void @sdiv_constpow2() {
define void @udiv_constpow2() {
; CHECK-LABEL: 'udiv_constpow2'
-; CHECK-NEXT: Cost Model: Found costs of RThru:10 CodeSize:4 Lat:4 SizeLat:4 for: %I128 = udiv i128 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %I64 = udiv i64 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = udiv <2 x i64> undef, <i64 8, i64 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:64 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = udiv <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:128 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = udiv <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
-; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = udiv i32 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V2i32 = udiv <2 x i32> undef, <i32 2, i32 4>
-; CHECK-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = udiv <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:12 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = udiv <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; CHECK-NEXT: Cost Model: Found costs of RThru:24 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = udiv <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %I16 = udiv i16 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V2i16 = udiv <2 x i16> undef, <i16 2, i16 4>
-; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V4i16 = udiv <4 x i16> undef, <i16 2, i16 4, i16 8, i16 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = udiv <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; CHECK-NEXT: Cost Model: Found costs of RThru:12 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = udiv <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; CHECK-NEXT: Cost Model: Found costs of RThru:24 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = udiv <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = udiv i8 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V2i8 = udiv <2 x i8> undef, <i8 2, i8 4>
-; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V4i8 = udiv <4 x i8> undef, <i8 2, i8 4, i8 8, i8 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V8i8 = udiv <8 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = udiv <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:12 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = udiv <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:24 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = udiv <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %I128 = udiv i128 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = udiv i64 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = udiv <2 x i64> undef, <i64 8, i64 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = udiv <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V8i64 = udiv <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = udiv i32 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i32 = udiv <2 x i32> undef, <i32 2, i32 4>
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = udiv <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = udiv <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V16i32 = udiv <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I16 = udiv i16 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i16 = udiv <2 x i16> undef, <i16 2, i16 4>
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i16 = udiv <4 x i16> undef, <i16 2, i16 4, i16 8, i16 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = udiv <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = udiv <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V32i16 = udiv <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = udiv i8 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i8 = udiv <2 x i8> undef, <i8 2, i8 4>
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i8 = udiv <4 x i8> undef, <i8 2, i8 4, i8 8, i8 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i8 = udiv <8 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = udiv <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = udiv <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V64i8 = udiv <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
%I128 = udiv i128 undef, 16
@@ -694,29 +694,29 @@ define void @sdiv_uniformconstpow2() {
define void @udiv_uniformconstpow2() {
; CHECK-LABEL: 'udiv_uniformconstpow2'
-; CHECK-NEXT: Cost Model: Found costs of RThru:10 CodeSize:4 Lat:4 SizeLat:4 for: %I128 = udiv i128 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %I64 = udiv i64 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = udiv <2 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:64 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = udiv <4 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:128 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = udiv <8 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = udiv i32 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V2i32 = udiv <2 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = udiv <4 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:12 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = udiv <8 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:24 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = udiv <16 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %I16 = udiv i16 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V2i16 = udiv <2 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V4i16 = udiv <4 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = udiv <8 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:12 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = udiv <16 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:24 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = udiv <32 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = udiv i8 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V2i8 = udiv <2 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V4i8 = udiv <4 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V8i8 = udiv <8 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = udiv <16 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:12 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = udiv <32 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:24 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = udiv <64 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %I128 = udiv i128 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = udiv i64 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = udiv <2 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = udiv <4 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V8i64 = udiv <8 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = udiv i32 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i32 = udiv <2 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = udiv <4 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = udiv <8 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V16i32 = udiv <16 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I16 = udiv i16 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i16 = udiv <2 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i16 = udiv <4 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = udiv <8 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = udiv <16 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V32i16 = udiv <32 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = udiv i8 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i8 = udiv <2 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i8 = udiv <4 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i8 = udiv <8 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = udiv <16 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = udiv <32 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V64i8 = udiv <64 x i8> undef, splat (i8 16)
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
%I128 = udiv i128 undef, 16
diff --git a/llvm/test/Analysis/CostModel/AArch64/rem.ll b/llvm/test/Analysis/CostModel/AArch64/rem.ll
index 288cf9e4b2602..2fa62f1705911 100644
--- a/llvm/test/Analysis/CostModel/AArch64/rem.ll
+++ b/llvm/test/Analysis/CostModel/AArch64/rem.ll
@@ -578,29 +578,29 @@ define void @srem_constpow2() {
define void @urem_constpow2() {
; CHECK-LABEL: 'urem_constpow2'
-; CHECK-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %I128 = urem i128 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = urem i64 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:47 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = urem <2 x i64> undef, <i64 8, i64 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:94 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = urem <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:188 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = urem <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
-; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = urem i32 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V2i32 = urem <2 x i32> undef, <i32 2, i32 4>
-; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = urem <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = urem <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; CHECK-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = urem <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %I16 = urem i16 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V2i16 = urem <2 x i16> undef, <i16 2, i16 4>
-; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V4i16 = urem <4 x i16> undef, <i16 2, i16 4, i16 8, i16 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = urem <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = urem <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; CHECK-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = urem <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = urem i8 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V2i8 = urem <2 x i8> undef, <i8 2, i8 4>
-; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V4i8 = urem <4 x i8> undef, <i8 2, i8 4, i8 8, i8 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V8i8 = urem <8 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = urem <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = urem <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = urem <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %I128 = urem i128 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = urem i64 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = urem <2 x i64> undef, <i64 8, i64 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = urem <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V8i64 = urem <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = urem i32 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i32 = urem <2 x i32> undef, <i32 2, i32 4>
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = urem <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = urem <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V16i32 = urem <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I16 = urem i16 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i16 = urem <2 x i16> undef, <i16 2, i16 4>
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i16 = urem <4 x i16> undef, <i16 2, i16 4, i16 8, i16 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = urem <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = urem <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V32i16 = urem <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = urem i8 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i8 = urem <2 x i8> undef, <i8 2, i8 4>
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i8 = urem <4 x i8> undef, <i8 2, i8 4, i8 8, i8 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i8 = urem <8 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = urem <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = urem <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V64i8 = urem <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
%I128 = urem i128 undef, 16
@@ -694,29 +694,29 @@ define void @srem_uniformconstpow2() {
define void @urem_uniformconstpow2() {
; CHECK-LABEL: 'urem_uniformconstpow2'
-; CHECK-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %I128 = urem i128 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = urem i64 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:47 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = urem <2 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:94 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = urem <4 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:188 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = urem <8 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = urem i32 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V2i32 = urem <2 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = urem <4 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = urem <8 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = urem <16 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %I16 = urem i16 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V2i16 = urem <2 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V4i16 = urem <4 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = urem <8 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = urem <16 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = urem <32 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = urem i8 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V2i8 = urem <2 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V4i8 = urem <4 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V8i8 = urem <8 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = urem <16 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = urem <32 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = urem <64 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %I128 = urem i128 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = urem i64 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = urem <2 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = urem <4 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V8i64 = urem <8 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = urem i32 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i32 = urem <2 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = urem <4 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = urem <8 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V16i32 = urem <16 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I16 = urem i16 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i16 = urem <2 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i16 = urem <4 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = urem <8 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = urem <16 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V32i16 = urem <32 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = urem i8 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i8 = urem <2 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i8 = urem <4 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i8 = urem <8 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = urem <16 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = urem <32 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V64i8 = urem <64 x i8> undef, splat (i8 16)
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
%I128 = urem i128 undef, 16
diff --git a/llvm/test/Analysis/CostModel/AArch64/sve-div.ll b/llvm/test/Analysis/CostModel/AArch64/sve-div.ll
index 6341a697f0755..84a9ca0fab6d8 100644
--- a/llvm/test/Analysis/CostModel/AArch64/sve-div.ll
+++ b/llvm/test/Analysis/CostModel/AArch64/sve-div.ll
@@ -408,42 +408,42 @@ define void @sdiv_uniformconstpow2() {
define void @udiv_uniformconstpow2() {
; CHECK-LABEL: 'udiv_uniformconstpow2'
-; CHECK-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = udiv <2 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:12 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = udiv <4 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:24 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = udiv <8 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V2i32 = udiv <2 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = udiv <4 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:12 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = udiv <8 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:24 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = udiv <16 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V2i16 = udiv <2 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V4i16 = udiv <4 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = udiv <8 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:12 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = udiv <16 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:24 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = udiv <32 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V2i8 = udiv <2 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V4i8 = udiv <4 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V8i8 = udiv <8 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = udiv <16 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:12 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = udiv <32 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:24 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = udiv <64 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV2i64 = udiv <vscale x 2 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %NV4i64 = udiv <vscale x 4 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %NV8i64 = udiv <vscale x 8 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV2i32 = udiv <vscale x 2 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV4i32 = udiv <vscale x 4 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %NV8i32 = udiv <vscale x 8 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %NV16i32 = udiv <vscale x 16 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV2i16 = udiv <vscale x 2 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV4i16 = udiv <vscale x 4 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV8i16 = udiv <vscale x 8 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %NV16i16 = udiv <vscale x 16 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %NV32i16 = udiv <vscale x 32 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV2i8 = udiv <vscale x 2 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV4i8 = udiv <vscale x 4 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV8i8 = udiv <vscale x 8 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV16i8 = udiv <vscale x 16 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %NV32i8 = udiv <vscale x 32 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %NV64i8 = udiv <vscale x 64 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = udiv <2 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = udiv <4 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V8i64 = udiv <8 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i32 = udiv <2 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = udiv <4 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = udiv <8 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V16i32 = udiv <16 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i16 = udiv <2 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i16 = udiv <4 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = udiv <8 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = udiv <16 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V32i16 = udiv <32 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i8 = udiv <2 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i8 = udiv <4 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i8 = udiv <8 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = udiv <16 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = udiv <32 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V64i8 = udiv <64 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV2i64 = udiv <vscale x 2 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %NV4i64 = udiv <vscale x 4 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV8i64 = udiv <vscale x 8 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV2i32 = udiv <vscale x 2 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV4i32 = udiv <vscale x 4 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %NV8i32 = udiv <vscale x 8 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV16i32 = udiv <vscale x 16 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV2i16 = udiv <vscale x 2 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV4i16 = udiv <vscale x 4 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV8i16 = udiv <vscale x 8 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %NV16i16 = udiv <vscale x 16 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV32i16 = udiv <vscale x 32 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV2i8 = udiv <vscale x 2 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV4i8 = udiv <vscale x 4 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV8i8 = udiv <vscale x 8 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV16i8 = udiv <vscale x 16 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %NV32i8 = udiv <vscale x 32 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV64i8 = udiv <vscale x 64 x i8> undef, splat (i8 16)
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
%V2i64 = udiv <2 x i64> undef, splat (i64 16)
diff --git a/llvm/test/Analysis/CostModel/AArch64/sve-rem.ll b/llvm/test/Analysis/CostModel/AArch64/sve-rem.ll
index 0f1915c9f2128..eac8b66bcd216 100644
--- a/llvm/test/Analysis/CostModel/AArch64/sve-rem.ll
+++ b/llvm/test/Analysis/CostModel/AArch64/sve-rem.ll
@@ -410,43 +410,43 @@ define void @srem_uniformconstpow2() {
define void @urem_uniformconstpow2() {
; CHECK-LABEL: 'urem_uniformconstpow2'
-; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = urem <2 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = urem <4 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = urem <8 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V2i32 = urem <2 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = urem <4 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = urem <8 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = urem <16 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V2i16 = urem <2 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V4i16 = urem <4 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = urem <8 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = urem <16 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = urem <32 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V2i8 = urem <2 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V4i8 = urem <4 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V8i8 = urem <8 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = urem <16 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = urem <32 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = urem <64 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = urem <2 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = urem <4 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V8i64 = urem <8 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i32 = urem <2 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = urem <4 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = urem <8 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V16i32 = urem <16 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i16 = urem <2 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i16 = urem <4 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = urem <8 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = urem <16 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V32i16 = urem <32 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i8 = urem <2 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i8 = urem <4 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i8 = urem <8 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = urem <16 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = urem <32 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V64i8 = urem <64 x i8> undef, splat (i8 16)
; CHECK-NEXT: Cost Model: Found costs of RThru:Invalid CodeSize:4 Lat:4 SizeLat:4 for: %NV2i128 = urem <vscale x 2 x i128> undef, splat (i128 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %NV2i64 = urem <vscale x 2 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:12 CodeSize:4 Lat:4 SizeLat:4 for: %NV4i64 = urem <vscale x 4 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:24 CodeSize:4 Lat:4 SizeLat:4 for: %NV8i64 = urem <vscale x 8 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %NV2i32 = urem <vscale x 2 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %NV4i32 = urem <vscale x 4 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:12 CodeSize:4 Lat:4 SizeLat:4 for: %NV8i32 = urem <vscale x 8 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:24 CodeSize:4 Lat:4 SizeLat:4 for: %NV16i32 = urem <vscale x 16 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %NV2i16 = urem <vscale x 2 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %NV4i16 = urem <vscale x 4 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %NV8i16 = urem <vscale x 8 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:12 CodeSize:4 Lat:4 SizeLat:4 for: %NV16i16 = urem <vscale x 16 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:24 CodeSize:4 Lat:4 SizeLat:4 for: %NV32i16 = urem <vscale x 32 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %NV2i8 = urem <vscale x 2 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %NV4i8 = urem <vscale x 4 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %NV8i8 = urem <vscale x 8 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %NV16i8 = urem <vscale x 16 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:12 CodeSize:4 Lat:4 SizeLat:4 for: %NV32i8 = urem <vscale x 32 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:24 CodeSize:4 Lat:4 SizeLat:4 for: %NV64i8 = urem <vscale x 64 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV2i64 = urem <vscale x 2 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %NV4i64 = urem <vscale x 4 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV8i64 = urem <vscale x 8 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV2i32 = urem <vscale x 2 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV4i32 = urem <vscale x 4 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %NV8i32 = urem <vscale x 8 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV16i32 = urem <vscale x 16 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV2i16 = urem <vscale x 2 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV4i16 = urem <vscale x 4 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV8i16 = urem <vscale x 8 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %NV16i16 = urem <vscale x 16 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV32i16 = urem <vscale x 32 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV2i8 = urem <vscale x 2 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV4i8 = urem <vscale x 4 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV8i8 = urem <vscale x 8 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV16i8 = urem <vscale x 16 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %NV32i8 = urem <vscale x 32 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV64i8 = urem <vscale x 64 x i8> undef, splat (i8 16)
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
%V2i64 = urem <2 x i64> undef, splat (i64 16)
diff --git a/llvm/test/Analysis/CostModel/X86/div.ll b/llvm/test/Analysis/CostModel/X86/div.ll
index c76398ecf9edc..3af5b2dd217da 100644
--- a/llvm/test/Analysis/CostModel/X86/div.ll
+++ b/llvm/test/Analysis/CostModel/X86/div.ll
@@ -769,100 +769,138 @@ define i32 @sdiv_constpow2() {
}
define i32 @udiv_constpow2() {
-; SSE-LABEL: 'udiv_constpow2'
-; SSE-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = udiv i64 undef, 16
-; SSE-NEXT: Cost Model: Found costs of RThru:40 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = udiv <2 x i64> undef, <i64 8, i64 16>
-; SSE-NEXT: Cost Model: Found costs of RThru:80 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = udiv <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
-; SSE-NEXT: Cost Model: Found costs of RThru:160 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = udiv <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
-; SSE-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = udiv i32 undef, 16
-; SSE-NEXT: Cost Model: Found costs of RThru:15 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = udiv <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
-; SSE-NEXT: Cost Model: Found costs of RThru:30 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = udiv <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; SSE-NEXT: Cost Model: Found costs of RThru:60 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = udiv <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; SSE-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I16 = udiv i16 undef, 16
-; SSE-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = udiv <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; SSE-NEXT: Cost Model: Found costs of RThru:12 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = udiv <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; SSE-NEXT: Cost Model: Found costs of RThru:24 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = udiv <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; SSE-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = udiv i8 undef, 16
-; SSE-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = udiv <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; SSE-NEXT: Cost Model: Found costs of RThru:28 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = udiv <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; SSE-NEXT: Cost Model: Found costs of RThru:56 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = udiv <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; SSE-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
+; SSE2-LABEL: 'udiv_constpow2'
+; SSE2-NEXT: Cost Model: Found costs of 1 for: %I64 = udiv i64 undef, 16
+; SSE2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:5 Lat:6 SizeLat:7 for: %V2i64 = udiv <2 x i64> undef, <i64 8, i64 16>
+; SSE2-NEXT: Cost Model: Found costs of RThru:8 CodeSize:10 Lat:12 SizeLat:14 for: %V4i64 = udiv <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
+; SSE2-NEXT: Cost Model: Found costs of RThru:16 CodeSize:20 Lat:24 SizeLat:28 for: %V8i64 = udiv <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
+; SSE2-NEXT: Cost Model: Found costs of 1 for: %I32 = udiv i32 undef, 16
+; SSE2-NEXT: Cost Model: Found costs of RThru:12 CodeSize:15 Lat:12 SizeLat:19 for: %V4i32 = udiv <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
+; SSE2-NEXT: Cost Model: Found costs of RThru:24 CodeSize:30 Lat:24 SizeLat:38 for: %V8i32 = udiv <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; SSE2-NEXT: Cost Model: Found costs of RThru:48 CodeSize:60 Lat:48 SizeLat:76 for: %V16i32 = udiv <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; SSE2-NEXT: Cost Model: Found costs of 1 for: %I16 = udiv i16 undef, 16
+; SSE2-NEXT: Cost Model: Found costs of RThru:16 CodeSize:31 Lat:19 SizeLat:31 for: %V8i16 = udiv <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; SSE2-NEXT: Cost Model: Found costs of RThru:32 CodeSize:62 Lat:38 SizeLat:62 for: %V16i16 = udiv <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; SSE2-NEXT: Cost Model: Found costs of RThru:64 CodeSize:124 Lat:76 SizeLat:124 for: %V32i16 = udiv <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; SSE2-NEXT: Cost Model: Found costs of 1 for: %I8 = udiv i8 undef, 16
+; SSE2-NEXT: Cost Model: Found costs of RThru:14 CodeSize:27 Lat:28 SizeLat:30 for: %V16i8 = udiv <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; SSE2-NEXT: Cost Model: Found costs of RThru:28 CodeSize:54 Lat:56 SizeLat:60 for: %V32i8 = udiv <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; SSE2-NEXT: Cost Model: Found costs of RThru:56 CodeSize:108 Lat:112 SizeLat:120 for: %V64i8 = udiv <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; SSE2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
+;
+; SSE42-LABEL: 'udiv_constpow2'
+; SSE42-NEXT: Cost Model: Found costs of 1 for: %I64 = udiv i64 undef, 16
+; SSE42-NEXT: Cost Model: Found costs of RThru:4 CodeSize:5 Lat:6 SizeLat:7 for: %V2i64 = udiv <2 x i64> undef, <i64 8, i64 16>
+; SSE42-NEXT: Cost Model: Found costs of RThru:8 CodeSize:10 Lat:12 SizeLat:14 for: %V4i64 = udiv <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
+; SSE42-NEXT: Cost Model: Found costs of RThru:16 CodeSize:20 Lat:24 SizeLat:28 for: %V8i64 = udiv <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
+; SSE42-NEXT: Cost Model: Found costs of 1 for: %I32 = udiv i32 undef, 16
+; SSE42-NEXT: Cost Model: Found costs of RThru:16 CodeSize:15 Lat:17 SizeLat:19 for: %V4i32 = udiv <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
+; SSE42-NEXT: Cost Model: Found costs of RThru:32 CodeSize:30 Lat:34 SizeLat:38 for: %V8i32 = udiv <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; SSE42-NEXT: Cost Model: Found costs of RThru:64 CodeSize:60 Lat:68 SizeLat:76 for: %V16i32 = udiv <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; SSE42-NEXT: Cost Model: Found costs of 1 for: %I16 = udiv i16 undef, 16
+; SSE42-NEXT: Cost Model: Found costs of RThru:22 CodeSize:23 Lat:26 SizeLat:27 for: %V8i16 = udiv <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; SSE42-NEXT: Cost Model: Found costs of RThru:44 CodeSize:46 Lat:52 SizeLat:54 for: %V16i16 = udiv <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; SSE42-NEXT: Cost Model: Found costs of RThru:88 CodeSize:92 Lat:104 SizeLat:108 for: %V32i16 = udiv <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; SSE42-NEXT: Cost Model: Found costs of 1 for: %I8 = udiv i8 undef, 16
+; SSE42-NEXT: Cost Model: Found costs of RThru:16 CodeSize:18 Lat:27 SizeLat:24 for: %V16i8 = udiv <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; SSE42-NEXT: Cost Model: Found costs of RThru:32 CodeSize:36 Lat:54 SizeLat:48 for: %V32i8 = udiv <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; SSE42-NEXT: Cost Model: Found costs of RThru:64 CodeSize:72 Lat:108 SizeLat:96 for: %V64i8 = udiv <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; SSE42-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX1-LABEL: 'udiv_constpow2'
-; AVX1-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = udiv i64 undef, 16
-; AVX1-NEXT: Cost Model: Found costs of RThru:40 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = udiv <2 x i64> undef, <i64 8, i64 16>
-; AVX1-NEXT: Cost Model: Found costs of RThru:80 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = udiv <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
-; AVX1-NEXT: Cost Model: Found costs of RThru:160 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = udiv <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
-; AVX1-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = udiv i32 undef, 16
-; AVX1-NEXT: Cost Model: Found costs of RThru:15 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = udiv <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
-; AVX1-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = udiv <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; AVX1-NEXT: Cost Model: Found costs of RThru:64 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = udiv <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; AVX1-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I16 = udiv i16 undef, 16
-; AVX1-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = udiv <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; AVX1-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = udiv <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; AVX1-NEXT: Cost Model: Found costs of RThru:28 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = udiv <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; AVX1-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = udiv i8 undef, 16
-; AVX1-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = udiv <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; AVX1-NEXT: Cost Model: Found costs of RThru:30 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = udiv <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; AVX1-NEXT: Cost Model: Found costs of RThru:60 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = udiv <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; AVX1-NEXT: Cost Model: Found costs of 1 for: %I64 = udiv i64 undef, 16
+; AVX1-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:6 for: %V2i64 = udiv <2 x i64> undef, <i64 8, i64 16>
+; AVX1-NEXT: Cost Model: Found costs of RThru:6 CodeSize:11 Lat:7 SizeLat:15 for: %V4i64 = udiv <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
+; AVX1-NEXT: Cost Model: Found costs of RThru:12 CodeSize:22 Lat:14 SizeLat:30 for: %V8i64 = udiv <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
+; AVX1-NEXT: Cost Model: Found costs of 1 for: %I32 = udiv i32 undef, 16
+; AVX1-NEXT: Cost Model: Found costs of RThru:6 CodeSize:12 Lat:7 SizeLat:16 for: %V4i32 = udiv <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
+; AVX1-NEXT: Cost Model: Found costs of RThru:14 CodeSize:26 Lat:14 SizeLat:34 for: %V8i32 = udiv <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; AVX1-NEXT: Cost Model: Found costs of RThru:28 CodeSize:52 Lat:28 SizeLat:68 for: %V16i32 = udiv <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; AVX1-NEXT: Cost Model: Found costs of 1 for: %I16 = udiv i16 undef, 16
+; AVX1-NEXT: Cost Model: Found costs of RThru:13 CodeSize:14 Lat:16 SizeLat:22 for: %V8i16 = udiv <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; AVX1-NEXT: Cost Model: Found costs of RThru:28 CodeSize:31 Lat:30 SizeLat:48 for: %V16i16 = udiv <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; AVX1-NEXT: Cost Model: Found costs of RThru:56 CodeSize:62 Lat:60 SizeLat:96 for: %V32i16 = udiv <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; AVX1-NEXT: Cost Model: Found costs of 1 for: %I8 = udiv i8 undef, 16
+; AVX1-NEXT: Cost Model: Found costs of RThru:11 CodeSize:12 Lat:27 SizeLat:18 for: %V16i8 = udiv <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; AVX1-NEXT: Cost Model: Found costs of RThru:23 CodeSize:30 Lat:23 SizeLat:43 for: %V32i8 = udiv <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; AVX1-NEXT: Cost Model: Found costs of RThru:46 CodeSize:60 Lat:46 SizeLat:86 for: %V64i8 = udiv <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
; AVX1-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX2-LABEL: 'udiv_constpow2'
-; AVX2-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = udiv i64 undef, 16
-; AVX2-NEXT: Cost Model: Found costs of RThru:40 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = udiv <2 x i64> undef, <i64 8, i64 16>
-; AVX2-NEXT: Cost Model: Found costs of RThru:80 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = udiv <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
-; AVX2-NEXT: Cost Model: Found costs of RThru:160 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = udiv <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
-; AVX2-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = udiv i32 undef, 16
-; AVX2-NEXT: Cost Model: Found costs of RThru:15 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = udiv <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
-; AVX2-NEXT: Cost Model: Found costs of RThru:15 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = udiv <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; AVX2-NEXT: Cost Model: Found costs of RThru:30 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = udiv <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; AVX2-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I16 = udiv i16 undef, 16
-; AVX2-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = udiv <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; AVX2-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = udiv <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; AVX2-NEXT: Cost Model: Found costs of RThru:12 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = udiv <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; AVX2-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = udiv i8 undef, 16
-; AVX2-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = udiv <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; AVX2-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = udiv <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; AVX2-NEXT: Cost Model: Found costs of RThru:28 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = udiv <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; AVX2-NEXT: Cost Model: Found costs of 1 for: %I64 = udiv i64 undef, 16
+; AVX2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:3 SizeLat:1 for: %V2i64 = udiv <2 x i64> undef, <i64 8, i64 16>
+; AVX2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:4 SizeLat:2 for: %V4i64 = udiv <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
+; AVX2-NEXT: Cost Model: Found costs of RThru:8 CodeSize:2 Lat:8 SizeLat:4 for: %V8i64 = udiv <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
+; AVX2-NEXT: Cost Model: Found costs of 1 for: %I32 = udiv i32 undef, 16
+; AVX2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:3 SizeLat:3 for: %V4i32 = udiv <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
+; AVX2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:4 SizeLat:3 for: %V8i32 = udiv <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; AVX2-NEXT: Cost Model: Found costs of RThru:8 CodeSize:2 Lat:8 SizeLat:6 for: %V16i32 = udiv <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; AVX2-NEXT: Cost Model: Found costs of 1 for: %I16 = udiv i16 undef, 16
+; AVX2-NEXT: Cost Model: Found costs of RThru:5 CodeSize:5 Lat:11 SizeLat:10 for: %V8i16 = udiv <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; AVX2-NEXT: Cost Model: Found costs of RThru:8 CodeSize:10 Lat:10 SizeLat:14 for: %V16i16 = udiv <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; AVX2-NEXT: Cost Model: Found costs of RThru:16 CodeSize:20 Lat:20 SizeLat:28 for: %V32i16 = udiv <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; AVX2-NEXT: Cost Model: Found costs of 1 for: %I8 = udiv i8 undef, 16
+; AVX2-NEXT: Cost Model: Found costs of RThru:6 CodeSize:12 Lat:27 SizeLat:18 for: %V16i8 = udiv <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; AVX2-NEXT: Cost Model: Found costs of RThru:8 CodeSize:12 Lat:30 SizeLat:24 for: %V32i8 = udiv <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; AVX2-NEXT: Cost Model: Found costs of RThru:16 CodeSize:24 Lat:60 SizeLat:48 for: %V64i8 = udiv <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
; AVX2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX512F-LABEL: 'udiv_constpow2'
-; AVX512F-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = udiv i64 undef, 16
-; AVX512F-NEXT: Cost Model: Found costs of RThru:40 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = udiv <2 x i64> undef, <i64 8, i64 16>
-; AVX512F-NEXT: Cost Model: Found costs of RThru:80 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = udiv <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
-; AVX512F-NEXT: Cost Model: Found costs of RThru:160 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = udiv <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
-; AVX512F-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = udiv i32 undef, 16
-; AVX512F-NEXT: Cost Model: Found costs of RThru:15 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = udiv <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
-; AVX512F-NEXT: Cost Model: Found costs of RThru:15 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = udiv <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; AVX512F-NEXT: Cost Model: Found costs of RThru:15 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = udiv <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; AVX512F-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I16 = udiv i16 undef, 16
-; AVX512F-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = udiv <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; AVX512F-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = udiv <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; AVX512F-NEXT: Cost Model: Found costs of RThru:12 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = udiv <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; AVX512F-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = udiv i8 undef, 16
-; AVX512F-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = udiv <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; AVX512F-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = udiv <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; AVX512F-NEXT: Cost Model: Found costs of RThru:28 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = udiv <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; AVX512F-NEXT: Cost Model: Found costs of 1 for: %I64 = udiv i64 undef, 16
+; AVX512F-NEXT: Cost Model: Found costs of 1 for: %V2i64 = udiv <2 x i64> undef, <i64 8, i64 16>
+; AVX512F-NEXT: Cost Model: Found costs of 1 for: %V4i64 = udiv <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
+; AVX512F-NEXT: Cost Model: Found costs of 1 for: %V8i64 = udiv <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
+; AVX512F-NEXT: Cost Model: Found costs of 1 for: %I32 = udiv i32 undef, 16
+; AVX512F-NEXT: Cost Model: Found costs of 1 for: %V4i32 = udiv <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
+; AVX512F-NEXT: Cost Model: Found costs of 1 for: %V8i32 = udiv <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; AVX512F-NEXT: Cost Model: Found costs of 1 for: %V16i32 = udiv <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; AVX512F-NEXT: Cost Model: Found costs of 1 for: %I16 = udiv i16 undef, 16
+; AVX512F-NEXT: Cost Model: Found costs of RThru:5 CodeSize:5 Lat:11 SizeLat:10 for: %V8i16 = udiv <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; AVX512F-NEXT: Cost Model: Found costs of RThru:8 CodeSize:10 Lat:10 SizeLat:14 for: %V16i16 = udiv <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; AVX512F-NEXT: Cost Model: Found costs of RThru:11 CodeSize:11 Lat:16 SizeLat:15 for: %V32i16 = udiv <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; AVX512F-NEXT: Cost Model: Found costs of 1 for: %I8 = udiv i8 undef, 16
+; AVX512F-NEXT: Cost Model: Found costs of RThru:6 CodeSize:12 Lat:27 SizeLat:18 for: %V16i8 = udiv <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; AVX512F-NEXT: Cost Model: Found costs of RThru:8 CodeSize:12 Lat:30 SizeLat:24 for: %V32i8 = udiv <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; AVX512F-NEXT: Cost Model: Found costs of RThru:15 CodeSize:30 Lat:19 SizeLat:36 for: %V64i8 = udiv <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
; AVX512F-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX512BW-LABEL: 'udiv_constpow2'
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = udiv i64 undef, 16
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:40 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = udiv <2 x i64> undef, <i64 8, i64 16>
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:80 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = udiv <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:160 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = udiv <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = udiv i32 undef, 16
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:15 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = udiv <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:15 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = udiv <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:15 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = udiv <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I16 = udiv i16 undef, 16
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = udiv <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = udiv <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = udiv <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = udiv i8 undef, 16
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = udiv <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = udiv <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = udiv <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %I64 = udiv i64 undef, 16
+; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %V2i64 = udiv <2 x i64> undef, <i64 8, i64 16>
+; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %V4i64 = udiv <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
+; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %V8i64 = udiv <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
+; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %I32 = udiv i32 undef, 16
+; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %V4i32 = udiv <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
+; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %V8i32 = udiv <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %V16i32 = udiv <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %I16 = udiv i16 undef, 16
+; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %V8i16 = udiv <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %V16i16 = udiv <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %V32i16 = udiv <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %I8 = udiv i8 undef, 16
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:4 CodeSize:4 Lat:8 SizeLat:5 for: %V16i8 = udiv <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:4 CodeSize:12 Lat:30 SizeLat:18 for: %V32i8 = udiv <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:7 CodeSize:15 Lat:27 SizeLat:18 for: %V64i8 = udiv <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
; AVX512BW-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
+;
+; SLM-LABEL: 'udiv_constpow2'
+; SLM-NEXT: Cost Model: Found costs of 1 for: %I64 = udiv i64 undef, 16
+; SLM-NEXT: Cost Model: Found costs of RThru:4 CodeSize:5 Lat:6 SizeLat:7 for: %V2i64 = udiv <2 x i64> undef, <i64 8, i64 16>
+; SLM-NEXT: Cost Model: Found costs of RThru:8 CodeSize:10 Lat:12 SizeLat:14 for: %V4i64 = udiv <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
+; SLM-NEXT: Cost Model: Found costs of RThru:16 CodeSize:20 Lat:24 SizeLat:28 for: %V8i64 = udiv <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
+; SLM-NEXT: Cost Model: Found costs of 1 for: %I32 = udiv i32 undef, 16
+; SLM-NEXT: Cost Model: Found costs of RThru:16 CodeSize:15 Lat:17 SizeLat:19 for: %V4i32 = udiv <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
+; SLM-NEXT: Cost Model: Found costs of RThru:32 CodeSize:30 Lat:34 SizeLat:38 for: %V8i32 = udiv <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; SLM-NEXT: Cost Model: Found costs of RThru:64 CodeSize:60 Lat:68 SizeLat:76 for: %V16i32 = udiv <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; SLM-NEXT: Cost Model: Found costs of 1 for: %I16 = udiv i16 undef, 16
+; SLM-NEXT: Cost Model: Found costs of RThru:22 CodeSize:23 Lat:26 SizeLat:27 for: %V8i16 = udiv <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; SLM-NEXT: Cost Model: Found costs of RThru:44 CodeSize:46 Lat:52 SizeLat:54 for: %V16i16 = udiv <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; SLM-NEXT: Cost Model: Found costs of RThru:88 CodeSize:92 Lat:104 SizeLat:108 for: %V32i16 = udiv <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; SLM-NEXT: Cost Model: Found costs of 1 for: %I8 = udiv i8 undef, 16
+; SLM-NEXT: Cost Model: Found costs of RThru:16 CodeSize:18 Lat:27 SizeLat:24 for: %V16i8 = udiv <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; SLM-NEXT: Cost Model: Found costs of RThru:32 CodeSize:36 Lat:54 SizeLat:48 for: %V32i8 = udiv <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; SLM-NEXT: Cost Model: Found costs of RThru:64 CodeSize:72 Lat:108 SizeLat:96 for: %V64i8 = udiv <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; SLM-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
%I64 = udiv i64 undef, 16
%V2i64 = udiv <2 x i64> undef, <i64 8, i64 16>
@@ -1046,98 +1084,98 @@ define i32 @sdiv_uniformconstpow2() {
define i32 @udiv_uniformconstpow2() {
; SSE-LABEL: 'udiv_uniformconstpow2'
-; SSE-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = udiv i64 undef, 16
-; SSE-NEXT: Cost Model: Found costs of RThru:40 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = udiv <2 x i64> undef, splat (i64 16)
-; SSE-NEXT: Cost Model: Found costs of RThru:80 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = udiv <4 x i64> undef, splat (i64 16)
-; SSE-NEXT: Cost Model: Found costs of RThru:160 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = udiv <8 x i64> undef, splat (i64 16)
-; SSE-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = udiv i32 undef, 16
-; SSE-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = udiv <4 x i32> undef, splat (i32 16)
-; SSE-NEXT: Cost Model: Found costs of RThru:10 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = udiv <8 x i32> undef, splat (i32 16)
-; SSE-NEXT: Cost Model: Found costs of RThru:20 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = udiv <16 x i32> undef, splat (i32 16)
-; SSE-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I16 = udiv i16 undef, 16
-; SSE-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = udiv <8 x i16> undef, splat (i16 16)
-; SSE-NEXT: Cost Model: Found costs of RThru:12 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = udiv <16 x i16> undef, splat (i16 16)
-; SSE-NEXT: Cost Model: Found costs of RThru:24 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = udiv <32 x i16> undef, splat (i16 16)
-; SSE-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = udiv i8 undef, 16
-; SSE-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = udiv <16 x i8> undef, splat (i8 16)
-; SSE-NEXT: Cost Model: Found costs of RThru:28 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = udiv <32 x i8> undef, splat (i8 16)
-; SSE-NEXT: Cost Model: Found costs of RThru:56 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = udiv <64 x i8> undef, splat (i8 16)
+; SSE-NEXT: Cost Model: Found costs of 1 for: %I64 = udiv i64 undef, 16
+; SSE-NEXT: Cost Model: Found costs of 1 for: %V2i64 = udiv <2 x i64> undef, splat (i64 16)
+; SSE-NEXT: Cost Model: Found costs of 2 for: %V4i64 = udiv <4 x i64> undef, splat (i64 16)
+; SSE-NEXT: Cost Model: Found costs of 4 for: %V8i64 = udiv <8 x i64> undef, splat (i64 16)
+; SSE-NEXT: Cost Model: Found costs of 1 for: %I32 = udiv i32 undef, 16
+; SSE-NEXT: Cost Model: Found costs of 1 for: %V4i32 = udiv <4 x i32> undef, splat (i32 16)
+; SSE-NEXT: Cost Model: Found costs of 2 for: %V8i32 = udiv <8 x i32> undef, splat (i32 16)
+; SSE-NEXT: Cost Model: Found costs of 4 for: %V16i32 = udiv <16 x i32> undef, splat (i32 16)
+; SSE-NEXT: Cost Model: Found costs of 1 for: %I16 = udiv i16 undef, 16
+; SSE-NEXT: Cost Model: Found costs of 1 for: %V8i16 = udiv <8 x i16> undef, splat (i16 16)
+; SSE-NEXT: Cost Model: Found costs of 2 for: %V16i16 = udiv <16 x i16> undef, splat (i16 16)
+; SSE-NEXT: Cost Model: Found costs of 4 for: %V32i16 = udiv <32 x i16> undef, splat (i16 16)
+; SSE-NEXT: Cost Model: Found costs of 1 for: %I8 = udiv i8 undef, 16
+; SSE-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:7 SizeLat:3 for: %V16i8 = udiv <16 x i8> undef, splat (i8 16)
+; SSE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:14 SizeLat:6 for: %V32i8 = udiv <32 x i8> undef, splat (i8 16)
+; SSE-NEXT: Cost Model: Found costs of RThru:4 CodeSize:8 Lat:28 SizeLat:12 for: %V64i8 = udiv <64 x i8> undef, splat (i8 16)
; SSE-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX1-LABEL: 'udiv_uniformconstpow2'
-; AVX1-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = udiv i64 undef, 16
-; AVX1-NEXT: Cost Model: Found costs of RThru:40 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = udiv <2 x i64> undef, splat (i64 16)
-; AVX1-NEXT: Cost Model: Found costs of RThru:80 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = udiv <4 x i64> undef, splat (i64 16)
-; AVX1-NEXT: Cost Model: Found costs of RThru:160 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = udiv <8 x i64> undef, splat (i64 16)
-; AVX1-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = udiv i32 undef, 16
-; AVX1-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = udiv <4 x i32> undef, splat (i32 16)
-; AVX1-NEXT: Cost Model: Found costs of RThru:12 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = udiv <8 x i32> undef, splat (i32 16)
-; AVX1-NEXT: Cost Model: Found costs of RThru:24 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = udiv <16 x i32> undef, splat (i32 16)
-; AVX1-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I16 = udiv i16 undef, 16
-; AVX1-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = udiv <8 x i16> undef, splat (i16 16)
-; AVX1-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = udiv <16 x i16> undef, splat (i16 16)
-; AVX1-NEXT: Cost Model: Found costs of RThru:28 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = udiv <32 x i16> undef, splat (i16 16)
-; AVX1-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = udiv i8 undef, 16
-; AVX1-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = udiv <16 x i8> undef, splat (i8 16)
-; AVX1-NEXT: Cost Model: Found costs of RThru:30 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = udiv <32 x i8> undef, splat (i8 16)
-; AVX1-NEXT: Cost Model: Found costs of RThru:60 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = udiv <64 x i8> undef, splat (i8 16)
+; AVX1-NEXT: Cost Model: Found costs of 1 for: %I64 = udiv i64 undef, 16
+; AVX1-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:2 SizeLat:1 for: %V2i64 = udiv <2 x i64> undef, splat (i64 16)
+; AVX1-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:6 SizeLat:5 for: %V4i64 = udiv <4 x i64> undef, splat (i64 16)
+; AVX1-NEXT: Cost Model: Found costs of RThru:6 CodeSize:8 Lat:12 SizeLat:10 for: %V8i64 = udiv <8 x i64> undef, splat (i64 16)
+; AVX1-NEXT: Cost Model: Found costs of 1 for: %I32 = udiv i32 undef, 16
+; AVX1-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:2 SizeLat:1 for: %V4i32 = udiv <4 x i32> undef, splat (i32 16)
+; AVX1-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:6 SizeLat:5 for: %V8i32 = udiv <8 x i32> undef, splat (i32 16)
+; AVX1-NEXT: Cost Model: Found costs of RThru:6 CodeSize:8 Lat:12 SizeLat:10 for: %V16i32 = udiv <16 x i32> undef, splat (i32 16)
+; AVX1-NEXT: Cost Model: Found costs of 1 for: %I16 = udiv i16 undef, 16
+; AVX1-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:2 SizeLat:1 for: %V8i16 = udiv <8 x i16> undef, splat (i16 16)
+; AVX1-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:6 SizeLat:5 for: %V16i16 = udiv <16 x i16> undef, splat (i16 16)
+; AVX1-NEXT: Cost Model: Found costs of RThru:6 CodeSize:8 Lat:12 SizeLat:10 for: %V32i16 = udiv <32 x i16> undef, splat (i16 16)
+; AVX1-NEXT: Cost Model: Found costs of 1 for: %I8 = udiv i8 undef, 16
+; AVX1-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:7 SizeLat:3 for: %V16i8 = udiv <16 x i8> undef, splat (i8 16)
+; AVX1-NEXT: Cost Model: Found costs of RThru:4 CodeSize:7 Lat:7 SizeLat:8 for: %V32i8 = udiv <32 x i8> undef, splat (i8 16)
+; AVX1-NEXT: Cost Model: Found costs of RThru:8 CodeSize:14 Lat:14 SizeLat:16 for: %V64i8 = udiv <64 x i8> undef, splat (i8 16)
; AVX1-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX2-LABEL: 'udiv_uniformconstpow2'
-; AVX2-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = udiv i64 undef, 16
-; AVX2-NEXT: Cost Model: Found costs of RThru:40 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = udiv <2 x i64> undef, splat (i64 16)
-; AVX2-NEXT: Cost Model: Found costs of RThru:80 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = udiv <4 x i64> undef, splat (i64 16)
-; AVX2-NEXT: Cost Model: Found costs of RThru:160 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = udiv <8 x i64> undef, splat (i64 16)
-; AVX2-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = udiv i32 undef, 16
-; AVX2-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = udiv <4 x i32> undef, splat (i32 16)
-; AVX2-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = udiv <8 x i32> undef, splat (i32 16)
-; AVX2-NEXT: Cost Model: Found costs of RThru:10 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = udiv <16 x i32> undef, splat (i32 16)
-; AVX2-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I16 = udiv i16 undef, 16
-; AVX2-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = udiv <8 x i16> undef, splat (i16 16)
-; AVX2-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = udiv <16 x i16> undef, splat (i16 16)
-; AVX2-NEXT: Cost Model: Found costs of RThru:12 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = udiv <32 x i16> undef, splat (i16 16)
-; AVX2-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = udiv i8 undef, 16
-; AVX2-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = udiv <16 x i8> undef, splat (i8 16)
-; AVX2-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = udiv <32 x i8> undef, splat (i8 16)
-; AVX2-NEXT: Cost Model: Found costs of RThru:28 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = udiv <64 x i8> undef, splat (i8 16)
+; AVX2-NEXT: Cost Model: Found costs of 1 for: %I64 = udiv i64 undef, 16
+; AVX2-NEXT: Cost Model: Found costs of 1 for: %V2i64 = udiv <2 x i64> undef, splat (i64 16)
+; AVX2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %V4i64 = udiv <4 x i64> undef, splat (i64 16)
+; AVX2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:2 Lat:4 SizeLat:4 for: %V8i64 = udiv <8 x i64> undef, splat (i64 16)
+; AVX2-NEXT: Cost Model: Found costs of 1 for: %I32 = udiv i32 undef, 16
+; AVX2-NEXT: Cost Model: Found costs of 1 for: %V4i32 = udiv <4 x i32> undef, splat (i32 16)
+; AVX2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %V8i32 = udiv <8 x i32> undef, splat (i32 16)
+; AVX2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:2 Lat:4 SizeLat:4 for: %V16i32 = udiv <16 x i32> undef, splat (i32 16)
+; AVX2-NEXT: Cost Model: Found costs of 1 for: %I16 = udiv i16 undef, 16
+; AVX2-NEXT: Cost Model: Found costs of 1 for: %V8i16 = udiv <8 x i16> undef, splat (i16 16)
+; AVX2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %V16i16 = udiv <16 x i16> undef, splat (i16 16)
+; AVX2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:2 Lat:4 SizeLat:4 for: %V32i16 = udiv <32 x i16> undef, splat (i16 16)
+; AVX2-NEXT: Cost Model: Found costs of 1 for: %I8 = udiv i8 undef, 16
+; AVX2-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:8 SizeLat:3 for: %V16i8 = udiv <16 x i8> undef, splat (i8 16)
+; AVX2-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:8 SizeLat:4 for: %V32i8 = udiv <32 x i8> undef, splat (i8 16)
+; AVX2-NEXT: Cost Model: Found costs of RThru:4 CodeSize:4 Lat:16 SizeLat:8 for: %V64i8 = udiv <64 x i8> undef, splat (i8 16)
; AVX2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX512F-LABEL: 'udiv_uniformconstpow2'
-; AVX512F-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = udiv i64 undef, 16
-; AVX512F-NEXT: Cost Model: Found costs of RThru:40 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = udiv <2 x i64> undef, splat (i64 16)
-; AVX512F-NEXT: Cost Model: Found costs of RThru:80 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = udiv <4 x i64> undef, splat (i64 16)
-; AVX512F-NEXT: Cost Model: Found costs of RThru:160 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = udiv <8 x i64> undef, splat (i64 16)
-; AVX512F-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = udiv i32 undef, 16
-; AVX512F-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = udiv <4 x i32> undef, splat (i32 16)
-; AVX512F-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = udiv <8 x i32> undef, splat (i32 16)
-; AVX512F-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = udiv <16 x i32> undef, splat (i32 16)
-; AVX512F-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I16 = udiv i16 undef, 16
-; AVX512F-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = udiv <8 x i16> undef, splat (i16 16)
-; AVX512F-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = udiv <16 x i16> undef, splat (i16 16)
-; AVX512F-NEXT: Cost Model: Found costs of RThru:12 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = udiv <32 x i16> undef, splat (i16 16)
-; AVX512F-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = udiv i8 undef, 16
-; AVX512F-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = udiv <16 x i8> undef, splat (i8 16)
-; AVX512F-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = udiv <32 x i8> undef, splat (i8 16)
-; AVX512F-NEXT: Cost Model: Found costs of RThru:28 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = udiv <64 x i8> undef, splat (i8 16)
+; AVX512F-NEXT: Cost Model: Found costs of 1 for: %I64 = udiv i64 undef, 16
+; AVX512F-NEXT: Cost Model: Found costs of 1 for: %V2i64 = udiv <2 x i64> undef, splat (i64 16)
+; AVX512F-NEXT: Cost Model: Found costs of 1 for: %V4i64 = udiv <4 x i64> undef, splat (i64 16)
+; AVX512F-NEXT: Cost Model: Found costs of 1 for: %V8i64 = udiv <8 x i64> undef, splat (i64 16)
+; AVX512F-NEXT: Cost Model: Found costs of 1 for: %I32 = udiv i32 undef, 16
+; AVX512F-NEXT: Cost Model: Found costs of 1 for: %V4i32 = udiv <4 x i32> undef, splat (i32 16)
+; AVX512F-NEXT: Cost Model: Found costs of 1 for: %V8i32 = udiv <8 x i32> undef, splat (i32 16)
+; AVX512F-NEXT: Cost Model: Found costs of 1 for: %V16i32 = udiv <16 x i32> undef, splat (i32 16)
+; AVX512F-NEXT: Cost Model: Found costs of 1 for: %I16 = udiv i16 undef, 16
+; AVX512F-NEXT: Cost Model: Found costs of 1 for: %V8i16 = udiv <8 x i16> undef, splat (i16 16)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:7 SizeLat:4 for: %V16i16 = udiv <16 x i16> undef, splat (i16 16)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:5 CodeSize:5 Lat:10 SizeLat:7 for: %V32i16 = udiv <32 x i16> undef, splat (i16 16)
+; AVX512F-NEXT: Cost Model: Found costs of 1 for: %I8 = udiv i8 undef, 16
+; AVX512F-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:8 SizeLat:3 for: %V16i8 = udiv <16 x i8> undef, splat (i8 16)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:8 SizeLat:4 for: %V32i8 = udiv <32 x i8> undef, splat (i8 16)
+; AVX512F-NEXT: Cost Model: Found costs of RThru:2 CodeSize:5 Lat:12 SizeLat:6 for: %V64i8 = udiv <64 x i8> undef, splat (i8 16)
; AVX512F-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
; AVX512BW-LABEL: 'udiv_uniformconstpow2'
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = udiv i64 undef, 16
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:40 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = udiv <2 x i64> undef, splat (i64 16)
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:80 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = udiv <4 x i64> undef, splat (i64 16)
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:160 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = udiv <8 x i64> undef, splat (i64 16)
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = udiv i32 undef, 16
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = udiv <4 x i32> undef, splat (i32 16)
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = udiv <8 x i32> undef, splat (i32 16)
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = udiv <16 x i32> undef, splat (i32 16)
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I16 = udiv i16 undef, 16
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = udiv <8 x i16> undef, splat (i16 16)
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = udiv <16 x i16> undef, splat (i16 16)
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:6 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = udiv <32 x i16> undef, splat (i16 16)
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = udiv i8 undef, 16
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = udiv <16 x i8> undef, splat (i8 16)
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = udiv <32 x i8> undef, splat (i8 16)
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = udiv <64 x i8> undef, splat (i8 16)
+; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %I64 = udiv i64 undef, 16
+; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %V2i64 = udiv <2 x i64> undef, splat (i64 16)
+; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %V4i64 = udiv <4 x i64> undef, splat (i64 16)
+; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %V8i64 = udiv <8 x i64> undef, splat (i64 16)
+; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %I32 = udiv i32 undef, 16
+; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %V4i32 = udiv <4 x i32> undef, splat (i32 16)
+; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %V8i32 = udiv <8 x i32> undef, splat (i32 16)
+; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %V16i32 = udiv <16 x i32> undef, splat (i32 16)
+; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %I16 = udiv i16 undef, 16
+; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %V8i16 = udiv <8 x i16> undef, splat (i16 16)
+; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %V16i16 = udiv <16 x i16> undef, splat (i16 16)
+; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %V32i16 = udiv <32 x i16> undef, splat (i16 16)
+; AVX512BW-NEXT: Cost Model: Found costs of 1 for: %I8 = udiv i8 undef, 16
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:7 SizeLat:3 for: %V16i8 = udiv <16 x i8> undef, splat (i8 16)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:8 SizeLat:3 for: %V32i8 = udiv <32 x i8> undef, splat (i8 16)
+; AVX512BW-NEXT: Cost Model: Found costs of RThru:1 CodeSize:2 Lat:8 SizeLat:3 for: %V64i8 = udiv <64 x i8> undef, splat (i8 16)
; AVX512BW-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
%I64 = udiv i64 undef, 16
diff --git a/llvm/test/Analysis/CostModel/X86/rem.ll b/llvm/test/Analysis/CostModel/X86/rem.ll
index 9dda1bcc6bb44..06b23c0cf6428 100644
--- a/llvm/test/Analysis/CostModel/X86/rem.ll
+++ b/llvm/test/Analysis/CostModel/X86/rem.ll
@@ -922,99 +922,61 @@ define i32 @srem_constpow2() {
define i32 @urem_constpow2() {
; SSE-LABEL: 'urem_constpow2'
-; SSE-NEXT: Cost Model: Found costs of 4 for: %I64 = urem i64 undef, 16
-; SSE-NEXT: Cost Model: Found costs of RThru:160 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = urem <2 x i64> undef, <i64 8, i64 16>
-; SSE-NEXT: Cost Model: Found costs of RThru:320 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = urem <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
-; SSE-NEXT: Cost Model: Found costs of RThru:640 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = urem <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
-; SSE-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = urem i32 undef, 16
-; SSE-NEXT: Cost Model: Found costs of RThru:20 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = urem <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
-; SSE-NEXT: Cost Model: Found costs of RThru:40 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = urem <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; SSE-NEXT: Cost Model: Found costs of RThru:80 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = urem <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; SSE-NEXT: Cost Model: Found costs of 4 for: %I16 = urem i16 undef, 16
-; SSE-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = urem <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; SSE-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = urem <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; SSE-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = urem <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; SSE-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = urem i8 undef, 16
-; SSE-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = urem <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; SSE-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = urem <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; SSE-NEXT: Cost Model: Found costs of RThru:64 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = urem <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; SSE-NEXT: Cost Model: Found costs of 1 for: %I64 = urem i64 undef, 16
+; SSE-NEXT: Cost Model: Found costs of 1 for: %V2i64 = urem <2 x i64> undef, <i64 8, i64 16>
+; SSE-NEXT: Cost Model: Found costs of 2 for: %V4i64 = urem <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
+; SSE-NEXT: Cost Model: Found costs of 4 for: %V8i64 = urem <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
+; SSE-NEXT: Cost Model: Found costs of 1 for: %I32 = urem i32 undef, 16
+; SSE-NEXT: Cost Model: Found costs of 1 for: %V4i32 = urem <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
+; SSE-NEXT: Cost Model: Found costs of 2 for: %V8i32 = urem <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; SSE-NEXT: Cost Model: Found costs of 4 for: %V16i32 = urem <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; SSE-NEXT: Cost Model: Found costs of 1 for: %I16 = urem i16 undef, 16
+; SSE-NEXT: Cost Model: Found costs of 1 for: %V8i16 = urem <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; SSE-NEXT: Cost Model: Found costs of 2 for: %V16i16 = urem <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; SSE-NEXT: Cost Model: Found costs of 4 for: %V32i16 = urem <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; SSE-NEXT: Cost Model: Found costs of 1 for: %I8 = urem i8 undef, 16
+; SSE-NEXT: Cost Model: Found costs of 1 for: %V16i8 = urem <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; SSE-NEXT: Cost Model: Found costs of 2 for: %V32i8 = urem <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; SSE-NEXT: Cost Model: Found costs of 4 for: %V64i8 = urem <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
; SSE-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
-; AVX1-LABEL: 'urem_constpow2'
-; AVX1-NEXT: Cost Model: Found costs of 4 for: %I64 = urem i64 undef, 16
-; AVX1-NEXT: Cost Model: Found costs of RThru:160 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = urem <2 x i64> undef, <i64 8, i64 16>
-; AVX1-NEXT: Cost Model: Found costs of RThru:320 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = urem <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
-; AVX1-NEXT: Cost Model: Found costs of RThru:640 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = urem <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
-; AVX1-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = urem i32 undef, 16
-; AVX1-NEXT: Cost Model: Found costs of RThru:20 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = urem <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
-; AVX1-NEXT: Cost Model: Found costs of RThru:42 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = urem <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; AVX1-NEXT: Cost Model: Found costs of RThru:84 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = urem <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; AVX1-NEXT: Cost Model: Found costs of 4 for: %I16 = urem i16 undef, 16
-; AVX1-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = urem <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; AVX1-NEXT: Cost Model: Found costs of RThru:18 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = urem <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; AVX1-NEXT: Cost Model: Found costs of RThru:36 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = urem <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; AVX1-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = urem i8 undef, 16
-; AVX1-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = urem <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; AVX1-NEXT: Cost Model: Found costs of RThru:34 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = urem <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; AVX1-NEXT: Cost Model: Found costs of RThru:68 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = urem <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; AVX1-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
-;
-; AVX2-LABEL: 'urem_constpow2'
-; AVX2-NEXT: Cost Model: Found costs of 4 for: %I64 = urem i64 undef, 16
-; AVX2-NEXT: Cost Model: Found costs of RThru:160 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = urem <2 x i64> undef, <i64 8, i64 16>
-; AVX2-NEXT: Cost Model: Found costs of RThru:320 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = urem <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
-; AVX2-NEXT: Cost Model: Found costs of RThru:640 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = urem <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
-; AVX2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = urem i32 undef, 16
-; AVX2-NEXT: Cost Model: Found costs of RThru:20 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = urem <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
-; AVX2-NEXT: Cost Model: Found costs of RThru:19 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = urem <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; AVX2-NEXT: Cost Model: Found costs of RThru:38 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = urem <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; AVX2-NEXT: Cost Model: Found costs of 4 for: %I16 = urem i16 undef, 16
-; AVX2-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = urem <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; AVX2-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = urem <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; AVX2-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = urem <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; AVX2-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = urem i8 undef, 16
-; AVX2-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = urem <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; AVX2-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = urem <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; AVX2-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = urem <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; AVX2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
-;
-; AVX512F-LABEL: 'urem_constpow2'
-; AVX512F-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = urem i64 undef, 16
-; AVX512F-NEXT: Cost Model: Found costs of RThru:120 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = urem <2 x i64> undef, <i64 8, i64 16>
-; AVX512F-NEXT: Cost Model: Found costs of RThru:240 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = urem <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
-; AVX512F-NEXT: Cost Model: Found costs of RThru:480 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = urem <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
-; AVX512F-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = urem i32 undef, 16
-; AVX512F-NEXT: Cost Model: Found costs of RThru:20 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = urem <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
-; AVX512F-NEXT: Cost Model: Found costs of RThru:19 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = urem <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; AVX512F-NEXT: Cost Model: Found costs of RThru:17 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = urem <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; AVX512F-NEXT: Cost Model: Found costs of 4 for: %I16 = urem i16 undef, 16
-; AVX512F-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = urem <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; AVX512F-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = urem <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; AVX512F-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = urem <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; AVX512F-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = urem i8 undef, 16
-; AVX512F-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = urem <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; AVX512F-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = urem <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; AVX512F-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = urem <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; AVX512F-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
+; AVX-LABEL: 'urem_constpow2'
+; AVX-NEXT: Cost Model: Found costs of 1 for: %I64 = urem i64 undef, 16
+; AVX-NEXT: Cost Model: Found costs of 1 for: %V2i64 = urem <2 x i64> undef, <i64 8, i64 16>
+; AVX-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:1 SizeLat:2 for: %V4i64 = urem <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
+; AVX-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:2 SizeLat:4 for: %V8i64 = urem <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
+; AVX-NEXT: Cost Model: Found costs of 1 for: %I32 = urem i32 undef, 16
+; AVX-NEXT: Cost Model: Found costs of 1 for: %V4i32 = urem <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
+; AVX-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:1 SizeLat:2 for: %V8i32 = urem <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; AVX-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:2 SizeLat:4 for: %V16i32 = urem <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; AVX-NEXT: Cost Model: Found costs of 1 for: %I16 = urem i16 undef, 16
+; AVX-NEXT: Cost Model: Found costs of 1 for: %V8i16 = urem <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; AVX-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:1 SizeLat:2 for: %V16i16 = urem <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; AVX-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:2 SizeLat:4 for: %V32i16 = urem <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; AVX-NEXT: Cost Model: Found costs of 1 for: %I8 = urem i8 undef, 16
+; AVX-NEXT: Cost Model: Found costs of 1 for: %V16i8 = urem <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; AVX-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:1 SizeLat:2 for: %V32i8 = urem <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; AVX-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:2 SizeLat:4 for: %V64i8 = urem <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; AVX-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
-; AVX512BW-LABEL: 'urem_constpow2'
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = urem i64 undef, 16
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:120 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = urem <2 x i64> undef, <i64 8, i64 16>
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:240 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = urem <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:480 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = urem <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = urem i32 undef, 16
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:20 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = urem <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:19 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = urem <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:17 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = urem <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; AVX512BW-NEXT: Cost Model: Found costs of 4 for: %I16 = urem i16 undef, 16
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = urem <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = urem <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = urem <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = urem i8 undef, 16
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = urem <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = urem <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = urem <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
+; AVX512-LABEL: 'urem_constpow2'
+; AVX512-NEXT: Cost Model: Found costs of 1 for: %I64 = urem i64 undef, 16
+; AVX512-NEXT: Cost Model: Found costs of 1 for: %V2i64 = urem <2 x i64> undef, <i64 8, i64 16>
+; AVX512-NEXT: Cost Model: Found costs of 1 for: %V4i64 = urem <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
+; AVX512-NEXT: Cost Model: Found costs of 1 for: %V8i64 = urem <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
+; AVX512-NEXT: Cost Model: Found costs of 1 for: %I32 = urem i32 undef, 16
+; AVX512-NEXT: Cost Model: Found costs of 1 for: %V4i32 = urem <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
+; AVX512-NEXT: Cost Model: Found costs of 1 for: %V8i32 = urem <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; AVX512-NEXT: Cost Model: Found costs of 1 for: %V16i32 = urem <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; AVX512-NEXT: Cost Model: Found costs of 1 for: %I16 = urem i16 undef, 16
+; AVX512-NEXT: Cost Model: Found costs of 1 for: %V8i16 = urem <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; AVX512-NEXT: Cost Model: Found costs of 1 for: %V16i16 = urem <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; AVX512-NEXT: Cost Model: Found costs of 1 for: %V32i16 = urem <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; AVX512-NEXT: Cost Model: Found costs of 1 for: %I8 = urem i8 undef, 16
+; AVX512-NEXT: Cost Model: Found costs of 1 for: %V16i8 = urem <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; AVX512-NEXT: Cost Model: Found costs of 1 for: %V32i8 = urem <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; AVX512-NEXT: Cost Model: Found costs of 1 for: %V64i8 = urem <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; AVX512-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
%I64 = urem i64 undef, 16
%V2i64 = urem <2 x i64> undef, <i64 8, i64 16>
@@ -1236,99 +1198,61 @@ define i32 @srem_uniformconstpow2() {
define i32 @urem_uniformconstpow2() {
; SSE-LABEL: 'urem_uniformconstpow2'
-; SSE-NEXT: Cost Model: Found costs of 4 for: %I64 = urem i64 undef, 16
-; SSE-NEXT: Cost Model: Found costs of RThru:160 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = urem <2 x i64> undef, splat (i64 16)
-; SSE-NEXT: Cost Model: Found costs of RThru:320 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = urem <4 x i64> undef, splat (i64 16)
-; SSE-NEXT: Cost Model: Found costs of RThru:640 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = urem <8 x i64> undef, splat (i64 16)
-; SSE-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = urem i32 undef, 16
-; SSE-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = urem <4 x i32> undef, splat (i32 16)
-; SSE-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = urem <8 x i32> undef, splat (i32 16)
-; SSE-NEXT: Cost Model: Found costs of RThru:28 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = urem <16 x i32> undef, splat (i32 16)
-; SSE-NEXT: Cost Model: Found costs of 4 for: %I16 = urem i16 undef, 16
-; SSE-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = urem <8 x i16> undef, splat (i16 16)
-; SSE-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = urem <16 x i16> undef, splat (i16 16)
-; SSE-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = urem <32 x i16> undef, splat (i16 16)
-; SSE-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = urem i8 undef, 16
-; SSE-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = urem <16 x i8> undef, splat (i8 16)
-; SSE-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = urem <32 x i8> undef, splat (i8 16)
-; SSE-NEXT: Cost Model: Found costs of RThru:64 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = urem <64 x i8> undef, splat (i8 16)
+; SSE-NEXT: Cost Model: Found costs of 1 for: %I64 = urem i64 undef, 16
+; SSE-NEXT: Cost Model: Found costs of 1 for: %V2i64 = urem <2 x i64> undef, splat (i64 16)
+; SSE-NEXT: Cost Model: Found costs of 2 for: %V4i64 = urem <4 x i64> undef, splat (i64 16)
+; SSE-NEXT: Cost Model: Found costs of 4 for: %V8i64 = urem <8 x i64> undef, splat (i64 16)
+; SSE-NEXT: Cost Model: Found costs of 1 for: %I32 = urem i32 undef, 16
+; SSE-NEXT: Cost Model: Found costs of 1 for: %V4i32 = urem <4 x i32> undef, splat (i32 16)
+; SSE-NEXT: Cost Model: Found costs of 2 for: %V8i32 = urem <8 x i32> undef, splat (i32 16)
+; SSE-NEXT: Cost Model: Found costs of 4 for: %V16i32 = urem <16 x i32> undef, splat (i32 16)
+; SSE-NEXT: Cost Model: Found costs of 1 for: %I16 = urem i16 undef, 16
+; SSE-NEXT: Cost Model: Found costs of 1 for: %V8i16 = urem <8 x i16> undef, splat (i16 16)
+; SSE-NEXT: Cost Model: Found costs of 2 for: %V16i16 = urem <16 x i16> undef, splat (i16 16)
+; SSE-NEXT: Cost Model: Found costs of 4 for: %V32i16 = urem <32 x i16> undef, splat (i16 16)
+; SSE-NEXT: Cost Model: Found costs of 1 for: %I8 = urem i8 undef, 16
+; SSE-NEXT: Cost Model: Found costs of 1 for: %V16i8 = urem <16 x i8> undef, splat (i8 16)
+; SSE-NEXT: Cost Model: Found costs of 2 for: %V32i8 = urem <32 x i8> undef, splat (i8 16)
+; SSE-NEXT: Cost Model: Found costs of 4 for: %V64i8 = urem <64 x i8> undef, splat (i8 16)
; SSE-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
-; AVX1-LABEL: 'urem_uniformconstpow2'
-; AVX1-NEXT: Cost Model: Found costs of 4 for: %I64 = urem i64 undef, 16
-; AVX1-NEXT: Cost Model: Found costs of RThru:160 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = urem <2 x i64> undef, splat (i64 16)
-; AVX1-NEXT: Cost Model: Found costs of RThru:320 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = urem <4 x i64> undef, splat (i64 16)
-; AVX1-NEXT: Cost Model: Found costs of RThru:640 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = urem <8 x i64> undef, splat (i64 16)
-; AVX1-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = urem i32 undef, 16
-; AVX1-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = urem <4 x i32> undef, splat (i32 16)
-; AVX1-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = urem <8 x i32> undef, splat (i32 16)
-; AVX1-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = urem <16 x i32> undef, splat (i32 16)
-; AVX1-NEXT: Cost Model: Found costs of 4 for: %I16 = urem i16 undef, 16
-; AVX1-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = urem <8 x i16> undef, splat (i16 16)
-; AVX1-NEXT: Cost Model: Found costs of RThru:18 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = urem <16 x i16> undef, splat (i16 16)
-; AVX1-NEXT: Cost Model: Found costs of RThru:36 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = urem <32 x i16> undef, splat (i16 16)
-; AVX1-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = urem i8 undef, 16
-; AVX1-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = urem <16 x i8> undef, splat (i8 16)
-; AVX1-NEXT: Cost Model: Found costs of RThru:34 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = urem <32 x i8> undef, splat (i8 16)
-; AVX1-NEXT: Cost Model: Found costs of RThru:68 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = urem <64 x i8> undef, splat (i8 16)
-; AVX1-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
-;
-; AVX2-LABEL: 'urem_uniformconstpow2'
-; AVX2-NEXT: Cost Model: Found costs of 4 for: %I64 = urem i64 undef, 16
-; AVX2-NEXT: Cost Model: Found costs of RThru:160 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = urem <2 x i64> undef, splat (i64 16)
-; AVX2-NEXT: Cost Model: Found costs of RThru:320 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = urem <4 x i64> undef, splat (i64 16)
-; AVX2-NEXT: Cost Model: Found costs of RThru:640 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = urem <8 x i64> undef, splat (i64 16)
-; AVX2-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = urem i32 undef, 16
-; AVX2-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = urem <4 x i32> undef, splat (i32 16)
-; AVX2-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = urem <8 x i32> undef, splat (i32 16)
-; AVX2-NEXT: Cost Model: Found costs of RThru:14 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = urem <16 x i32> undef, splat (i32 16)
-; AVX2-NEXT: Cost Model: Found costs of 4 for: %I16 = urem i16 undef, 16
-; AVX2-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = urem <8 x i16> undef, splat (i16 16)
-; AVX2-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = urem <16 x i16> undef, splat (i16 16)
-; AVX2-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = urem <32 x i16> undef, splat (i16 16)
-; AVX2-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = urem i8 undef, 16
-; AVX2-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = urem <16 x i8> undef, splat (i8 16)
-; AVX2-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = urem <32 x i8> undef, splat (i8 16)
-; AVX2-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = urem <64 x i8> undef, splat (i8 16)
-; AVX2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
-;
-; AVX512F-LABEL: 'urem_uniformconstpow2'
-; AVX512F-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = urem i64 undef, 16
-; AVX512F-NEXT: Cost Model: Found costs of RThru:120 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = urem <2 x i64> undef, splat (i64 16)
-; AVX512F-NEXT: Cost Model: Found costs of RThru:240 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = urem <4 x i64> undef, splat (i64 16)
-; AVX512F-NEXT: Cost Model: Found costs of RThru:480 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = urem <8 x i64> undef, splat (i64 16)
-; AVX512F-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = urem i32 undef, 16
-; AVX512F-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = urem <4 x i32> undef, splat (i32 16)
-; AVX512F-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = urem <8 x i32> undef, splat (i32 16)
-; AVX512F-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = urem <16 x i32> undef, splat (i32 16)
-; AVX512F-NEXT: Cost Model: Found costs of 4 for: %I16 = urem i16 undef, 16
-; AVX512F-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = urem <8 x i16> undef, splat (i16 16)
-; AVX512F-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = urem <16 x i16> undef, splat (i16 16)
-; AVX512F-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = urem <32 x i16> undef, splat (i16 16)
-; AVX512F-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = urem i8 undef, 16
-; AVX512F-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = urem <16 x i8> undef, splat (i8 16)
-; AVX512F-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = urem <32 x i8> undef, splat (i8 16)
-; AVX512F-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = urem <64 x i8> undef, splat (i8 16)
-; AVX512F-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
+; AVX-LABEL: 'urem_uniformconstpow2'
+; AVX-NEXT: Cost Model: Found costs of 1 for: %I64 = urem i64 undef, 16
+; AVX-NEXT: Cost Model: Found costs of 1 for: %V2i64 = urem <2 x i64> undef, splat (i64 16)
+; AVX-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:1 SizeLat:2 for: %V4i64 = urem <4 x i64> undef, splat (i64 16)
+; AVX-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:2 SizeLat:4 for: %V8i64 = urem <8 x i64> undef, splat (i64 16)
+; AVX-NEXT: Cost Model: Found costs of 1 for: %I32 = urem i32 undef, 16
+; AVX-NEXT: Cost Model: Found costs of 1 for: %V4i32 = urem <4 x i32> undef, splat (i32 16)
+; AVX-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:1 SizeLat:2 for: %V8i32 = urem <8 x i32> undef, splat (i32 16)
+; AVX-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:2 SizeLat:4 for: %V16i32 = urem <16 x i32> undef, splat (i32 16)
+; AVX-NEXT: Cost Model: Found costs of 1 for: %I16 = urem i16 undef, 16
+; AVX-NEXT: Cost Model: Found costs of 1 for: %V8i16 = urem <8 x i16> undef, splat (i16 16)
+; AVX-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:1 SizeLat:2 for: %V16i16 = urem <16 x i16> undef, splat (i16 16)
+; AVX-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:2 SizeLat:4 for: %V32i16 = urem <32 x i16> undef, splat (i16 16)
+; AVX-NEXT: Cost Model: Found costs of 1 for: %I8 = urem i8 undef, 16
+; AVX-NEXT: Cost Model: Found costs of 1 for: %V16i8 = urem <16 x i8> undef, splat (i8 16)
+; AVX-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:1 SizeLat:2 for: %V32i8 = urem <32 x i8> undef, splat (i8 16)
+; AVX-NEXT: Cost Model: Found costs of RThru:2 CodeSize:2 Lat:2 SizeLat:4 for: %V64i8 = urem <64 x i8> undef, splat (i8 16)
+; AVX-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
-; AVX512BW-LABEL: 'urem_uniformconstpow2'
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = urem i64 undef, 16
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:120 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = urem <2 x i64> undef, splat (i64 16)
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:240 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = urem <4 x i64> undef, splat (i64 16)
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:480 CodeSize:4 Lat:4 SizeLat:4 for: %V8i64 = urem <8 x i64> undef, splat (i64 16)
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = urem i32 undef, 16
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = urem <4 x i32> undef, splat (i32 16)
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = urem <8 x i32> undef, splat (i32 16)
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:7 CodeSize:4 Lat:4 SizeLat:4 for: %V16i32 = urem <16 x i32> undef, splat (i32 16)
-; AVX512BW-NEXT: Cost Model: Found costs of 4 for: %I16 = urem i16 undef, 16
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = urem <8 x i16> undef, splat (i16 16)
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = urem <16 x i16> undef, splat (i16 16)
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V32i16 = urem <32 x i16> undef, splat (i16 16)
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:5 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = urem i8 undef, 16
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = urem <16 x i8> undef, splat (i8 16)
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = urem <32 x i8> undef, splat (i8 16)
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V64i8 = urem <64 x i8> undef, splat (i8 16)
-; AVX512BW-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
+; AVX512-LABEL: 'urem_uniformconstpow2'
+; AVX512-NEXT: Cost Model: Found costs of 1 for: %I64 = urem i64 undef, 16
+; AVX512-NEXT: Cost Model: Found costs of 1 for: %V2i64 = urem <2 x i64> undef, splat (i64 16)
+; AVX512-NEXT: Cost Model: Found costs of 1 for: %V4i64 = urem <4 x i64> undef, splat (i64 16)
+; AVX512-NEXT: Cost Model: Found costs of 1 for: %V8i64 = urem <8 x i64> undef, splat (i64 16)
+; AVX512-NEXT: Cost Model: Found costs of 1 for: %I32 = urem i32 undef, 16
+; AVX512-NEXT: Cost Model: Found costs of 1 for: %V4i32 = urem <4 x i32> undef, splat (i32 16)
+; AVX512-NEXT: Cost Model: Found costs of 1 for: %V8i32 = urem <8 x i32> undef, splat (i32 16)
+; AVX512-NEXT: Cost Model: Found costs of 1 for: %V16i32 = urem <16 x i32> undef, splat (i32 16)
+; AVX512-NEXT: Cost Model: Found costs of 1 for: %I16 = urem i16 undef, 16
+; AVX512-NEXT: Cost Model: Found costs of 1 for: %V8i16 = urem <8 x i16> undef, splat (i16 16)
+; AVX512-NEXT: Cost Model: Found costs of 1 for: %V16i16 = urem <16 x i16> undef, splat (i16 16)
+; AVX512-NEXT: Cost Model: Found costs of 1 for: %V32i16 = urem <32 x i16> undef, splat (i16 16)
+; AVX512-NEXT: Cost Model: Found costs of 1 for: %I8 = urem i8 undef, 16
+; AVX512-NEXT: Cost Model: Found costs of 1 for: %V16i8 = urem <16 x i8> undef, splat (i8 16)
+; AVX512-NEXT: Cost Model: Found costs of 1 for: %V32i8 = urem <32 x i8> undef, splat (i8 16)
+; AVX512-NEXT: Cost Model: Found costs of 1 for: %V64i8 = urem <64 x i8> undef, splat (i8 16)
+; AVX512-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef
;
%I64 = urem i64 undef, 16
%V2i64 = urem <2 x i64> undef, <i64 16, i64 16>
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/load-binop-store.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/load-binop-store.ll
index 0c71c8cab439e..8c82c6ec8e7cb 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/load-binop-store.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/load-binop-store.ll
@@ -324,116 +324,3 @@ entry:
store i16 %a1, ptr %inc2, align 2
ret void
}
-
-; Vector UDiv costs 7 (4 for the division, 3 to load constants)
-; Scalar UDiv costs 5, (4 for the div by 9, 1 for the div by 2
-define void @udiv_pow2(ptr %d, ptr %s) {
-; CHECK-LABEL: @udiv_pow2(
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[L0:%.*]] = load i16, ptr [[S:%.*]], align 2
-; CHECK-NEXT: [[S1:%.*]] = getelementptr i16, ptr [[S]], i64 1
-; CHECK-NEXT: [[L1:%.*]] = load i16, ptr [[S1]], align 2
-; CHECK-NEXT: [[A0:%.*]] = udiv i16 [[L0]], 2
-; CHECK-NEXT: [[A1:%.*]] = udiv i16 [[L1]], 9
-; CHECK-NEXT: store i16 [[A0]], ptr [[D:%.*]], align 2
-; CHECK-NEXT: [[D1:%.*]] = getelementptr i16, ptr [[D]], i64 1
-; CHECK-NEXT: store i16 [[A1]], ptr [[D1]], align 2
-; CHECK-NEXT: ret void
-;
-; DEFAULT-LABEL: @udiv_pow2(
-; DEFAULT-NEXT: entry:
-; DEFAULT-NEXT: [[L0:%.*]] = load i16, ptr [[S:%.*]], align 2
-; DEFAULT-NEXT: [[S1:%.*]] = getelementptr i16, ptr [[S]], i64 1
-; DEFAULT-NEXT: [[L1:%.*]] = load i16, ptr [[S1]], align 2
-; DEFAULT-NEXT: [[A0:%.*]] = udiv i16 [[L0]], 2
-; DEFAULT-NEXT: [[A1:%.*]] = udiv i16 [[L1]], 9
-; DEFAULT-NEXT: store i16 [[A0]], ptr [[D:%.*]], align 2
-; DEFAULT-NEXT: [[D1:%.*]] = getelementptr i16, ptr [[D]], i64 1
-; DEFAULT-NEXT: store i16 [[A1]], ptr [[D1]], align 2
-; DEFAULT-NEXT: ret void
-;
-entry:
- %l0 = load i16, ptr %s
- %s1 = getelementptr i16, ptr %s, i64 1
- %l1 = load i16, ptr %s1
-
- %a0 = udiv i16 %l0, 2
- %a1 = udiv i16 %l1, 9
-
- store i16 %a0, ptr %d
- %d1 = getelementptr i16, ptr %d, i64 1
- store i16 %a1, ptr %d1
- ret void
-}
-
-; Vector UDiv costs 1 since shift by single constant
-; Scalar UDiv costs 2 since can be implemented as 2 shifts
-define void @udiv_pow2_all_same(ptr %d, ptr %s) {
-; CHECK-LABEL: @udiv_pow2_all_same(
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr [[S:%.*]], align 2
-; CHECK-NEXT: [[TMP2:%.*]] = udiv <2 x i16> [[TMP1]], splat (i16 2)
-; CHECK-NEXT: store <2 x i16> [[TMP2]], ptr [[D:%.*]], align 2
-; CHECK-NEXT: ret void
-;
-; DEFAULT-LABEL: @udiv_pow2_all_same(
-; DEFAULT-NEXT: entry:
-; DEFAULT-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr [[S:%.*]], align 2
-; DEFAULT-NEXT: [[TMP2:%.*]] = udiv <2 x i16> [[TMP1]], splat (i16 2)
-; DEFAULT-NEXT: store <2 x i16> [[TMP2]], ptr [[D:%.*]], align 2
-; DEFAULT-NEXT: ret void
-;
-entry:
- %l0 = load i16, ptr %s
- %s1 = getelementptr i16, ptr %s, i64 1
- %l1 = load i16, ptr %s1
-
- %a0 = udiv i16 %l0, 2
- %a1 = udiv i16 %l1, 2
-
- store i16 %a0, ptr %d
- %d1 = getelementptr i16, ptr %d, i64 1
- store i16 %a1, ptr %d1
- ret void
-}
-
-; Vector UDiv costs 4 (1 for the shift, 3 to load constants)
-; Scalar UDiv cost 2 since can be implemented as 2 shifts
-define void @udiv_all_pow2(ptr %d, ptr %s) {
-; CHECK-LABEL: @udiv_all_pow2(
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[L0:%.*]] = load i16, ptr [[S:%.*]], align 2
-; CHECK-NEXT: [[S1:%.*]] = getelementptr i16, ptr [[S]], i64 1
-; CHECK-NEXT: [[L1:%.*]] = load i16, ptr [[S1]], align 2
-; CHECK-NEXT: [[A0:%.*]] = udiv i16 [[L0]], 2
-; CHECK-NEXT: [[A1:%.*]] = udiv i16 [[L1]], 4
-; CHECK-NEXT: store i16 [[A0]], ptr [[D:%.*]], align 2
-; CHECK-NEXT: [[D1:%.*]] = getelementptr i16, ptr [[D]], i64 1
-; CHECK-NEXT: store i16 [[A1]], ptr [[D1]], align 2
-; CHECK-NEXT: ret void
-;
-; DEFAULT-LABEL: @udiv_all_pow2(
-; DEFAULT-NEXT: entry:
-; DEFAULT-NEXT: [[L0:%.*]] = load i16, ptr [[S:%.*]], align 2
-; DEFAULT-NEXT: [[S1:%.*]] = getelementptr i16, ptr [[S]], i64 1
-; DEFAULT-NEXT: [[L1:%.*]] = load i16, ptr [[S1]], align 2
-; DEFAULT-NEXT: [[A0:%.*]] = udiv i16 [[L0]], 2
-; DEFAULT-NEXT: [[A1:%.*]] = udiv i16 [[L1]], 4
-; DEFAULT-NEXT: store i16 [[A0]], ptr [[D:%.*]], align 2
-; DEFAULT-NEXT: [[D1:%.*]] = getelementptr i16, ptr [[D]], i64 1
-; DEFAULT-NEXT: store i16 [[A1]], ptr [[D1]], align 2
-; DEFAULT-NEXT: ret void
-;
-entry:
- %l0 = load i16, ptr %s
- %s1 = getelementptr i16, ptr %s, i64 1
- %l1 = load i16, ptr %s1
-
- %a0 = udiv i16 %l0, 2
- %a1 = udiv i16 %l1, 4
-
- store i16 %a0, ptr %d
- %d1 = getelementptr i16, ptr %d, i64 1
- store i16 %a1, ptr %d1
- ret void
-}
>From fa061bffda0416e6d9963e7de1a8af977deb9f2d Mon Sep 17 00:00:00 2001
From: bababuck <buchner.ryan at gmail.com>
Date: Wed, 11 Feb 2026 10:49:06 -0800
Subject: [PATCH 13/19] [TTI] Refactor, creating getArithmeticInstrCostImpl()
Now, getArithmeticInstrCost() is a thin wrapper around getArithmeticInstrCostImpl(),
along with the generic peephole optimization logic (i.e. UDiv by power of 2 -> LShr).
Backends should override getArithmeticInstrCostImpl() rather than getArithmeticInstrCost()
if they want to gain access to the generic optimization logic.
---
llvm/include/llvm/CodeGen/BasicTTIImpl.h | 40 ++++++++-----------
.../AArch64/AArch64TargetTransformInfo.cpp | 27 +++++--------
.../AArch64/AArch64TargetTransformInfo.h | 2 +-
.../AMDGPU/AMDGPUTargetTransformInfo.cpp | 4 +-
.../lib/Target/ARM/ARMTargetTransformInfo.cpp | 2 +-
llvm/lib/Target/BPF/BPFTargetTransformInfo.h | 4 +-
.../Hexagon/HexagonTargetTransformInfo.cpp | 8 ++--
.../Target/Lanai/LanaiTargetTransformInfo.h | 8 ++--
.../Target/NVPTX/NVPTXTargetTransformInfo.cpp | 8 ++--
.../Target/PowerPC/PPCTargetTransformInfo.cpp | 8 ++--
.../Target/RISCV/RISCVTargetTransformInfo.cpp | 27 +++++--------
.../Target/RISCV/RISCVTargetTransformInfo.h | 2 +-
.../SystemZ/SystemZTargetTransformInfo.cpp | 8 ++--
.../WebAssemblyTargetTransformInfo.cpp | 2 +-
.../lib/Target/X86/X86TargetTransformInfo.cpp | 22 ++--------
llvm/lib/Target/X86/X86TargetTransformInfo.h | 2 +-
16 files changed, 71 insertions(+), 103 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/BasicTTIImpl.h b/llvm/include/llvm/CodeGen/BasicTTIImpl.h
index c807b06a292b4..545c2bedd4282 100644
--- a/llvm/include/llvm/CodeGen/BasicTTIImpl.h
+++ b/llvm/include/llvm/CodeGen/BasicTTIImpl.h
@@ -1048,36 +1048,30 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
unsigned getMaxInterleaveFactor(ElementCount VF) const override { return 1; }
- bool getConvertedArithmeticInstructionCost(unsigned ISDOpcode, Type *Ty,
- TTI::TargetCostKind CostKind,
- TTI::OperandValueInfo Opd1Info,
- TTI::OperandValueInfo Opd2Info,
- ArrayRef<const Value *> Args,
- const Instruction *CxtI,
- InstructionCost &Cost) const {
+ InstructionCost getArithmeticInstrCost(
+ unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
+ TTI::OperandValueInfo Opd1Info = {TTI::OK_AnyValue, TTI::OP_None},
+ TTI::OperandValueInfo Opd2Info = {TTI::OK_AnyValue, TTI::OP_None},
+ ArrayRef<const Value *> Args = {},
+ const Instruction *CxtI = nullptr) const override {
+
// Vector unsigned division/remainder will be simplified to shifts/masks.
- if ((ISDOpcode == ISD::UDIV || ISDOpcode == ISD::UREM) &&
- Opd2Info.isConstant() && Opd2Info.isPowerOf2()) {
- if (ISDOpcode == ISD::UDIV)
- Cost = getArithmeticInstrCost(Instruction::LShr, Ty, CostKind,
- Opd1Info.getNoProps(),
- Opd2Info.getNoProps());
- // UREM
- else
- Cost = getArithmeticInstrCost(Instruction::And, Ty, CostKind,
- Opd1Info.getNoProps(),
- Opd2Info.getNoProps());
- return true;
- }
- return false;
+ if ((Opcode == Instruction::UDiv || Opcode == Instruction::URem) &&
+ Opd2Info.isConstant() && Opd2Info.isPowerOf2())
+ return getArithmeticInstrCost(
+ Opcode == Instruction::UDiv ? Instruction::LShr : Instruction::And,
+ Ty, CostKind, Opd1Info.getNoProps(), Opd2Info.getNoProps());
+
+ return getArithmeticInstrCostImpl(Opcode, Ty, CostKind, Opd1Info, Opd2Info,
+ Args, CxtI);
}
- InstructionCost getArithmeticInstrCost(
+ virtual InstructionCost getArithmeticInstrCostImpl(
unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
TTI::OperandValueInfo Opd1Info = {TTI::OK_AnyValue, TTI::OP_None},
TTI::OperandValueInfo Opd2Info = {TTI::OK_AnyValue, TTI::OP_None},
ArrayRef<const Value *> Args = {},
- const Instruction *CxtI = nullptr) const override {
+ const Instruction *CxtI = nullptr) const {
// Check if any of the operands are vector operands.
const TargetLoweringBase *TLI = getTLI();
int ISD = TLI->InstructionOpcodeToISD(Opcode);
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
index fa473342fd6a7..98aaf7dc8eab6 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -4242,7 +4242,7 @@ std::optional<InstructionCost> AArch64TTIImpl::getFP16BF16PromoteCost(
return Cost;
}
-InstructionCost AArch64TTIImpl::getArithmeticInstrCost(
+InstructionCost AArch64TTIImpl::getArithmeticInstrCostImpl(
unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
TTI::OperandValueInfo Op1Info, TTI::OperandValueInfo Op2Info,
ArrayRef<const Value *> Args, const Instruction *CxtI) const {
@@ -4257,8 +4257,8 @@ InstructionCost AArch64TTIImpl::getArithmeticInstrCost(
// TODO: Handle more cost kinds.
if (CostKind != TTI::TCK_RecipThroughput)
- return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info,
- Op2Info, Args, CxtI);
+ return BaseT::getArithmeticInstrCostImpl(Opcode, Ty, CostKind, Op1Info,
+ Op2Info, Args, CxtI);
// Legalize the type.
std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(Ty);
@@ -4290,15 +4290,10 @@ InstructionCost AArch64TTIImpl::getArithmeticInstrCost(
return LT.first;
}
- InstructionCost ConvertedCost;
- if (getConvertedArithmeticInstructionCost(ISD, Ty, CostKind, Op1Info, Op2Info,
- Args, CxtI, ConvertedCost))
- return ConvertedCost;
-
switch (ISD) {
default:
- return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info,
- Op2Info);
+ return BaseT::getArithmeticInstrCostImpl(Opcode, Ty, CostKind, Op1Info,
+ Op2Info);
case ISD::SREM:
case ISD::SDIV:
/*
@@ -4449,7 +4444,7 @@ InstructionCost AArch64TTIImpl::getArithmeticInstrCost(
if (!VT.isVector() && VT.getSizeInBits() > 64)
return getCallInstrCost(/*Function*/ nullptr, Ty, {Ty, Ty}, CostKind);
- InstructionCost Cost = BaseT::getArithmeticInstrCost(
+ InstructionCost Cost = BaseT::getArithmeticInstrCostImpl(
Opcode, Ty, CostKind, Op1Info, Op2Info);
if (Ty->isVectorTy() && (ISD == ISD::SDIV || ISD == ISD::UDIV)) {
if (TLI->isOperationLegalOrCustom(ISD, LT.second) && ST->hasSVE()) {
@@ -4484,7 +4479,7 @@ InstructionCost AArch64TTIImpl::getArithmeticInstrCost(
if ((Op1Info.isConstant() && Op1Info.isUniform()) ||
(Op2Info.isConstant() && Op2Info.isUniform())) {
if (auto *VTy = dyn_cast<FixedVectorType>(Ty)) {
- InstructionCost DivCost = BaseT::getArithmeticInstrCost(
+ InstructionCost DivCost = BaseT::getArithmeticInstrCostImpl(
Opcode, Ty->getScalarType(), CostKind, Op1Info, Op2Info);
return (4 + DivCost) * VTy->getNumElements();
}
@@ -4561,15 +4556,15 @@ InstructionCost AArch64TTIImpl::getArithmeticInstrCost(
if (!Ty->getScalarType()->isFP128Ty())
return 2 * LT.first;
- return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info,
- Op2Info);
+ return BaseT::getArithmeticInstrCostImpl(Opcode, Ty, CostKind, Op1Info,
+ Op2Info);
case ISD::FREM:
// Pass nullptr as fmod/fmodf calls are emitted by the backend even when
// those functions are not declared in the module.
if (!Ty->isVectorTy())
return getCallInstrCost(/*Function*/ nullptr, Ty, {Ty, Ty}, CostKind);
- return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info,
- Op2Info);
+ return BaseT::getArithmeticInstrCostImpl(Opcode, Ty, CostKind, Op1Info,
+ Op2Info);
}
}
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
index 0cdcd6ef4fcad..561eaeb09efbd 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
@@ -255,7 +255,7 @@ class AArch64TTIImpl final : public BasicTTIImplBase<AArch64TTIImpl> {
InstructionCost getSpliceCost(VectorType *Tp, int Index,
TTI::TargetCostKind CostKind) const;
- InstructionCost getArithmeticInstrCost(
+ InstructionCost getArithmeticInstrCostImpl(
unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None},
TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None},
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
index 3e02587f61336..b698b786aac50 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
@@ -680,8 +680,8 @@ InstructionCost GCNTTIImpl::getArithmeticInstrCost(
break;
}
- return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info,
- Args, CxtI);
+ return BaseT::getArithmeticInstrCostImpl(Opcode, Ty, CostKind, Op1Info,
+ Op2Info, Args, CxtI);
}
// Return true if there's a potential benefit from using v2f16/v2i16
diff --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
index a7766d91af3f2..e2e6b61383db2 100644
--- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
@@ -1513,7 +1513,7 @@ InstructionCost ARMTTIImpl::getArithmeticInstrCost(
if (const auto *Entry = CostTableLookup(CostTbl, ISDOpcode, LT.second))
return LT.first * Entry->Cost;
- InstructionCost Cost = BaseT::getArithmeticInstrCost(
+ InstructionCost Cost = BaseT::getArithmeticInstrCostImpl(
Opcode, Ty, CostKind, Op1Info, Op2Info);
// This is somewhat of a hack. The problem that we are facing is that SROA
diff --git a/llvm/lib/Target/BPF/BPFTargetTransformInfo.h b/llvm/lib/Target/BPF/BPFTargetTransformInfo.h
index d7b2ceff105c9..f28fa922edffe 100644
--- a/llvm/lib/Target/BPF/BPFTargetTransformInfo.h
+++ b/llvm/lib/Target/BPF/BPFTargetTransformInfo.h
@@ -68,8 +68,8 @@ class BPFTTIImpl final : public BasicTTIImplBase<BPFTTIImpl> {
if (ISD == ISD::ADD && CostKind == TTI::TCK_RecipThroughput)
return SCEVCheapExpansionBudget.getValue() + 1;
- return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info,
- Op2Info);
+ return BaseT::getArithmeticInstrCostImpl(Opcode, Ty, CostKind, Op1Info,
+ Op2Info);
}
TTI::MemCmpExpansionOptions
diff --git a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
index 25ede7d262544..e9f86e5bbac93 100644
--- a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
@@ -265,8 +265,8 @@ InstructionCost HexagonTTIImpl::getArithmeticInstrCost(
ArrayRef<const Value *> Args, const Instruction *CxtI) const {
// TODO: Handle more cost kinds.
if (CostKind != TTI::TCK_RecipThroughput)
- return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info,
- Op2Info, Args, CxtI);
+ return BaseT::getArithmeticInstrCostImpl(Opcode, Ty, CostKind, Op1Info,
+ Op2Info, Args, CxtI);
if (Ty->isVectorTy()) {
if (!isHVXVectorType(Ty) && Ty->isFPOrFPVectorTy())
@@ -275,8 +275,8 @@ InstructionCost HexagonTTIImpl::getArithmeticInstrCost(
if (LT.second.isFloatingPoint())
return LT.first + FloatFactor * getTypeNumElements(Ty);
}
- return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info,
- Args, CxtI);
+ return BaseT::getArithmeticInstrCostImpl(Opcode, Ty, CostKind, Op1Info,
+ Op2Info, Args, CxtI);
}
InstructionCost HexagonTTIImpl::getCastInstrCost(unsigned Opcode, Type *DstTy,
diff --git a/llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h b/llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h
index 0342af65c1ef7..0f87e72750a36 100644
--- a/llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h
+++ b/llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h
@@ -101,8 +101,8 @@ class LanaiTTIImpl final : public BasicTTIImplBase<LanaiTTIImpl> {
switch (ISD) {
default:
- return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info,
- Op2Info);
+ return BaseT::getArithmeticInstrCostImpl(Opcode, Ty, CostKind, Op1Info,
+ Op2Info);
case ISD::MUL:
case ISD::SDIV:
case ISD::UDIV:
@@ -112,8 +112,8 @@ class LanaiTTIImpl final : public BasicTTIImplBase<LanaiTTIImpl> {
// instruction cost was arbitrarily chosen to reduce the desirability
// of emitting arithmetic instructions that are emulated in software.
// TODO: Investigate the performance impact given specialized lowerings.
- return 64 * BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info,
- Op2Info);
+ return 64 * BaseT::getArithmeticInstrCostImpl(Opcode, Ty, CostKind,
+ Op1Info, Op2Info);
}
}
};
diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp b/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
index c1fe9300785a3..549ba2aa10032 100644
--- a/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
@@ -508,8 +508,8 @@ InstructionCost NVPTXTTIImpl::getArithmeticInstrCost(
switch (ISD) {
default:
- return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info,
- Op2Info);
+ return BaseT::getArithmeticInstrCostImpl(Opcode, Ty, CostKind, Op1Info,
+ Op2Info);
case ISD::ADD:
case ISD::MUL:
case ISD::XOR:
@@ -521,8 +521,8 @@ InstructionCost NVPTXTTIImpl::getArithmeticInstrCost(
if (LT.second.SimpleTy == MVT::i64)
return 2 * LT.first;
// Delegate other cases to the basic TTI.
- return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info,
- Op2Info);
+ return BaseT::getArithmeticInstrCostImpl(Opcode, Ty, CostKind, Op1Info,
+ Op2Info);
}
}
diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
index 90d5128c75adc..9fc07e494c17c 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
@@ -606,12 +606,12 @@ InstructionCost PPCTTIImpl::getArithmeticInstrCost(
// TODO: Handle more cost kinds.
if (CostKind != TTI::TCK_RecipThroughput)
- return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info,
- Op2Info, Args, CxtI);
+ return BaseT::getArithmeticInstrCostImpl(Opcode, Ty, CostKind, Op1Info,
+ Op2Info, Args, CxtI);
// Fallback to the default implementation.
- InstructionCost Cost = BaseT::getArithmeticInstrCost(
- Opcode, Ty, CostKind, Op1Info, Op2Info);
+ InstructionCost Cost =
+ BaseT::getArithmeticInstrCostImpl(Opcode, Ty, CostKind, Op1Info, Op2Info);
return Cost * CostFactor;
}
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 1f68d708ec1cb..77a9ccf1d47f5 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2594,34 +2594,29 @@ RISCVTTIImpl::getIndexedVectorInstrCostFromEnd(unsigned Opcode, Type *Val,
nullptr);
}
-InstructionCost RISCVTTIImpl::getArithmeticInstrCost(
+InstructionCost RISCVTTIImpl::getArithmeticInstrCostImpl(
unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
TTI::OperandValueInfo Op1Info, TTI::OperandValueInfo Op2Info,
ArrayRef<const Value *> Args, const Instruction *CxtI) const {
// TODO: Handle more cost kinds.
if (CostKind != TTI::TCK_RecipThroughput)
- return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info,
- Args, CxtI);
+ return BaseT::getArithmeticInstrCostImpl(Opcode, Ty, CostKind, Op1Info,
+ Op2Info, Args, CxtI);
if (isa<FixedVectorType>(Ty) && !ST->useRVVForFixedLengthVectors())
- return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info,
- Args, CxtI);
+ return BaseT::getArithmeticInstrCostImpl(Opcode, Ty, CostKind, Op1Info,
+ Op2Info, Args, CxtI);
// Skip if scalar size of Ty is bigger than ELEN.
if (isa<VectorType>(Ty) && Ty->getScalarSizeInBits() > ST->getELen())
- return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info,
- Args, CxtI);
+ return BaseT::getArithmeticInstrCostImpl(Opcode, Ty, CostKind, Op1Info,
+ Op2Info, Args, CxtI);
// Legalize the type.
std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(Ty);
unsigned ISDOpcode = TLI->InstructionOpcodeToISD(Opcode);
- InstructionCost ConvertedCost;
- if (getConvertedArithmeticInstructionCost(ISDOpcode, Ty, CostKind, Op1Info,
- Op2Info, Args, CxtI, ConvertedCost))
- return ConvertedCost;
-
// TODO: Handle scalar type.
if (!LT.second.isVector()) {
static const CostTblEntry DivTbl[]{
@@ -2637,8 +2632,8 @@ InstructionCost RISCVTTIImpl::getArithmeticInstrCost(
if (const auto *Entry = CostTableLookup(DivTbl, ISDOpcode, LT.second))
return Entry->Cost * LT.first;
- return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info,
- Args, CxtI);
+ return BaseT::getArithmeticInstrCostImpl(Opcode, Ty, CostKind, Op1Info,
+ Op2Info, Args, CxtI);
}
// f16 with zvfhmin and bf16 will be promoted to f32.
@@ -2729,8 +2724,8 @@ InstructionCost RISCVTTIImpl::getArithmeticInstrCost(
// Assuming all other instructions have the same cost until a need arises to
// differentiate them.
return CastCost + ConstantMatCost +
- BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info,
- Args, CxtI);
+ BaseT::getArithmeticInstrCostImpl(Opcode, Ty, CostKind, Op1Info,
+ Op2Info, Args, CxtI);
}
InstructionCost InstrCost = getRISCVInstructionCost(Op, LT.second, CostKind);
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
index faa87b4fc48dd..8db7aaffdebdc 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
@@ -261,7 +261,7 @@ class RISCVTTIImpl final : public BasicTTIImplBase<RISCVTTIImpl> {
TTI::TargetCostKind CostKind,
unsigned Index) const override;
- InstructionCost getArithmeticInstrCost(
+ InstructionCost getArithmeticInstrCostImpl(
unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None},
TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None},
diff --git a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
index 4322773f4afd6..46f8b8f555fcf 100644
--- a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
@@ -546,8 +546,8 @@ InstructionCost SystemZTTIImpl::getArithmeticInstrCost(
// TODO: Handle more cost kinds.
if (CostKind != TTI::TCK_RecipThroughput)
- return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info,
- Op2Info, Args, CxtI);
+ return BaseT::getArithmeticInstrCostImpl(Opcode, Ty, CostKind, Op1Info,
+ Op2Info, Args, CxtI);
// TODO: return a good value for BB-VECTORIZER that includes the
// immediate loads, which we do not want to count for the loop
@@ -720,8 +720,8 @@ InstructionCost SystemZTTIImpl::getArithmeticInstrCost(
}
// Fallback to the default implementation.
- return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info,
- Args, CxtI);
+ return BaseT::getArithmeticInstrCostImpl(Opcode, Ty, CostKind, Op1Info,
+ Op2Info, Args, CxtI);
}
InstructionCost
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
index 33498805112c0..71afd94d3dd6d 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
@@ -79,7 +79,7 @@ InstructionCost WebAssemblyTTIImpl::getArithmeticInstrCost(
}
InstructionCost Cost =
- BasicTTIImplBase<WebAssemblyTTIImpl>::getArithmeticInstrCost(
+ BasicTTIImplBase<WebAssemblyTTIImpl>::getArithmeticInstrCostImpl(
Opcode, Ty, CostKind, Op1Info, Op2Info);
if (auto *VTy = dyn_cast<VectorType>(Ty)) {
diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
index 1401bbb1f64ef..60259e3bd472c 100644
--- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -250,7 +250,7 @@ unsigned X86TTIImpl::getMaxInterleaveFactor(ElementCount VF) const {
return 2;
}
-InstructionCost X86TTIImpl::getArithmeticInstrCost(
+InstructionCost X86TTIImpl::getArithmeticInstrCostImpl(
unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
TTI::OperandValueInfo Op1Info, TTI::OperandValueInfo Op2Info,
ArrayRef<const Value *> Args, const Instruction *CxtI) const {
@@ -276,11 +276,6 @@ InstructionCost X86TTIImpl::getArithmeticInstrCost(
int ISD = TLI->InstructionOpcodeToISD(Opcode);
assert(ISD && "Invalid opcode");
- InstructionCost ConvertedCost;
- if (getConvertedArithmeticInstructionCost(ISD, Ty, CostKind, Op1Info, Op2Info,
- Args, CxtI, ConvertedCost))
- return ConvertedCost;
-
if (ISD == ISD::MUL && Args.size() == 2 && LT.second.isVector() &&
(LT.second.getScalarType() == MVT::i32 ||
LT.second.getScalarType() == MVT::i64)) {
@@ -371,17 +366,6 @@ InstructionCost X86TTIImpl::getArithmeticInstrCost(
return Cost;
}
- // Vector unsigned division/remainder will be simplified to shifts/masks.
- if ((ISD == ISD::UDIV || ISD == ISD::UREM) && Op2Info.isConstant() &&
- Op2Info.isPowerOf2()) {
- if (ISD == ISD::UDIV)
- return getArithmeticInstrCost(Instruction::LShr, Ty, CostKind,
- Op1Info.getNoProps(), Op2Info.getNoProps());
- // UREM
- return getArithmeticInstrCost(Instruction::And, Ty, CostKind,
- Op1Info.getNoProps(), Op2Info.getNoProps());
- }
-
static const CostKindTblEntry GFNIUniformConstCostTable[] = {
{ ISD::SHL, MVT::v16i8, { 1, 6, 1, 2 } }, // gf2p8affineqb
{ ISD::SRL, MVT::v16i8, { 1, 6, 1, 2 } }, // gf2p8affineqb
@@ -1523,8 +1507,8 @@ InstructionCost X86TTIImpl::getArithmeticInstrCost(
}
// Fallback to the default implementation.
- return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info,
- Args, CxtI);
+ return BaseT::getArithmeticInstrCostImpl(Opcode, Ty, CostKind, Op1Info,
+ Op2Info, Args, CxtI);
}
InstructionCost
diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.h b/llvm/lib/Target/X86/X86TargetTransformInfo.h
index b3dde1555d0a0..9bdd49638834b 100644
--- a/llvm/lib/Target/X86/X86TargetTransformInfo.h
+++ b/llvm/lib/Target/X86/X86TargetTransformInfo.h
@@ -138,7 +138,7 @@ class X86TTIImpl final : public BasicTTIImplBase<X86TTIImpl> {
getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const override;
unsigned getLoadStoreVecRegBitWidth(unsigned AS) const override;
unsigned getMaxInterleaveFactor(ElementCount VF) const override;
- InstructionCost getArithmeticInstrCost(
+ InstructionCost getArithmeticInstrCostImpl(
unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None},
TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None},
>From b2e9aa8b5fd97ee1e4a425f0ef2e9c36f07abda7 Mon Sep 17 00:00:00 2001
From: bababuck <buchner.ryan at gmail.com>
Date: Tue, 10 Feb 2026 15:01:05 -0800
Subject: [PATCH 14/19] [AArch64] Update AArch64 cost tests
---
llvm/test/Analysis/CostModel/AArch64/div.ll | 92 +++++++++----------
llvm/test/Analysis/CostModel/AArch64/rem.ll | 92 +++++++++----------
.../Analysis/CostModel/AArch64/sve-div.ll | 72 +++++++--------
.../Analysis/CostModel/AArch64/sve-rem.ll | 74 +++++++--------
4 files changed, 165 insertions(+), 165 deletions(-)
diff --git a/llvm/test/Analysis/CostModel/AArch64/div.ll b/llvm/test/Analysis/CostModel/AArch64/div.ll
index 3a2358dba51b2..565815dd827d7 100644
--- a/llvm/test/Analysis/CostModel/AArch64/div.ll
+++ b/llvm/test/Analysis/CostModel/AArch64/div.ll
@@ -578,29 +578,29 @@ define void @sdiv_constpow2() {
define void @udiv_constpow2() {
; CHECK-LABEL: 'udiv_constpow2'
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %I128 = udiv i128 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = udiv i64 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = udiv <2 x i64> undef, <i64 8, i64 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = udiv <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V8i64 = udiv <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = udiv i32 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i32 = udiv <2 x i32> undef, <i32 2, i32 4>
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = udiv <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = udiv <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V16i32 = udiv <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I16 = udiv i16 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i16 = udiv <2 x i16> undef, <i16 2, i16 4>
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i16 = udiv <4 x i16> undef, <i16 2, i16 4, i16 8, i16 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = udiv <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = udiv <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V32i16 = udiv <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = udiv i8 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i8 = udiv <2 x i8> undef, <i8 2, i8 4>
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i8 = udiv <4 x i8> undef, <i8 2, i8 4, i8 8, i8 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i8 = udiv <8 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = udiv <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = udiv <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V64i8 = udiv <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %I128 = udiv i128 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %I64 = udiv i64 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i64 = udiv <2 x i64> undef, <i64 8, i64 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V4i64 = udiv <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V8i64 = udiv <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %I32 = udiv i32 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i32 = udiv <2 x i32> undef, <i32 2, i32 4>
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V4i32 = udiv <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V8i32 = udiv <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V16i32 = udiv <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %I16 = udiv i16 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i16 = udiv <2 x i16> undef, <i16 2, i16 4>
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V4i16 = udiv <4 x i16> undef, <i16 2, i16 4, i16 8, i16 16>
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V8i16 = udiv <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V16i16 = udiv <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V32i16 = udiv <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %I8 = udiv i8 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i8 = udiv <2 x i8> undef, <i8 2, i8 4>
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V4i8 = udiv <4 x i8> undef, <i8 2, i8 4, i8 8, i8 16>
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V8i8 = udiv <8 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V16i8 = udiv <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V32i8 = udiv <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V64i8 = udiv <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
%I128 = udiv i128 undef, 16
@@ -694,29 +694,29 @@ define void @sdiv_uniformconstpow2() {
define void @udiv_uniformconstpow2() {
; CHECK-LABEL: 'udiv_uniformconstpow2'
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %I128 = udiv i128 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = udiv i64 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = udiv <2 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = udiv <4 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V8i64 = udiv <8 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = udiv i32 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i32 = udiv <2 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = udiv <4 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = udiv <8 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V16i32 = udiv <16 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I16 = udiv i16 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i16 = udiv <2 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i16 = udiv <4 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = udiv <8 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = udiv <16 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V32i16 = udiv <32 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = udiv i8 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i8 = udiv <2 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i8 = udiv <4 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i8 = udiv <8 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = udiv <16 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = udiv <32 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V64i8 = udiv <64 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %I128 = udiv i128 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %I64 = udiv i64 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i64 = udiv <2 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V4i64 = udiv <4 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V8i64 = udiv <8 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %I32 = udiv i32 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i32 = udiv <2 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V4i32 = udiv <4 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V8i32 = udiv <8 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V16i32 = udiv <16 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %I16 = udiv i16 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i16 = udiv <2 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V4i16 = udiv <4 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V8i16 = udiv <8 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V16i16 = udiv <16 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V32i16 = udiv <32 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %I8 = udiv i8 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i8 = udiv <2 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V4i8 = udiv <4 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V8i8 = udiv <8 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V16i8 = udiv <16 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V32i8 = udiv <32 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V64i8 = udiv <64 x i8> undef, splat (i8 16)
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
%I128 = udiv i128 undef, 16
diff --git a/llvm/test/Analysis/CostModel/AArch64/rem.ll b/llvm/test/Analysis/CostModel/AArch64/rem.ll
index 2fa62f1705911..4d34819dde516 100644
--- a/llvm/test/Analysis/CostModel/AArch64/rem.ll
+++ b/llvm/test/Analysis/CostModel/AArch64/rem.ll
@@ -578,29 +578,29 @@ define void @srem_constpow2() {
define void @urem_constpow2() {
; CHECK-LABEL: 'urem_constpow2'
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %I128 = urem i128 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = urem i64 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = urem <2 x i64> undef, <i64 8, i64 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = urem <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V8i64 = urem <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = urem i32 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i32 = urem <2 x i32> undef, <i32 2, i32 4>
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = urem <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = urem <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V16i32 = urem <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I16 = urem i16 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i16 = urem <2 x i16> undef, <i16 2, i16 4>
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i16 = urem <4 x i16> undef, <i16 2, i16 4, i16 8, i16 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = urem <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = urem <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V32i16 = urem <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = urem i8 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i8 = urem <2 x i8> undef, <i8 2, i8 4>
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i8 = urem <4 x i8> undef, <i8 2, i8 4, i8 8, i8 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i8 = urem <8 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = urem <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = urem <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V64i8 = urem <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %I128 = urem i128 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %I64 = urem i64 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i64 = urem <2 x i64> undef, <i64 8, i64 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V4i64 = urem <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V8i64 = urem <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %I32 = urem i32 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i32 = urem <2 x i32> undef, <i32 2, i32 4>
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V4i32 = urem <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V8i32 = urem <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V16i32 = urem <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %I16 = urem i16 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i16 = urem <2 x i16> undef, <i16 2, i16 4>
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V4i16 = urem <4 x i16> undef, <i16 2, i16 4, i16 8, i16 16>
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V8i16 = urem <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V16i16 = urem <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V32i16 = urem <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %I8 = urem i8 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i8 = urem <2 x i8> undef, <i8 2, i8 4>
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V4i8 = urem <4 x i8> undef, <i8 2, i8 4, i8 8, i8 16>
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V8i8 = urem <8 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V16i8 = urem <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V32i8 = urem <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V64i8 = urem <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
%I128 = urem i128 undef, 16
@@ -694,29 +694,29 @@ define void @srem_uniformconstpow2() {
define void @urem_uniformconstpow2() {
; CHECK-LABEL: 'urem_uniformconstpow2'
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %I128 = urem i128 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = urem i64 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = urem <2 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = urem <4 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V8i64 = urem <8 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = urem i32 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i32 = urem <2 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = urem <4 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = urem <8 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V16i32 = urem <16 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I16 = urem i16 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i16 = urem <2 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i16 = urem <4 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = urem <8 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = urem <16 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V32i16 = urem <32 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = urem i8 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i8 = urem <2 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i8 = urem <4 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i8 = urem <8 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = urem <16 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = urem <32 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V64i8 = urem <64 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %I128 = urem i128 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %I64 = urem i64 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i64 = urem <2 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V4i64 = urem <4 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V8i64 = urem <8 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %I32 = urem i32 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i32 = urem <2 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V4i32 = urem <4 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V8i32 = urem <8 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V16i32 = urem <16 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %I16 = urem i16 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i16 = urem <2 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V4i16 = urem <4 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V8i16 = urem <8 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V16i16 = urem <16 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V32i16 = urem <32 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %I8 = urem i8 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i8 = urem <2 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V4i8 = urem <4 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V8i8 = urem <8 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V16i8 = urem <16 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V32i8 = urem <32 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V64i8 = urem <64 x i8> undef, splat (i8 16)
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
%I128 = urem i128 undef, 16
diff --git a/llvm/test/Analysis/CostModel/AArch64/sve-div.ll b/llvm/test/Analysis/CostModel/AArch64/sve-div.ll
index 84a9ca0fab6d8..c12ce203d41ec 100644
--- a/llvm/test/Analysis/CostModel/AArch64/sve-div.ll
+++ b/llvm/test/Analysis/CostModel/AArch64/sve-div.ll
@@ -408,42 +408,42 @@ define void @sdiv_uniformconstpow2() {
define void @udiv_uniformconstpow2() {
; CHECK-LABEL: 'udiv_uniformconstpow2'
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = udiv <2 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = udiv <4 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V8i64 = udiv <8 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i32 = udiv <2 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = udiv <4 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = udiv <8 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V16i32 = udiv <16 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i16 = udiv <2 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i16 = udiv <4 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = udiv <8 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = udiv <16 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V32i16 = udiv <32 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i8 = udiv <2 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i8 = udiv <4 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i8 = udiv <8 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = udiv <16 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = udiv <32 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V64i8 = udiv <64 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV2i64 = udiv <vscale x 2 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %NV4i64 = udiv <vscale x 4 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV8i64 = udiv <vscale x 8 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV2i32 = udiv <vscale x 2 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV4i32 = udiv <vscale x 4 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %NV8i32 = udiv <vscale x 8 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV16i32 = udiv <vscale x 16 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV2i16 = udiv <vscale x 2 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV4i16 = udiv <vscale x 4 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV8i16 = udiv <vscale x 8 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %NV16i16 = udiv <vscale x 16 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV32i16 = udiv <vscale x 32 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV2i8 = udiv <vscale x 2 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV4i8 = udiv <vscale x 4 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV8i8 = udiv <vscale x 8 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV16i8 = udiv <vscale x 16 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %NV32i8 = udiv <vscale x 32 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV64i8 = udiv <vscale x 64 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i64 = udiv <2 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V4i64 = udiv <4 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V8i64 = udiv <8 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i32 = udiv <2 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V4i32 = udiv <4 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V8i32 = udiv <8 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V16i32 = udiv <16 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i16 = udiv <2 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V4i16 = udiv <4 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V8i16 = udiv <8 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V16i16 = udiv <16 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V32i16 = udiv <32 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i8 = udiv <2 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V4i8 = udiv <4 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V8i8 = udiv <8 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V16i8 = udiv <16 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V32i8 = udiv <32 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V64i8 = udiv <64 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %NV2i64 = udiv <vscale x 2 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %NV4i64 = udiv <vscale x 4 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %NV8i64 = udiv <vscale x 8 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %NV2i32 = udiv <vscale x 2 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %NV4i32 = udiv <vscale x 4 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %NV8i32 = udiv <vscale x 8 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %NV16i32 = udiv <vscale x 16 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %NV2i16 = udiv <vscale x 2 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %NV4i16 = udiv <vscale x 4 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %NV8i16 = udiv <vscale x 8 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %NV16i16 = udiv <vscale x 16 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %NV32i16 = udiv <vscale x 32 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %NV2i8 = udiv <vscale x 2 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %NV4i8 = udiv <vscale x 4 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %NV8i8 = udiv <vscale x 8 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %NV16i8 = udiv <vscale x 16 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %NV32i8 = udiv <vscale x 32 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %NV64i8 = udiv <vscale x 64 x i8> undef, splat (i8 16)
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
%V2i64 = udiv <2 x i64> undef, splat (i64 16)
diff --git a/llvm/test/Analysis/CostModel/AArch64/sve-rem.ll b/llvm/test/Analysis/CostModel/AArch64/sve-rem.ll
index eac8b66bcd216..4353a495be4ba 100644
--- a/llvm/test/Analysis/CostModel/AArch64/sve-rem.ll
+++ b/llvm/test/Analysis/CostModel/AArch64/sve-rem.ll
@@ -410,43 +410,43 @@ define void @srem_uniformconstpow2() {
define void @urem_uniformconstpow2() {
; CHECK-LABEL: 'urem_uniformconstpow2'
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = urem <2 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = urem <4 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V8i64 = urem <8 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i32 = urem <2 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = urem <4 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = urem <8 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V16i32 = urem <16 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i16 = urem <2 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i16 = urem <4 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = urem <8 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = urem <16 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V32i16 = urem <32 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i8 = urem <2 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i8 = urem <4 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i8 = urem <8 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = urem <16 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = urem <32 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %V64i8 = urem <64 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:Invalid CodeSize:4 Lat:4 SizeLat:4 for: %NV2i128 = urem <vscale x 2 x i128> undef, splat (i128 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV2i64 = urem <vscale x 2 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %NV4i64 = urem <vscale x 4 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV8i64 = urem <vscale x 8 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV2i32 = urem <vscale x 2 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV4i32 = urem <vscale x 4 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %NV8i32 = urem <vscale x 8 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV16i32 = urem <vscale x 16 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV2i16 = urem <vscale x 2 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV4i16 = urem <vscale x 4 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV8i16 = urem <vscale x 8 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %NV16i16 = urem <vscale x 16 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV32i16 = urem <vscale x 32 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV2i8 = urem <vscale x 2 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV4i8 = urem <vscale x 4 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV8i8 = urem <vscale x 8 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV16i8 = urem <vscale x 16 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %NV32i8 = urem <vscale x 32 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV64i8 = urem <vscale x 64 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i64 = urem <2 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V4i64 = urem <4 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V8i64 = urem <8 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i32 = urem <2 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V4i32 = urem <4 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V8i32 = urem <8 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V16i32 = urem <16 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i16 = urem <2 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V4i16 = urem <4 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V8i16 = urem <8 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V16i16 = urem <16 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V32i16 = urem <32 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i8 = urem <2 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V4i8 = urem <4 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V8i8 = urem <8 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %V16i8 = urem <16 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V32i8 = urem <32 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V64i8 = urem <64 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:Invalid CodeSize:1 Lat:1 SizeLat:1 for: %NV2i128 = urem <vscale x 2 x i128> undef, splat (i128 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %NV2i64 = urem <vscale x 2 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %NV4i64 = urem <vscale x 4 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %NV8i64 = urem <vscale x 8 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %NV2i32 = urem <vscale x 2 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %NV4i32 = urem <vscale x 4 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %NV8i32 = urem <vscale x 8 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %NV16i32 = urem <vscale x 16 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %NV2i16 = urem <vscale x 2 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %NV4i16 = urem <vscale x 4 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %NV8i16 = urem <vscale x 8 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %NV16i16 = urem <vscale x 16 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %NV32i16 = urem <vscale x 32 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %NV2i8 = urem <vscale x 2 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %NV4i8 = urem <vscale x 4 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %NV8i8 = urem <vscale x 8 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of 1 for: %NV16i8 = urem <vscale x 16 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %NV32i8 = urem <vscale x 32 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %NV64i8 = urem <vscale x 64 x i8> undef, splat (i8 16)
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
%V2i64 = urem <2 x i64> undef, splat (i64 16)
>From 21c8c943223044bcaaad2fa8f9358bec8f08ed75 Mon Sep 17 00:00:00 2001
From: bababuck <buchner.ryan at gmail.com>
Date: Tue, 14 Apr 2026 08:38:04 -0700
Subject: [PATCH 15/19] Revert "[TTI] Refactor, creating
getArithmeticInstrCostImpl()"
This reverts commit fa061bffda0416e6d9963e7de1a8af977deb9f2d.
---
llvm/include/llvm/CodeGen/BasicTTIImpl.h | 40 +++++++++++--------
.../AArch64/AArch64TargetTransformInfo.cpp | 27 ++++++++-----
.../AArch64/AArch64TargetTransformInfo.h | 2 +-
.../AMDGPU/AMDGPUTargetTransformInfo.cpp | 4 +-
.../lib/Target/ARM/ARMTargetTransformInfo.cpp | 2 +-
llvm/lib/Target/BPF/BPFTargetTransformInfo.h | 4 +-
.../Hexagon/HexagonTargetTransformInfo.cpp | 8 ++--
.../Target/Lanai/LanaiTargetTransformInfo.h | 8 ++--
.../Target/NVPTX/NVPTXTargetTransformInfo.cpp | 8 ++--
.../Target/PowerPC/PPCTargetTransformInfo.cpp | 8 ++--
.../Target/RISCV/RISCVTargetTransformInfo.cpp | 27 ++++++++-----
.../Target/RISCV/RISCVTargetTransformInfo.h | 2 +-
.../SystemZ/SystemZTargetTransformInfo.cpp | 6 +--
.../WebAssemblyTargetTransformInfo.cpp | 2 +-
.../lib/Target/X86/X86TargetTransformInfo.cpp | 22 ++++++++--
llvm/lib/Target/X86/X86TargetTransformInfo.h | 2 +-
16 files changed, 102 insertions(+), 70 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/BasicTTIImpl.h b/llvm/include/llvm/CodeGen/BasicTTIImpl.h
index 5b12ed5b0a3fc..ff8a6d002bfd5 100644
--- a/llvm/include/llvm/CodeGen/BasicTTIImpl.h
+++ b/llvm/include/llvm/CodeGen/BasicTTIImpl.h
@@ -1049,30 +1049,36 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
unsigned getMaxInterleaveFactor(ElementCount VF) const override { return 1; }
- InstructionCost getArithmeticInstrCost(
- unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
- TTI::OperandValueInfo Opd1Info = {TTI::OK_AnyValue, TTI::OP_None},
- TTI::OperandValueInfo Opd2Info = {TTI::OK_AnyValue, TTI::OP_None},
- ArrayRef<const Value *> Args = {},
- const Instruction *CxtI = nullptr) const override {
-
+ bool getConvertedArithmeticInstructionCost(unsigned ISDOpcode, Type *Ty,
+ TTI::TargetCostKind CostKind,
+ TTI::OperandValueInfo Opd1Info,
+ TTI::OperandValueInfo Opd2Info,
+ ArrayRef<const Value *> Args,
+ const Instruction *CxtI,
+ InstructionCost &Cost) const {
// Vector unsigned division/remainder will be simplified to shifts/masks.
- if ((Opcode == Instruction::UDiv || Opcode == Instruction::URem) &&
- Opd2Info.isConstant() && Opd2Info.isPowerOf2())
- return getArithmeticInstrCost(
- Opcode == Instruction::UDiv ? Instruction::LShr : Instruction::And,
- Ty, CostKind, Opd1Info.getNoProps(), Opd2Info.getNoProps());
-
- return getArithmeticInstrCostImpl(Opcode, Ty, CostKind, Opd1Info, Opd2Info,
- Args, CxtI);
+ if ((ISDOpcode == ISD::UDIV || ISDOpcode == ISD::UREM) &&
+ Opd2Info.isConstant() && Opd2Info.isPowerOf2()) {
+ if (ISDOpcode == ISD::UDIV)
+ Cost = getArithmeticInstrCost(Instruction::LShr, Ty, CostKind,
+ Opd1Info.getNoProps(),
+ Opd2Info.getNoProps());
+ // UREM
+ else
+ Cost = getArithmeticInstrCost(Instruction::And, Ty, CostKind,
+ Opd1Info.getNoProps(),
+ Opd2Info.getNoProps());
+ return true;
+ }
+ return false;
}
- virtual InstructionCost getArithmeticInstrCostImpl(
+ InstructionCost getArithmeticInstrCost(
unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
TTI::OperandValueInfo Opd1Info = {TTI::OK_AnyValue, TTI::OP_None},
TTI::OperandValueInfo Opd2Info = {TTI::OK_AnyValue, TTI::OP_None},
ArrayRef<const Value *> Args = {},
- const Instruction *CxtI = nullptr) const {
+ const Instruction *CxtI = nullptr) const override {
// Check if any of the operands are vector operands.
const TargetLoweringBase *TLI = getTLI();
int ISD = TLI->InstructionOpcodeToISD(Opcode);
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
index b6c990bdabcc1..cdba394ee3b15 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -4327,7 +4327,7 @@ std::optional<InstructionCost> AArch64TTIImpl::getFP16BF16PromoteCost(
return Cost;
}
-InstructionCost AArch64TTIImpl::getArithmeticInstrCostImpl(
+InstructionCost AArch64TTIImpl::getArithmeticInstrCost(
unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
TTI::OperandValueInfo Op1Info, TTI::OperandValueInfo Op2Info,
ArrayRef<const Value *> Args, const Instruction *CxtI) const {
@@ -4342,8 +4342,8 @@ InstructionCost AArch64TTIImpl::getArithmeticInstrCostImpl(
// TODO: Handle more cost kinds.
if (CostKind != TTI::TCK_RecipThroughput)
- return BaseT::getArithmeticInstrCostImpl(Opcode, Ty, CostKind, Op1Info,
- Op2Info, Args, CxtI);
+ return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info,
+ Op2Info, Args, CxtI);
// Legalize the type.
std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(Ty);
@@ -4375,10 +4375,15 @@ InstructionCost AArch64TTIImpl::getArithmeticInstrCostImpl(
return LT.first;
}
+ InstructionCost ConvertedCost;
+ if (getConvertedArithmeticInstructionCost(ISD, Ty, CostKind, Op1Info, Op2Info,
+ Args, CxtI, ConvertedCost))
+ return ConvertedCost;
+
switch (ISD) {
default:
- return BaseT::getArithmeticInstrCostImpl(Opcode, Ty, CostKind, Op1Info,
- Op2Info);
+ return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info,
+ Op2Info);
case ISD::SREM:
case ISD::SDIV:
/*
@@ -4529,7 +4534,7 @@ InstructionCost AArch64TTIImpl::getArithmeticInstrCostImpl(
if (!VT.isVector() && VT.getSizeInBits() > 64)
return getCallInstrCost(/*Function*/ nullptr, Ty, {Ty, Ty}, CostKind);
- InstructionCost Cost = BaseT::getArithmeticInstrCostImpl(
+ InstructionCost Cost = BaseT::getArithmeticInstrCost(
Opcode, Ty, CostKind, Op1Info, Op2Info);
if (Ty->isVectorTy() && (ISD == ISD::SDIV || ISD == ISD::UDIV)) {
if (TLI->isOperationLegalOrCustom(ISD, LT.second) && ST->hasSVE()) {
@@ -4564,7 +4569,7 @@ InstructionCost AArch64TTIImpl::getArithmeticInstrCostImpl(
if ((Op1Info.isConstant() && Op1Info.isUniform()) ||
(Op2Info.isConstant() && Op2Info.isUniform())) {
if (auto *VTy = dyn_cast<FixedVectorType>(Ty)) {
- InstructionCost DivCost = BaseT::getArithmeticInstrCostImpl(
+ InstructionCost DivCost = BaseT::getArithmeticInstrCost(
Opcode, Ty->getScalarType(), CostKind, Op1Info, Op2Info);
return (4 + DivCost) * VTy->getNumElements();
}
@@ -4641,15 +4646,15 @@ InstructionCost AArch64TTIImpl::getArithmeticInstrCostImpl(
if (!Ty->getScalarType()->isFP128Ty())
return 2 * LT.first;
- return BaseT::getArithmeticInstrCostImpl(Opcode, Ty, CostKind, Op1Info,
- Op2Info);
+ return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info,
+ Op2Info);
case ISD::FREM:
// Pass nullptr as fmod/fmodf calls are emitted by the backend even when
// those functions are not declared in the module.
if (!Ty->isVectorTy())
return getCallInstrCost(/*Function*/ nullptr, Ty, {Ty, Ty}, CostKind);
- return BaseT::getArithmeticInstrCostImpl(Opcode, Ty, CostKind, Op1Info,
- Op2Info);
+ return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info,
+ Op2Info);
}
}
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
index c7acd108b82ee..cde391bdcaea8 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
@@ -253,7 +253,7 @@ class AArch64TTIImpl final : public BasicTTIImplBase<AArch64TTIImpl> {
InstructionCost getSpliceCost(VectorType *Tp, int Index,
TTI::TargetCostKind CostKind) const;
- InstructionCost getArithmeticInstrCostImpl(
+ InstructionCost getArithmeticInstrCost(
unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None},
TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None},
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
index c3c8fb9b23c95..030a9008c34dc 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
@@ -678,8 +678,8 @@ InstructionCost GCNTTIImpl::getArithmeticInstrCost(
break;
}
- return BaseT::getArithmeticInstrCostImpl(Opcode, Ty, CostKind, Op1Info,
- Op2Info, Args, CxtI);
+ return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info,
+ Args, CxtI);
}
// Return true if there's a potential benefit from using v2f16/v2i16
diff --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
index 6c3b98b2bafc9..03392fc2d84bc 100644
--- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
@@ -1513,7 +1513,7 @@ InstructionCost ARMTTIImpl::getArithmeticInstrCost(
if (const auto *Entry = CostTableLookup(CostTbl, ISDOpcode, LT.second))
return LT.first * Entry->Cost;
- InstructionCost Cost = BaseT::getArithmeticInstrCostImpl(
+ InstructionCost Cost = BaseT::getArithmeticInstrCost(
Opcode, Ty, CostKind, Op1Info, Op2Info);
// This is somewhat of a hack. The problem that we are facing is that SROA
diff --git a/llvm/lib/Target/BPF/BPFTargetTransformInfo.h b/llvm/lib/Target/BPF/BPFTargetTransformInfo.h
index f28fa922edffe..d7b2ceff105c9 100644
--- a/llvm/lib/Target/BPF/BPFTargetTransformInfo.h
+++ b/llvm/lib/Target/BPF/BPFTargetTransformInfo.h
@@ -68,8 +68,8 @@ class BPFTTIImpl final : public BasicTTIImplBase<BPFTTIImpl> {
if (ISD == ISD::ADD && CostKind == TTI::TCK_RecipThroughput)
return SCEVCheapExpansionBudget.getValue() + 1;
- return BaseT::getArithmeticInstrCostImpl(Opcode, Ty, CostKind, Op1Info,
- Op2Info);
+ return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info,
+ Op2Info);
}
TTI::MemCmpExpansionOptions
diff --git a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
index 318722a928cdb..c2e9b3527e1ee 100644
--- a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
@@ -265,8 +265,8 @@ InstructionCost HexagonTTIImpl::getArithmeticInstrCost(
ArrayRef<const Value *> Args, const Instruction *CxtI) const {
// TODO: Handle more cost kinds.
if (CostKind != TTI::TCK_RecipThroughput)
- return BaseT::getArithmeticInstrCostImpl(Opcode, Ty, CostKind, Op1Info,
- Op2Info, Args, CxtI);
+ return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info,
+ Op2Info, Args, CxtI);
if (Ty->isVectorTy()) {
if (!isHVXVectorType(Ty) && Ty->isFPOrFPVectorTy())
@@ -275,8 +275,8 @@ InstructionCost HexagonTTIImpl::getArithmeticInstrCost(
if (LT.second.isFloatingPoint())
return LT.first + FloatFactor * getTypeNumElements(Ty);
}
- return BaseT::getArithmeticInstrCostImpl(Opcode, Ty, CostKind, Op1Info,
- Op2Info, Args, CxtI);
+ return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info,
+ Args, CxtI);
}
InstructionCost HexagonTTIImpl::getCastInstrCost(unsigned Opcode, Type *DstTy,
diff --git a/llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h b/llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h
index 0f87e72750a36..0342af65c1ef7 100644
--- a/llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h
+++ b/llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h
@@ -101,8 +101,8 @@ class LanaiTTIImpl final : public BasicTTIImplBase<LanaiTTIImpl> {
switch (ISD) {
default:
- return BaseT::getArithmeticInstrCostImpl(Opcode, Ty, CostKind, Op1Info,
- Op2Info);
+ return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info,
+ Op2Info);
case ISD::MUL:
case ISD::SDIV:
case ISD::UDIV:
@@ -112,8 +112,8 @@ class LanaiTTIImpl final : public BasicTTIImplBase<LanaiTTIImpl> {
// instruction cost was arbitrarily chosen to reduce the desirability
// of emitting arithmetic instructions that are emulated in software.
// TODO: Investigate the performance impact given specialized lowerings.
- return 64 * BaseT::getArithmeticInstrCostImpl(Opcode, Ty, CostKind,
- Op1Info, Op2Info);
+ return 64 * BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info,
+ Op2Info);
}
}
};
diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp b/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
index a7b30daef28fe..a491d0ed4a912 100644
--- a/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
@@ -508,8 +508,8 @@ InstructionCost NVPTXTTIImpl::getArithmeticInstrCost(
switch (ISD) {
default:
- return BaseT::getArithmeticInstrCostImpl(Opcode, Ty, CostKind, Op1Info,
- Op2Info);
+ return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info,
+ Op2Info);
case ISD::ADD:
case ISD::MUL:
case ISD::XOR:
@@ -521,8 +521,8 @@ InstructionCost NVPTXTTIImpl::getArithmeticInstrCost(
if (LT.second.SimpleTy == MVT::i64)
return 2 * LT.first;
// Delegate other cases to the basic TTI.
- return BaseT::getArithmeticInstrCostImpl(Opcode, Ty, CostKind, Op1Info,
- Op2Info);
+ return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info,
+ Op2Info);
}
}
diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
index 4817aed6b9cb0..6971db1acfc8e 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
@@ -605,12 +605,12 @@ InstructionCost PPCTTIImpl::getArithmeticInstrCost(
// TODO: Handle more cost kinds.
if (CostKind != TTI::TCK_RecipThroughput)
- return BaseT::getArithmeticInstrCostImpl(Opcode, Ty, CostKind, Op1Info,
- Op2Info, Args, CxtI);
+ return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info,
+ Op2Info, Args, CxtI);
// Fallback to the default implementation.
- InstructionCost Cost =
- BaseT::getArithmeticInstrCostImpl(Opcode, Ty, CostKind, Op1Info, Op2Info);
+ InstructionCost Cost = BaseT::getArithmeticInstrCost(
+ Opcode, Ty, CostKind, Op1Info, Op2Info);
return Cost * CostFactor;
}
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index c709d5c7f5b36..40aa2cb086562 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2669,29 +2669,34 @@ RISCVTTIImpl::getIndexedVectorInstrCostFromEnd(unsigned Opcode, Type *Val,
nullptr);
}
-InstructionCost RISCVTTIImpl::getArithmeticInstrCostImpl(
+InstructionCost RISCVTTIImpl::getArithmeticInstrCost(
unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
TTI::OperandValueInfo Op1Info, TTI::OperandValueInfo Op2Info,
ArrayRef<const Value *> Args, const Instruction *CxtI) const {
// TODO: Handle more cost kinds.
if (CostKind != TTI::TCK_RecipThroughput)
- return BaseT::getArithmeticInstrCostImpl(Opcode, Ty, CostKind, Op1Info,
- Op2Info, Args, CxtI);
+ return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info,
+ Args, CxtI);
if (isa<FixedVectorType>(Ty) && !ST->useRVVForFixedLengthVectors())
- return BaseT::getArithmeticInstrCostImpl(Opcode, Ty, CostKind, Op1Info,
- Op2Info, Args, CxtI);
+ return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info,
+ Args, CxtI);
// Skip if scalar size of Ty is bigger than ELEN.
if (isa<VectorType>(Ty) && Ty->getScalarSizeInBits() > ST->getELen())
- return BaseT::getArithmeticInstrCostImpl(Opcode, Ty, CostKind, Op1Info,
- Op2Info, Args, CxtI);
+ return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info,
+ Args, CxtI);
// Legalize the type.
std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(Ty);
unsigned ISDOpcode = TLI->InstructionOpcodeToISD(Opcode);
+ InstructionCost ConvertedCost;
+ if (getConvertedArithmeticInstructionCost(ISDOpcode, Ty, CostKind, Op1Info,
+ Op2Info, Args, CxtI, ConvertedCost))
+ return ConvertedCost;
+
// TODO: Handle scalar type.
if (!LT.second.isVector()) {
static const CostTblEntry DivTbl[]{
@@ -2707,8 +2712,8 @@ InstructionCost RISCVTTIImpl::getArithmeticInstrCostImpl(
if (const auto *Entry = CostTableLookup(DivTbl, ISDOpcode, LT.second))
return Entry->Cost * LT.first;
- return BaseT::getArithmeticInstrCostImpl(Opcode, Ty, CostKind, Op1Info,
- Op2Info, Args, CxtI);
+ return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info,
+ Args, CxtI);
}
// f16 with zvfhmin and bf16 will be promoted to f32.
@@ -2799,8 +2804,8 @@ InstructionCost RISCVTTIImpl::getArithmeticInstrCostImpl(
// Assuming all other instructions have the same cost until a need arises to
// differentiate them.
return CastCost + ConstantMatCost +
- BaseT::getArithmeticInstrCostImpl(Opcode, Ty, CostKind, Op1Info,
- Op2Info, Args, CxtI);
+ BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info,
+ Args, CxtI);
}
InstructionCost InstrCost = getRISCVInstructionCost(Op, LT.second, CostKind);
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
index de77dfad574d7..ad4d20bdc8956 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
@@ -262,7 +262,7 @@ class RISCVTTIImpl final : public BasicTTIImplBase<RISCVTTIImpl> {
TTI::TargetCostKind CostKind,
unsigned Index) const override;
- InstructionCost getArithmeticInstrCostImpl(
+ InstructionCost getArithmeticInstrCost(
unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None},
TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None},
diff --git a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
index 67e3d3088c94a..c3e3be0068a81 100644
--- a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
@@ -587,7 +587,7 @@ InstructionCost SystemZTTIImpl::getArithmeticInstrCost(
// TODO: Handle more cost kinds.
if (CostKind != TTI::TCK_RecipThroughput)
- return BaseT::getArithmeticInstrCostImpl(Opcode, Ty, CostKind, Op1Info,
+ return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info,
Op2Info, Args, CxtI);
if (CxtI && Ty && !Ty->isVectorTy() && isFoldableRMW(CxtI, Ty))
return TTI::TCC_Free;
@@ -762,8 +762,8 @@ InstructionCost SystemZTTIImpl::getArithmeticInstrCost(
}
// Fallback to the default implementation.
- return BaseT::getArithmeticInstrCostImpl(Opcode, Ty, CostKind, Op1Info,
- Op2Info, Args, CxtI);
+ return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info,
+ Args, CxtI);
}
InstructionCost
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
index a50956bc937b0..1bd3a6b950944 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
@@ -79,7 +79,7 @@ InstructionCost WebAssemblyTTIImpl::getArithmeticInstrCost(
}
InstructionCost Cost =
- BasicTTIImplBase<WebAssemblyTTIImpl>::getArithmeticInstrCostImpl(
+ BasicTTIImplBase<WebAssemblyTTIImpl>::getArithmeticInstrCost(
Opcode, Ty, CostKind, Op1Info, Op2Info);
if (auto *VTy = dyn_cast<VectorType>(Ty)) {
diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
index 3f05a6eb3b114..f74081b960f11 100644
--- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -250,7 +250,7 @@ unsigned X86TTIImpl::getMaxInterleaveFactor(ElementCount VF) const {
return 2;
}
-InstructionCost X86TTIImpl::getArithmeticInstrCostImpl(
+InstructionCost X86TTIImpl::getArithmeticInstrCost(
unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
TTI::OperandValueInfo Op1Info, TTI::OperandValueInfo Op2Info,
ArrayRef<const Value *> Args, const Instruction *CxtI) const {
@@ -276,6 +276,11 @@ InstructionCost X86TTIImpl::getArithmeticInstrCostImpl(
int ISD = TLI->InstructionOpcodeToISD(Opcode);
assert(ISD && "Invalid opcode");
+ InstructionCost ConvertedCost;
+ if (getConvertedArithmeticInstructionCost(ISD, Ty, CostKind, Op1Info, Op2Info,
+ Args, CxtI, ConvertedCost))
+ return ConvertedCost;
+
if (ISD == ISD::MUL && Args.size() == 2 && LT.second.isVector() &&
(LT.second.getScalarType() == MVT::i32 ||
LT.second.getScalarType() == MVT::i64)) {
@@ -366,6 +371,17 @@ InstructionCost X86TTIImpl::getArithmeticInstrCostImpl(
return Cost;
}
+ // Vector unsigned division/remainder will be simplified to shifts/masks.
+ if ((ISD == ISD::UDIV || ISD == ISD::UREM) && Op2Info.isConstant() &&
+ Op2Info.isPowerOf2()) {
+ if (ISD == ISD::UDIV)
+ return getArithmeticInstrCost(Instruction::LShr, Ty, CostKind,
+ Op1Info.getNoProps(), Op2Info.getNoProps());
+ // UREM
+ return getArithmeticInstrCost(Instruction::And, Ty, CostKind,
+ Op1Info.getNoProps(), Op2Info.getNoProps());
+ }
+
static const CostKindTblEntry GFNIUniformConstCostTable[] = {
{ ISD::SHL, MVT::v16i8, { 1, 6, 1, 2 } }, // gf2p8affineqb
{ ISD::SRL, MVT::v16i8, { 1, 6, 1, 2 } }, // gf2p8affineqb
@@ -1507,8 +1523,8 @@ InstructionCost X86TTIImpl::getArithmeticInstrCostImpl(
}
// Fallback to the default implementation.
- return BaseT::getArithmeticInstrCostImpl(Opcode, Ty, CostKind, Op1Info,
- Op2Info, Args, CxtI);
+ return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info,
+ Args, CxtI);
}
InstructionCost
diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.h b/llvm/lib/Target/X86/X86TargetTransformInfo.h
index 595ad8f97068a..ee1afdd8aaea9 100644
--- a/llvm/lib/Target/X86/X86TargetTransformInfo.h
+++ b/llvm/lib/Target/X86/X86TargetTransformInfo.h
@@ -138,7 +138,7 @@ class X86TTIImpl final : public BasicTTIImplBase<X86TTIImpl> {
getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const override;
unsigned getLoadStoreVecRegBitWidth(unsigned AS) const override;
unsigned getMaxInterleaveFactor(ElementCount VF) const override;
- InstructionCost getArithmeticInstrCostImpl(
+ InstructionCost getArithmeticInstrCost(
unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None},
TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None},
>From 45b56bdd4f5c6ce5ce94df4ce6f7b136157d467c Mon Sep 17 00:00:00 2001
From: bababuck <buchner.ryan at gmail.com>
Date: Tue, 14 Apr 2026 14:26:02 -0700
Subject: [PATCH 16/19] Rollback changed so that only the RISCV backend is
modified
---
llvm/include/llvm/CodeGen/BasicTTIImpl.h | 24 -----
.../AArch64/AArch64TargetTransformInfo.cpp | 15 ++-
.../Target/RISCV/RISCVTargetTransformInfo.cpp | 29 +++++-
.../Target/RISCV/RISCVTargetTransformInfo.h | 5 +
.../lib/Target/X86/X86TargetTransformInfo.cpp | 5 -
llvm/test/Analysis/CostModel/AArch64/div.ll | 92 +++++++++----------
llvm/test/Analysis/CostModel/AArch64/rem.ll | 92 +++++++++----------
.../Analysis/CostModel/AArch64/sve-div.ll | 72 +++++++--------
.../Analysis/CostModel/AArch64/sve-rem.ll | 74 +++++++--------
.../Analysis/CostModel/RISCV/arith-int.ll | 23 +++++
10 files changed, 228 insertions(+), 203 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/BasicTTIImpl.h b/llvm/include/llvm/CodeGen/BasicTTIImpl.h
index ff8a6d002bfd5..7dbd8bc658161 100644
--- a/llvm/include/llvm/CodeGen/BasicTTIImpl.h
+++ b/llvm/include/llvm/CodeGen/BasicTTIImpl.h
@@ -1049,30 +1049,6 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
unsigned getMaxInterleaveFactor(ElementCount VF) const override { return 1; }
- bool getConvertedArithmeticInstructionCost(unsigned ISDOpcode, Type *Ty,
- TTI::TargetCostKind CostKind,
- TTI::OperandValueInfo Opd1Info,
- TTI::OperandValueInfo Opd2Info,
- ArrayRef<const Value *> Args,
- const Instruction *CxtI,
- InstructionCost &Cost) const {
- // Vector unsigned division/remainder will be simplified to shifts/masks.
- if ((ISDOpcode == ISD::UDIV || ISDOpcode == ISD::UREM) &&
- Opd2Info.isConstant() && Opd2Info.isPowerOf2()) {
- if (ISDOpcode == ISD::UDIV)
- Cost = getArithmeticInstrCost(Instruction::LShr, Ty, CostKind,
- Opd1Info.getNoProps(),
- Opd2Info.getNoProps());
- // UREM
- else
- Cost = getArithmeticInstrCost(Instruction::And, Ty, CostKind,
- Opd1Info.getNoProps(),
- Opd2Info.getNoProps());
- return true;
- }
- return false;
- }
-
InstructionCost getArithmeticInstrCost(
unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
TTI::OperandValueInfo Opd1Info = {TTI::OK_AnyValue, TTI::OP_None},
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
index cdba394ee3b15..ff99eeefde6e3 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -4375,11 +4375,6 @@ InstructionCost AArch64TTIImpl::getArithmeticInstrCost(
return LT.first;
}
- InstructionCost ConvertedCost;
- if (getConvertedArithmeticInstructionCost(ISD, Ty, CostKind, Op1Info, Op2Info,
- Args, CxtI, ConvertedCost))
- return ConvertedCost;
-
switch (ISD) {
default:
return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info,
@@ -4503,6 +4498,16 @@ InstructionCost AArch64TTIImpl::getArithmeticInstrCost(
case ISD::UREM: {
auto VT = TLI->getValueType(DL, Ty);
if (Op2Info.isConstant()) {
+ // If the operand is a power of 2 we can use the shift or and cost.
+ if (ISD == ISD::UDIV && Op2Info.isPowerOf2())
+ return getArithmeticInstrCost(Instruction::LShr, Ty, CostKind,
+ Op1Info.getNoProps(),
+ Op2Info.getNoProps());
+ if (ISD == ISD::UREM && Op2Info.isPowerOf2())
+ return getArithmeticInstrCost(Instruction::And, Ty, CostKind,
+ Op1Info.getNoProps(),
+ Op2Info.getNoProps());
+
if (ISD == ISD::UDIV || ISD == ISD::UREM) {
// Divides by a constant are expanded to MULHU + SUB + SRL + ADD + SRL.
// The MULHU will be expanded to UMULL for the types not listed below,
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 40aa2cb086562..312dc069c8a1a 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2669,6 +2669,27 @@ RISCVTTIImpl::getIndexedVectorInstrCostFromEnd(unsigned Opcode, Type *Val,
nullptr);
}
+std::optional<InstructionCost>
+RISCVTTIImpl::getConvertedArithmeticInstructionCost(
+ unsigned ISDOpcode, Type *Ty, TTI::TargetCostKind CostKind,
+ TTI::OperandValueInfo Opd1Info, TTI::OperandValueInfo Opd2Info,
+ ArrayRef<const Value *> Args, const Instruction *CxtI) const {
+ // Vector unsigned division/remainder will be simplified to shifts/masks.
+ if ((ISDOpcode == ISD::UDIV || ISDOpcode == ISD::UREM) &&
+ Opd2Info.isConstant() && Opd2Info.isPowerOf2()) {
+ if (ISDOpcode == ISD::UDIV)
+ return getArithmeticInstrCost(Instruction::LShr, Ty, CostKind,
+ Opd1Info.getNoProps(),
+ Opd2Info.getNoProps());
+ // UREM
+ else
+ return getArithmeticInstrCost(Instruction::And, Ty, CostKind,
+ Opd1Info.getNoProps(),
+ Opd2Info.getNoProps());
+ }
+ return std::nullopt;
+}
+
InstructionCost RISCVTTIImpl::getArithmeticInstrCost(
unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
TTI::OperandValueInfo Op1Info, TTI::OperandValueInfo Op2Info,
@@ -2692,10 +2713,10 @@ InstructionCost RISCVTTIImpl::getArithmeticInstrCost(
std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(Ty);
unsigned ISDOpcode = TLI->InstructionOpcodeToISD(Opcode);
- InstructionCost ConvertedCost;
- if (getConvertedArithmeticInstructionCost(ISDOpcode, Ty, CostKind, Op1Info,
- Op2Info, Args, CxtI, ConvertedCost))
- return ConvertedCost;
+ if (std::optional<InstructionCost> ConvertedCost =
+ getConvertedArithmeticInstructionCost(ISDOpcode, Ty, CostKind,
+ Op1Info, Op2Info, Args, CxtI))
+ return *ConvertedCost;
// TODO: Handle scalar type.
if (!LT.second.isVector()) {
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
index ad4d20bdc8956..88a009d3680ad 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
@@ -224,6 +224,11 @@ class RISCVTTIImpl final : public BasicTTIImplBase<RISCVTTIImpl> {
getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty, FastMathFlags FMF,
TTI::TargetCostKind CostKind) const override;
+ std::optional<InstructionCost> getConvertedArithmeticInstructionCost(
+ unsigned ISDOpcode, Type *Ty, TTI::TargetCostKind CostKind,
+ TTI::OperandValueInfo Opd1Info, TTI::OperandValueInfo Opd2Info,
+ ArrayRef<const Value *> Args, const Instruction *CxtI) const;
+
InstructionCost
getArithmeticReductionCost(unsigned Opcode, VectorType *Ty,
std::optional<FastMathFlags> FMF,
diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
index f74081b960f11..d309ea2dc1763 100644
--- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -276,11 +276,6 @@ InstructionCost X86TTIImpl::getArithmeticInstrCost(
int ISD = TLI->InstructionOpcodeToISD(Opcode);
assert(ISD && "Invalid opcode");
- InstructionCost ConvertedCost;
- if (getConvertedArithmeticInstructionCost(ISD, Ty, CostKind, Op1Info, Op2Info,
- Args, CxtI, ConvertedCost))
- return ConvertedCost;
-
if (ISD == ISD::MUL && Args.size() == 2 && LT.second.isVector() &&
(LT.second.getScalarType() == MVT::i32 ||
LT.second.getScalarType() == MVT::i64)) {
diff --git a/llvm/test/Analysis/CostModel/AArch64/div.ll b/llvm/test/Analysis/CostModel/AArch64/div.ll
index 565815dd827d7..3a2358dba51b2 100644
--- a/llvm/test/Analysis/CostModel/AArch64/div.ll
+++ b/llvm/test/Analysis/CostModel/AArch64/div.ll
@@ -578,29 +578,29 @@ define void @sdiv_constpow2() {
define void @udiv_constpow2() {
; CHECK-LABEL: 'udiv_constpow2'
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %I128 = udiv i128 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %I64 = udiv i64 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i64 = udiv <2 x i64> undef, <i64 8, i64 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V4i64 = udiv <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V8i64 = udiv <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %I32 = udiv i32 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i32 = udiv <2 x i32> undef, <i32 2, i32 4>
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V4i32 = udiv <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V8i32 = udiv <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V16i32 = udiv <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %I16 = udiv i16 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i16 = udiv <2 x i16> undef, <i16 2, i16 4>
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V4i16 = udiv <4 x i16> undef, <i16 2, i16 4, i16 8, i16 16>
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V8i16 = udiv <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V16i16 = udiv <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V32i16 = udiv <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %I8 = udiv i8 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i8 = udiv <2 x i8> undef, <i8 2, i8 4>
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V4i8 = udiv <4 x i8> undef, <i8 2, i8 4, i8 8, i8 16>
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V8i8 = udiv <8 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V16i8 = udiv <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V32i8 = udiv <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V64i8 = udiv <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %I128 = udiv i128 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = udiv i64 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = udiv <2 x i64> undef, <i64 8, i64 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = udiv <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V8i64 = udiv <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = udiv i32 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i32 = udiv <2 x i32> undef, <i32 2, i32 4>
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = udiv <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = udiv <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V16i32 = udiv <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I16 = udiv i16 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i16 = udiv <2 x i16> undef, <i16 2, i16 4>
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i16 = udiv <4 x i16> undef, <i16 2, i16 4, i16 8, i16 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = udiv <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = udiv <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V32i16 = udiv <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = udiv i8 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i8 = udiv <2 x i8> undef, <i8 2, i8 4>
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i8 = udiv <4 x i8> undef, <i8 2, i8 4, i8 8, i8 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i8 = udiv <8 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = udiv <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = udiv <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V64i8 = udiv <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
%I128 = udiv i128 undef, 16
@@ -694,29 +694,29 @@ define void @sdiv_uniformconstpow2() {
define void @udiv_uniformconstpow2() {
; CHECK-LABEL: 'udiv_uniformconstpow2'
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %I128 = udiv i128 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %I64 = udiv i64 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i64 = udiv <2 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V4i64 = udiv <4 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V8i64 = udiv <8 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %I32 = udiv i32 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i32 = udiv <2 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V4i32 = udiv <4 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V8i32 = udiv <8 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V16i32 = udiv <16 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %I16 = udiv i16 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i16 = udiv <2 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V4i16 = udiv <4 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V8i16 = udiv <8 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V16i16 = udiv <16 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V32i16 = udiv <32 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %I8 = udiv i8 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i8 = udiv <2 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V4i8 = udiv <4 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V8i8 = udiv <8 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V16i8 = udiv <16 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V32i8 = udiv <32 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V64i8 = udiv <64 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %I128 = udiv i128 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = udiv i64 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = udiv <2 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = udiv <4 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V8i64 = udiv <8 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = udiv i32 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i32 = udiv <2 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = udiv <4 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = udiv <8 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V16i32 = udiv <16 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I16 = udiv i16 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i16 = udiv <2 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i16 = udiv <4 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = udiv <8 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = udiv <16 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V32i16 = udiv <32 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = udiv i8 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i8 = udiv <2 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i8 = udiv <4 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i8 = udiv <8 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = udiv <16 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = udiv <32 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V64i8 = udiv <64 x i8> undef, splat (i8 16)
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
%I128 = udiv i128 undef, 16
diff --git a/llvm/test/Analysis/CostModel/AArch64/rem.ll b/llvm/test/Analysis/CostModel/AArch64/rem.ll
index 4d34819dde516..2fa62f1705911 100644
--- a/llvm/test/Analysis/CostModel/AArch64/rem.ll
+++ b/llvm/test/Analysis/CostModel/AArch64/rem.ll
@@ -578,29 +578,29 @@ define void @srem_constpow2() {
define void @urem_constpow2() {
; CHECK-LABEL: 'urem_constpow2'
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %I128 = urem i128 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %I64 = urem i64 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i64 = urem <2 x i64> undef, <i64 8, i64 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V4i64 = urem <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V8i64 = urem <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %I32 = urem i32 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i32 = urem <2 x i32> undef, <i32 2, i32 4>
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V4i32 = urem <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V8i32 = urem <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V16i32 = urem <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %I16 = urem i16 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i16 = urem <2 x i16> undef, <i16 2, i16 4>
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V4i16 = urem <4 x i16> undef, <i16 2, i16 4, i16 8, i16 16>
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V8i16 = urem <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V16i16 = urem <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V32i16 = urem <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %I8 = urem i8 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i8 = urem <2 x i8> undef, <i8 2, i8 4>
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V4i8 = urem <4 x i8> undef, <i8 2, i8 4, i8 8, i8 16>
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V8i8 = urem <8 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V16i8 = urem <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V32i8 = urem <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
-; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V64i8 = urem <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %I128 = urem i128 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = urem i64 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = urem <2 x i64> undef, <i64 8, i64 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = urem <4 x i64> undef, <i64 2, i64 4, i64 8, i64 16>
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V8i64 = urem <8 x i64> undef, <i64 2, i64 4, i64 8, i64 16, i64 32, i64 64, i64 128, i64 256>
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = urem i32 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i32 = urem <2 x i32> undef, <i32 2, i32 4>
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = urem <4 x i32> undef, <i32 2, i32 4, i32 8, i32 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = urem <8 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V16i32 = urem <16 x i32> undef, <i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256>
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I16 = urem i16 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i16 = urem <2 x i16> undef, <i16 2, i16 4>
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i16 = urem <4 x i16> undef, <i16 2, i16 4, i16 8, i16 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = urem <8 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = urem <16 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V32i16 = urem <32 x i16> undef, <i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 128, i16 256>
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = urem i8 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i8 = urem <2 x i8> undef, <i8 2, i8 4>
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i8 = urem <4 x i8> undef, <i8 2, i8 4, i8 8, i8 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i8 = urem <8 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = urem <16 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = urem <32 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V64i8 = urem <64 x i8> undef, <i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16, i8 2, i8 4, i8 8, i8 16>
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
%I128 = urem i128 undef, 16
@@ -694,29 +694,29 @@ define void @srem_uniformconstpow2() {
define void @urem_uniformconstpow2() {
; CHECK-LABEL: 'urem_uniformconstpow2'
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %I128 = urem i128 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %I64 = urem i64 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i64 = urem <2 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V4i64 = urem <4 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V8i64 = urem <8 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %I32 = urem i32 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i32 = urem <2 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V4i32 = urem <4 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V8i32 = urem <8 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V16i32 = urem <16 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %I16 = urem i16 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i16 = urem <2 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V4i16 = urem <4 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V8i16 = urem <8 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V16i16 = urem <16 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V32i16 = urem <32 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %I8 = urem i8 undef, 16
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i8 = urem <2 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V4i8 = urem <4 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V8i8 = urem <8 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V16i8 = urem <16 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V32i8 = urem <32 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V64i8 = urem <64 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %I128 = urem i128 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I64 = urem i64 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = urem <2 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = urem <4 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V8i64 = urem <8 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I32 = urem i32 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i32 = urem <2 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = urem <4 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = urem <8 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V16i32 = urem <16 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I16 = urem i16 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i16 = urem <2 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i16 = urem <4 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = urem <8 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = urem <16 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V32i16 = urem <32 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %I8 = urem i8 undef, 16
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i8 = urem <2 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i8 = urem <4 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i8 = urem <8 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = urem <16 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = urem <32 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V64i8 = urem <64 x i8> undef, splat (i8 16)
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
%I128 = urem i128 undef, 16
diff --git a/llvm/test/Analysis/CostModel/AArch64/sve-div.ll b/llvm/test/Analysis/CostModel/AArch64/sve-div.ll
index c12ce203d41ec..84a9ca0fab6d8 100644
--- a/llvm/test/Analysis/CostModel/AArch64/sve-div.ll
+++ b/llvm/test/Analysis/CostModel/AArch64/sve-div.ll
@@ -408,42 +408,42 @@ define void @sdiv_uniformconstpow2() {
define void @udiv_uniformconstpow2() {
; CHECK-LABEL: 'udiv_uniformconstpow2'
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i64 = udiv <2 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V4i64 = udiv <4 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V8i64 = udiv <8 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i32 = udiv <2 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V4i32 = udiv <4 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V8i32 = udiv <8 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V16i32 = udiv <16 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i16 = udiv <2 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V4i16 = udiv <4 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V8i16 = udiv <8 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V16i16 = udiv <16 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V32i16 = udiv <32 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i8 = udiv <2 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V4i8 = udiv <4 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V8i8 = udiv <8 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V16i8 = udiv <16 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V32i8 = udiv <32 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V64i8 = udiv <64 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %NV2i64 = udiv <vscale x 2 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %NV4i64 = udiv <vscale x 4 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %NV8i64 = udiv <vscale x 8 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %NV2i32 = udiv <vscale x 2 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %NV4i32 = udiv <vscale x 4 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %NV8i32 = udiv <vscale x 8 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %NV16i32 = udiv <vscale x 16 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %NV2i16 = udiv <vscale x 2 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %NV4i16 = udiv <vscale x 4 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %NV8i16 = udiv <vscale x 8 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %NV16i16 = udiv <vscale x 16 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %NV32i16 = udiv <vscale x 32 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %NV2i8 = udiv <vscale x 2 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %NV4i8 = udiv <vscale x 4 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %NV8i8 = udiv <vscale x 8 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %NV16i8 = udiv <vscale x 16 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %NV32i8 = udiv <vscale x 32 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %NV64i8 = udiv <vscale x 64 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = udiv <2 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = udiv <4 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V8i64 = udiv <8 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i32 = udiv <2 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = udiv <4 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = udiv <8 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V16i32 = udiv <16 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i16 = udiv <2 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i16 = udiv <4 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = udiv <8 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = udiv <16 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V32i16 = udiv <32 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i8 = udiv <2 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i8 = udiv <4 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i8 = udiv <8 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = udiv <16 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = udiv <32 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V64i8 = udiv <64 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV2i64 = udiv <vscale x 2 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %NV4i64 = udiv <vscale x 4 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV8i64 = udiv <vscale x 8 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV2i32 = udiv <vscale x 2 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV4i32 = udiv <vscale x 4 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %NV8i32 = udiv <vscale x 8 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV16i32 = udiv <vscale x 16 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV2i16 = udiv <vscale x 2 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV4i16 = udiv <vscale x 4 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV8i16 = udiv <vscale x 8 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %NV16i16 = udiv <vscale x 16 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV32i16 = udiv <vscale x 32 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV2i8 = udiv <vscale x 2 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV4i8 = udiv <vscale x 4 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV8i8 = udiv <vscale x 8 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV16i8 = udiv <vscale x 16 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %NV32i8 = udiv <vscale x 32 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV64i8 = udiv <vscale x 64 x i8> undef, splat (i8 16)
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
%V2i64 = udiv <2 x i64> undef, splat (i64 16)
diff --git a/llvm/test/Analysis/CostModel/AArch64/sve-rem.ll b/llvm/test/Analysis/CostModel/AArch64/sve-rem.ll
index 4353a495be4ba..eac8b66bcd216 100644
--- a/llvm/test/Analysis/CostModel/AArch64/sve-rem.ll
+++ b/llvm/test/Analysis/CostModel/AArch64/sve-rem.ll
@@ -410,43 +410,43 @@ define void @srem_uniformconstpow2() {
define void @urem_uniformconstpow2() {
; CHECK-LABEL: 'urem_uniformconstpow2'
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i64 = urem <2 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V4i64 = urem <4 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V8i64 = urem <8 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i32 = urem <2 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V4i32 = urem <4 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V8i32 = urem <8 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V16i32 = urem <16 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i16 = urem <2 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V4i16 = urem <4 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V8i16 = urem <8 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V16i16 = urem <16 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V32i16 = urem <32 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V2i8 = urem <2 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V4i8 = urem <4 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V8i8 = urem <8 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %V16i8 = urem <16 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %V32i8 = urem <32 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %V64i8 = urem <64 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:Invalid CodeSize:1 Lat:1 SizeLat:1 for: %NV2i128 = urem <vscale x 2 x i128> undef, splat (i128 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %NV2i64 = urem <vscale x 2 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %NV4i64 = urem <vscale x 4 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %NV8i64 = urem <vscale x 8 x i64> undef, splat (i64 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %NV2i32 = urem <vscale x 2 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %NV4i32 = urem <vscale x 4 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %NV8i32 = urem <vscale x 8 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %NV16i32 = urem <vscale x 16 x i32> undef, splat (i32 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %NV2i16 = urem <vscale x 2 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %NV4i16 = urem <vscale x 4 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %NV8i16 = urem <vscale x 8 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %NV16i16 = urem <vscale x 16 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %NV32i16 = urem <vscale x 32 x i16> undef, splat (i16 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %NV2i8 = urem <vscale x 2 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %NV4i8 = urem <vscale x 4 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %NV8i8 = urem <vscale x 8 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of 1 for: %NV16i8 = urem <vscale x 16 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:1 SizeLat:1 for: %NV32i8 = urem <vscale x 32 x i8> undef, splat (i8 16)
-; CHECK-NEXT: Cost Model: Found costs of RThru:4 CodeSize:1 Lat:1 SizeLat:1 for: %NV64i8 = urem <vscale x 64 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i64 = urem <2 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V4i64 = urem <4 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V8i64 = urem <8 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i32 = urem <2 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i32 = urem <4 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V8i32 = urem <8 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V16i32 = urem <16 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i16 = urem <2 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i16 = urem <4 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i16 = urem <8 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V16i16 = urem <16 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V32i16 = urem <32 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V2i8 = urem <2 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V4i8 = urem <4 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V8i8 = urem <8 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %V16i8 = urem <16 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %V32i8 = urem <32 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V64i8 = urem <64 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:Invalid CodeSize:4 Lat:4 SizeLat:4 for: %NV2i128 = urem <vscale x 2 x i128> undef, splat (i128 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV2i64 = urem <vscale x 2 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %NV4i64 = urem <vscale x 4 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV8i64 = urem <vscale x 8 x i64> undef, splat (i64 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV2i32 = urem <vscale x 2 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV4i32 = urem <vscale x 4 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %NV8i32 = urem <vscale x 8 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV16i32 = urem <vscale x 16 x i32> undef, splat (i32 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV2i16 = urem <vscale x 2 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV4i16 = urem <vscale x 4 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV8i16 = urem <vscale x 8 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %NV16i16 = urem <vscale x 16 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV32i16 = urem <vscale x 32 x i16> undef, splat (i16 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV2i8 = urem <vscale x 2 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV4i8 = urem <vscale x 4 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV8i8 = urem <vscale x 8 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:4 Lat:4 SizeLat:4 for: %NV16i8 = urem <vscale x 16 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:4 Lat:4 SizeLat:4 for: %NV32i8 = urem <vscale x 32 x i8> undef, splat (i8 16)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NV64i8 = urem <vscale x 64 x i8> undef, splat (i8 16)
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
%V2i64 = urem <2 x i64> undef, splat (i64 16)
diff --git a/llvm/test/Analysis/CostModel/RISCV/arith-int.ll b/llvm/test/Analysis/CostModel/RISCV/arith-int.ll
index 7e9a190966fb4..b2078148d7825 100644
--- a/llvm/test/Analysis/CostModel/RISCV/arith-int.ll
+++ b/llvm/test/Analysis/CostModel/RISCV/arith-int.ll
@@ -1700,3 +1700,26 @@ define i32 @xor() {
xor <vscale x 8 x i64> undef, undef
ret i32 undef
}
+
+define void @transforms() {
+; CHECK-LABEL: 'transforms'
+; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %udiv.nonpow2 = udiv i16 poison, 7
+; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %udiv.pow2 = udiv i16 poison, 8
+; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %urem.nonpow2 = urem i16 poison, 3
+; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %urem.pow2 = urem i16 poison, 4
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+; SIFIVE-X280-LABEL: 'transforms'
+; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %udiv.nonpow2 = udiv i16 poison, 7
+; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %udiv.pow2 = udiv i16 poison, 8
+; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %urem.nonpow2 = urem i16 poison, 3
+; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %urem.pow2 = urem i16 poison, 4
+; SIFIVE-X280-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+ %udiv.nonpow2 = udiv i16 poison, 7
+ %udiv.pow2 = udiv i16 poison, 8
+
+ %urem.nonpow2 = urem i16 poison, 3
+ %urem.pow2 = urem i16 poison, 4
+ ret void
+}
>From 07e89f354867f227775e738c0a387f10d23b109c Mon Sep 17 00:00:00 2001
From: bababuck <buchner.ryan at gmail.com>
Date: Tue, 14 Apr 2026 17:08:45 -0700
Subject: [PATCH 17/19] Use Combined over Converted in naming, add comment
---
.../lib/Target/RISCV/RISCVTargetTransformInfo.cpp | 15 ++++++++++-----
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h | 2 +-
2 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 312dc069c8a1a..d73b3613d1994 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2669,8 +2669,13 @@ RISCVTTIImpl::getIndexedVectorInstrCostFromEnd(unsigned Opcode, Type *Val,
nullptr);
}
+/// Check to see if this instruction is expected to be combined to a simpler
+/// operation during/before lowering. If so return the cost of the combined
+/// operation rather than provided one. For instance, `udiv i16 %X, 2` is likely
+/// to be combined to `lshr i16 %X, 1`, so return the cost of a `lshr` rather
+/// than the cost of a `udiv`
std::optional<InstructionCost>
-RISCVTTIImpl::getConvertedArithmeticInstructionCost(
+RISCVTTIImpl::getCombinedArithmeticInstructionCost(
unsigned ISDOpcode, Type *Ty, TTI::TargetCostKind CostKind,
TTI::OperandValueInfo Opd1Info, TTI::OperandValueInfo Opd2Info,
ArrayRef<const Value *> Args, const Instruction *CxtI) const {
@@ -2713,10 +2718,10 @@ InstructionCost RISCVTTIImpl::getArithmeticInstrCost(
std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(Ty);
unsigned ISDOpcode = TLI->InstructionOpcodeToISD(Opcode);
- if (std::optional<InstructionCost> ConvertedCost =
- getConvertedArithmeticInstructionCost(ISDOpcode, Ty, CostKind,
- Op1Info, Op2Info, Args, CxtI))
- return *ConvertedCost;
+ if (std::optional<InstructionCost> CombinedCost =
+ getCombinedArithmeticInstructionCost(ISDOpcode, Ty, CostKind, Op1Info,
+ Op2Info, Args, CxtI))
+ return *CombinedCost;
// TODO: Handle scalar type.
if (!LT.second.isVector()) {
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
index 88a009d3680ad..57721a8299fd9 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
@@ -224,7 +224,7 @@ class RISCVTTIImpl final : public BasicTTIImplBase<RISCVTTIImpl> {
getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty, FastMathFlags FMF,
TTI::TargetCostKind CostKind) const override;
- std::optional<InstructionCost> getConvertedArithmeticInstructionCost(
+ std::optional<InstructionCost> getCombinedArithmeticInstructionCost(
unsigned ISDOpcode, Type *Ty, TTI::TargetCostKind CostKind,
TTI::OperandValueInfo Opd1Info, TTI::OperandValueInfo Opd2Info,
ArrayRef<const Value *> Args, const Instruction *CxtI) const;
>From 87b0c97b505732ecd214c2c781ab44a09d999f9d Mon Sep 17 00:00:00 2001
From: bababuck <buchner.ryan at gmail.com>
Date: Tue, 14 Apr 2026 17:08:57 -0700
Subject: [PATCH 18/19] No else after return
---
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index d73b3613d1994..266f3017de864 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2687,10 +2687,8 @@ RISCVTTIImpl::getCombinedArithmeticInstructionCost(
Opd1Info.getNoProps(),
Opd2Info.getNoProps());
// UREM
- else
- return getArithmeticInstrCost(Instruction::And, Ty, CostKind,
- Opd1Info.getNoProps(),
- Opd2Info.getNoProps());
+ return getArithmeticInstrCost(Instruction::And, Ty, CostKind,
+ Opd1Info.getNoProps(), Opd2Info.getNoProps());
}
return std::nullopt;
}
>From f6bdf4e026371e519b0a24cc53f86940259e3cb4 Mon Sep 17 00:00:00 2001
From: Ryan Buchner <buchner.ryan at gmail.com>
Date: Fri, 17 Apr 2026 10:07:17 -0700
Subject: [PATCH 19/19] Update
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
Co-authored-by: Luke Lau <luke_lau at icloud.com>
---
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 266f3017de864..e6842d589a927 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -2684,7 +2684,7 @@ RISCVTTIImpl::getCombinedArithmeticInstructionCost(
Opd2Info.isConstant() && Opd2Info.isPowerOf2()) {
if (ISDOpcode == ISD::UDIV)
return getArithmeticInstrCost(Instruction::LShr, Ty, CostKind,
- Opd1Info.getNoProps(),
+ Opd1Info,
Opd2Info.getNoProps());
// UREM
return getArithmeticInstrCost(Instruction::And, Ty, CostKind,
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