[llvm] [LV][NFC] Regen CHECK lines in LoopVectorize/X86/replicating-load-store-costs.ll (PR #192682)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 17 08:13:28 PDT 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-transforms
Author: David Sherwood (david-arm)
<details>
<summary>Changes</summary>
---
Patch is 93.28 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/192682.diff
1 Files Affected:
- (modified) llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll (+525-525)
``````````diff
diff --git a/llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll b/llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll
index a5a4191995591..9e810203aefee 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll
@@ -7,20 +7,20 @@ define void @test_store_initially_interleave(i32 %n, ptr noalias %src) #0 {
; I64-LABEL: define void @test_store_initially_interleave(
; I64-SAME: i32 [[N:%.*]], ptr noalias [[SRC:%.*]]) #[[ATTR0:[0-9]+]] {
; I64-NEXT: [[ITER_CHECK:.*:]]
-; I64-NEXT: [[TMP4:%.*]] = add i32 [[N]], 1
-; I64-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i32 [[TMP4]], 4
+; I64-NEXT: [[TMP0:%.*]] = add i32 [[N]], 1
+; I64-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i32 [[TMP0]], 4
; I64-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
; I64: [[VECTOR_SCEVCHECK]]:
; I64-NEXT: [[TMP1:%.*]] = icmp slt i32 [[N]], 0
; I64-NEXT: br i1 [[TMP1]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VECTOR_MAIN_LOOP_ITER_CHECK:.*]]
; I64: [[VECTOR_MAIN_LOOP_ITER_CHECK]]:
-; I64-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ule i32 [[TMP4]], 16
+; I64-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ule i32 [[TMP0]], 16
; I64-NEXT: br i1 [[MIN_ITERS_CHECK1]], label %[[VEC_EPILOG_PH:.*]], label %[[VECTOR_PH:.*]]
; I64: [[VECTOR_PH]]:
-; I64-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[TMP4]], 16
+; I64-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[TMP0]], 16
; I64-NEXT: [[TMP2:%.*]] = icmp eq i32 [[N_MOD_VF]], 0
; I64-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i32 16, i32 [[N_MOD_VF]]
-; I64-NEXT: [[N_VEC:%.*]] = sub i32 [[TMP4]], [[TMP3]]
+; I64-NEXT: [[N_VEC:%.*]] = sub i32 [[TMP0]], [[TMP3]]
; I64-NEXT: br label %[[VECTOR_BODY:.*]]
; I64: [[VECTOR_BODY]]:
; I64-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
@@ -28,142 +28,142 @@ define void @test_store_initially_interleave(i32 %n, ptr noalias %src) #0 {
; I64-NEXT: [[STEP_ADD:%.*]] = add nuw <4 x i32> [[VEC_IND]], splat (i32 4)
; I64-NEXT: [[STEP_ADD_2:%.*]] = add nuw <4 x i32> [[STEP_ADD]], splat (i32 4)
; I64-NEXT: [[STEP_ADD_3:%.*]] = add nuw <4 x i32> [[STEP_ADD_2]], splat (i32 4)
-; I64-NEXT: [[TMP5:%.*]] = add i32 [[INDEX]], 1
-; I64-NEXT: [[TMP6:%.*]] = add i32 [[INDEX]], 2
-; I64-NEXT: [[TMP7:%.*]] = add i32 [[INDEX]], 3
-; I64-NEXT: [[TMP8:%.*]] = add i32 [[INDEX]], 4
-; I64-NEXT: [[TMP9:%.*]] = add i32 [[INDEX]], 5
-; I64-NEXT: [[TMP10:%.*]] = add i32 [[INDEX]], 6
-; I64-NEXT: [[TMP11:%.*]] = add i32 [[INDEX]], 7
-; I64-NEXT: [[TMP12:%.*]] = add i32 [[INDEX]], 8
-; I64-NEXT: [[TMP13:%.*]] = add i32 [[INDEX]], 9
-; I64-NEXT: [[TMP14:%.*]] = add i32 [[INDEX]], 10
-; I64-NEXT: [[TMP15:%.*]] = add i32 [[INDEX]], 11
-; I64-NEXT: [[TMP16:%.*]] = add i32 [[INDEX]], 12
-; I64-NEXT: [[TMP17:%.*]] = add i32 [[INDEX]], 13
-; I64-NEXT: [[TMP18:%.*]] = add i32 [[INDEX]], 14
-; I64-NEXT: [[TMP19:%.*]] = add i32 [[INDEX]], 15
-; I64-NEXT: [[TMP20:%.*]] = uitofp <4 x i32> [[VEC_IND]] to <4 x double>
-; I64-NEXT: [[CONV:%.*]] = extractelement <4 x double> [[TMP20]], i32 0
-; I64-NEXT: [[TMP57:%.*]] = extractelement <4 x double> [[TMP20]], i32 1
-; I64-NEXT: [[TMP58:%.*]] = extractelement <4 x double> [[TMP20]], i32 2
-; I64-NEXT: [[TMP59:%.*]] = extractelement <4 x double> [[TMP20]], i32 3
-; I64-NEXT: [[TMP21:%.*]] = uitofp <4 x i32> [[STEP_ADD]] to <4 x double>
-; I64-NEXT: [[TMP60:%.*]] = extractelement <4 x double> [[TMP21]], i32 0
-; I64-NEXT: [[TMP61:%.*]] = extractelement <4 x double> [[TMP21]], i32 1
-; I64-NEXT: [[TMP62:%.*]] = extractelement <4 x double> [[TMP21]], i32 2
-; I64-NEXT: [[TMP63:%.*]] = extractelement <4 x double> [[TMP21]], i32 3
-; I64-NEXT: [[TMP22:%.*]] = uitofp <4 x i32> [[STEP_ADD_2]] to <4 x double>
-; I64-NEXT: [[TMP64:%.*]] = extractelement <4 x double> [[TMP22]], i32 0
-; I64-NEXT: [[TMP65:%.*]] = extractelement <4 x double> [[TMP22]], i32 1
-; I64-NEXT: [[TMP66:%.*]] = extractelement <4 x double> [[TMP22]], i32 2
-; I64-NEXT: [[TMP67:%.*]] = extractelement <4 x double> [[TMP22]], i32 3
-; I64-NEXT: [[TMP23:%.*]] = uitofp <4 x i32> [[STEP_ADD_3]] to <4 x double>
-; I64-NEXT: [[TMP68:%.*]] = extractelement <4 x double> [[TMP23]], i32 0
-; I64-NEXT: [[TMP69:%.*]] = extractelement <4 x double> [[TMP23]], i32 1
-; I64-NEXT: [[TMP70:%.*]] = extractelement <4 x double> [[TMP23]], i32 2
-; I64-NEXT: [[TMP71:%.*]] = extractelement <4 x double> [[TMP23]], i32 3
-; I64-NEXT: [[ADD_PTR_I:%.*]] = getelementptr nusw { ptr, ptr, ptr }, ptr null, i32 [[INDEX]]
-; I64-NEXT: [[TMP25:%.*]] = getelementptr nusw { ptr, ptr, ptr }, ptr null, i32 [[TMP5]]
-; I64-NEXT: [[TMP26:%.*]] = getelementptr nusw { ptr, ptr, ptr }, ptr null, i32 [[TMP6]]
-; I64-NEXT: [[TMP27:%.*]] = getelementptr nusw { ptr, ptr, ptr }, ptr null, i32 [[TMP7]]
-; I64-NEXT: [[TMP28:%.*]] = getelementptr nusw { ptr, ptr, ptr }, ptr null, i32 [[TMP8]]
-; I64-NEXT: [[TMP29:%.*]] = getelementptr nusw { ptr, ptr, ptr }, ptr null, i32 [[TMP9]]
-; I64-NEXT: [[TMP30:%.*]] = getelementptr nusw { ptr, ptr, ptr }, ptr null, i32 [[TMP10]]
-; I64-NEXT: [[TMP31:%.*]] = getelementptr nusw { ptr, ptr, ptr }, ptr null, i32 [[TMP11]]
-; I64-NEXT: [[TMP32:%.*]] = getelementptr nusw { ptr, ptr, ptr }, ptr null, i32 [[TMP12]]
-; I64-NEXT: [[TMP33:%.*]] = getelementptr nusw { ptr, ptr, ptr }, ptr null, i32 [[TMP13]]
-; I64-NEXT: [[TMP34:%.*]] = getelementptr nusw { ptr, ptr, ptr }, ptr null, i32 [[TMP14]]
-; I64-NEXT: [[TMP35:%.*]] = getelementptr nusw { ptr, ptr, ptr }, ptr null, i32 [[TMP15]]
-; I64-NEXT: [[TMP36:%.*]] = getelementptr nusw { ptr, ptr, ptr }, ptr null, i32 [[TMP16]]
-; I64-NEXT: [[TMP37:%.*]] = getelementptr nusw { ptr, ptr, ptr }, ptr null, i32 [[TMP17]]
-; I64-NEXT: [[TMP38:%.*]] = getelementptr nusw { ptr, ptr, ptr }, ptr null, i32 [[TMP18]]
-; I64-NEXT: [[TMP39:%.*]] = getelementptr nusw { ptr, ptr, ptr }, ptr null, i32 [[TMP19]]
-; I64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ADD_PTR_I]], align 4
-; I64-NEXT: [[TMP41:%.*]] = load ptr, ptr [[TMP25]], align 4
-; I64-NEXT: [[TMP42:%.*]] = load ptr, ptr [[TMP26]], align 4
-; I64-NEXT: [[TMP43:%.*]] = load ptr, ptr [[TMP27]], align 4
-; I64-NEXT: [[TMP44:%.*]] = load ptr, ptr [[TMP28]], align 4
-; I64-NEXT: [[TMP45:%.*]] = load ptr, ptr [[TMP29]], align 4
-; I64-NEXT: [[TMP46:%.*]] = load ptr, ptr [[TMP30]], align 4
-; I64-NEXT: [[TMP47:%.*]] = load ptr, ptr [[TMP31]], align 4
-; I64-NEXT: [[TMP48:%.*]] = load ptr, ptr [[TMP32]], align 4
-; I64-NEXT: [[TMP49:%.*]] = load ptr, ptr [[TMP33]], align 4
-; I64-NEXT: [[TMP50:%.*]] = load ptr, ptr [[TMP34]], align 4
-; I64-NEXT: [[TMP51:%.*]] = load ptr, ptr [[TMP35]], align 4
-; I64-NEXT: [[TMP52:%.*]] = load ptr, ptr [[TMP36]], align 4
-; I64-NEXT: [[TMP53:%.*]] = load ptr, ptr [[TMP37]], align 4
-; I64-NEXT: [[TMP54:%.*]] = load ptr, ptr [[TMP38]], align 4
+; I64-NEXT: [[TMP4:%.*]] = add i32 [[INDEX]], 1
+; I64-NEXT: [[TMP5:%.*]] = add i32 [[INDEX]], 2
+; I64-NEXT: [[TMP6:%.*]] = add i32 [[INDEX]], 3
+; I64-NEXT: [[TMP7:%.*]] = add i32 [[INDEX]], 4
+; I64-NEXT: [[TMP8:%.*]] = add i32 [[INDEX]], 5
+; I64-NEXT: [[TMP9:%.*]] = add i32 [[INDEX]], 6
+; I64-NEXT: [[TMP10:%.*]] = add i32 [[INDEX]], 7
+; I64-NEXT: [[TMP11:%.*]] = add i32 [[INDEX]], 8
+; I64-NEXT: [[TMP12:%.*]] = add i32 [[INDEX]], 9
+; I64-NEXT: [[TMP13:%.*]] = add i32 [[INDEX]], 10
+; I64-NEXT: [[TMP14:%.*]] = add i32 [[INDEX]], 11
+; I64-NEXT: [[TMP15:%.*]] = add i32 [[INDEX]], 12
+; I64-NEXT: [[TMP16:%.*]] = add i32 [[INDEX]], 13
+; I64-NEXT: [[TMP17:%.*]] = add i32 [[INDEX]], 14
+; I64-NEXT: [[TMP18:%.*]] = add i32 [[INDEX]], 15
+; I64-NEXT: [[TMP19:%.*]] = uitofp <4 x i32> [[VEC_IND]] to <4 x double>
+; I64-NEXT: [[TMP20:%.*]] = extractelement <4 x double> [[TMP19]], i32 0
+; I64-NEXT: [[TMP21:%.*]] = extractelement <4 x double> [[TMP19]], i32 1
+; I64-NEXT: [[TMP22:%.*]] = extractelement <4 x double> [[TMP19]], i32 2
+; I64-NEXT: [[TMP23:%.*]] = extractelement <4 x double> [[TMP19]], i32 3
+; I64-NEXT: [[TMP24:%.*]] = uitofp <4 x i32> [[STEP_ADD]] to <4 x double>
+; I64-NEXT: [[TMP25:%.*]] = extractelement <4 x double> [[TMP24]], i32 0
+; I64-NEXT: [[TMP26:%.*]] = extractelement <4 x double> [[TMP24]], i32 1
+; I64-NEXT: [[TMP27:%.*]] = extractelement <4 x double> [[TMP24]], i32 2
+; I64-NEXT: [[TMP28:%.*]] = extractelement <4 x double> [[TMP24]], i32 3
+; I64-NEXT: [[TMP29:%.*]] = uitofp <4 x i32> [[STEP_ADD_2]] to <4 x double>
+; I64-NEXT: [[TMP30:%.*]] = extractelement <4 x double> [[TMP29]], i32 0
+; I64-NEXT: [[TMP31:%.*]] = extractelement <4 x double> [[TMP29]], i32 1
+; I64-NEXT: [[TMP32:%.*]] = extractelement <4 x double> [[TMP29]], i32 2
+; I64-NEXT: [[TMP33:%.*]] = extractelement <4 x double> [[TMP29]], i32 3
+; I64-NEXT: [[TMP34:%.*]] = uitofp <4 x i32> [[STEP_ADD_3]] to <4 x double>
+; I64-NEXT: [[TMP35:%.*]] = extractelement <4 x double> [[TMP34]], i32 0
+; I64-NEXT: [[TMP36:%.*]] = extractelement <4 x double> [[TMP34]], i32 1
+; I64-NEXT: [[TMP37:%.*]] = extractelement <4 x double> [[TMP34]], i32 2
+; I64-NEXT: [[TMP38:%.*]] = extractelement <4 x double> [[TMP34]], i32 3
+; I64-NEXT: [[TMP39:%.*]] = getelementptr nusw { ptr, ptr, ptr }, ptr null, i32 [[INDEX]]
+; I64-NEXT: [[TMP40:%.*]] = getelementptr nusw { ptr, ptr, ptr }, ptr null, i32 [[TMP4]]
+; I64-NEXT: [[TMP41:%.*]] = getelementptr nusw { ptr, ptr, ptr }, ptr null, i32 [[TMP5]]
+; I64-NEXT: [[TMP42:%.*]] = getelementptr nusw { ptr, ptr, ptr }, ptr null, i32 [[TMP6]]
+; I64-NEXT: [[TMP43:%.*]] = getelementptr nusw { ptr, ptr, ptr }, ptr null, i32 [[TMP7]]
+; I64-NEXT: [[TMP44:%.*]] = getelementptr nusw { ptr, ptr, ptr }, ptr null, i32 [[TMP8]]
+; I64-NEXT: [[TMP45:%.*]] = getelementptr nusw { ptr, ptr, ptr }, ptr null, i32 [[TMP9]]
+; I64-NEXT: [[TMP46:%.*]] = getelementptr nusw { ptr, ptr, ptr }, ptr null, i32 [[TMP10]]
+; I64-NEXT: [[TMP47:%.*]] = getelementptr nusw { ptr, ptr, ptr }, ptr null, i32 [[TMP11]]
+; I64-NEXT: [[TMP48:%.*]] = getelementptr nusw { ptr, ptr, ptr }, ptr null, i32 [[TMP12]]
+; I64-NEXT: [[TMP49:%.*]] = getelementptr nusw { ptr, ptr, ptr }, ptr null, i32 [[TMP13]]
+; I64-NEXT: [[TMP50:%.*]] = getelementptr nusw { ptr, ptr, ptr }, ptr null, i32 [[TMP14]]
+; I64-NEXT: [[TMP51:%.*]] = getelementptr nusw { ptr, ptr, ptr }, ptr null, i32 [[TMP15]]
+; I64-NEXT: [[TMP52:%.*]] = getelementptr nusw { ptr, ptr, ptr }, ptr null, i32 [[TMP16]]
+; I64-NEXT: [[TMP53:%.*]] = getelementptr nusw { ptr, ptr, ptr }, ptr null, i32 [[TMP17]]
+; I64-NEXT: [[TMP54:%.*]] = getelementptr nusw { ptr, ptr, ptr }, ptr null, i32 [[TMP18]]
; I64-NEXT: [[TMP55:%.*]] = load ptr, ptr [[TMP39]], align 4
-; I64-NEXT: store double [[CONV]], ptr [[TMP0]], align 4
-; I64-NEXT: store double [[TMP57]], ptr [[TMP41]], align 4
-; I64-NEXT: store double [[TMP58]], ptr [[TMP42]], align 4
-; I64-NEXT: store double [[TMP59]], ptr [[TMP43]], align 4
-; I64-NEXT: store double [[TMP60]], ptr [[TMP44]], align 4
-; I64-NEXT: store double [[TMP61]], ptr [[TMP45]], align 4
-; I64-NEXT: store double [[TMP62]], ptr [[TMP46]], align 4
-; I64-NEXT: store double [[TMP63]], ptr [[TMP47]], align 4
-; I64-NEXT: store double [[TMP64]], ptr [[TMP48]], align 4
-; I64-NEXT: store double [[TMP65]], ptr [[TMP49]], align 4
-; I64-NEXT: store double [[TMP66]], ptr [[TMP50]], align 4
-; I64-NEXT: store double [[TMP67]], ptr [[TMP51]], align 4
-; I64-NEXT: store double [[TMP68]], ptr [[TMP52]], align 4
-; I64-NEXT: store double [[TMP69]], ptr [[TMP53]], align 4
-; I64-NEXT: store double [[TMP70]], ptr [[TMP54]], align 4
-; I64-NEXT: store double [[TMP71]], ptr [[TMP55]], align 4
+; I64-NEXT: [[TMP56:%.*]] = load ptr, ptr [[TMP40]], align 4
+; I64-NEXT: [[TMP57:%.*]] = load ptr, ptr [[TMP41]], align 4
+; I64-NEXT: [[TMP58:%.*]] = load ptr, ptr [[TMP42]], align 4
+; I64-NEXT: [[TMP59:%.*]] = load ptr, ptr [[TMP43]], align 4
+; I64-NEXT: [[TMP60:%.*]] = load ptr, ptr [[TMP44]], align 4
+; I64-NEXT: [[TMP61:%.*]] = load ptr, ptr [[TMP45]], align 4
+; I64-NEXT: [[TMP62:%.*]] = load ptr, ptr [[TMP46]], align 4
+; I64-NEXT: [[TMP63:%.*]] = load ptr, ptr [[TMP47]], align 4
+; I64-NEXT: [[TMP64:%.*]] = load ptr, ptr [[TMP48]], align 4
+; I64-NEXT: [[TMP65:%.*]] = load ptr, ptr [[TMP49]], align 4
+; I64-NEXT: [[TMP66:%.*]] = load ptr, ptr [[TMP50]], align 4
+; I64-NEXT: [[TMP67:%.*]] = load ptr, ptr [[TMP51]], align 4
+; I64-NEXT: [[TMP68:%.*]] = load ptr, ptr [[TMP52]], align 4
+; I64-NEXT: [[TMP69:%.*]] = load ptr, ptr [[TMP53]], align 4
+; I64-NEXT: [[TMP70:%.*]] = load ptr, ptr [[TMP54]], align 4
+; I64-NEXT: store double [[TMP20]], ptr [[TMP55]], align 4
+; I64-NEXT: store double [[TMP21]], ptr [[TMP56]], align 4
+; I64-NEXT: store double [[TMP22]], ptr [[TMP57]], align 4
+; I64-NEXT: store double [[TMP23]], ptr [[TMP58]], align 4
+; I64-NEXT: store double [[TMP25]], ptr [[TMP59]], align 4
+; I64-NEXT: store double [[TMP26]], ptr [[TMP60]], align 4
+; I64-NEXT: store double [[TMP27]], ptr [[TMP61]], align 4
+; I64-NEXT: store double [[TMP28]], ptr [[TMP62]], align 4
+; I64-NEXT: store double [[TMP30]], ptr [[TMP63]], align 4
+; I64-NEXT: store double [[TMP31]], ptr [[TMP64]], align 4
+; I64-NEXT: store double [[TMP32]], ptr [[TMP65]], align 4
+; I64-NEXT: store double [[TMP33]], ptr [[TMP66]], align 4
+; I64-NEXT: store double [[TMP35]], ptr [[TMP67]], align 4
+; I64-NEXT: store double [[TMP36]], ptr [[TMP68]], align 4
+; I64-NEXT: store double [[TMP37]], ptr [[TMP69]], align 4
+; I64-NEXT: store double [[TMP38]], ptr [[TMP70]], align 4
; I64-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 16
; I64-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[STEP_ADD_3]], splat (i32 4)
-; I64-NEXT: [[TMP72:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
-; I64-NEXT: br i1 [[TMP72]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; I64-NEXT: [[TMP71:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
+; I64-NEXT: br i1 [[TMP71]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; I64: [[MIDDLE_BLOCK]]:
; I64-NEXT: br label %[[VEC_EPILOG_ITER_CHECK:.*]]
; I64: [[VEC_EPILOG_ITER_CHECK]]:
; I64-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ule i32 [[TMP3]], 4
; I64-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VEC_EPILOG_PH]], !prof [[PROF3:![0-9]+]]
; I64: [[VEC_EPILOG_PH]]:
-; I64-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_MAIN_LOOP_ITER_CHECK]] ]
-; I64-NEXT: [[N_MOD_VF2:%.*]] = urem i32 [[TMP4]], 4
-; I64-NEXT: [[TMP73:%.*]] = icmp eq i32 [[N_MOD_VF2]], 0
-; I64-NEXT: [[TMP74:%.*]] = select i1 [[TMP73]], i32 4, i32 [[N_MOD_VF2]]
-; I64-NEXT: [[N_VEC3:%.*]] = sub i32 [[TMP4]], [[TMP74]]
-; I64-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[BC_RESUME_VAL]], i64 0
+; I64-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_MAIN_LOOP_ITER_CHECK]] ]
+; I64-NEXT: [[N_MOD_VF2:%.*]] = urem i32 [[TMP0]], 4
+; I64-NEXT: [[TMP72:%.*]] = icmp eq i32 [[N_MOD_VF2]], 0
+; I64-NEXT: [[TMP73:%.*]] = select i1 [[TMP72]], i32 4, i32 [[N_MOD_VF2]]
+; I64-NEXT: [[N_VEC3:%.*]] = sub i32 [[TMP0]], [[TMP73]]
+; I64-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[VEC_EPILOG_RESUME_VAL]], i64 0
; I64-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer
; I64-NEXT: [[INDUCTION:%.*]] = add <4 x i32> [[BROADCAST_SPLAT]], <i32 0, i32 1, i32 2, i32 3>
; I64-NEXT: br label %[[VEC_EPILOG_VECTOR_BODY:.*]]
; I64: [[VEC_EPILOG_VECTOR_BODY]]:
-; I64-NEXT: [[INDEX4:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT6:%.*]], %[[VEC_EPILOG_VECTOR_BODY]] ]
+; I64-NEXT: [[INDEX4:%.*]] = phi i32 [ [[VEC_EPILOG_RESUME_VAL]], %[[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT6:%.*]], %[[VEC_EPILOG_VECTOR_BODY]] ]
; I64-NEXT: [[VEC_IND5:%.*]] = phi <4 x i32> [ [[INDUCTION]], %[[VEC_EPILOG_PH]] ], [ [[VEC_IND_NEXT7:%.*]], %[[VEC_EPILOG_VECTOR_BODY]] ]
-; I64-NEXT: [[TMP76:%.*]] = add i32 [[INDEX4]], 1
-; I64-NEXT: [[TMP77:%.*]] = add i32 [[INDEX4]], 2
-; I64-NEXT: [[TMP78:%.*]] = add i32 [[INDEX4]], 3
-; I64-NEXT: [[TMP79:%.*]] = uitofp <4 x i32> [[VEC_IND5]] to <4 x double>
-; I64-NEXT: [[TMP88:%.*]] = extractelement <4 x double> [[TMP79]], i32 0
-; I64-NEXT: [[TMP89:%.*]] = extractelement <4 x double> [[TMP79]], i32 1
-; I64-NEXT: [[TMP90:%.*]] = extractelement <4 x double> [[TMP79]], i32 2
-; I64-NEXT: [[TMP91:%.*]] = extractelement <4 x double> [[TMP79]], i32 3
-; I64-NEXT: [[TMP84:%.*]] = getelementptr nusw { ptr, ptr, ptr }, ptr null, i32 [[INDEX4]]
+; I64-NEXT: [[TMP74:%.*]] = add i32 [[INDEX4]], 1
+; I64-NEXT: [[TMP75:%.*]] = add i32 [[INDEX4]], 2
+; I64-NEXT: [[TMP76:%.*]] = add i32 [[INDEX4]], 3
+; I64-NEXT: [[TMP77:%.*]] = uitofp <4 x i32> [[VEC_IND5]] to <4 x double>
+; I64-NEXT: [[TMP78:%.*]] = extractelement <4 x double> [[TMP77]], i32 0
+; I64-NEXT: [[TMP79:%.*]] = extractelement <4 x double> [[TMP77]], i32 1
+; I64-NEXT: [[TMP80:%.*]] = extractelement <4 x double> [[TMP77]], i32 2
+; I64-NEXT: [[TMP81:%.*]] = extractelement <4 x double> [[TMP77]], i32 3
+; I64-NEXT: [[TMP82:%.*]] = getelementptr nusw { ptr, ptr, ptr }, ptr null, i32 [[INDEX4]]
+; I64-NEXT: [[TMP83:%.*]] = getelementptr nusw { ptr, ptr, ptr }, ptr null, i32 [[TMP74]]
+; I64-NEXT: [[TMP84:%.*]] = getelementptr nusw { ptr, ptr, ptr }, ptr null, i32 [[TMP75]]
; I64-NEXT: [[TMP85:%.*]] = getelementptr nusw { ptr, ptr, ptr }, ptr null, i32 [[TMP76]]
-; I64-NEXT: [[TMP86:%.*]] = getelementptr nusw { ptr, ptr, ptr }, ptr null, i32 [[TMP77]]
-; I64-NEXT: [[TMP93:%.*]] = getelementptr nusw { ptr, ptr, ptr }, ptr null, i32 [[TMP78]]
-; I64-NEXT: [[TMP94:%.*]] = load ptr, ptr [[TMP84]], align 4
-; I64-NEXT: [[TMP95:%.*]] = load ptr, ptr [[TMP85]], align 4
-; I64-NEXT: [[TMP96:%.*]] = load ptr, ptr [[TMP86]], align 4
-; I64-NEXT: [[TMP87:%.*]] = load ptr, ptr [[TMP93]], align 4
-; I64-NEXT: store double [[TMP88]], ptr [[TMP94]], align 4
-; I64-NEXT: store double [[TMP89]], ptr [[TMP95]], align 4
-; I64-NEXT: store double [[TMP90]], ptr [[TMP96]], align 4
-; I64-NEXT: store double [[TMP91]], ptr [[TMP87]], align 4
+; I64-NEXT: [[TMP86:%.*]] = load ptr, ptr [[TMP82]], align 4
+; I64-NEXT: [[TMP87:%.*]] = load ptr, ptr [[TMP83]], align 4
+; I64-NEXT: [[TMP88:%.*]] = load ptr, ptr [[TMP84]], align 4
+; I64-NEXT: [[TMP89:%.*]] = load ptr, ptr [[TMP85]], align 4
+; I64-NEXT: store double [[TMP78]], ptr [[TMP86]], align 4
+; I64-NEXT: store double [[TMP79]], ptr [[TMP87]], align 4
+; I64-NEXT: store double [[TMP80]], ptr [[TMP88]], align 4
+; I64-NEXT: store double [[TMP81]], ptr [[TMP89]], align 4
; I64-NEXT: [[INDEX_NEXT6]] = add nuw i32 [[INDEX4]], 4
; I64-NEXT: [[VEC_IND_NEXT7]] = add <4 x i32> [[VEC_IND5]], splat (i32 4)
-; I64-NEXT: [[TMP92:%.*]] = icmp eq i32 [[INDEX_NEXT6]], [[N_VEC3]]
-; I64-NEXT: br i1 [[TMP92]], label %[[VEC_EPILOG_MIDDLE_BLOCK:.*]], label %[[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
+; I64-NEXT: [[TMP90:%.*]] = icmp eq i32 [[INDEX_NEXT6]], [[N_VEC3]]
+; I64-NEXT: br i1 [[TMP90]], label %[[VEC_EPILOG_MIDDLE_BLOCK:.*]], label %[[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
; I64: [[VEC_EPILOG_MIDDLE_BLOCK]]:
; I64-NEXT: br label %[[VEC_EPILOG_SCALAR_PH]]
; I64: [[VEC_EPILOG_SCALAR_PH]]:
;
; I32-LABEL: define void @test_store_initially_interleave(
; I32-SAME: i32 [[N:%.*]], ptr noalias [[SRC:%.*]]) #[[ATTR0:[0-9]+]] {
-; I32-NEXT: [[ENTRY:.*:]]
+; I32-NEXT: [[ITER_CHECK:.*:]]
; I32-NEXT: [[TMP0:%.*]] = add i32 [[N]], 1
; I32-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i3...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/192682
More information about the llvm-commits
mailing list