[llvm] [RISCV] Add zero-store merging and load-from-store promotion (PR #192662)

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git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp --diff_from_common_commit
``````````

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``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
index b4bd30743..5e1f44bb4 100644
--- a/llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
@@ -73,7 +73,8 @@ static bool isPromotableLoadFromStore(const MachineInstr &MI) {
   }
 }
 
-static std::optional<unsigned> getMatchingWideOpcode(unsigned Opc, bool IsRV64) {
+static std::optional<unsigned> getMatchingWideOpcode(unsigned Opc,
+                                                     bool IsRV64) {
   switch (Opc) {
   default:
     return std::nullopt;
@@ -242,8 +243,7 @@ bool RISCVLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
         }
 
         // Try zero store merging
-        if (isPromotableZeroStoreInst(*MBBI) &&
-            tryToMergeZeroStInst(MBBI)) {
+        if (isPromotableZeroStoreInst(*MBBI) && tryToMergeZeroStInst(MBBI)) {
           MadeChange = true;
           continue;
         }
@@ -767,8 +767,8 @@ RISCVLoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
       IsCandidate = IsPromotableZeroStore && isPromotableZeroStoreInst(MI) &&
                     MI.getOpcode() == FirstMI.getOpcode();
     } else {
-      IsCandidate =
-          MI.getOpcode() == FirstMI.getOpcode() && TII->isLdStSafeToPair(MI, TRI);
+      IsCandidate = MI.getOpcode() == FirstMI.getOpcode() &&
+                    TII->isLdStSafeToPair(MI, TRI);
     }
 
     if (IsCandidate) {
@@ -783,8 +783,7 @@ RISCVLoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
 
       Register MIBaseReg = MI.getOperand(1).getReg();
       int64_t MIOffset = MI.getOperand(2).getImm();
-      int64_t MIOffsetStride =
-          FindNarrowMerge ? getMemScale(MI) : OffsetStride;
+      int64_t MIOffsetStride = FindNarrowMerge ? getMemScale(MI) : OffsetStride;
 
       if (BaseReg == MIBaseReg) {
         // For narrow merges, check if offsets are adjacent
@@ -873,9 +872,10 @@ RISCVLoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
 }
 
 // Merge two adjacent zero stores into a single wider store.
-MachineBasicBlock::iterator RISCVLoadStoreOpt::mergeNarrowZeroStores(
-    MachineBasicBlock::iterator I, MachineBasicBlock::iterator MergeMI,
-    bool MergeForward) {
+MachineBasicBlock::iterator
+RISCVLoadStoreOpt::mergeNarrowZeroStores(MachineBasicBlock::iterator I,
+                                         MachineBasicBlock::iterator MergeMI,
+                                         bool MergeForward) {
   assert(isPromotableZeroStoreInst(*I) && isPromotableZeroStoreInst(*MergeMI) &&
          "Expected promotable zero stores.");
 
@@ -908,9 +908,10 @@ MachineBasicBlock::iterator RISCVLoadStoreOpt::mergeNarrowZeroStores(
   int64_t OffsetImm = std::min(IOffset, MIOffset);
 
   // Get the wider opcode
-  std::optional<unsigned> NewOpcodeOpt = getMatchingWideOpcode(Opc, STI->is64Bit());
+  std::optional<unsigned> NewOpcodeOpt =
+      getMatchingWideOpcode(Opc, STI->is64Bit());
   if (!NewOpcodeOpt)
-    return NextI;  // Can't widen this instruction
+    return NextI; // Can't widen this instruction
 
   unsigned NewOpcode = *NewOpcodeOpt;
 
@@ -941,9 +942,9 @@ MachineBasicBlock::iterator RISCVLoadStoreOpt::mergeNarrowZeroStores(
 
 // Find a store instruction that writes to the address from which the current
 // load instruction reads. Return true if one is found.
-bool RISCVLoadStoreOpt::findMatchingStore(
-    MachineBasicBlock::iterator I, unsigned Limit,
-    MachineBasicBlock::iterator &StoreI) {
+bool RISCVLoadStoreOpt::findMatchingStore(MachineBasicBlock::iterator I,
+                                          unsigned Limit,
+                                          MachineBasicBlock::iterator &StoreI) {
   MachineBasicBlock::iterator B = I->getParent()->begin();
   MachineBasicBlock::iterator MBBI = I;
   MachineInstr &LoadMI = *I;
@@ -1013,8 +1014,9 @@ bool RISCVLoadStoreOpt::findMatchingStore(
 
 // Promote load from store: replace a load with a register copy or bit
 // extraction when the load reads from a location that was just stored.
-MachineBasicBlock::iterator RISCVLoadStoreOpt::promoteLoadFromStore(
-    MachineBasicBlock::iterator LoadI, MachineBasicBlock::iterator StoreI) {
+MachineBasicBlock::iterator
+RISCVLoadStoreOpt::promoteLoadFromStore(MachineBasicBlock::iterator LoadI,
+                                        MachineBasicBlock::iterator StoreI) {
   MachineBasicBlock::iterator NextI =
       next_nodbg(LoadI, LoadI->getParent()->end());
 
@@ -1054,7 +1056,9 @@ MachineBasicBlock::iterator RISCVLoadStoreOpt::promoteLoadFromStore(
 
     // If we need to shift, skip this optimization (would require temp register)
     if (ShiftAmount != 0) {
-      LLVM_DEBUG(dbgs() << "  Skipping promotion: would need temporary register for shift\n");
+      LLVM_DEBUG(
+          dbgs()
+          << "  Skipping promotion: would need temporary register for shift\n");
       return NextI;
     }
 
@@ -1070,13 +1074,11 @@ MachineBasicBlock::iterator RISCVLoadStoreOpt::promoteLoadFromStore(
     case RISCV::LHU:
       // Zero-extend halfword: use SLLI + SRLI
       BuildMI(*LoadI->getParent(), LoadI, LoadI->getDebugLoc(),
-              TII->get(STI->is64Bit() ? RISCV::SLLI : RISCV::SLLI),
-              LdRt)
+              TII->get(STI->is64Bit() ? RISCV::SLLI : RISCV::SLLI), LdRt)
           .addReg(StRt)
           .addImm(STI->is64Bit() ? 48 : 16);
       BuildMI(*LoadI->getParent(), LoadI, LoadI->getDebugLoc(),
-              TII->get(STI->is64Bit() ? RISCV::SRLI : RISCV::SRLI),
-              LdRt)
+              TII->get(STI->is64Bit() ? RISCV::SRLI : RISCV::SRLI), LdRt)
           .addReg(LdRt)
           .addImm(STI->is64Bit() ? 48 : 16);
       break;
@@ -1085,13 +1087,11 @@ MachineBasicBlock::iterator RISCVLoadStoreOpt::promoteLoadFromStore(
       // Sign-extending loads: use SLLI + SRAI
       int ShiftBits = (STI->is64Bit() ? 64 : 32) - (LoadSize * 8);
       BuildMI(*LoadI->getParent(), LoadI, LoadI->getDebugLoc(),
-              TII->get(STI->is64Bit() ? RISCV::SLLI : RISCV::SLLI),
-              LdRt)
+              TII->get(STI->is64Bit() ? RISCV::SLLI : RISCV::SLLI), LdRt)
           .addReg(StRt)
           .addImm(ShiftBits);
       BuildMI(*LoadI->getParent(), LoadI, LoadI->getDebugLoc(),
-              TII->get(STI->is64Bit() ? RISCV::SRAI : RISCV::SRAI),
-              LdRt)
+              TII->get(STI->is64Bit() ? RISCV::SRAI : RISCV::SRAI), LdRt)
           .addReg(LdRt)
           .addImm(ShiftBits);
       break;

``````````

</details>


https://github.com/llvm/llvm-project/pull/192662