[llvm] [AArch64] Add C1-Premium scheduling model (PR #185398)
Asher Dobrescu via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 17 04:25:53 PDT 2026
================
@@ -0,0 +1,2523 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=c1-premium -instruction-tables < %p/../Inputs/basic-instructions.s | FileCheck %s
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.13 add w2, w3, #4095
+# CHECK-NEXT: 1 1 0.13 add w30, w29, #1, lsl #12
+# CHECK-NEXT: 1 1 0.13 add w13, w5, #4095, lsl #12
+# CHECK-NEXT: 1 1 0.13 add x5, x7, #1638
+# CHECK-NEXT: 1 1 0.13 add w20, wsp, #801
+# CHECK-NEXT: 1 1 0.13 add wsp, wsp, #1104
+# CHECK-NEXT: 1 1 0.13 add wsp, w30, #4084
+# CHECK-NEXT: 1 1 0.13 add x0, x24, #291
+# CHECK-NEXT: 1 1 0.13 add x3, x24, #4095, lsl #12
+# CHECK-NEXT: 1 1 0.13 add x8, sp, #1074
+# CHECK-NEXT: 1 1 0.13 add sp, x29, #3816
+# CHECK-NEXT: 1 1 0.13 sub w0, wsp, #4077
+# CHECK-NEXT: 1 1 0.13 sub w4, w20, #546, lsl #12
+# CHECK-NEXT: 1 1 0.13 sub sp, sp, #288
+# CHECK-NEXT: 1 1 0.13 sub wsp, w19, #16
+# CHECK-NEXT: 1 1 0.25 adds w13, w23, #291, lsl #12
+# CHECK-NEXT: 1 1 0.25 cmn w2, #4095
+# CHECK-NEXT: 1 1 0.25 adds w20, wsp, #0
+# CHECK-NEXT: 1 1 0.25 cmn x3, #1, lsl #12
+# CHECK-NEXT: 1 1 0.25 cmp wsp, #2342
+# CHECK-NEXT: 1 1 0.25 cmp sp, #20, lsl #12
+# CHECK-NEXT: 1 1 0.25 cmp x30, #4095
+# CHECK-NEXT: 1 1 0.25 subs x4, sp, #3822
+# CHECK-NEXT: 1 1 0.25 cmn w3, #291, lsl #12
+# CHECK-NEXT: 1 1 0.25 cmn wsp, #1365
+# CHECK-NEXT: 1 1 0.25 cmn sp, #1092, lsl #12
+# CHECK-NEXT: 1 1 0.13 mov x10, #-63432
+# CHECK-NEXT: 1 1 0.13 add wsp, wsp, w10
+# CHECK-NEXT: 1 2 0.13 add x25, x9, w25, uxtb
+# CHECK-NEXT: 1 1 0.13 add w3, w5, w7
+# CHECK-NEXT: 1 1 0.13 add wzr, w3, w5
+# CHECK-NEXT: 1 1 0.13 add w20, wzr, w4
+# CHECK-NEXT: 1 1 0.13 add w4, w6, wzr
+# CHECK-NEXT: 1 1 0.13 add w11, w13, w15
+# CHECK-NEXT: 1 1 0.13 add w9, w3, wzr, lsl #1
+# CHECK-NEXT: 1 2 0.13 add w17, w29, w20, lsl #31
+# CHECK-NEXT: 1 2 0.13 add w21, w22, w23, lsr #0
+# CHECK-NEXT: 1 2 0.13 add w24, w25, w26, lsr #18
+# CHECK-NEXT: 1 2 0.13 add w27, w28, w29, lsr #31
+# CHECK-NEXT: 1 2 0.13 add w2, w3, w4, asr #0
+# CHECK-NEXT: 1 2 0.13 add w5, w6, w7, asr #21
+# CHECK-NEXT: 1 2 0.13 add w8, w9, w10, asr #31
+# CHECK-NEXT: 1 1 0.13 add x3, x5, x7
+# CHECK-NEXT: 1 1 0.13 add xzr, x3, x5
+# CHECK-NEXT: 1 1 0.13 add x20, xzr, x4
+# CHECK-NEXT: 1 1 0.13 add x4, x6, xzr
+# CHECK-NEXT: 1 1 0.13 add x11, x13, x15
+# CHECK-NEXT: 1 2 0.13 add x9, x3, xzr, lsl #10
+# CHECK-NEXT: 1 1 0.13 add x17, x29, x20, lsl #3
+# CHECK-NEXT: 1 2 0.13 add x21, x22, x23, lsr #0
+# CHECK-NEXT: 1 2 0.13 add x24, x25, x26, lsr #18
+# CHECK-NEXT: 1 2 0.13 add x27, x28, x29, lsr #63
+# CHECK-NEXT: 1 2 0.13 add x2, x3, x4, asr #0
+# CHECK-NEXT: 1 2 0.13 add x5, x6, x7, asr #21
+# CHECK-NEXT: 1 2 0.13 add x8, x9, x10, asr #63
+# CHECK-NEXT: 1 1 0.25 adds w3, w5, w7
+# CHECK-NEXT: 1 2 0.25 adds w17, wsp, w25
+# CHECK-NEXT: 1 2 0.25 adds x13, x23, w8, uxtb
+# CHECK-NEXT: 1 1 0.25 cmn w3, w5
+# CHECK-NEXT: 1 1 0.25 adds w20, wzr, w4
+# CHECK-NEXT: 1 1 0.25 adds w4, w6, wzr
+# CHECK-NEXT: 1 1 0.25 adds w11, w13, w15
+# CHECK-NEXT: 1 1 0.25 adds w9, w3, wzr, lsl #1
+# CHECK-NEXT: 1 2 0.25 adds w17, w29, w20, lsl #31
+# CHECK-NEXT: 1 2 0.25 adds w21, w22, w23, lsr #0
+# CHECK-NEXT: 1 2 0.25 adds w24, w25, w26, lsr #18
+# CHECK-NEXT: 1 2 0.25 adds w27, w28, w29, lsr #31
+# CHECK-NEXT: 1 2 0.25 adds w2, w3, w4, asr #0
+# CHECK-NEXT: 1 2 0.25 adds w5, w6, w7, asr #21
+# CHECK-NEXT: 1 2 0.25 adds w8, w9, w10, asr #31
+# CHECK-NEXT: 1 1 0.25 adds x3, x5, x7
+# CHECK-NEXT: 1 1 0.25 cmn x3, x5
+# CHECK-NEXT: 1 1 0.25 adds x20, xzr, x4
+# CHECK-NEXT: 1 1 0.25 adds x4, x6, xzr
+# CHECK-NEXT: 1 1 0.25 adds x11, x13, x15
+# CHECK-NEXT: 1 2 0.25 adds x9, x3, xzr, lsl #10
+# CHECK-NEXT: 1 1 0.25 adds x17, x29, x20, lsl #3
+# CHECK-NEXT: 1 2 0.25 adds x21, x22, x23, lsr #0
+# CHECK-NEXT: 1 2 0.25 adds x24, x25, x26, lsr #18
+# CHECK-NEXT: 1 2 0.25 adds x27, x28, x29, lsr #63
+# CHECK-NEXT: 1 2 0.25 adds x2, x3, x4, asr #0
+# CHECK-NEXT: 1 2 0.25 adds x5, x6, x7, asr #21
+# CHECK-NEXT: 1 2 0.25 adds x8, x9, x10, asr #63
+# CHECK-NEXT: 1 1 0.13 sub w3, w5, w7
+# CHECK-NEXT: 1 1 0.13 sub wzr, w3, w5
+# CHECK-NEXT: 1 1 0.13 sub w4, w6, wzr
+# CHECK-NEXT: 1 1 0.13 sub w11, w13, w15
+# CHECK-NEXT: 1 1 0.13 sub w9, w3, wzr, lsl #1
+# CHECK-NEXT: 1 2 0.13 sub w17, w29, w20, lsl #31
+# CHECK-NEXT: 1 2 0.13 sub w21, w22, w23, lsr #0
+# CHECK-NEXT: 1 2 0.13 sub w24, w25, w26, lsr #18
+# CHECK-NEXT: 1 2 0.13 sub w27, w28, w29, lsr #31
+# CHECK-NEXT: 1 2 0.13 sub w2, w3, w4, asr #0
+# CHECK-NEXT: 1 2 0.13 sub w5, w6, w7, asr #21
+# CHECK-NEXT: 1 2 0.13 sub w8, w9, w10, asr #31
+# CHECK-NEXT: 1 1 0.13 sub x3, x5, x7
+# CHECK-NEXT: 1 1 0.13 sub xzr, x3, x5
+# CHECK-NEXT: 1 1 0.13 sub x4, x6, xzr
+# CHECK-NEXT: 1 1 0.13 sub x11, x13, x15
+# CHECK-NEXT: 1 2 0.13 sub x9, x3, xzr, lsl #10
+# CHECK-NEXT: 1 1 0.13 sub x17, x29, x20, lsl #3
+# CHECK-NEXT: 1 2 0.13 sub x21, x22, x23, lsr #0
+# CHECK-NEXT: 1 2 0.13 sub x24, x25, x26, lsr #18
+# CHECK-NEXT: 1 2 0.13 sub x27, x28, x29, lsr #63
+# CHECK-NEXT: 1 2 0.13 sub x2, x3, x4, asr #0
+# CHECK-NEXT: 1 2 0.13 sub x5, x6, x7, asr #21
+# CHECK-NEXT: 1 2 0.13 sub x8, x9, x10, asr #63
+# CHECK-NEXT: 1 1 0.13 sub w13, wsp, w10
+# CHECK-NEXT: 1 2 0.13 sub x16, x2, w19, uxtb
+# CHECK-NEXT: 1 2 0.25 subs x13, x15, x14, sxtx #1
+# CHECK-NEXT: 1 1 0.25 subs w3, w5, w7
+# CHECK-NEXT: 1 1 0.25 cmp w3, w5
+# CHECK-NEXT: 1 1 0.25 subs w4, w6, wzr
+# CHECK-NEXT: 1 1 0.25 subs w11, w13, w15
+# CHECK-NEXT: 1 1 0.25 subs w9, w3, wzr, lsl #1
+# CHECK-NEXT: 1 2 0.25 subs w17, w29, w20, lsl #31
+# CHECK-NEXT: 1 2 0.25 subs w21, w22, w23, lsr #0
+# CHECK-NEXT: 1 2 0.25 subs w24, w25, w26, lsr #18
+# CHECK-NEXT: 1 2 0.25 subs w27, w28, w29, lsr #31
+# CHECK-NEXT: 1 2 0.25 subs w2, w3, w4, asr #0
+# CHECK-NEXT: 1 2 0.25 subs w5, w6, w7, asr #21
+# CHECK-NEXT: 1 2 0.25 subs w8, w9, w10, asr #31
+# CHECK-NEXT: 1 1 0.25 subs x3, x5, x7
+# CHECK-NEXT: 1 1 0.25 cmp x3, x5
+# CHECK-NEXT: 1 1 0.25 subs x4, x6, xzr
+# CHECK-NEXT: 1 1 0.25 subs x11, x13, x15
+# CHECK-NEXT: 1 2 0.25 subs x9, x3, xzr, lsl #10
+# CHECK-NEXT: 1 1 0.25 subs x17, x29, x20, lsl #3
+# CHECK-NEXT: 1 2 0.25 subs x21, x22, x23, lsr #0
+# CHECK-NEXT: 1 2 0.25 subs x24, x25, x26, lsr #18
+# CHECK-NEXT: 1 2 0.25 subs x27, x28, x29, lsr #63
+# CHECK-NEXT: 1 2 0.25 subs x2, x3, x4, asr #0
+# CHECK-NEXT: 1 2 0.25 subs x5, x6, x7, asr #21
+# CHECK-NEXT: 1 2 0.25 subs x8, x9, x10, asr #63
+# CHECK-NEXT: 1 1 0.25 cmn wzr, w4
+# CHECK-NEXT: 1 1 0.25 cmn w5, wzr
+# CHECK-NEXT: 1 1 0.25 cmn w6, w7
+# CHECK-NEXT: 1 1 0.25 cmn w8, w9, lsl #1
+# CHECK-NEXT: 1 2 0.25 cmn w10, w11, lsl #31
+# CHECK-NEXT: 1 2 0.25 cmn w12, w13, lsr #0
+# CHECK-NEXT: 1 2 0.25 cmn w14, w15, lsr #21
+# CHECK-NEXT: 1 2 0.25 cmn w16, w17, lsr #31
+# CHECK-NEXT: 1 2 0.25 cmn w18, w19, asr #0
+# CHECK-NEXT: 1 2 0.25 cmn w20, w21, asr #22
+# CHECK-NEXT: 1 2 0.25 cmn w22, w23, asr #31
+# CHECK-NEXT: 1 1 0.25 cmn x0, x3
+# CHECK-NEXT: 1 1 0.25 cmn xzr, x4
+# CHECK-NEXT: 1 1 0.25 cmn x5, xzr
+# CHECK-NEXT: 1 1 0.25 cmn x6, x7
+# CHECK-NEXT: 1 2 0.25 cmn x8, x9, lsl #15
+# CHECK-NEXT: 1 1 0.25 cmn x10, x11, lsl #3
+# CHECK-NEXT: 1 2 0.25 cmn x12, x13, lsr #0
+# CHECK-NEXT: 1 2 0.25 cmn x14, x15, lsr #41
+# CHECK-NEXT: 1 2 0.25 cmn x16, x17, lsr #63
+# CHECK-NEXT: 1 2 0.25 cmn x18, x19, asr #0
+# CHECK-NEXT: 1 2 0.25 cmn x20, x21, asr #55
+# CHECK-NEXT: 1 2 0.25 cmn x22, x23, asr #63
+# CHECK-NEXT: 1 1 0.25 cmp w0, w3
+# CHECK-NEXT: 1 1 0.25 cmp wzr, w4
+# CHECK-NEXT: 1 1 0.25 cmp w5, wzr
+# CHECK-NEXT: 1 1 0.25 cmp w6, w7
+# CHECK-NEXT: 1 1 0.25 cmp w8, w9, lsl #1
+# CHECK-NEXT: 1 2 0.25 cmp w10, w11, lsl #31
+# CHECK-NEXT: 1 2 0.25 cmp w12, w13, lsr #0
+# CHECK-NEXT: 1 2 0.25 cmp w14, w15, lsr #21
+# CHECK-NEXT: 1 2 0.25 cmp w18, w19, asr #0
+# CHECK-NEXT: 1 2 0.25 cmp w20, w21, asr #22
+# CHECK-NEXT: 1 2 0.25 cmp w22, w23, asr #31
+# CHECK-NEXT: 1 2 0.25 cmp wsp, w26
+# CHECK-NEXT: 1 2 0.25 cmp x16, w27, uxtb
+# CHECK-NEXT: 1 1 0.25 cmp x0, x3
+# CHECK-NEXT: 1 1 0.25 cmp xzr, x4
+# CHECK-NEXT: 1 1 0.25 cmp x5, xzr
+# CHECK-NEXT: 1 1 0.25 cmp x6, x7
+# CHECK-NEXT: 1 2 0.25 cmp x8, x9, lsl #15
+# CHECK-NEXT: 1 1 0.25 cmp x10, x11, lsl #3
+# CHECK-NEXT: 1 2 0.25 cmp x12, x13, lsr #0
+# CHECK-NEXT: 1 2 0.25 cmp x14, x15, lsr #41
+# CHECK-NEXT: 1 2 0.25 cmp x16, x17, lsr #63
+# CHECK-NEXT: 1 2 0.25 cmp x18, x19, asr #0
+# CHECK-NEXT: 1 2 0.25 cmp x20, x21, asr #55
+# CHECK-NEXT: 1 2 0.25 cmp x22, x23, asr #63
+# CHECK-NEXT: 1 1 0.25 cmp wzr, w0
+# CHECK-NEXT: 1 1 0.25 cmp xzr, x0
+# CHECK-NEXT: 1 1 0.13 mov sp, x30
+# CHECK-NEXT: 1 1 0.13 mov wsp, w20
+# CHECK-NEXT: 1 1 0.13 mov x11, sp
+# CHECK-NEXT: 1 1 0.13 mov w24, wsp
+# CHECK-NEXT: 1 1 0.13 adc w29, w27, w25
+# CHECK-NEXT: 1 1 0.13 adc wzr, w3, w4
+# CHECK-NEXT: 1 1 0.13 adc w9, wzr, w10
+# CHECK-NEXT: 1 1 0.13 adc w20, w0, wzr
+# CHECK-NEXT: 1 1 0.13 adc x29, x27, x25
+# CHECK-NEXT: 1 1 0.13 adc xzr, x3, x4
+# CHECK-NEXT: 1 1 0.13 adc x9, xzr, x10
+# CHECK-NEXT: 1 1 0.13 adc x20, x0, xzr
+# CHECK-NEXT: 1 1 0.25 adcs w29, w27, w25
+# CHECK-NEXT: 1 1 0.25 adcs wzr, w3, w4
+# CHECK-NEXT: 1 1 0.25 adcs w9, wzr, w10
+# CHECK-NEXT: 1 1 0.25 adcs w20, w0, wzr
+# CHECK-NEXT: 1 1 0.25 adcs x29, x27, x25
+# CHECK-NEXT: 1 1 0.25 adcs xzr, x3, x4
+# CHECK-NEXT: 1 1 0.25 adcs x9, xzr, x10
+# CHECK-NEXT: 1 1 0.25 adcs x20, x0, xzr
+# CHECK-NEXT: 1 1 0.13 sbc w29, w27, w25
+# CHECK-NEXT: 1 1 0.13 sbc wzr, w3, w4
+# CHECK-NEXT: 1 1 0.13 ngc w9, w10
+# CHECK-NEXT: 1 1 0.13 sbc w20, w0, wzr
+# CHECK-NEXT: 1 1 0.13 sbc x29, x27, x25
+# CHECK-NEXT: 1 1 0.13 sbc xzr, x3, x4
+# CHECK-NEXT: 1 1 0.13 ngc x9, x10
+# CHECK-NEXT: 1 1 0.13 sbc x20, x0, xzr
+# CHECK-NEXT: 1 1 0.25 sbcs w29, w27, w25
+# CHECK-NEXT: 1 1 0.25 sbcs wzr, w3, w4
+# CHECK-NEXT: 1 1 0.25 ngcs w9, w10
+# CHECK-NEXT: 1 1 0.25 sbcs w20, w0, wzr
+# CHECK-NEXT: 1 1 0.25 sbcs x29, x27, x25
+# CHECK-NEXT: 1 1 0.25 sbcs xzr, x3, x4
+# CHECK-NEXT: 1 1 0.25 ngcs x9, x10
+# CHECK-NEXT: 1 1 0.25 sbcs x20, x0, xzr
+# CHECK-NEXT: 1 1 0.13 ngc w3, w12
+# CHECK-NEXT: 1 1 0.13 ngc wzr, w9
+# CHECK-NEXT: 1 1 0.13 ngc w23, wzr
+# CHECK-NEXT: 1 1 0.13 ngc x29, x30
+# CHECK-NEXT: 1 1 0.13 ngc xzr, x0
+# CHECK-NEXT: 1 1 0.13 ngc x0, xzr
+# CHECK-NEXT: 1 1 0.25 ngcs w3, w12
+# CHECK-NEXT: 1 1 0.25 ngcs wzr, w9
+# CHECK-NEXT: 1 1 0.25 ngcs w23, wzr
+# CHECK-NEXT: 1 1 0.25 ngcs x29, x30
+# CHECK-NEXT: 1 1 0.25 ngcs xzr, x0
+# CHECK-NEXT: 1 1 0.25 ngcs x0, xzr
+# CHECK-NEXT: 1 1 0.13 sbfx x1, x2, #3, #2
+# CHECK-NEXT: 1 1 0.13 asr x3, x4, #63
+# CHECK-NEXT: 1 1 0.13 asr wzr, wzr, #31
+# CHECK-NEXT: 1 1 0.13 sbfx w12, w9, #0, #1
+# CHECK-NEXT: 1 1 0.13 ubfiz x4, x5, #52, #11
+# CHECK-NEXT: 1 1 0.13 ubfx xzr, x4, #0, #1
+# CHECK-NEXT: 1 1 0.13 ubfiz x4, xzr, #1, #6
+# CHECK-NEXT: 1 1 0.13 lsr x5, x6, #12
+# CHECK-NEXT: 1 2 0.13 bfi x4, x5, #52, #11
+# CHECK-NEXT: 1 2 0.13 bfxil xzr, x4, #0, #1
+# CHECK-NEXT: 1 2 0.13 bfc x4, #1, #6
+# CHECK-NEXT: 1 2 0.13 bfxil x5, x6, #12, #52
+# CHECK-NEXT: 1 1 0.13 sxtb w1, w2
+# CHECK-NEXT: 1 1 0.13 sxtb xzr, w3
+# CHECK-NEXT: 1 1 0.13 sxth w9, w10
+# CHECK-NEXT: 1 1 0.13 sxth x0, w1
+# CHECK-NEXT: 1 1 0.13 sxtw x3, w30
+# CHECK-NEXT: 1 1 0.13 uxtb w1, w2
+# CHECK-NEXT: 1 1 0.13 uxth w9, w10
+# CHECK-NEXT: 1 1 0.13 ubfx x3, x30, #0, #32
+# CHECK-NEXT: 1 1 0.13 asr w3, w2, #0
+# CHECK-NEXT: 1 1 0.13 asr w9, w10, #31
+# CHECK-NEXT: 1 1 0.13 asr x20, x21, #63
+# CHECK-NEXT: 1 1 0.13 asr w1, wzr, #3
+# CHECK-NEXT: 1 1 0.13 lsr w3, w2, #0
+# CHECK-NEXT: 1 1 0.13 lsr w9, w10, #31
+# CHECK-NEXT: 1 1 0.13 lsr x20, x21, #63
+# CHECK-NEXT: 1 1 0.13 lsr wzr, wzr, #3
+# CHECK-NEXT: 1 1 0.13 lsl w9, w10, #31
+# CHECK-NEXT: 1 1 0.13 lsl x20, x21, #63
+# CHECK-NEXT: 1 1 0.13 lsl w1, wzr, #3
+# CHECK-NEXT: 1 1 0.13 sbfiz x2, x3, #63, #1
+# CHECK-NEXT: 1 1 0.13 sbfiz x9, x10, #5, #59
+# CHECK-NEXT: 1 1 0.13 sbfiz w11, w12, #31, #1
+# CHECK-NEXT: 1 1 0.13 sbfiz w13, w14, #29, #3
+# CHECK-NEXT: 1 1 0.13 sbfiz xzr, xzr, #10, #11
+# CHECK-NEXT: 1 1 0.13 sbfx w9, w10, #0, #1
+# CHECK-NEXT: 1 1 0.13 asr x2, x3, #63
+# CHECK-NEXT: 1 1 0.13 asr x19, x20, #0
+# CHECK-NEXT: 1 1 0.13 asr x9, x10, #5
+# CHECK-NEXT: 1 1 0.13 asr w9, w10, #0
+# CHECK-NEXT: 1 1 0.13 asr w11, w12, #31
+# CHECK-NEXT: 1 1 0.13 asr w13, w14, #29
+# CHECK-NEXT: 1 1 0.13 sbfx xzr, xzr, #10, #11
+# CHECK-NEXT: 1 2 0.13 bfi x2, x3, #63, #1
+# CHECK-NEXT: 1 2 0.13 bfi x9, x10, #5, #59
+# CHECK-NEXT: 1 2 0.13 bfi w11, w12, #31, #1
+# CHECK-NEXT: 1 2 0.13 bfi w13, w14, #29, #3
+# CHECK-NEXT: 1 2 0.13 bfc xzr, #10, #11
+# CHECK-NEXT: 1 2 0.13 bfxil w9, w10, #0, #1
+# CHECK-NEXT: 1 2 0.13 bfxil x2, x3, #63, #1
+# CHECK-NEXT: 1 2 0.13 bfxil x19, x20, #0, #64
+# CHECK-NEXT: 1 2 0.13 bfxil x9, x10, #5, #59
+# CHECK-NEXT: 1 2 0.13 bfxil w9, w10, #0, #32
+# CHECK-NEXT: 1 2 0.13 bfxil w11, w12, #31, #1
+# CHECK-NEXT: 1 2 0.13 bfxil w13, w14, #29, #3
+# CHECK-NEXT: 1 2 0.13 bfxil xzr, xzr, #10, #11
+# CHECK-NEXT: 1 1 0.13 lsl x2, x3, #63
+# CHECK-NEXT: 1 1 0.13 lsl x9, x10, #5
+# CHECK-NEXT: 1 1 0.13 lsl w11, w12, #31
+# CHECK-NEXT: 1 1 0.13 lsl w13, w14, #29
+# CHECK-NEXT: 1 1 0.13 ubfiz xzr, xzr, #10, #11
+# CHECK-NEXT: 1 1 0.13 ubfx w9, w10, #0, #1
+# CHECK-NEXT: 1 1 0.13 lsr x2, x3, #63
+# CHECK-NEXT: 1 1 0.13 lsr x19, x20, #0
+# CHECK-NEXT: 1 1 0.13 lsr x9, x10, #5
+# CHECK-NEXT: 1 1 0.13 lsr w9, w10, #0
+# CHECK-NEXT: 1 1 0.13 lsr w11, w12, #31
+# CHECK-NEXT: 1 1 0.13 lsr w13, w14, #29
+# CHECK-NEXT: 1 1 0.13 ubfx xzr, xzr, #10, #11
+# CHECK-NEXT: 1 2 0.33 cbz w5, #4
+# CHECK-NEXT: 1 2 0.33 cbz x5, #0
+# CHECK-NEXT: 1 2 0.33 cbnz x2, #-4
+# CHECK-NEXT: 1 2 0.33 cbnz x26, #1048572
+# CHECK-NEXT: 1 2 0.33 cbz wzr, #0
+# CHECK-NEXT: 1 2 0.33 cbnz xzr, #0
+# CHECK-NEXT: 1 2 0.33 cbnz w21, test
+# CHECK-NEXT: 1 2 0.33 b.ne #4
+# CHECK-NEXT: 1 2 0.33 b.ge #1048572
+# CHECK-NEXT: 1 2 0.33 b.ge #-4
+# CHECK-NEXT: 1 1 0.25 ccmp w1, #31, #0, eq
+# CHECK-NEXT: 1 1 0.25 ccmp w3, #0, #15, hs
+# CHECK-NEXT: 1 1 0.25 ccmp wzr, #15, #13, hs
+# CHECK-NEXT: 1 1 0.25 ccmp x9, #31, #0, le
+# CHECK-NEXT: 1 1 0.25 ccmp x3, #0, #15, gt
+# CHECK-NEXT: 1 1 0.25 ccmp xzr, #5, #7, ne
+# CHECK-NEXT: 1 1 0.25 ccmn w1, #31, #0, eq
+# CHECK-NEXT: 1 1 0.25 ccmn w3, #0, #15, hs
+# CHECK-NEXT: 1 1 0.25 ccmn wzr, #15, #13, hs
+# CHECK-NEXT: 1 1 0.25 ccmn x9, #31, #0, le
+# CHECK-NEXT: 1 1 0.25 ccmn x3, #0, #15, gt
+# CHECK-NEXT: 1 1 0.25 ccmn xzr, #5, #7, ne
+# CHECK-NEXT: 1 1 0.25 ccmp w1, wzr, #0, eq
+# CHECK-NEXT: 1 1 0.25 ccmp w3, w0, #15, hs
+# CHECK-NEXT: 1 1 0.25 ccmp wzr, w15, #13, hs
+# CHECK-NEXT: 1 1 0.25 ccmp x9, xzr, #0, le
+# CHECK-NEXT: 1 1 0.25 ccmp x3, x0, #15, gt
+# CHECK-NEXT: 1 1 0.25 ccmp xzr, x5, #7, ne
+# CHECK-NEXT: 1 1 0.25 ccmn w1, wzr, #0, eq
+# CHECK-NEXT: 1 1 0.25 ccmn w3, w0, #15, hs
+# CHECK-NEXT: 1 1 0.25 ccmn wzr, w15, #13, hs
+# CHECK-NEXT: 1 1 0.25 ccmn x9, xzr, #0, le
+# CHECK-NEXT: 1 1 0.25 ccmn x3, x0, #15, gt
+# CHECK-NEXT: 1 1 0.25 ccmn xzr, x5, #7, ne
+# CHECK-NEXT: 1 1 0.13 csel w1, w0, w19, ne
+# CHECK-NEXT: 1 1 0.13 csel wzr, w5, w9, eq
+# CHECK-NEXT: 1 1 0.13 csel w9, wzr, w30, gt
+# CHECK-NEXT: 1 1 0.13 csel w1, w28, wzr, mi
+# CHECK-NEXT: 1 1 0.13 csel x19, x23, x29, lt
+# CHECK-NEXT: 1 1 0.13 csel xzr, x3, x4, ge
+# CHECK-NEXT: 1 1 0.13 csel x5, xzr, x6, hs
+# CHECK-NEXT: 1 1 0.13 csel x7, x8, xzr, lo
+# CHECK-NEXT: 1 1 0.13 csinc w1, w0, w19, ne
+# CHECK-NEXT: 1 1 0.13 csinc wzr, w5, w9, eq
+# CHECK-NEXT: 1 1 0.13 csinc w9, wzr, w30, gt
+# CHECK-NEXT: 1 1 0.13 csinc w1, w28, wzr, mi
+# CHECK-NEXT: 1 1 0.13 csinc x19, x23, x29, lt
+# CHECK-NEXT: 1 1 0.13 csinc xzr, x3, x4, ge
+# CHECK-NEXT: 1 1 0.13 csinc x5, xzr, x6, hs
+# CHECK-NEXT: 1 1 0.13 csinc x7, x8, xzr, lo
+# CHECK-NEXT: 1 1 0.13 csinv w1, w0, w19, ne
+# CHECK-NEXT: 1 1 0.13 csinv wzr, w5, w9, eq
+# CHECK-NEXT: 1 1 0.13 csinv w9, wzr, w30, gt
+# CHECK-NEXT: 1 1 0.13 csinv w1, w28, wzr, mi
+# CHECK-NEXT: 1 1 0.13 csinv x19, x23, x29, lt
+# CHECK-NEXT: 1 1 0.13 csinv xzr, x3, x4, ge
+# CHECK-NEXT: 1 1 0.13 csinv x5, xzr, x6, hs
+# CHECK-NEXT: 1 1 0.13 csinv x7, x8, xzr, lo
+# CHECK-NEXT: 1 1 0.13 csneg w1, w0, w19, ne
+# CHECK-NEXT: 1 1 0.13 csneg wzr, w5, w9, eq
+# CHECK-NEXT: 1 1 0.13 csneg w9, wzr, w30, gt
+# CHECK-NEXT: 1 1 0.13 csneg w1, w28, wzr, mi
+# CHECK-NEXT: 1 1 0.13 csneg x19, x23, x29, lt
+# CHECK-NEXT: 1 1 0.13 csneg xzr, x3, x4, ge
+# CHECK-NEXT: 1 1 0.13 csneg x5, xzr, x6, hs
+# CHECK-NEXT: 1 1 0.13 csneg x7, x8, xzr, lo
+# CHECK-NEXT: 1 1 0.13 cset w3, eq
+# CHECK-NEXT: 1 1 0.13 cset x9, pl
+# CHECK-NEXT: 1 1 0.13 csetm w20, ne
+# CHECK-NEXT: 1 1 0.13 csetm x30, ge
+# CHECK-NEXT: 1 1 0.13 csinc w2, wzr, wzr, al
+# CHECK-NEXT: 1 1 0.13 csinv x3, xzr, xzr, nv
+# CHECK-NEXT: 1 1 0.13 cinc w3, w5, gt
+# CHECK-NEXT: 1 1 0.13 cinc wzr, w4, le
+# CHECK-NEXT: 1 1 0.13 cset w9, lt
+# CHECK-NEXT: 1 1 0.13 cinc x3, x5, gt
+# CHECK-NEXT: 1 1 0.13 cinc xzr, x4, le
+# CHECK-NEXT: 1 1 0.13 cset x9, lt
+# CHECK-NEXT: 1 1 0.13 csinc w5, w6, w6, nv
+# CHECK-NEXT: 1 1 0.13 csinc x1, x2, x2, al
+# CHECK-NEXT: 1 1 0.13 cinv w3, w5, gt
+# CHECK-NEXT: 1 1 0.13 cinv wzr, w4, le
+# CHECK-NEXT: 1 1 0.13 csetm w9, lt
+# CHECK-NEXT: 1 1 0.13 cinv x3, x5, gt
+# CHECK-NEXT: 1 1 0.13 cinv xzr, x4, le
+# CHECK-NEXT: 1 1 0.13 csetm x9, lt
+# CHECK-NEXT: 1 1 0.13 csinv x1, x0, x0, al
+# CHECK-NEXT: 1 1 0.13 csinv w9, w8, w8, nv
+# CHECK-NEXT: 1 1 0.13 cneg w3, w5, gt
+# CHECK-NEXT: 1 1 0.13 cneg wzr, w4, le
+# CHECK-NEXT: 1 1 0.13 cneg w9, wzr, lt
+# CHECK-NEXT: 1 1 0.13 cneg x3, x5, gt
+# CHECK-NEXT: 1 1 0.13 cneg xzr, x4, le
+# CHECK-NEXT: 1 1 0.13 cneg x9, xzr, lt
+# CHECK-NEXT: 1 1 0.13 csneg x4, x8, x8, al
+# CHECK-NEXT: 1 1 0.13 rbit w0, w7
+# CHECK-NEXT: 1 1 0.13 rbit x18, x3
+# CHECK-NEXT: 1 1 0.13 rev16 w17, w1
+# CHECK-NEXT: 1 1 0.13 rev16 x5, x2
+# CHECK-NEXT: 1 1 0.13 rev w18, w0
+# CHECK-NEXT: 1 1 0.13 rev32 x20, x1
+# CHECK-NEXT: 1 1 0.13 rev x22, x2
+# CHECK-NEXT: 1 1 0.13 clz w24, w3
+# CHECK-NEXT: 1 1 0.13 clz x26, x4
+# CHECK-NEXT: 1 1 0.13 cls w3, w5
+# CHECK-NEXT: 1 1 0.13 cls x20, x5
+# CHECK-NEXT: 1 5 5.00 udiv w0, w7, w10
+# CHECK-NEXT: 1 5 5.00 udiv x9, x22, x4
+# CHECK-NEXT: 1 5 5.00 sdiv w12, w21, w0
+# CHECK-NEXT: 1 5 5.00 sdiv x13, x2, x1
+# CHECK-NEXT: 1 1 0.13 lsl w11, w12, w13
+# CHECK-NEXT: 1 1 0.13 lsl x14, x15, x16
+# CHECK-NEXT: 1 1 0.13 lsr w17, w18, w19
+# CHECK-NEXT: 1 1 0.13 lsr x20, x21, x22
+# CHECK-NEXT: 1 1 0.13 asr w23, w24, w25
+# CHECK-NEXT: 1 1 0.13 asr x26, x27, x28
+# CHECK-NEXT: 1 1 0.13 ror w0, w1, w2
+# CHECK-NEXT: 1 1 0.13 ror x3, x4, x5
+# CHECK-NEXT: 1 1 0.13 lsl w6, w7, w8
+# CHECK-NEXT: 1 1 0.13 lsl x9, x10, x11
+# CHECK-NEXT: 1 1 0.13 lsr w12, w13, w14
+# CHECK-NEXT: 1 1 0.13 lsr x15, x16, x17
+# CHECK-NEXT: 1 1 0.13 asr w18, w19, w20
+# CHECK-NEXT: 1 1 0.13 asr x21, x22, x23
+# CHECK-NEXT: 1 1 0.13 ror w24, w25, w26
+# CHECK-NEXT: 1 1 0.13 ror x27, x28, x29
+# CHECK-NEXT: 1 2 0.50 crc32cb w30, w23, w15
+# CHECK-NEXT: 1 2 0.50 crc32cb wzr, w12, w14
+# CHECK-NEXT: 1 2 0.50 crc32cb w28, w10, w11
+# CHECK-NEXT: 1 2 0.50 crc32b w27, w12, w15
+# CHECK-NEXT: 1 2 0.50 crc32h w3, w15, w21
+# CHECK-NEXT: 1 2 0.50 crc32w w9, w18, w24
+# CHECK-NEXT: 1 2 0.50 crc32x w19, w6, x25
+# CHECK-NEXT: 1 2 0.50 crc32ch w25, w26, w16
+# CHECK-NEXT: 1 2 0.50 crc32cw w27, w12, w23
+# CHECK-NEXT: 1 2 0.50 crc32cx w21, w28, x5
+# CHECK-NEXT: 1 2 0.25 smulh x30, x29, x28
+# CHECK-NEXT: 1 2 0.25 smulh xzr, x27, x26
+# CHECK-NEXT: 1 2 0.25 umulh x30, x29, x28
+# CHECK-NEXT: 1 2 0.25 umulh x23, x30, xzr
+# CHECK-NEXT: 1 3 0.25 madd w1, w3, w7, w4
+# CHECK-NEXT: 1 3 0.25 madd wzr, w0, w9, w11
+# CHECK-NEXT: 1 3 0.25 madd w13, wzr, w4, w4
+# CHECK-NEXT: 1 3 0.25 madd w19, w30, wzr, w29
+# CHECK-NEXT: 1 2 0.25 mul w4, w5, w6
+# CHECK-NEXT: 1 3 0.25 madd x1, x3, x7, x4
+# CHECK-NEXT: 1 3 0.25 madd xzr, x0, x9, x11
+# CHECK-NEXT: 1 3 0.25 madd x13, xzr, x4, x4
+# CHECK-NEXT: 1 3 0.25 madd x19, x30, xzr, x29
+# CHECK-NEXT: 1 2 0.25 mul x4, x5, x6
+# CHECK-NEXT: 1 3 0.25 msub w1, w3, w7, w4
+# CHECK-NEXT: 1 3 0.25 msub wzr, w0, w9, w11
+# CHECK-NEXT: 1 3 0.25 msub w13, wzr, w4, w4
+# CHECK-NEXT: 1 3 0.25 msub w19, w30, wzr, w29
+# CHECK-NEXT: 1 2 0.25 mneg w4, w5, w6
+# CHECK-NEXT: 1 3 0.25 msub x1, x3, x7, x4
+# CHECK-NEXT: 1 3 0.25 msub xzr, x0, x9, x11
+# CHECK-NEXT: 1 3 0.25 msub x13, xzr, x4, x4
+# CHECK-NEXT: 1 3 0.25 msub x19, x30, xzr, x29
+# CHECK-NEXT: 1 2 0.25 mneg x4, x5, x6
+# CHECK-NEXT: 1 3 0.25 smaddl x3, w5, w2, x9
+# CHECK-NEXT: 1 3 0.25 smaddl xzr, w10, w11, x12
+# CHECK-NEXT: 1 3 0.25 smaddl x13, wzr, w14, x15
+# CHECK-NEXT: 1 3 0.25 smaddl x16, w17, wzr, x18
+# CHECK-NEXT: 1 2 0.25 smull x19, w20, w21
+# CHECK-NEXT: 1 3 0.25 smsubl x3, w5, w2, x9
+# CHECK-NEXT: 1 3 0.25 smsubl xzr, w10, w11, x12
+# CHECK-NEXT: 1 3 0.25 smsubl x13, wzr, w14, x15
+# CHECK-NEXT: 1 3 0.25 smsubl x16, w17, wzr, x18
+# CHECK-NEXT: 1 2 0.25 smnegl x19, w20, w21
+# CHECK-NEXT: 1 3 0.25 umaddl x3, w5, w2, x9
+# CHECK-NEXT: 1 3 0.25 umaddl xzr, w10, w11, x12
+# CHECK-NEXT: 1 3 0.25 umaddl x13, wzr, w14, x15
+# CHECK-NEXT: 1 3 0.25 umaddl x16, w17, wzr, x18
+# CHECK-NEXT: 1 2 0.25 umull x19, w20, w21
+# CHECK-NEXT: 1 3 0.25 umsubl x3, w5, w2, x9
+# CHECK-NEXT: 1 3 0.25 umsubl x16, w17, wzr, x18
+# CHECK-NEXT: 1 2 0.25 umnegl x19, w20, w21
+# CHECK-NEXT: 1 2 0.25 smulh x23, x22, xzr
+# CHECK-NEXT: 1 2 0.25 umulh x23, x22, xzr
+# CHECK-NEXT: 1 2 0.25 mul x19, x20, xzr
+# CHECK-NEXT: 1 2 0.25 mneg w21, w22, w23
+# CHECK-NEXT: 1 2 0.25 smull x11, w13, w17
+# CHECK-NEXT: 1 2 0.25 umull x11, w13, w17
+# CHECK-NEXT: 1 2 0.25 smnegl x11, w13, w17
+# CHECK-NEXT: 1 2 0.25 umnegl x11, w13, w17
+# CHECK-NEXT: 1 3 0.13 extr w3, w5, w7, #0
+# CHECK-NEXT: 1 3 0.13 extr w11, w13, w17, #31
+# CHECK-NEXT: 1 3 0.13 extr x3, x5, x7, #15
+# CHECK-NEXT: 1 3 0.13 extr x11, x13, x17, #63
+# CHECK-NEXT: 1 1 0.13 ror x19, x23, #24
+# CHECK-NEXT: 1 1 0.13 ror x29, xzr, #63
+# CHECK-NEXT: 1 1 0.13 ror w9, w13, #31
+# CHECK-NEXT: 1 2 0.50 fcmp h5, h21
+# CHECK-NEXT: 1 2 0.50 fcmp h5, #0.0
+# CHECK-NEXT: 1 2 0.50 fcmpe h22, h21
+# CHECK-NEXT: 1 2 0.50 fcmpe h13, #0.0
+# CHECK-NEXT: 1 2 0.50 fcmp s3, s5
+# CHECK-NEXT: 1 2 0.50 fcmp s31, #0.0
+# CHECK-NEXT: 1 2 0.50 fcmpe s29, s30
+# CHECK-NEXT: 1 2 0.50 fcmpe s15, #0.0
+# CHECK-NEXT: 1 2 0.50 fcmp d4, d12
+# CHECK-NEXT: 1 2 0.50 fcmp d23, #0.0
+# CHECK-NEXT: 1 2 0.50 fcmpe d26, d22
+# CHECK-NEXT: 1 2 0.50 fcmpe d29, #0.0
+# CHECK-NEXT: 1 2 0.50 fccmp s1, s31, #0, eq
+# CHECK-NEXT: 1 2 0.50 fccmp s3, s0, #15, hs
+# CHECK-NEXT: 1 2 0.50 fccmp s31, s15, #13, hs
+# CHECK-NEXT: 1 2 0.50 fccmp d9, d31, #0, le
+# CHECK-NEXT: 1 2 0.50 fccmp d3, d0, #15, gt
+# CHECK-NEXT: 1 2 0.50 fccmp d31, d5, #7, ne
+# CHECK-NEXT: 1 2 0.50 fccmp h31, h3, #11, hs
+# CHECK-NEXT: 1 2 0.50 fccmpe h6, h1, #12, ne
+# CHECK-NEXT: 1 2 0.50 fccmpe s1, s31, #0, eq
+# CHECK-NEXT: 1 2 0.50 fccmpe s3, s0, #15, hs
+# CHECK-NEXT: 1 2 0.50 fccmpe s31, s15, #13, hs
+# CHECK-NEXT: 1 2 0.50 fccmpe d9, d31, #0, le
+# CHECK-NEXT: 1 2 0.50 fccmpe d3, d0, #15, gt
+# CHECK-NEXT: 1 2 0.50 fccmpe d31, d5, #7, ne
+# CHECK-NEXT: 1 2 0.50 fcsel s3, s20, s9, pl
+# CHECK-NEXT: 1 2 0.50 fcsel d9, d10, d11, mi
+# CHECK-NEXT: 1 2 0.50 fcsel h26, h2, h11, hs
+# CHECK-NEXT: 1 2 0.50 fmov h18, h28
+# CHECK-NEXT: 1 2 0.50 fmov s0, s1
+# CHECK-NEXT: 1 2 0.50 fabs s2, s3
+# CHECK-NEXT: 1 2 0.50 fneg h2, h9
+# CHECK-NEXT: 1 2 0.50 fneg s4, s5
+# CHECK-NEXT: 1 8 4.00 fsqrt s6, s7
+# CHECK-NEXT: 1 3 0.50 fcvt d8, s9
+# CHECK-NEXT: 1 3 0.50 fcvt h10, s11
+# CHECK-NEXT: 1 2 0.50 frintn h12, h3
+# CHECK-NEXT: 1 2 0.50 frintn s12, s13
+# CHECK-NEXT: 1 2 0.50 frintp h17, h31
+# CHECK-NEXT: 1 2 0.50 frintp s14, s15
+# CHECK-NEXT: 1 2 0.50 frintm h0, h21
+# CHECK-NEXT: 1 2 0.50 frintm s16, s17
+# CHECK-NEXT: 1 2 0.50 frintz h10, h29
+# CHECK-NEXT: 1 2 0.50 frintz s18, s19
+# CHECK-NEXT: 1 2 0.50 frinta h22, h10
+# CHECK-NEXT: 1 2 0.50 frinta s20, s21
+# CHECK-NEXT: 1 2 0.50 frintx h4, h5
+# CHECK-NEXT: 1 2 0.50 frintx s22, s23
+# CHECK-NEXT: 1 2 0.50 frinti s24, s25
+# CHECK-NEXT: 1 2 0.50 frinti h31, h14
+# CHECK-NEXT: 1 2 0.50 fmov d0, d1
+# CHECK-NEXT: 1 2 0.50 fabs d2, d3
+# CHECK-NEXT: 1 2 0.50 fneg d4, d5
+# CHECK-NEXT: 1 5 8.00 fsqrt h13, h24
+# CHECK-NEXT: 1 12 2.00 fsqrt d6, d7
+# CHECK-NEXT: 1 3 0.50 fcvt s8, d9
+# CHECK-NEXT: 1 3 0.50 fcvt h10, d11
+# CHECK-NEXT: 1 2 0.50 frintn d12, d13
+# CHECK-NEXT: 1 2 0.50 frintp d14, d15
+# CHECK-NEXT: 1 2 0.50 frintm d16, d17
+# CHECK-NEXT: 1 2 0.50 frintz d18, d19
+# CHECK-NEXT: 1 2 0.50 frinta d20, d21
+# CHECK-NEXT: 1 2 0.50 frintx d22, d23
+# CHECK-NEXT: 1 2 0.50 frinti d24, d25
+# CHECK-NEXT: 1 3 0.50 fcvt s26, h27
+# CHECK-NEXT: 1 3 0.50 fcvt d28, h29
+# CHECK-NEXT: 1 3 0.50 fmul s20, s19, s17
+# CHECK-NEXT: 1 5 8.00 fdiv h1, h26, h23
+# CHECK-NEXT: 1 8 4.00 fdiv s1, s2, s3
----------------
Asher8118 wrote:
I think these and the `# CHECK-NEXT: 1 12 2.00 fdiv d1, d2, d3` on line 591 are meant to be FP divides when not in Streaming SVE mode. In which case, their throughput should be 1 for all of them.
https://github.com/llvm/llvm-project/pull/185398
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