[llvm] b771613 - [RISCV] Add tests for Zvzip CodeGen (#192591)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 17 03:14:14 PDT 2026
Author: Pengcheng Wang
Date: 2026-04-17T18:14:08+08:00
New Revision: b7716135a88f1424fbb400124d3b57a269b38c75
URL: https://github.com/llvm/llvm-project/commit/b7716135a88f1424fbb400124d3b57a269b38c75
DIFF: https://github.com/llvm/llvm-project/commit/b7716135a88f1424fbb400124d3b57a269b38c75.diff
LOG: [RISCV] Add tests for Zvzip CodeGen (#192591)
Then we can add CodeGen support incrementally.
Added:
Modified:
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-zipeven-zipodd.ll
llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
index 3a14f87c3f18a..5903271cf0d1d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
@@ -8,6 +8,9 @@
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh,+zvl256b,+experimental-xrivosvizip \
; RUN: -lower-interleaved-accesses=false -verify-machineinstrs \
; RUN: | FileCheck %s --check-prefixes=CHECK,ZIP
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh,+zvl256b,+experimental-zvzip \
+; RUN: -lower-interleaved-accesses=false -verify-machineinstrs \
+; RUN: | FileCheck %s --check-prefixes=CHECK,ZVZIP
define void @vnsrl_0_i8(ptr %in, ptr %out) {
; CHECK-LABEL: vnsrl_0_i8:
@@ -68,6 +71,15 @@ define void @vnsrl_0_i16(ptr %in, ptr %out) {
; ZIP-NEXT: vnsrl.wi v8, v8, 0
; ZIP-NEXT: vse16.v v8, (a1)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_0_i16:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
+; ZVZIP-NEXT: vle16.v v8, (a0)
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v8, v8, 0
+; ZVZIP-NEXT: vse16.v v8, (a1)
+; ZVZIP-NEXT: ret
entry:
%0 = load <8 x i16>, ptr %in, align 2
%shuffle.i5 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
@@ -102,6 +114,15 @@ define void @vnsrl_16_i16(ptr %in, ptr %out) {
; ZIP-NEXT: vnsrl.wi v8, v8, 16
; ZIP-NEXT: vse16.v v8, (a1)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_16_i16:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
+; ZVZIP-NEXT: vle16.v v8, (a0)
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v8, v8, 16
+; ZVZIP-NEXT: vse16.v v8, (a1)
+; ZVZIP-NEXT: ret
entry:
%0 = load <8 x i16>, ptr %in, align 2
%shuffle.i5 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
@@ -136,6 +157,15 @@ define void @vnsrl_0_half(ptr %in, ptr %out) {
; ZIP-NEXT: vnsrl.wi v8, v8, 0
; ZIP-NEXT: vse16.v v8, (a1)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_0_half:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
+; ZVZIP-NEXT: vle16.v v8, (a0)
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v8, v8, 0
+; ZVZIP-NEXT: vse16.v v8, (a1)
+; ZVZIP-NEXT: ret
entry:
%0 = load <8 x half>, ptr %in, align 2
%shuffle.i5 = shufflevector <8 x half> %0, <8 x half> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
@@ -170,6 +200,15 @@ define void @vnsrl_16_half(ptr %in, ptr %out) {
; ZIP-NEXT: vnsrl.wi v8, v8, 16
; ZIP-NEXT: vse16.v v8, (a1)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_16_half:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
+; ZVZIP-NEXT: vle16.v v8, (a0)
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v8, v8, 16
+; ZVZIP-NEXT: vse16.v v8, (a1)
+; ZVZIP-NEXT: ret
entry:
%0 = load <8 x half>, ptr %in, align 2
%shuffle.i5 = shufflevector <8 x half> %0, <8 x half> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
@@ -205,6 +244,15 @@ define void @vnsrl_0_i32(ptr %in, ptr %out) {
; ZIP-NEXT: vnsrl.wi v8, v8, 0
; ZIP-NEXT: vse32.v v8, (a1)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_0_i32:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 4, e32, mf2, ta, ma
+; ZVZIP-NEXT: vle32.v v8, (a0)
+; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v8, v8, 0
+; ZVZIP-NEXT: vse32.v v8, (a1)
+; ZVZIP-NEXT: ret
entry:
%0 = load <4 x i32>, ptr %in, align 4
%shuffle.i5 = shufflevector <4 x i32> %0, <4 x i32> poison, <2 x i32> <i32 0, i32 2>
@@ -243,6 +291,16 @@ define void @vnsrl_32_i32(ptr %in, ptr %out) {
; ZIP-NEXT: vnsrl.wx v8, v8, a0
; ZIP-NEXT: vse32.v v8, (a1)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_32_i32:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 4, e32, mf2, ta, ma
+; ZVZIP-NEXT: vle32.v v8, (a0)
+; ZVZIP-NEXT: li a0, 32
+; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-NEXT: vnsrl.wx v8, v8, a0
+; ZVZIP-NEXT: vse32.v v8, (a1)
+; ZVZIP-NEXT: ret
entry:
%0 = load <4 x i32>, ptr %in, align 4
%shuffle.i5 = shufflevector <4 x i32> %0, <4 x i32> poison, <2 x i32> <i32 1, i32 3>
@@ -278,6 +336,15 @@ define void @vnsrl_0_float(ptr %in, ptr %out) {
; ZIP-NEXT: vnsrl.wi v8, v8, 0
; ZIP-NEXT: vse32.v v8, (a1)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_0_float:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 4, e32, mf2, ta, ma
+; ZVZIP-NEXT: vle32.v v8, (a0)
+; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v8, v8, 0
+; ZVZIP-NEXT: vse32.v v8, (a1)
+; ZVZIP-NEXT: ret
entry:
%0 = load <4 x float>, ptr %in, align 4
%shuffle.i5 = shufflevector <4 x float> %0, <4 x float> poison, <2 x i32> <i32 0, i32 2>
@@ -316,6 +383,16 @@ define void @vnsrl_32_float(ptr %in, ptr %out) {
; ZIP-NEXT: vnsrl.wx v8, v8, a0
; ZIP-NEXT: vse32.v v8, (a1)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_32_float:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 4, e32, mf2, ta, ma
+; ZVZIP-NEXT: vle32.v v8, (a0)
+; ZVZIP-NEXT: li a0, 32
+; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-NEXT: vnsrl.wx v8, v8, a0
+; ZVZIP-NEXT: vse32.v v8, (a1)
+; ZVZIP-NEXT: ret
entry:
%0 = load <4 x float>, ptr %in, align 4
%shuffle.i5 = shufflevector <4 x float> %0, <4 x float> poison, <2 x i32> <i32 1, i32 3>
@@ -350,6 +427,16 @@ define void @vnsrl_0_i64(ptr %in, ptr %out) {
; ZIP-NEXT: ri.vunzip2a.vv v10, v8, v9
; ZIP-NEXT: vse64.v v10, (a1)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_0_i64:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma
+; ZVZIP-NEXT: vle64.v v8, (a0)
+; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; ZVZIP-NEXT: vslidedown.vi v9, v8, 2
+; ZVZIP-NEXT: vslideup.vi v8, v9, 1
+; ZVZIP-NEXT: vse64.v v8, (a1)
+; ZVZIP-NEXT: ret
entry:
%0 = load <4 x i64>, ptr %in, align 8
%shuffle.i5 = shufflevector <4 x i64> %0, <4 x i64> poison, <2 x i32> <i32 0, i32 2>
@@ -385,6 +472,17 @@ define void @vnsrl_64_i64(ptr %in, ptr %out) {
; ZIP-NEXT: ri.vunzip2b.vv v10, v8, v9
; ZIP-NEXT: vse64.v v10, (a1)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_64_i64:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma
+; ZVZIP-NEXT: vle64.v v8, (a0)
+; ZVZIP-NEXT: vmv.v.i v0, 1
+; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, mu
+; ZVZIP-NEXT: vslidedown.vi v9, v8, 2
+; ZVZIP-NEXT: vslidedown.vi v9, v8, 1, v0.t
+; ZVZIP-NEXT: vse64.v v9, (a1)
+; ZVZIP-NEXT: ret
entry:
%0 = load <4 x i64>, ptr %in, align 8
%shuffle.i5 = shufflevector <4 x i64> %0, <4 x i64> poison, <2 x i32> <i32 1, i32 3>
@@ -419,6 +517,16 @@ define void @vnsrl_0_double(ptr %in, ptr %out) {
; ZIP-NEXT: ri.vunzip2a.vv v10, v8, v9
; ZIP-NEXT: vse64.v v10, (a1)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_0_double:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma
+; ZVZIP-NEXT: vle64.v v8, (a0)
+; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; ZVZIP-NEXT: vslidedown.vi v9, v8, 2
+; ZVZIP-NEXT: vslideup.vi v8, v9, 1
+; ZVZIP-NEXT: vse64.v v8, (a1)
+; ZVZIP-NEXT: ret
entry:
%0 = load <4 x double>, ptr %in, align 8
%shuffle.i5 = shufflevector <4 x double> %0, <4 x double> poison, <2 x i32> <i32 0, i32 2>
@@ -454,6 +562,17 @@ define void @vnsrl_64_double(ptr %in, ptr %out) {
; ZIP-NEXT: ri.vunzip2b.vv v10, v8, v9
; ZIP-NEXT: vse64.v v10, (a1)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_64_double:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma
+; ZVZIP-NEXT: vle64.v v8, (a0)
+; ZVZIP-NEXT: vmv.v.i v0, 1
+; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, mu
+; ZVZIP-NEXT: vslidedown.vi v9, v8, 2
+; ZVZIP-NEXT: vslidedown.vi v9, v8, 1, v0.t
+; ZVZIP-NEXT: vse64.v v9, (a1)
+; ZVZIP-NEXT: ret
entry:
%0 = load <4 x double>, ptr %in, align 8
%shuffle.i5 = shufflevector <4 x double> %0, <4 x double> poison, <2 x i32> <i32 1, i32 3>
@@ -566,6 +685,15 @@ define void @vnsrl_0_i8_single_src(ptr %in, ptr %out) {
; ZIP-NEXT: vnsrl.wi v8, v8, 0
; ZIP-NEXT: vse8.v v8, (a1)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_0_i8_single_src:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
+; ZVZIP-NEXT: vle8.v v8, (a0)
+; ZVZIP-NEXT: vsetivli zero, 4, e8, mf8, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v8, v8, 0
+; ZVZIP-NEXT: vse8.v v8, (a1)
+; ZVZIP-NEXT: ret
entry:
%0 = load <8 x i8>, ptr %in, align 1
%shuffle.i5 = shufflevector <8 x i8> %0, <8 x i8> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
@@ -600,6 +728,15 @@ define void @vnsrl_8_i8_single_src(ptr %in, ptr %out) {
; ZIP-NEXT: vnsrl.wi v8, v8, 8
; ZIP-NEXT: vse8.v v8, (a1)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_8_i8_single_src:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
+; ZVZIP-NEXT: vle8.v v8, (a0)
+; ZVZIP-NEXT: vsetivli zero, 4, e8, mf8, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v8, v8, 8
+; ZVZIP-NEXT: vse8.v v8, (a1)
+; ZVZIP-NEXT: ret
entry:
%0 = load <8 x i8>, ptr %in, align 1
%shuffle.i5 = shufflevector <8 x i8> %0, <8 x i8> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
@@ -637,6 +774,16 @@ define void @vnsrl_0_i8_single_wideuse(ptr %in, ptr %out) {
; ZIP-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
; ZIP-NEXT: vse8.v v8, (a1)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_0_i8_single_wideuse:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
+; ZVZIP-NEXT: vle8.v v8, (a0)
+; ZVZIP-NEXT: vsetivli zero, 4, e8, mf8, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v8, v8, 0
+; ZVZIP-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
+; ZVZIP-NEXT: vse8.v v8, (a1)
+; ZVZIP-NEXT: ret
entry:
%0 = load <8 x i8>, ptr %in, align 1
%shuffle.i5 = shufflevector <8 x i8> %0, <8 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 poison, i32 poison, i32 poison, i32 poison>
@@ -684,6 +831,18 @@ define void @vnsrl_0_i32_single_src_m8(ptr %in, ptr %out) {
; ZIP-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; ZIP-NEXT: vse32.v v16, (a1)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_0_i32_single_src_m8:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: li a2, 64
+; ZVZIP-NEXT: vsetvli zero, a2, e32, m8, ta, ma
+; ZVZIP-NEXT: vle32.v v8, (a0)
+; ZVZIP-NEXT: li a0, 32
+; ZVZIP-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v16, v8, 0
+; ZVZIP-NEXT: vsetvli zero, a2, e32, m8, ta, ma
+; ZVZIP-NEXT: vse32.v v16, (a1)
+; ZVZIP-NEXT: ret
entry:
%0 = load <64 x i32>, ptr %in, align 4
%shuffle.i5 = shufflevector <64 x i32> %0, <64 x i32> poison, <64 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
@@ -729,6 +888,18 @@ define void @vnsrl_0_i32_single_src_m8_2(ptr %in, ptr %out) {
; ZIP-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; ZIP-NEXT: vse32.v v16, (a1)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_0_i32_single_src_m8_2:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: li a2, 64
+; ZVZIP-NEXT: vsetvli zero, a2, e32, m8, ta, ma
+; ZVZIP-NEXT: vle32.v v8, (a0)
+; ZVZIP-NEXT: li a0, 32
+; ZVZIP-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v16, v8, 0
+; ZVZIP-NEXT: vsetvli zero, a2, e32, m8, ta, ma
+; ZVZIP-NEXT: vse32.v v16, (a1)
+; ZVZIP-NEXT: ret
entry:
%0 = load <64 x i32>, ptr %in, align 4
%shuffle.i5 = shufflevector <64 x i32> %0, <64 x i32> poison, <64 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30, i32 32, i32 34, i32 36, i32 38, i32 40, i32 42, i32 44, i32 46, i32 48, i32 50, i32 52, i32 54, i32 56, i32 58, i32 60, i32 62, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
@@ -775,6 +946,19 @@ define void @vnsrl_0_i8_two_source(ptr %in0, ptr %in1, ptr %out) {
; ZIP-NEXT: vslideup.vi v9, v8, 4
; ZIP-NEXT: vse8.v v9, (a2)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_0_i8_two_source:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
+; ZVZIP-NEXT: vle8.v v8, (a1)
+; ZVZIP-NEXT: vle8.v v9, (a0)
+; ZVZIP-NEXT: vsetivli zero, 4, e8, mf8, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v8, v8, 0
+; ZVZIP-NEXT: vnsrl.wi v9, v9, 0
+; ZVZIP-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
+; ZVZIP-NEXT: vslideup.vi v9, v8, 4
+; ZVZIP-NEXT: vse8.v v9, (a2)
+; ZVZIP-NEXT: ret
entry:
%0 = load <8 x i8>, ptr %in0, align 1
%1 = load <8 x i8>, ptr %in1, align 1
@@ -822,6 +1006,19 @@ define void @vnsrl_8_8_two_source(ptr %in0, ptr %in1, ptr %out) {
; ZIP-NEXT: vslideup.vi v9, v8, 4
; ZIP-NEXT: vse8.v v9, (a2)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_8_8_two_source:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
+; ZVZIP-NEXT: vle8.v v8, (a1)
+; ZVZIP-NEXT: vle8.v v9, (a0)
+; ZVZIP-NEXT: vsetivli zero, 4, e8, mf8, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v8, v8, 8
+; ZVZIP-NEXT: vnsrl.wi v9, v9, 8
+; ZVZIP-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
+; ZVZIP-NEXT: vslideup.vi v9, v8, 4
+; ZVZIP-NEXT: vse8.v v9, (a2)
+; ZVZIP-NEXT: ret
entry:
%0 = load <8 x i8>, ptr %in0, align 1
%1 = load <8 x i8>, ptr %in1, align 1
@@ -869,6 +1066,19 @@ define void @vnsrl_0_i16_two_source(ptr %in0, ptr %in1, ptr %out) {
; ZIP-NEXT: vslideup.vi v9, v8, 2
; ZIP-NEXT: vse16.v v9, (a2)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_0_i16_two_source:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZVZIP-NEXT: vle16.v v8, (a1)
+; ZVZIP-NEXT: vle16.v v9, (a0)
+; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v8, v8, 0
+; ZVZIP-NEXT: vnsrl.wi v9, v9, 0
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZVZIP-NEXT: vslideup.vi v9, v8, 2
+; ZVZIP-NEXT: vse16.v v9, (a2)
+; ZVZIP-NEXT: ret
entry:
%0 = load <4 x i16>, ptr %in0, align 2
%1 = load <4 x i16>, ptr %in1, align 2
@@ -916,6 +1126,19 @@ define void @vnsrl_16_i16_two_source(ptr %in0, ptr %in1, ptr %out) {
; ZIP-NEXT: vslideup.vi v9, v8, 2
; ZIP-NEXT: vse16.v v9, (a2)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_16_i16_two_source:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZVZIP-NEXT: vle16.v v8, (a1)
+; ZVZIP-NEXT: vle16.v v9, (a0)
+; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v8, v8, 16
+; ZVZIP-NEXT: vnsrl.wi v9, v9, 16
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZVZIP-NEXT: vslideup.vi v9, v8, 2
+; ZVZIP-NEXT: vse16.v v9, (a2)
+; ZVZIP-NEXT: ret
entry:
%0 = load <4 x i16>, ptr %in0, align 2
%1 = load <4 x i16>, ptr %in1, align 2
@@ -963,6 +1186,19 @@ define void @vnsrl_0_half_two_source(ptr %in0, ptr %in1, ptr %out) {
; ZIP-NEXT: vslideup.vi v9, v8, 2
; ZIP-NEXT: vse16.v v9, (a2)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_0_half_two_source:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZVZIP-NEXT: vle16.v v8, (a1)
+; ZVZIP-NEXT: vle16.v v9, (a0)
+; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v8, v8, 0
+; ZVZIP-NEXT: vnsrl.wi v9, v9, 0
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZVZIP-NEXT: vslideup.vi v9, v8, 2
+; ZVZIP-NEXT: vse16.v v9, (a2)
+; ZVZIP-NEXT: ret
entry:
%0 = load <4 x half>, ptr %in0, align 2
%1 = load <4 x half>, ptr %in1, align 2
@@ -1010,6 +1246,19 @@ define void @vnsrl_16_half_two_source(ptr %in0, ptr %in1, ptr %out) {
; ZIP-NEXT: vslideup.vi v9, v8, 2
; ZIP-NEXT: vse16.v v9, (a2)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_16_half_two_source:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZVZIP-NEXT: vle16.v v8, (a1)
+; ZVZIP-NEXT: vle16.v v9, (a0)
+; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v8, v8, 16
+; ZVZIP-NEXT: vnsrl.wi v9, v9, 16
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZVZIP-NEXT: vslideup.vi v9, v8, 2
+; ZVZIP-NEXT: vse16.v v9, (a2)
+; ZVZIP-NEXT: ret
entry:
%0 = load <4 x half>, ptr %in0, align 2
%1 = load <4 x half>, ptr %in1, align 2
@@ -1045,6 +1294,15 @@ define void @vnsrl_0_i32_two_source(ptr %in0, ptr %in1, ptr %out) {
; ZIP-NEXT: vslideup.vi v8, v9, 1
; ZIP-NEXT: vse32.v v8, (a2)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_0_i32_two_source:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-NEXT: vle32.v v8, (a0)
+; ZVZIP-NEXT: vle32.v v9, (a1)
+; ZVZIP-NEXT: vslideup.vi v8, v9, 1
+; ZVZIP-NEXT: vse32.v v8, (a2)
+; ZVZIP-NEXT: ret
entry:
%0 = load <2 x i32>, ptr %in0, align 4
%1 = load <2 x i32>, ptr %in1, align 4
@@ -1082,6 +1340,16 @@ define void @vnsrl_32_i32_two_source(ptr %in0, ptr %in1, ptr %out) {
; ZIP-NEXT: ri.vzipodd.vv v10, v8, v9
; ZIP-NEXT: vse32.v v10, (a2)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_32_i32_two_source:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
+; ZVZIP-NEXT: vle32.v v8, (a0)
+; ZVZIP-NEXT: vle32.v v9, (a1)
+; ZVZIP-NEXT: vmv.v.i v0, 1
+; ZVZIP-NEXT: vslidedown.vi v9, v8, 1, v0.t
+; ZVZIP-NEXT: vse32.v v9, (a2)
+; ZVZIP-NEXT: ret
entry:
%0 = load <2 x i32>, ptr %in0, align 4
%1 = load <2 x i32>, ptr %in1, align 4
@@ -1117,6 +1385,15 @@ define void @vnsrl_0_float_two_source(ptr %in0, ptr %in1, ptr %out) {
; ZIP-NEXT: vslideup.vi v8, v9, 1
; ZIP-NEXT: vse32.v v8, (a2)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_0_float_two_source:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-NEXT: vle32.v v8, (a0)
+; ZVZIP-NEXT: vle32.v v9, (a1)
+; ZVZIP-NEXT: vslideup.vi v8, v9, 1
+; ZVZIP-NEXT: vse32.v v8, (a2)
+; ZVZIP-NEXT: ret
entry:
%0 = load <2 x float>, ptr %in0, align 4
%1 = load <2 x float>, ptr %in1, align 4
@@ -1154,6 +1431,16 @@ define void @vnsrl_32_float_two_source(ptr %in0, ptr %in1, ptr %out) {
; ZIP-NEXT: ri.vzipodd.vv v10, v8, v9
; ZIP-NEXT: vse32.v v10, (a2)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_32_float_two_source:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
+; ZVZIP-NEXT: vle32.v v8, (a0)
+; ZVZIP-NEXT: vle32.v v9, (a1)
+; ZVZIP-NEXT: vmv.v.i v0, 1
+; ZVZIP-NEXT: vslidedown.vi v9, v8, 1, v0.t
+; ZVZIP-NEXT: vse32.v v9, (a2)
+; ZVZIP-NEXT: ret
entry:
%0 = load <2 x float>, ptr %in0, align 4
%1 = load <2 x float>, ptr %in1, align 4
@@ -1189,6 +1476,15 @@ define void @vnsrl_0_i64_two_source(ptr %in0, ptr %in1, ptr %out) {
; ZIP-NEXT: vslideup.vi v8, v9, 1
; ZIP-NEXT: vse64.v v8, (a2)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_0_i64_two_source:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; ZVZIP-NEXT: vle64.v v8, (a0)
+; ZVZIP-NEXT: vle64.v v9, (a1)
+; ZVZIP-NEXT: vslideup.vi v8, v9, 1
+; ZVZIP-NEXT: vse64.v v8, (a2)
+; ZVZIP-NEXT: ret
entry:
%0 = load <2 x i64>, ptr %in0, align 8
%1 = load <2 x i64>, ptr %in1, align 8
@@ -1226,6 +1522,16 @@ define void @vnsrl_64_i64_two_source(ptr %in0, ptr %in1, ptr %out) {
; ZIP-NEXT: ri.vzipodd.vv v10, v8, v9
; ZIP-NEXT: vse64.v v10, (a2)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_64_i64_two_source:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, mu
+; ZVZIP-NEXT: vle64.v v8, (a0)
+; ZVZIP-NEXT: vle64.v v9, (a1)
+; ZVZIP-NEXT: vmv.v.i v0, 1
+; ZVZIP-NEXT: vslidedown.vi v9, v8, 1, v0.t
+; ZVZIP-NEXT: vse64.v v9, (a2)
+; ZVZIP-NEXT: ret
entry:
%0 = load <2 x i64>, ptr %in0, align 8
%1 = load <2 x i64>, ptr %in1, align 8
@@ -1260,6 +1566,15 @@ define void @vnsrl_0_double_two_source(ptr %in0, ptr %in1, ptr %out) {
; ZIP-NEXT: vslideup.vi v8, v9, 1
; ZIP-NEXT: vse64.v v8, (a2)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_0_double_two_source:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; ZVZIP-NEXT: vle64.v v8, (a0)
+; ZVZIP-NEXT: vle64.v v9, (a1)
+; ZVZIP-NEXT: vslideup.vi v8, v9, 1
+; ZVZIP-NEXT: vse64.v v8, (a2)
+; ZVZIP-NEXT: ret
entry:
%0 = load <2 x double>, ptr %in0, align 8
%1 = load <2 x double>, ptr %in1, align 8
@@ -1295,6 +1610,16 @@ define void @vnsrl_64_double_two_source(ptr %in0, ptr %in1, ptr %out) {
; ZIP-NEXT: ri.vzipodd.vv v10, v8, v9
; ZIP-NEXT: vse64.v v10, (a2)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_64_double_two_source:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, mu
+; ZVZIP-NEXT: vle64.v v8, (a0)
+; ZVZIP-NEXT: vle64.v v9, (a1)
+; ZVZIP-NEXT: vmv.v.i v0, 1
+; ZVZIP-NEXT: vslidedown.vi v9, v8, 1, v0.t
+; ZVZIP-NEXT: vse64.v v9, (a2)
+; ZVZIP-NEXT: ret
entry:
%0 = load <2 x double>, ptr %in0, align 8
%1 = load <2 x double>, ptr %in1, align 8
@@ -1320,6 +1645,12 @@ define <2 x i64> @unzip2a_dual_v2i64(<2 x i64> %a, <2 x i64> %b) {
; ZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; ZIP-NEXT: vslideup.vi v8, v9, 1
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: unzip2a_dual_v2i64:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; ZVZIP-NEXT: vslideup.vi v8, v9, 1
+; ZVZIP-NEXT: ret
entry:
%c = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 0, i32 2>
ret <2 x i64> %c
@@ -1370,6 +1701,18 @@ define <4 x i64> @unzip2a_dual_v4i64(<4 x i64> %a, <4 x i64> %b) {
; ZIP-NEXT: vslideup.vi v9, v11, 2
; ZIP-NEXT: vmv.v.v v8, v9
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: unzip2a_dual_v4i64:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 4, e64, m1, ta, mu
+; ZVZIP-NEXT: vmv.v.i v0, 8
+; ZVZIP-NEXT: vslideup.vi v10, v9, 2
+; ZVZIP-NEXT: vslideup.vi v10, v9, 1, v0.t
+; ZVZIP-NEXT: vmv.v.i v0, 2
+; ZVZIP-NEXT: vslidedown.vi v8, v8, 1, v0.t
+; ZVZIP-NEXT: vmv.v.i v0, 12
+; ZVZIP-NEXT: vmerge.vvm v8, v8, v10, v0
+; ZVZIP-NEXT: ret
entry:
%c = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
ret <4 x i64> %c
@@ -1506,6 +1849,25 @@ define <16 x i64> @unzip2a_dual_v16i64(<16 x i64> %a, <16 x i64> %b) {
; ZIP-NEXT: vslideup.vi v12, v16, 8
; ZIP-NEXT: vmv.v.v v8, v12
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: unzip2a_dual_v16i64:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 16, e16, m1, ta, ma
+; ZVZIP-NEXT: vid.v v16
+; ZVZIP-NEXT: lui a0, 5
+; ZVZIP-NEXT: addi a0, a0, 1365
+; ZVZIP-NEXT: vmv.s.x v20, a0
+; ZVZIP-NEXT: li a0, -256
+; ZVZIP-NEXT: vadd.vv v21, v16, v16
+; ZVZIP-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; ZVZIP-NEXT: vcompress.vm v16, v8, v20
+; ZVZIP-NEXT: vmv.s.x v0, a0
+; ZVZIP-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vadd.vi v8, v21, -16
+; ZVZIP-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; ZVZIP-NEXT: vrgatherei16.vv v16, v12, v8, v0.t
+; ZVZIP-NEXT: vmv.v.v v8, v16
+; ZVZIP-NEXT: ret
entry:
%c = shufflevector <16 x i64> %a, <16 x i64> %b, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
ret <16 x i64> %c
@@ -1554,6 +1916,18 @@ define <4 x i64> @unzip2a_dual_v4i64_exact(<4 x i64> %a, <4 x i64> %b) vscale_ra
; ZIP-NEXT: ri.vunzip2a.vv v10, v8, v9
; ZIP-NEXT: vmv.v.v v8, v10
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: unzip2a_dual_v4i64_exact:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 4, e64, m1, ta, mu
+; ZVZIP-NEXT: vmv.v.i v0, 8
+; ZVZIP-NEXT: vslideup.vi v10, v9, 2
+; ZVZIP-NEXT: vslideup.vi v10, v9, 1, v0.t
+; ZVZIP-NEXT: vmv.v.i v0, 2
+; ZVZIP-NEXT: vslidedown.vi v8, v8, 1, v0.t
+; ZVZIP-NEXT: vmv.v.i v0, 12
+; ZVZIP-NEXT: vmerge.vvm v8, v8, v10, v0
+; ZVZIP-NEXT: ret
entry:
%c = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
ret <4 x i64> %c
@@ -1603,6 +1977,18 @@ define <4 x i64> @unzip2a_dual_v4i64_exact_nf2(<4 x i64> %a, <4 x i64> %b) vscal
; ZIP-NEXT: ri.vunzip2a.vv v9, v8, v10
; ZIP-NEXT: vmv.v.v v8, v9
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: unzip2a_dual_v4i64_exact_nf2:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 4, e64, m1, ta, mu
+; ZVZIP-NEXT: vmv.v.i v0, 8
+; ZVZIP-NEXT: vslideup.vi v10, v9, 2
+; ZVZIP-NEXT: vslideup.vi v10, v9, 1, v0.t
+; ZVZIP-NEXT: vmv.v.i v0, 2
+; ZVZIP-NEXT: vslidedown.vi v8, v8, 1, v0.t
+; ZVZIP-NEXT: vmv.v.i v0, 12
+; ZVZIP-NEXT: vmerge.vvm v8, v8, v10, v0
+; ZVZIP-NEXT: ret
entry:
%c = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
ret <4 x i64> %c
@@ -1730,6 +2116,46 @@ define <16 x i64> @unzip2a_dual_v16i64_exact(<16 x i64> %a, <16 x i64> %b) vscal
; ZIP-NEXT: ri.vunzip2a.vv v16, v8, v12
; ZIP-NEXT: vmv.v.v v8, v16
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: unzip2a_dual_v16i64_exact:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 4, e64, m1, ta, mu
+; ZVZIP-NEXT: vslideup.vi v19, v15, 2
+; ZVZIP-NEXT: vmv.v.i v16, 8
+; ZVZIP-NEXT: vmv.v.i v17, 2
+; ZVZIP-NEXT: vmv.v.i v18, 12
+; ZVZIP-NEXT: vmv.v.v v0, v16
+; ZVZIP-NEXT: vslideup.vi v19, v15, 1, v0.t
+; ZVZIP-NEXT: vmv.v.v v0, v17
+; ZVZIP-NEXT: vslidedown.vi v14, v14, 1, v0.t
+; ZVZIP-NEXT: vmv.v.v v0, v18
+; ZVZIP-NEXT: vmerge.vvm v15, v14, v19, v0
+; ZVZIP-NEXT: vslideup.vi v14, v13, 2
+; ZVZIP-NEXT: vmv.v.v v0, v16
+; ZVZIP-NEXT: vslideup.vi v14, v13, 1, v0.t
+; ZVZIP-NEXT: vmv.v.v v0, v17
+; ZVZIP-NEXT: vslidedown.vi v12, v12, 1, v0.t
+; ZVZIP-NEXT: vmv.v.v v0, v18
+; ZVZIP-NEXT: vmerge.vvm v14, v12, v14, v0
+; ZVZIP-NEXT: vslideup.vi v12, v11, 2
+; ZVZIP-NEXT: li a0, -256
+; ZVZIP-NEXT: vmv.v.v v0, v16
+; ZVZIP-NEXT: vslideup.vi v12, v11, 1, v0.t
+; ZVZIP-NEXT: vmv.v.v v0, v17
+; ZVZIP-NEXT: vslidedown.vi v10, v10, 1, v0.t
+; ZVZIP-NEXT: vmv.v.v v0, v18
+; ZVZIP-NEXT: vmerge.vvm v13, v10, v12, v0
+; ZVZIP-NEXT: vslideup.vi v10, v9, 2
+; ZVZIP-NEXT: vmv.v.v v0, v16
+; ZVZIP-NEXT: vslideup.vi v10, v9, 1, v0.t
+; ZVZIP-NEXT: vmv.v.v v0, v17
+; ZVZIP-NEXT: vslidedown.vi v8, v8, 1, v0.t
+; ZVZIP-NEXT: vmv.v.v v0, v18
+; ZVZIP-NEXT: vmerge.vvm v12, v8, v10, v0
+; ZVZIP-NEXT: vmv.s.x v0, a0
+; ZVZIP-NEXT: vsetivli zero, 16, e64, m4, ta, ma
+; ZVZIP-NEXT: vmerge.vvm v8, v12, v12, v0
+; ZVZIP-NEXT: ret
entry:
%c = shufflevector <16 x i64> %a, <16 x i64> %b, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
ret <16 x i64> %c
@@ -1781,6 +2207,19 @@ define <4 x i64> @unzip2b_dual_v4i64(<4 x i64> %a, <4 x i64> %b) {
; ZIP-NEXT: vslideup.vi v9, v11, 2
; ZIP-NEXT: vmv.v.v v8, v9
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: unzip2b_dual_v4i64:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 4, e64, m1, ta, mu
+; ZVZIP-NEXT: vmv.v.i v0, 2
+; ZVZIP-NEXT: vslidedown.vi v10, v8, 1
+; ZVZIP-NEXT: vslidedown.vi v10, v8, 2, v0.t
+; ZVZIP-NEXT: vmv.v.i v0, 4
+; ZVZIP-NEXT: vmv1r.v v8, v9
+; ZVZIP-NEXT: vslideup.vi v8, v9, 1, v0.t
+; ZVZIP-NEXT: vmv.v.i v0, 12
+; ZVZIP-NEXT: vmerge.vvm v8, v10, v8, v0
+; ZVZIP-NEXT: ret
entry:
%c = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
ret <4 x i64> %c
@@ -1830,6 +2269,19 @@ define <4 x i64> @unzip2b_dual_v4i64_exact(<4 x i64> %a, <4 x i64> %b) vscale_ra
; ZIP-NEXT: ri.vunzip2b.vv v10, v8, v9
; ZIP-NEXT: vmv.v.v v8, v10
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: unzip2b_dual_v4i64_exact:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 4, e64, m1, ta, mu
+; ZVZIP-NEXT: vmv.v.i v0, 2
+; ZVZIP-NEXT: vslidedown.vi v10, v8, 1
+; ZVZIP-NEXT: vslidedown.vi v10, v8, 2, v0.t
+; ZVZIP-NEXT: vmv.v.i v0, 4
+; ZVZIP-NEXT: vmv1r.v v8, v9
+; ZVZIP-NEXT: vslideup.vi v8, v9, 1, v0.t
+; ZVZIP-NEXT: vmv.v.i v0, 12
+; ZVZIP-NEXT: vmerge.vvm v8, v10, v8, v0
+; ZVZIP-NEXT: ret
entry:
%c = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
ret <4 x i64> %c
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll
index bb33b906a11ad..1ccb16f7946d9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll
@@ -5,6 +5,8 @@
; RUN: llc -mtriple=riscv64 -mattr=+v,+m,+zvl512b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,V512,RV64-V512
; RUN: llc -mtriple=riscv32 -mattr=+v,+m,+experimental-xrivosvizip -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZIP,RV32-ZIP
; RUN: llc -mtriple=riscv64 -mattr=+v,+m,+experimental-xrivosvizip -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZIP,RV64-ZIP
+; RUN: llc -mtriple=riscv32 -mattr=+v,+m,+experimental-zvzip -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVZIP,RV32-ZVZIP
+; RUN: llc -mtriple=riscv64 -mattr=+v,+m,+experimental-zvzip -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVZIP,RV64-ZVZIP
; Test optimizing interleaves to widening arithmetic.
@@ -24,6 +26,15 @@ define <4 x i8> @interleave_v2i8(<2 x i8> %x, <2 x i8> %y) {
; ZIP-NEXT: ri.vzip2a.vv v10, v8, v9
; ZIP-NEXT: vmv1r.v v8, v10
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: interleave_v2i8:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; ZVZIP-NEXT: vwaddu.vv v10, v8, v9
+; ZVZIP-NEXT: li a0, -1
+; ZVZIP-NEXT: vwmaccu.vx v10, a0, v9
+; ZVZIP-NEXT: vmv1r.v v8, v10
+; ZVZIP-NEXT: ret
%a = shufflevector <2 x i8> %x, <2 x i8> %y, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
ret <4 x i8> %a
}
@@ -44,6 +55,15 @@ define <4 x i16> @interleave_v2i16(<2 x i16> %x, <2 x i16> %y) {
; ZIP-NEXT: ri.vzip2a.vv v10, v8, v9
; ZIP-NEXT: vmv1r.v v8, v10
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: interleave_v2i16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-NEXT: vwaddu.vv v10, v8, v9
+; ZVZIP-NEXT: li a0, -1
+; ZVZIP-NEXT: vwmaccu.vx v10, a0, v9
+; ZVZIP-NEXT: vmv1r.v v8, v10
+; ZVZIP-NEXT: ret
%a = shufflevector <2 x i16> %x, <2 x i16> %y, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
ret <4 x i16> %a
}
@@ -65,6 +85,15 @@ define <4 x i32> @interleave_v2i32(<2 x i32> %x, <2 x i32> %y) {
; ZIP-NEXT: ri.vzip2a.vv v10, v9, v8
; ZIP-NEXT: vmv.v.v v8, v10
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: interleave_v2i32:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-NEXT: vwaddu.vv v10, v9, v8
+; ZVZIP-NEXT: li a0, -1
+; ZVZIP-NEXT: vwmaccu.vx v10, a0, v8
+; ZVZIP-NEXT: vmv1r.v v8, v10
+; ZVZIP-NEXT: ret
%a = shufflevector <2 x i32> %x, <2 x i32> %y, <4 x i32> <i32 2, i32 0, i32 3, i32 1>
ret <4 x i32> %a
}
@@ -103,6 +132,19 @@ define <4 x i64> @interleave_v2i64(<2 x i64> %x, <2 x i64> %y) {
; ZIP-NEXT: ri.vzip2a.vv v10, v8, v12
; ZIP-NEXT: vmv.v.v v8, v10
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: interleave_v2i64:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; ZVZIP-NEXT: vmv1r.v v10, v9
+; ZVZIP-NEXT: vmv.v.i v0, 10
+; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; ZVZIP-NEXT: vslideup.vi v12, v10, 1
+; ZVZIP-NEXT: vslideup.vi v12, v10, 2
+; ZVZIP-NEXT: vmv2r.v v10, v8
+; ZVZIP-NEXT: vslideup.vi v10, v8, 1
+; ZVZIP-NEXT: vmerge.vvm v8, v10, v12, v0
+; ZVZIP-NEXT: ret
%a = shufflevector <2 x i64> %x, <2 x i64> %y, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
ret <4 x i64> %a
}
@@ -133,6 +175,15 @@ define <8 x i8> @interleave_v4i8(<4 x i8> %x, <4 x i8> %y) {
; ZIP-NEXT: ri.vzip2a.vv v10, v9, v8
; ZIP-NEXT: vmv1r.v v8, v10
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: interleave_v4i8:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; ZVZIP-NEXT: vwaddu.vv v10, v9, v8
+; ZVZIP-NEXT: li a0, -1
+; ZVZIP-NEXT: vwmaccu.vx v10, a0, v8
+; ZVZIP-NEXT: vmv1r.v v8, v10
+; ZVZIP-NEXT: ret
%a = shufflevector <4 x i8> %x, <4 x i8> %y, <8 x i32> <i32 4, i32 0, i32 5, i32 1, i32 6, i32 2, i32 7, i32 3>
ret <8 x i8> %a
}
@@ -163,6 +214,15 @@ define <8 x i16> @interleave_v4i16(<4 x i16> %x, <4 x i16> %y) {
; ZIP-NEXT: ri.vzip2a.vv v10, v8, v9
; ZIP-NEXT: vmv.v.v v8, v10
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: interleave_v4i16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVZIP-NEXT: vwaddu.vv v10, v8, v9
+; ZVZIP-NEXT: li a0, -1
+; ZVZIP-NEXT: vwmaccu.vx v10, a0, v9
+; ZVZIP-NEXT: vmv1r.v v8, v10
+; ZVZIP-NEXT: ret
%a = shufflevector <4 x i16> %x, <4 x i16> %y, <8 x i32> <i32 0, i32 4, i32 poison, i32 5, i32 2, i32 poison, i32 3, i32 7>
ret <8 x i16> %a
}
@@ -194,6 +254,16 @@ define <8 x i32> @interleave_v4i32(<4 x i32> %x, <4 x i32> %y) {
; ZIP-NEXT: ri.vzip2a.vv v10, v8, v12
; ZIP-NEXT: vmv.v.v v8, v10
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: interleave_v4i32:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVZIP-NEXT: vmv1r.v v10, v9
+; ZVZIP-NEXT: vmv1r.v v11, v8
+; ZVZIP-NEXT: vwaddu.vv v8, v11, v10
+; ZVZIP-NEXT: li a0, -1
+; ZVZIP-NEXT: vwmaccu.vx v8, a0, v10
+; ZVZIP-NEXT: ret
%a = shufflevector <4 x i32> %x, <4 x i32> %y, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
ret <8 x i32> %a
}
@@ -229,6 +299,17 @@ define <4 x i32> @interleave_v4i32_offset_2(<4 x i32> %x, <4 x i32> %y) {
; ZIP-NEXT: ri.vzip2a.vv v9, v8, v10
; ZIP-NEXT: vmv.v.v v8, v9
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: interleave_v4i32_offset_2:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; ZVZIP-NEXT: vslidedown.vi v10, v9, 2
+; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-NEXT: vwaddu.vv v9, v8, v10
+; ZVZIP-NEXT: li a0, -1
+; ZVZIP-NEXT: vwmaccu.vx v9, a0, v10
+; ZVZIP-NEXT: vmv1r.v v8, v9
+; ZVZIP-NEXT: ret
%a = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 0, i32 6, i32 1, i32 7>
ret <4 x i32> %a
}
@@ -271,6 +352,19 @@ define <4 x i32> @interleave_v4i32_offset_1(<4 x i32> %x, <4 x i32> %y) {
; ZIP-NEXT: ri.vzip2a.vv v11, v8, v9
; ZIP-NEXT: vmerge.vvm v8, v11, v10, v0
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: interleave_v4i32_offset_1:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, mu
+; ZVZIP-NEXT: vmv.v.i v0, 8
+; ZVZIP-NEXT: vmv1r.v v10, v9
+; ZVZIP-NEXT: vslideup.vi v10, v9, 1, v0.t
+; ZVZIP-NEXT: vmv.v.i v0, 10
+; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; ZVZIP-NEXT: vzext.vf2 v9, v8
+; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVZIP-NEXT: vmerge.vvm v8, v9, v10, v0
+; ZVZIP-NEXT: ret
%a = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 0, i32 5, i32 1, i32 6>
ret <4 x i32> %a
}
@@ -300,6 +394,15 @@ define <16 x i8> @interleave_v8i8(<8 x i8> %x, <8 x i8> %y) {
; ZIP-NEXT: ri.vzip2a.vv v10, v8, v9
; ZIP-NEXT: vmv.v.v v8, v10
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: interleave_v8i8:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; ZVZIP-NEXT: vwaddu.vv v10, v8, v9
+; ZVZIP-NEXT: li a0, -1
+; ZVZIP-NEXT: vwmaccu.vx v10, a0, v9
+; ZVZIP-NEXT: vmv1r.v v8, v10
+; ZVZIP-NEXT: ret
%a = shufflevector <8 x i8> %x, <8 x i8> %y, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
ret <16 x i8> %a
}
@@ -332,6 +435,16 @@ define <16 x i16> @interleave_v8i16(<8 x i16> %x, <8 x i16> %y) {
; ZIP-NEXT: ri.vzip2a.vv v10, v12, v8
; ZIP-NEXT: vmv.v.v v8, v10
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: interleave_v8i16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVZIP-NEXT: vmv1r.v v10, v9
+; ZVZIP-NEXT: vmv1r.v v11, v8
+; ZVZIP-NEXT: vwaddu.vv v8, v10, v11
+; ZVZIP-NEXT: li a0, -1
+; ZVZIP-NEXT: vwmaccu.vx v8, a0, v11
+; ZVZIP-NEXT: ret
%a = shufflevector <8 x i16> %x, <8 x i16> %y, <16 x i32> <i32 8, i32 0, i32 9, i32 1, i32 10, i32 2, i32 11, i32 3, i32 12, i32 4, i32 13, i32 5, i32 14, i32 6, i32 15, i32 7>
ret <16 x i16> %a
}
@@ -363,6 +476,16 @@ define <16 x i32> @interleave_v8i32(<8 x i32> %x, <8 x i32> %y) {
; ZIP-NEXT: ri.vzip2a.vv v12, v8, v16
; ZIP-NEXT: vmv.v.v v8, v12
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: interleave_v8i32:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; ZVZIP-NEXT: vmv2r.v v12, v10
+; ZVZIP-NEXT: vmv2r.v v14, v8
+; ZVZIP-NEXT: vwaddu.vv v8, v14, v12
+; ZVZIP-NEXT: li a0, -1
+; ZVZIP-NEXT: vwmaccu.vx v8, a0, v12
+; ZVZIP-NEXT: ret
%a = shufflevector <8 x i32> %x, <8 x i32> %y, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
ret <16 x i32> %a
}
@@ -395,6 +518,16 @@ define <32 x i8> @interleave_v16i8(<16 x i8> %x, <16 x i8> %y) {
; ZIP-NEXT: ri.vzip2a.vv v10, v8, v12
; ZIP-NEXT: vmv.v.v v8, v10
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: interleave_v16i8:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; ZVZIP-NEXT: vmv1r.v v10, v9
+; ZVZIP-NEXT: vmv1r.v v11, v8
+; ZVZIP-NEXT: vwaddu.vv v8, v11, v10
+; ZVZIP-NEXT: li a0, -1
+; ZVZIP-NEXT: vwmaccu.vx v8, a0, v10
+; ZVZIP-NEXT: ret
%a = shufflevector <16 x i8> %x, <16 x i8> %y, <32 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
ret <32 x i8> %a
}
@@ -427,6 +560,16 @@ define <32 x i16> @interleave_v16i16(<16 x i16> %x, <16 x i16> %y) {
; ZIP-NEXT: ri.vzip2a.vv v12, v8, v16
; ZIP-NEXT: vmv.v.v v8, v12
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: interleave_v16i16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVZIP-NEXT: vmv2r.v v12, v10
+; ZVZIP-NEXT: vmv2r.v v14, v8
+; ZVZIP-NEXT: vwaddu.vv v8, v14, v12
+; ZVZIP-NEXT: li a0, -1
+; ZVZIP-NEXT: vwmaccu.vx v8, a0, v12
+; ZVZIP-NEXT: ret
%a = shufflevector <16 x i16> %x, <16 x i16> %y, <32 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
ret <32 x i16> %a
}
@@ -460,6 +603,16 @@ define <32 x i32> @interleave_v16i32(<16 x i32> %x, <16 x i32> %y) {
; ZIP-NEXT: ri.vzip2a.vv v16, v8, v24
; ZIP-NEXT: vmv.v.v v8, v16
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: interleave_v16i32:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; ZVZIP-NEXT: vmv4r.v v16, v12
+; ZVZIP-NEXT: vmv4r.v v20, v8
+; ZVZIP-NEXT: vwaddu.vv v8, v20, v16
+; ZVZIP-NEXT: li a0, -1
+; ZVZIP-NEXT: vwmaccu.vx v8, a0, v16
+; ZVZIP-NEXT: ret
%a = shufflevector <16 x i32> %x, <16 x i32> %y, <32 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
ret <32 x i32> %a
}
@@ -494,6 +647,17 @@ define <64 x i8> @interleave_v32i8(<32 x i8> %x, <32 x i8> %y) {
; ZIP-NEXT: ri.vzip2a.vv v12, v8, v16
; ZIP-NEXT: vmv.v.v v8, v12
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: interleave_v32i8:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: li a0, 32
+; ZVZIP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
+; ZVZIP-NEXT: vmv2r.v v12, v10
+; ZVZIP-NEXT: vmv2r.v v14, v8
+; ZVZIP-NEXT: vwaddu.vv v8, v14, v12
+; ZVZIP-NEXT: li a0, -1
+; ZVZIP-NEXT: vwmaccu.vx v8, a0, v12
+; ZVZIP-NEXT: ret
%a = shufflevector <32 x i8> %x, <32 x i8> %y, <64 x i32> <i32 0, i32 32, i32 1, i32 33, i32 2, i32 34, i32 3, i32 35, i32 4, i32 36, i32 5, i32 37, i32 6, i32 38, i32 7, i32 39, i32 8, i32 40, i32 9, i32 41, i32 10, i32 42, i32 11, i32 43, i32 12, i32 44, i32 13, i32 45, i32 14, i32 46, i32 15, i32 47, i32 16, i32 48, i32 17, i32 49, i32 18, i32 50, i32 19, i32 51, i32 20, i32 52, i32 21, i32 53, i32 22, i32 54, i32 23, i32 55, i32 24, i32 56, i32 25, i32 57, i32 26, i32 58, i32 27, i32 59, i32 28, i32 60, i32 29, i32 61, i32 30, i32 62, i32 31, i32 63>
ret <64 x i8> %a
}
@@ -529,6 +693,17 @@ define <64 x i16> @interleave_v32i16(<32 x i16> %x, <32 x i16> %y) {
; ZIP-NEXT: ri.vzip2a.vv v16, v8, v24
; ZIP-NEXT: vmv.v.v v8, v16
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: interleave_v32i16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: li a0, 32
+; ZVZIP-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; ZVZIP-NEXT: vmv4r.v v16, v12
+; ZVZIP-NEXT: vmv4r.v v20, v8
+; ZVZIP-NEXT: vwaddu.vv v8, v20, v16
+; ZVZIP-NEXT: li a0, -1
+; ZVZIP-NEXT: vwmaccu.vx v8, a0, v16
+; ZVZIP-NEXT: ret
%a = shufflevector <32 x i16> %x, <32 x i16> %y, <64 x i32> <i32 0, i32 32, i32 1, i32 33, i32 2, i32 34, i32 3, i32 35, i32 4, i32 36, i32 5, i32 37, i32 6, i32 38, i32 7, i32 39, i32 8, i32 40, i32 9, i32 41, i32 10, i32 42, i32 11, i32 43, i32 12, i32 44, i32 13, i32 45, i32 14, i32 46, i32 15, i32 47, i32 16, i32 48, i32 17, i32 49, i32 18, i32 50, i32 19, i32 51, i32 20, i32 52, i32 21, i32 53, i32 22, i32 54, i32 23, i32 55, i32 24, i32 56, i32 25, i32 57, i32 26, i32 58, i32 27, i32 59, i32 28, i32 60, i32 29, i32 61, i32 30, i32 62, i32 31, i32 63>
ret <64 x i16> %a
}
@@ -668,6 +843,45 @@ define <64 x i32> @interleave_v32i32(<32 x i32> %x, <32 x i32> %y) {
; ZIP-NEXT: addi sp, sp, 16
; ZIP-NEXT: .cfi_def_cfa_offset 0
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: interleave_v32i32:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: addi sp, sp, -16
+; ZVZIP-NEXT: .cfi_def_cfa_offset 16
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 3
+; ZVZIP-NEXT: sub sp, sp, a0
+; ZVZIP-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; ZVZIP-NEXT: addi a0, sp, 16
+; ZVZIP-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vsetivli zero, 16, e32, m8, ta, ma
+; ZVZIP-NEXT: vslidedown.vi v24, v16, 16
+; ZVZIP-NEXT: li a0, 32
+; ZVZIP-NEXT: lui a1, 699051
+; ZVZIP-NEXT: vslidedown.vi v0, v8, 16
+; ZVZIP-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; ZVZIP-NEXT: vzext.vf2 v8, v24
+; ZVZIP-NEXT: addi a1, a1, -1366
+; ZVZIP-NEXT: vzext.vf2 v24, v0
+; ZVZIP-NEXT: vmv.s.x v0, a1
+; ZVZIP-NEXT: vsll.vx v8, v8, a0
+; ZVZIP-NEXT: vsetvli zero, a0, e32, m8, ta, ma
+; ZVZIP-NEXT: vmerge.vvm v24, v24, v8, v0
+; ZVZIP-NEXT: addi a0, sp, 16
+; ZVZIP-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; ZVZIP-NEXT: vwaddu.vv v0, v8, v16
+; ZVZIP-NEXT: li a0, -1
+; ZVZIP-NEXT: vwmaccu.vx v0, a0, v16
+; ZVZIP-NEXT: vmv8r.v v8, v0
+; ZVZIP-NEXT: vmv8r.v v16, v24
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 3
+; ZVZIP-NEXT: add sp, sp, a0
+; ZVZIP-NEXT: .cfi_def_cfa sp, 16
+; ZVZIP-NEXT: addi sp, sp, 16
+; ZVZIP-NEXT: .cfi_def_cfa_offset 0
+; ZVZIP-NEXT: ret
%a = shufflevector <32 x i32> %x, <32 x i32> %y, <64 x i32> <i32 0, i32 32, i32 1, i32 33, i32 2, i32 34, i32 3, i32 35, i32 4, i32 36, i32 5, i32 37, i32 6, i32 38, i32 7, i32 39, i32 8, i32 40, i32 9, i32 41, i32 10, i32 42, i32 11, i32 43, i32 12, i32 44, i32 13, i32 45, i32 14, i32 46, i32 15, i32 47, i32 16, i32 48, i32 17, i32 49, i32 18, i32 50, i32 19, i32 51, i32 20, i32 52, i32 21, i32 53, i32 22, i32 54, i32 23, i32 55, i32 24, i32 56, i32 25, i32 57, i32 26, i32 58, i32 27, i32 59, i32 28, i32 60, i32 29, i32 61, i32 30, i32 62, i32 31, i32 63>
ret <64 x i32> %a
}
@@ -702,6 +916,17 @@ define <4 x i8> @unary_interleave_v4i8(<4 x i8> %x) {
; ZIP-NEXT: ri.vzip2a.vv v9, v8, v10
; ZIP-NEXT: vmv1r.v v8, v9
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: unary_interleave_v4i8:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; ZVZIP-NEXT: vslidedown.vi v10, v8, 2
+; ZVZIP-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; ZVZIP-NEXT: vwaddu.vv v9, v8, v10
+; ZVZIP-NEXT: li a0, -1
+; ZVZIP-NEXT: vwmaccu.vx v9, a0, v10
+; ZVZIP-NEXT: vmv1r.v v8, v9
+; ZVZIP-NEXT: ret
%a = shufflevector <4 x i8> %x, <4 x i8> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
ret <4 x i8> %a
}
@@ -740,6 +965,17 @@ define <4 x i8> @unary_interleave_v4i8_invalid(<4 x i8> %x) {
; ZIP-NEXT: vrgather.vv v9, v8, v10
; ZIP-NEXT: vmv1r.v v8, v9
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: unary_interleave_v4i8_invalid:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: lui a0, 16
+; ZVZIP-NEXT: addi a0, a0, 768
+; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVZIP-NEXT: vmv.s.x v10, a0
+; ZVZIP-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; ZVZIP-NEXT: vrgather.vv v9, v8, v10
+; ZVZIP-NEXT: vmv1r.v v8, v9
+; ZVZIP-NEXT: ret
%a = shufflevector <4 x i8> %x, <4 x i8> poison, <4 x i32> <i32 0, i32 3, i32 1, i32 4>
ret <4 x i8> %a
}
@@ -774,6 +1010,17 @@ define <4 x i16> @unary_interleave_v4i16(<4 x i16> %x) {
; ZIP-NEXT: ri.vzip2a.vv v9, v8, v10
; ZIP-NEXT: vmv1r.v v8, v9
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: unary_interleave_v4i16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
+; ZVZIP-NEXT: vslidedown.vi v10, v8, 2
+; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-NEXT: vwaddu.vv v9, v8, v10
+; ZVZIP-NEXT: li a0, -1
+; ZVZIP-NEXT: vwmaccu.vx v9, a0, v10
+; ZVZIP-NEXT: vmv1r.v v8, v9
+; ZVZIP-NEXT: ret
%a = shufflevector <4 x i16> %x, <4 x i16> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
ret <4 x i16> %a
}
@@ -808,6 +1055,17 @@ define <4 x i32> @unary_interleave_v4i32(<4 x i32> %x) {
; ZIP-NEXT: ri.vzip2a.vv v9, v8, v10
; ZIP-NEXT: vmv.v.v v8, v9
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: unary_interleave_v4i32:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; ZVZIP-NEXT: vslidedown.vi v10, v8, 2
+; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-NEXT: vwaddu.vv v9, v8, v10
+; ZVZIP-NEXT: li a0, -1
+; ZVZIP-NEXT: vwmaccu.vx v9, a0, v10
+; ZVZIP-NEXT: vmv1r.v v8, v9
+; ZVZIP-NEXT: ret
%a = shufflevector <4 x i32> %x, <4 x i32> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
ret <4 x i32> %a
}
@@ -859,6 +1117,19 @@ define <4 x i64> @unary_interleave_v4i64(<4 x i64> %x) {
; ZIP-NEXT: ri.vzip2a.vv v10, v8, v12
; ZIP-NEXT: vmv.v.v v8, v10
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: unary_interleave_v4i64:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: lui a0, 12304
+; ZVZIP-NEXT: addi a0, a0, 512
+; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVZIP-NEXT: vmv.s.x v10, a0
+; ZVZIP-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVZIP-NEXT: vsext.vf2 v12, v10
+; ZVZIP-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; ZVZIP-NEXT: vrgatherei16.vv v10, v8, v12
+; ZVZIP-NEXT: vmv.v.v v8, v10
+; ZVZIP-NEXT: ret
%a = shufflevector <4 x i64> %x, <4 x i64> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
ret <4 x i64> %a
}
@@ -893,6 +1164,17 @@ define <8 x i8> @unary_interleave_v8i8(<8 x i8> %x) {
; ZIP-NEXT: ri.vzip2a.vv v9, v8, v10
; ZIP-NEXT: vmv1r.v v8, v9
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: unary_interleave_v8i8:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; ZVZIP-NEXT: vslidedown.vi v10, v8, 4
+; ZVZIP-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; ZVZIP-NEXT: vwaddu.vv v9, v8, v10
+; ZVZIP-NEXT: li a0, -1
+; ZVZIP-NEXT: vwmaccu.vx v9, a0, v10
+; ZVZIP-NEXT: vmv1r.v v8, v9
+; ZVZIP-NEXT: ret
%a = shufflevector <8 x i8> %x, <8 x i8> poison, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 poison, i32 6, i32 3, i32 7>
ret <8 x i8> %a
}
@@ -927,6 +1209,17 @@ define <8 x i16> @unary_interleave_v8i16(<8 x i16> %x) {
; ZIP-NEXT: ri.vzip2a.vv v9, v10, v8
; ZIP-NEXT: vmv.v.v v8, v9
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: unary_interleave_v8i16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 4, e16, m1, ta, ma
+; ZVZIP-NEXT: vslidedown.vi v10, v8, 4
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVZIP-NEXT: vwaddu.vv v9, v10, v8
+; ZVZIP-NEXT: li a0, -1
+; ZVZIP-NEXT: vwmaccu.vx v9, a0, v8
+; ZVZIP-NEXT: vmv1r.v v8, v9
+; ZVZIP-NEXT: ret
%a = shufflevector <8 x i16> %x, <8 x i16> poison, <8 x i32> <i32 4, i32 poison, i32 5, i32 1, i32 6, i32 2, i32 7, i32 3>
ret <8 x i16> %a
}
@@ -961,6 +1254,17 @@ define <8 x i32> @unary_interleave_v8i32(<8 x i32> %x) {
; ZIP-NEXT: ri.vzip2a.vv v10, v8, v12
; ZIP-NEXT: vmv.v.v v8, v10
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: unary_interleave_v8i32:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 4, e32, m2, ta, ma
+; ZVZIP-NEXT: vslidedown.vi v12, v8, 4
+; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVZIP-NEXT: vwaddu.vv v10, v8, v12
+; ZVZIP-NEXT: li a0, -1
+; ZVZIP-NEXT: vwmaccu.vx v10, a0, v12
+; ZVZIP-NEXT: vmv2r.v v8, v10
+; ZVZIP-NEXT: ret
%a = shufflevector <8 x i32> %x, <8 x i32> poison, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
ret <8 x i32> %a
}
@@ -983,6 +1287,14 @@ define <4 x i8> @unary_interleave_10uu_v4i8(<4 x i8> %x) {
; ZIP-NEXT: vsll.vi v8, v8, 8
; ZIP-NEXT: vor.vv v8, v8, v9
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: unary_interleave_10uu_v4i8:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-NEXT: vsrl.vi v9, v8, 8
+; ZVZIP-NEXT: vsll.vi v8, v8, 8
+; ZVZIP-NEXT: vor.vv v8, v8, v9
+; ZVZIP-NEXT: ret
%a = shufflevector <4 x i8> %x, <4 x i8> poison, <4 x i32> <i32 1, i32 0, i32 poison, i32 poison>
ret <4 x i8> %a
}
@@ -1014,6 +1326,16 @@ define <16 x i16> @interleave_slp(<8 x i16> %v0, <8 x i16> %v1) {
; ZIP-NEXT: ri.vzip2a.vv v10, v8, v12
; ZIP-NEXT: vmv.v.v v8, v10
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: interleave_slp:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVZIP-NEXT: vmv1r.v v10, v9
+; ZVZIP-NEXT: vmv1r.v v11, v8
+; ZVZIP-NEXT: vwaddu.vv v8, v11, v10
+; ZVZIP-NEXT: li a0, -1
+; ZVZIP-NEXT: vwmaccu.vx v8, a0, v10
+; ZVZIP-NEXT: ret
entry:
%v2 = shufflevector <8 x i16> %v0, <8 x i16> poison, <16 x i32> <i32 0, i32 poison, i32 1, i32 poison, i32 2, i32 poison, i32 3, i32 poison, i32 4, i32 poison, i32 5, i32 poison, i32 6, i32 poison, i32 7, i32 poison>
%v3 = shufflevector <8 x i16> %v1, <8 x i16> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
@@ -1024,5 +1346,7 @@ entry:
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; RV32-V128: {{.*}}
; RV32-ZIP: {{.*}}
+; RV32-ZVZIP: {{.*}}
; RV64-V128: {{.*}}
; RV64-ZIP: {{.*}}
+; RV64-ZVZIP: {{.*}}
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-zipeven-zipodd.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-zipeven-zipodd.ll
index 14c17a65c6a0f..139688019705c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-zipeven-zipodd.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-zipeven-zipodd.ll
@@ -3,6 +3,8 @@
; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfhmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfhmin,+experimental-xrivosvizip -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZIP,ZIP-RV32
; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfhmin,+experimental-xrivosvizip -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZIP,ZIP-RV64
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfhmin,+experimental-zvzip -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVZIP,ZVZIP-RV32
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfhmin,+experimental-zvzip -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVZIP,ZVZIP-RV64
define <4 x i32> @zipeven_v4i32(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: zipeven_v4i32:
@@ -18,6 +20,13 @@ define <4 x i32> @zipeven_v4i32(<4 x i32> %a, <4 x i32> %b) {
; ZIP-NEXT: ri.vzipeven.vv v10, v8, v9
; ZIP-NEXT: vmv.v.v v8, v10
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: zipeven_v4i32:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, mu
+; ZVZIP-NEXT: vmv.v.i v0, 10
+; ZVZIP-NEXT: vslideup.vi v8, v9, 1, v0.t
+; ZVZIP-NEXT: ret
entry:
%c = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
ret <4 x i32> %c
@@ -38,6 +47,14 @@ define <4 x i32> @zipeven_v4i32_swapped(<4 x i32> %a, <4 x i32> %b) {
; ZIP-NEXT: ri.vzipeven.vv v10, v9, v8
; ZIP-NEXT: vmv.v.v v8, v10
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: zipeven_v4i32_swapped:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, mu
+; ZVZIP-NEXT: vmv.v.i v0, 10
+; ZVZIP-NEXT: vslideup.vi v9, v8, 1, v0.t
+; ZVZIP-NEXT: vmv.v.v v8, v9
+; ZVZIP-NEXT: ret
entry:
%c = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 0, i32 6, i32 2>
ret <4 x i32> %c
@@ -58,6 +75,14 @@ define <4 x i64> @zipeven_v4i64(<4 x i64> %a, <4 x i64> %b) {
; ZIP-NEXT: ri.vzipeven.vv v12, v8, v10
; ZIP-NEXT: vmv.v.v v8, v12
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: zipeven_v4i64:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
+; ZVZIP-NEXT: vmv.v.i v0, 10
+; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, mu
+; ZVZIP-NEXT: vslideup.vi v8, v10, 1, v0.t
+; ZVZIP-NEXT: ret
entry:
%c = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
ret <4 x i64> %c
@@ -77,6 +102,13 @@ define <4 x half> @zipeven_v4f16(<4 x half> %a, <4 x half> %b) {
; ZIP-NEXT: ri.vzipeven.vv v10, v8, v9
; ZIP-NEXT: vmv1r.v v8, v10
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: zipeven_v4f16:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
+; ZVZIP-NEXT: vmv.v.i v0, 10
+; ZVZIP-NEXT: vslideup.vi v8, v9, 1, v0.t
+; ZVZIP-NEXT: ret
entry:
%c = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
ret <4 x half> %c
@@ -96,6 +128,13 @@ define <4 x float> @zipeven_v4f32(<4 x float> %a, <4 x float> %b) {
; ZIP-NEXT: ri.vzipeven.vv v10, v8, v9
; ZIP-NEXT: vmv.v.v v8, v10
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: zipeven_v4f32:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, mu
+; ZVZIP-NEXT: vmv.v.i v0, 10
+; ZVZIP-NEXT: vslideup.vi v8, v9, 1, v0.t
+; ZVZIP-NEXT: ret
entry:
%c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
ret <4 x float> %c
@@ -116,6 +155,14 @@ define <4 x double> @zipeven_v4f64(<4 x double> %a, <4 x double> %b) {
; ZIP-NEXT: ri.vzipeven.vv v12, v8, v10
; ZIP-NEXT: vmv.v.v v8, v12
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: zipeven_v4f64:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
+; ZVZIP-NEXT: vmv.v.i v0, 10
+; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, mu
+; ZVZIP-NEXT: vslideup.vi v8, v10, 1, v0.t
+; ZVZIP-NEXT: ret
entry:
%c = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
ret <4 x double> %c
@@ -137,6 +184,14 @@ define <4 x i32> @zipodd_v4i32(<4 x i32> %a, <4 x i32> %b) {
; ZIP-NEXT: ri.vzipodd.vv v10, v8, v9
; ZIP-NEXT: vmv.v.v v8, v10
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: zipodd_v4i32:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, mu
+; ZVZIP-NEXT: vmv.v.i v0, 5
+; ZVZIP-NEXT: vslidedown.vi v9, v8, 1, v0.t
+; ZVZIP-NEXT: vmv.v.v v8, v9
+; ZVZIP-NEXT: ret
entry:
%c = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
ret <4 x i32> %c
@@ -156,6 +211,13 @@ define <4 x i32> @zipodd_v4i32_swapped(<4 x i32> %a, <4 x i32> %b) {
; ZIP-NEXT: ri.vzipodd.vv v10, v9, v8
; ZIP-NEXT: vmv.v.v v8, v10
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: zipodd_v4i32_swapped:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, mu
+; ZVZIP-NEXT: vmv.v.i v0, 5
+; ZVZIP-NEXT: vslidedown.vi v8, v9, 1, v0.t
+; ZVZIP-NEXT: ret
entry:
%c = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 5, i32 1, i32 7, i32 3>
ret <4 x i32> %c
@@ -172,6 +234,10 @@ define <4 x i32> @zipeven_v4i32_single(<4 x i32> %a) {
; ZIP-LABEL: zipeven_v4i32_single:
; ZIP: # %bb.0: # %entry
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: zipeven_v4i32_single:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: ret
entry:
%c = shufflevector <4 x i32> %a, <4 x i32> poison, <4 x i32> <i32 0, i32 poison, i32 2, i32 poison>
ret <4 x i32> %c
@@ -192,6 +258,12 @@ define <4 x i32> @zipodd_v4i32_single(<4 x i32> %a) {
; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZIP-NEXT: vslidedown.vi v8, v8, 1
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: zipodd_v4i32_single:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVZIP-NEXT: vslidedown.vi v8, v8, 1
+; ZVZIP-NEXT: ret
entry:
%c = shufflevector <4 x i32> %a, <4 x i32> poison, <4 x i32> <i32 1, i32 poison, i32 3, i32 poison>
ret <4 x i32> %c
@@ -211,6 +283,13 @@ define <4 x i32> @zipodd_v4i32_both(<4 x i32> %a) {
; ZIP-NEXT: ri.vzipodd.vv v9, v8, v8
; ZIP-NEXT: vmv.v.v v8, v9
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: zipodd_v4i32_both:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, mu
+; ZVZIP-NEXT: vmv.v.i v0, 5
+; ZVZIP-NEXT: vslidedown.vi v8, v8, 1, v0.t
+; ZVZIP-NEXT: ret
entry:
%c = shufflevector <4 x i32> %a, <4 x i32> poison, <4 x i32> <i32 1, i32 1, i32 3, i32 3>
ret <4 x i32> %c
@@ -232,6 +311,15 @@ define <4 x i32> @zipeven_v4i32_both(<4 x i32> %a) {
; ZIP-NEXT: ri.vzipeven.vv v9, v8, v8
; ZIP-NEXT: vmv.v.v v8, v9
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: zipeven_v4i32_both:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, mu
+; ZVZIP-NEXT: vmv.v.i v0, 10
+; ZVZIP-NEXT: vmv1r.v v9, v8
+; ZVZIP-NEXT: vslideup.vi v9, v8, 1, v0.t
+; ZVZIP-NEXT: vmv.v.v v8, v9
+; ZVZIP-NEXT: ret
entry:
%c = shufflevector <4 x i32> %a, <4 x i32> poison, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
ret <4 x i32> %c
@@ -249,6 +337,12 @@ define <4 x i32> @zipeven_v4i32_partial(<4 x i32> %a, <4 x i32> %b) {
; ZIP-NEXT: vsetivli zero, 2, e32, m1, tu, ma
; ZIP-NEXT: vslideup.vi v8, v9, 1
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: zipeven_v4i32_partial:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 2, e32, m1, tu, ma
+; ZVZIP-NEXT: vslideup.vi v8, v9, 1
+; ZVZIP-NEXT: ret
entry:
%c = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 poison>
ret <4 x i32> %c
@@ -269,6 +363,14 @@ define <4 x i32> @zipodd_v4i32_partial(<4 x i32> %a, <4 x i32> %b) {
; ZIP-NEXT: ri.vzipodd.vv v10, v8, v9
; ZIP-NEXT: vmv.v.v v8, v10
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: zipodd_v4i32_partial:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, mu
+; ZVZIP-NEXT: vmv.v.i v0, 5
+; ZVZIP-NEXT: vslidedown.vi v9, v8, 1, v0.t
+; ZVZIP-NEXT: vmv.v.v v8, v9
+; ZVZIP-NEXT: ret
entry:
%c = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 1, i32 5, i32 3, i32 poison>
ret <4 x i32> %c
@@ -289,6 +391,14 @@ define <8 x i32> @zipeven_v8i32(<8 x i32> %v1, <8 x i32> %v2) {
; ZIP-NEXT: ri.vzipeven.vv v12, v8, v10
; ZIP-NEXT: vmv.v.v v8, v12
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: zipeven_v8i32:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: li a0, 170
+; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, mu
+; ZVZIP-NEXT: vmv.s.x v0, a0
+; ZVZIP-NEXT: vslideup.vi v8, v10, 1, v0.t
+; ZVZIP-NEXT: ret
%out = shufflevector <8 x i32> %v1, <8 x i32> %v2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
ret <8 x i32> %out
}
@@ -309,6 +419,15 @@ define <8 x i32> @zipodd_v8i32(<8 x i32> %v1, <8 x i32> %v2) {
; ZIP-NEXT: ri.vzipodd.vv v12, v8, v10
; ZIP-NEXT: vmv.v.v v8, v12
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: zipodd_v8i32:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: li a0, 85
+; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, mu
+; ZVZIP-NEXT: vmv.s.x v0, a0
+; ZVZIP-NEXT: vslidedown.vi v10, v8, 1, v0.t
+; ZVZIP-NEXT: vmv.v.v v8, v10
+; ZVZIP-NEXT: ret
%out = shufflevector <8 x i32> %v1, <8 x i32> %v2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
ret <8 x i32> %out
}
@@ -329,6 +448,15 @@ define <16 x i64> @zipeven_v16i64(<16 x i64> %v1, <16 x i64> %v2) {
; ZIP-NEXT: ri.vzipeven.vv v24, v8, v16
; ZIP-NEXT: vmv.v.v v8, v24
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: zipeven_v16i64:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: lui a0, 11
+; ZVZIP-NEXT: addi a0, a0, -1366
+; ZVZIP-NEXT: vsetivli zero, 16, e64, m8, ta, mu
+; ZVZIP-NEXT: vmv.s.x v0, a0
+; ZVZIP-NEXT: vslideup.vi v8, v16, 1, v0.t
+; ZVZIP-NEXT: ret
%out = shufflevector <16 x i64> %v1, <16 x i64> %v2, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30>
ret <16 x i64> %out
}
@@ -350,6 +478,16 @@ define <16 x i64> @zipodd_v16i64(<16 x i64> %v1, <16 x i64> %v2) {
; ZIP-NEXT: ri.vzipodd.vv v24, v8, v16
; ZIP-NEXT: vmv.v.v v8, v24
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: zipodd_v16i64:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: lui a0, 5
+; ZVZIP-NEXT: addi a0, a0, 1365
+; ZVZIP-NEXT: vsetivli zero, 16, e64, m8, ta, mu
+; ZVZIP-NEXT: vmv.s.x v0, a0
+; ZVZIP-NEXT: vslidedown.vi v16, v8, 1, v0.t
+; ZVZIP-NEXT: vmv.v.v v8, v16
+; ZVZIP-NEXT: ret
%out = shufflevector <16 x i64> %v1, <16 x i64> %v2, <16 x i32> <i32 1, i32 17, i32 3, i32 19, i32 5, i32 21, i32 7, i32 23, i32 9, i32 25, i32 11, i32 27, i32 13, i32 29, i32 15, i32 31>
ret <16 x i64> %out
}
@@ -369,6 +507,14 @@ define <8 x i32> @zipeven_v8i32_as_v4i64(<8 x i32> %v1, <8 x i32> %v2) {
; ZIP-NEXT: ri.vzipeven.vv v12, v8, v10
; ZIP-NEXT: vmv.v.v v8, v12
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: zipeven_v8i32_as_v4i64:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: li a0, 204
+; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, mu
+; ZVZIP-NEXT: vmv.s.x v0, a0
+; ZVZIP-NEXT: vslideup.vi v8, v10, 2, v0.t
+; ZVZIP-NEXT: ret
%out = shufflevector <8 x i32> %v1, <8 x i32> %v2, <8 x i32> <i32 0, i32 1, i32 8, i32 9, i32 4, i32 5, i32 12, i32 13>
ret <8 x i32> %out
}
@@ -389,6 +535,15 @@ define <8 x i32> @zipodd_v8i32_as_v4i64(<8 x i32> %v1, <8 x i32> %v2) {
; ZIP-NEXT: ri.vzipodd.vv v12, v8, v10
; ZIP-NEXT: vmv.v.v v8, v12
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: zipodd_v8i32_as_v4i64:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: li a0, 51
+; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, mu
+; ZVZIP-NEXT: vmv.s.x v0, a0
+; ZVZIP-NEXT: vslidedown.vi v10, v8, 2, v0.t
+; ZVZIP-NEXT: vmv.v.v v8, v10
+; ZVZIP-NEXT: ret
%out = shufflevector <8 x i32> %v1, <8 x i32> %v2, <8 x i32> <i32 2, i32 3, i32 10, i32 11, i32 6, i32 7, i32 14, i32 15>
ret <8 x i32> %out
}
@@ -398,3 +553,5 @@ define <8 x i32> @zipodd_v8i32_as_v4i64(<8 x i32> %v1, <8 x i32> %v2) {
; RV64: {{.*}}
; ZIP-RV32: {{.*}}
; ZIP-RV64: {{.*}}
+; ZVZIP-RV32: {{.*}}
+; ZVZIP-RV64: {{.*}}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
index 5c04a09c9953b..e3b2f0ce47383 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
@@ -2,6 +2,7 @@
; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+m,+zvfh | FileCheck %s --check-prefixes=CHECK,V,RV32
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+m,+zvfh | FileCheck %s --check-prefixes=CHECK,V,RV64
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+m,+zvfh,+experimental-xrivosvizip | FileCheck %s --check-prefixes=CHECK,ZIP
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+m,+zvfh,+experimental-zvzip | FileCheck %s --check-prefixes=CHECK,ZVZIP
; Integers
@@ -91,6 +92,17 @@ define {<2 x i64>, <2 x i64>} @vector_deinterleave_v2i64_v4i64(<4 x i64> %vec) {
; ZIP-NEXT: vmv.v.v v8, v10
; ZIP-NEXT: vmv.v.v v9, v11
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_deinterleave_v2i64_v4i64:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 2, e64, m2, ta, ma
+; ZVZIP-NEXT: vslidedown.vi v10, v8, 2
+; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, mu
+; ZVZIP-NEXT: vmv.v.i v0, 1
+; ZVZIP-NEXT: vmv1r.v v9, v10
+; ZVZIP-NEXT: vslidedown.vi v9, v8, 1, v0.t
+; ZVZIP-NEXT: vslideup.vi v8, v10, 1
+; ZVZIP-NEXT: ret
%retval = call {<2 x i64>, <2 x i64>} @llvm.vector.deinterleave2.v4i64(<4 x i64> %vec)
ret {<2 x i64>, <2 x i64>} %retval
}
@@ -134,6 +146,36 @@ define {<4 x i64>, <4 x i64>} @vector_deinterleave_v4i64_v8i64(<8 x i64> %vec) {
; ZIP-NEXT: vmv.v.v v8, v12
; ZIP-NEXT: vmv.v.v v10, v14
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_deinterleave_v4i64_v8i64:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
+; ZVZIP-NEXT: vmv.v.i v0, 8
+; ZVZIP-NEXT: vsetivli zero, 4, e64, m4, ta, ma
+; ZVZIP-NEXT: vslidedown.vi v16, v8, 4
+; ZVZIP-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
+; ZVZIP-NEXT: vmv.v.i v10, 2
+; ZVZIP-NEXT: vmv2r.v v12, v8
+; ZVZIP-NEXT: vmv.v.i v11, 12
+; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, mu
+; ZVZIP-NEXT: vslideup.vi v14, v16, 2
+; ZVZIP-NEXT: vslideup.vi v14, v16, 1, v0.t
+; ZVZIP-NEXT: vmv1r.v v0, v10
+; ZVZIP-NEXT: vslidedown.vi v12, v8, 1, v0.t
+; ZVZIP-NEXT: vmv1r.v v0, v11
+; ZVZIP-NEXT: vmerge.vvm v12, v12, v14, v0
+; ZVZIP-NEXT: vslidedown.vi v14, v8, 1
+; ZVZIP-NEXT: vmv1r.v v0, v10
+; ZVZIP-NEXT: vslidedown.vi v14, v8, 2, v0.t
+; ZVZIP-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
+; ZVZIP-NEXT: vmv.v.i v0, 4
+; ZVZIP-NEXT: vmv2r.v v8, v16
+; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, mu
+; ZVZIP-NEXT: vslideup.vi v8, v16, 1, v0.t
+; ZVZIP-NEXT: vmv1r.v v0, v11
+; ZVZIP-NEXT: vmerge.vvm v10, v14, v8, v0
+; ZVZIP-NEXT: vmv2r.v v8, v12
+; ZVZIP-NEXT: ret
%retval = call {<4 x i64>, <4 x i64>} @llvm.vector.deinterleave2.v8i64(<8 x i64> %vec)
ret {<4 x i64>, <4 x i64>} %retval
}
@@ -172,6 +214,31 @@ define {<8 x i64>, <8 x i64>} @vector_deinterleave_v8i64_v16i64(<16 x i64> %vec)
; ZIP-NEXT: vmv.v.v v8, v16
; ZIP-NEXT: vmv.v.v v12, v20
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_deinterleave_v8i64_v16i64:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVZIP-NEXT: vid.v v16
+; ZVZIP-NEXT: vsetivli zero, 8, e64, m8, ta, ma
+; ZVZIP-NEXT: vslidedown.vi v24, v8, 8
+; ZVZIP-NEXT: li a0, 85
+; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVZIP-NEXT: vmv.v.i v0, -16
+; ZVZIP-NEXT: vmv.s.x v12, a0
+; ZVZIP-NEXT: li a0, 170
+; ZVZIP-NEXT: vadd.vv v13, v16, v16
+; ZVZIP-NEXT: vmv.s.x v20, a0
+; ZVZIP-NEXT: vadd.vi v21, v13, -8
+; ZVZIP-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; ZVZIP-NEXT: vcompress.vm v16, v8, v12
+; ZVZIP-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vadd.vi v22, v13, -7
+; ZVZIP-NEXT: vsetvli zero, zero, e64, m4, ta, mu
+; ZVZIP-NEXT: vcompress.vm v12, v8, v20
+; ZVZIP-NEXT: vrgatherei16.vv v16, v24, v21, v0.t
+; ZVZIP-NEXT: vrgatherei16.vv v12, v24, v22, v0.t
+; ZVZIP-NEXT: vmv.v.v v8, v16
+; ZVZIP-NEXT: ret
%retval = call {<8 x i64>, <8 x i64>} @llvm.vector.deinterleave2.v16i64(<16 x i64> %vec)
ret {<8 x i64>, <8 x i64>} %retval
}
@@ -475,6 +542,17 @@ define {<2 x double>, <2 x double>} @vector_deinterleave_v2f64_v4f64(<4 x double
; ZIP-NEXT: vmv.v.v v8, v10
; ZIP-NEXT: vmv.v.v v9, v12
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_deinterleave_v2f64_v4f64:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 2, e64, m2, ta, ma
+; ZVZIP-NEXT: vslidedown.vi v10, v8, 2
+; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, mu
+; ZVZIP-NEXT: vmv.v.i v0, 1
+; ZVZIP-NEXT: vmv1r.v v9, v10
+; ZVZIP-NEXT: vslidedown.vi v9, v8, 1, v0.t
+; ZVZIP-NEXT: vslideup.vi v8, v10, 1
+; ZVZIP-NEXT: ret
%retval = call {<2 x double>, <2 x double>} @llvm.vector.deinterleave2.v4f64(<4 x double> %vec)
ret {<2 x double>, <2 x double>} %retval
}
@@ -518,6 +596,36 @@ define {<4 x double>, <4 x double>} @vector_deinterleave_v4f64_v8f64(<8 x double
; ZIP-NEXT: vmv.v.v v8, v12
; ZIP-NEXT: vmv.v.v v10, v16
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_deinterleave_v4f64_v8f64:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
+; ZVZIP-NEXT: vmv.v.i v0, 8
+; ZVZIP-NEXT: vsetivli zero, 4, e64, m4, ta, ma
+; ZVZIP-NEXT: vslidedown.vi v16, v8, 4
+; ZVZIP-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
+; ZVZIP-NEXT: vmv.v.i v10, 2
+; ZVZIP-NEXT: vmv2r.v v12, v8
+; ZVZIP-NEXT: vmv.v.i v11, 12
+; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, mu
+; ZVZIP-NEXT: vslideup.vi v14, v16, 2
+; ZVZIP-NEXT: vslideup.vi v14, v16, 1, v0.t
+; ZVZIP-NEXT: vmv1r.v v0, v10
+; ZVZIP-NEXT: vslidedown.vi v12, v8, 1, v0.t
+; ZVZIP-NEXT: vmv1r.v v0, v11
+; ZVZIP-NEXT: vmerge.vvm v12, v12, v14, v0
+; ZVZIP-NEXT: vslidedown.vi v14, v8, 1
+; ZVZIP-NEXT: vmv1r.v v0, v10
+; ZVZIP-NEXT: vslidedown.vi v14, v8, 2, v0.t
+; ZVZIP-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
+; ZVZIP-NEXT: vmv.v.i v0, 4
+; ZVZIP-NEXT: vmv2r.v v8, v16
+; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, mu
+; ZVZIP-NEXT: vslideup.vi v8, v16, 1, v0.t
+; ZVZIP-NEXT: vmv1r.v v0, v11
+; ZVZIP-NEXT: vmerge.vvm v10, v14, v8, v0
+; ZVZIP-NEXT: vmv2r.v v8, v12
+; ZVZIP-NEXT: ret
%retval = call {<4 x double>, <4 x double>} @llvm.vector.deinterleave2.v8f64(<8 x double> %vec)
ret {<4 x double>, <4 x double>} %retval
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
index ac9f26314a9ab..192a94a0c262a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
@@ -2,6 +2,7 @@
; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+v,+zvfhmin,+zvfbfmin | FileCheck %s --check-prefixes=CHECK,V
; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+zvfhmin,+zvfbfmin | FileCheck %s --check-prefixes=CHECK,V
; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+zvfhmin,+zvfbfmin,+experimental-xrivosvizip | FileCheck %s --check-prefixes=CHECK,ZIP
+; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+zvfhmin,+zvfbfmin,+experimental-zvzip | FileCheck %s --check-prefixes=CHECK,ZVZIP
; Integers
@@ -39,6 +40,23 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>} @vector_deinterleave_nxv16i1_nxv
; ZIP-NEXT: vmsne.vi v0, v12, 0
; ZIP-NEXT: vmsne.vi v8, v14, 0
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_deinterleave_nxv16i1_nxv32i1:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; ZVZIP-NEXT: vmv.v.i v10, 0
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: vmerge.vim v8, v10, 1, v0
+; ZVZIP-NEXT: srli a0, a0, 2
+; ZVZIP-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v0, v0, a0
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; ZVZIP-NEXT: vmerge.vim v10, v10, 1, v0
+; ZVZIP-NEXT: vnsrl.wi v12, v8, 0
+; ZVZIP-NEXT: vnsrl.wi v14, v8, 8
+; ZVZIP-NEXT: vmsne.vi v0, v12, 0
+; ZVZIP-NEXT: vmsne.vi v8, v14, 0
+; ZVZIP-NEXT: ret
%retval = call {<vscale x 16 x i1>, <vscale x 16 x i1>} @llvm.vector.deinterleave2.nxv32i1(<vscale x 32 x i1> %vec)
ret {<vscale x 16 x i1>, <vscale x 16 x i1>} %retval
}
@@ -61,6 +79,15 @@ define {<vscale x 16 x i8>, <vscale x 16 x i8>} @vector_deinterleave_nxv16i8_nxv
; ZIP-NEXT: vmv.v.v v8, v12
; ZIP-NEXT: vmv.v.v v10, v14
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_deinterleave_nxv16i8_nxv32i8:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v12, v8, 0
+; ZVZIP-NEXT: vnsrl.wi v14, v8, 8
+; ZVZIP-NEXT: vmv.v.v v8, v12
+; ZVZIP-NEXT: vmv.v.v v10, v14
+; ZVZIP-NEXT: ret
%retval = call {<vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> %vec)
ret {<vscale x 16 x i8>, <vscale x 16 x i8>} %retval
}
@@ -83,6 +110,15 @@ define {<vscale x 8 x i16>, <vscale x 8 x i16>} @vector_deinterleave_nxv8i16_nxv
; ZIP-NEXT: vmv.v.v v8, v12
; ZIP-NEXT: vmv.v.v v10, v14
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_deinterleave_nxv8i16_nxv16i16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v12, v8, 0
+; ZVZIP-NEXT: vnsrl.wi v14, v8, 16
+; ZVZIP-NEXT: vmv.v.v v8, v12
+; ZVZIP-NEXT: vmv.v.v v10, v14
+; ZVZIP-NEXT: ret
%retval = call {<vscale x 8 x i16>, <vscale x 8 x i16>} @llvm.vector.deinterleave2.nxv16i16(<vscale x 16 x i16> %vec)
ret {<vscale x 8 x i16>, <vscale x 8 x i16>} %retval
}
@@ -106,6 +142,16 @@ define {<vscale x 4 x i32>, <vscale x 4 x i32>} @vector_deinterleave_nxv4i32_nxv
; ZIP-NEXT: vmv.v.v v8, v12
; ZIP-NEXT: vmv.v.v v10, v14
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_deinterleave_nxv4i32_nxvv8i32:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: li a0, 32
+; ZVZIP-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; ZVZIP-NEXT: vnsrl.wx v12, v8, a0
+; ZVZIP-NEXT: vnsrl.wi v14, v8, 0
+; ZVZIP-NEXT: vmv.v.v v8, v14
+; ZVZIP-NEXT: vmv.v.v v10, v12
+; ZVZIP-NEXT: ret
%retval = call {<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.vector.deinterleave2.nxv8i32(<vscale x 8 x i32> %vec)
ret {<vscale x 4 x i32>, <vscale x 4 x i32>} %retval
}
@@ -133,6 +179,20 @@ define {<vscale x 2 x i64>, <vscale x 2 x i64>} @vector_deinterleave_nxv2i64_nxv
; ZIP-NEXT: vmv.v.v v8, v12
; ZIP-NEXT: vmv.v.v v10, v14
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_deinterleave_nxv2i64_nxv4i64:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: li a0, 85
+; ZVZIP-NEXT: vsetvli a1, zero, e8, m1, ta, ma
+; ZVZIP-NEXT: vmv.v.x v16, a0
+; ZVZIP-NEXT: li a0, 170
+; ZVZIP-NEXT: vmv.v.x v20, a0
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m4, ta, ma
+; ZVZIP-NEXT: vcompress.vm v12, v8, v16
+; ZVZIP-NEXT: vcompress.vm v16, v8, v20
+; ZVZIP-NEXT: vmv2r.v v8, v12
+; ZVZIP-NEXT: vmv2r.v v10, v16
+; ZVZIP-NEXT: ret
%retval = call {<vscale x 2 x i64>, <vscale x 2 x i64>} @llvm.vector.deinterleave2.nxv4i64(<vscale x 4 x i64> %vec)
ret {<vscale x 2 x i64>, <vscale x 2 x i64>} %retval
}
@@ -160,6 +220,20 @@ define {<vscale x 4 x i64>, <vscale x 4 x i64>} @vector_deinterleave_nxv4i64_nxv
; ZIP-NEXT: vmv.v.v v8, v16
; ZIP-NEXT: vmv.v.v v12, v20
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_deinterleave_nxv4i64_nxv8i64:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: li a0, 85
+; ZVZIP-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
+; ZVZIP-NEXT: vmv.v.x v24, a0
+; ZVZIP-NEXT: li a0, 170
+; ZVZIP-NEXT: vmv.v.x v7, a0
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m8, ta, ma
+; ZVZIP-NEXT: vcompress.vm v16, v8, v24
+; ZVZIP-NEXT: vcompress.vm v24, v8, v7
+; ZVZIP-NEXT: vmv4r.v v8, v16
+; ZVZIP-NEXT: vmv4r.v v12, v24
+; ZVZIP-NEXT: ret
%retval = call {<vscale x 4 x i64>, <vscale x 4 x i64>} @llvm.vector.deinterleave2.nxv8i64(<vscale x 8 x i64> %vec)
ret {<vscale x 4 x i64>, <vscale x 4 x i64>} %retval
}
@@ -203,6 +277,24 @@ define {<vscale x 64 x i1>, <vscale x 64 x i1>} @vector_deinterleave_nxv64i1_nxv
; ZIP-NEXT: vmsne.vi v8, v0, 0
; ZIP-NEXT: vmv1r.v v0, v16
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_deinterleave_nxv64i1_nxv128i1:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
+; ZVZIP-NEXT: vmv.v.i v24, 0
+; ZVZIP-NEXT: vmerge.vim v16, v24, 1, v0
+; ZVZIP-NEXT: vmv1r.v v0, v8
+; ZVZIP-NEXT: vmerge.vim v24, v24, 1, v0
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v8, v16, 0
+; ZVZIP-NEXT: vnsrl.wi v0, v16, 8
+; ZVZIP-NEXT: vnsrl.wi v12, v24, 0
+; ZVZIP-NEXT: vnsrl.wi v4, v24, 8
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
+; ZVZIP-NEXT: vmsne.vi v16, v8, 0
+; ZVZIP-NEXT: vmsne.vi v8, v0, 0
+; ZVZIP-NEXT: vmv1r.v v0, v16
+; ZVZIP-NEXT: ret
%retval = call {<vscale x 64 x i1>, <vscale x 64 x i1>} @llvm.vector.deinterleave2.nxv128i1(<vscale x 128 x i1> %vec)
ret {<vscale x 64 x i1>, <vscale x 64 x i1>} %retval
}
@@ -229,6 +321,17 @@ define {<vscale x 64 x i8>, <vscale x 64 x i8>} @vector_deinterleave_nxv64i8_nxv
; ZIP-NEXT: vmv8r.v v8, v24
; ZIP-NEXT: vmv8r.v v16, v0
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_deinterleave_nxv64i8_nxv128i8:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
+; ZVZIP-NEXT: vmv8r.v v24, v8
+; ZVZIP-NEXT: vnsrl.wi v8, v24, 0
+; ZVZIP-NEXT: vnsrl.wi v0, v24, 8
+; ZVZIP-NEXT: vnsrl.wi v12, v16, 0
+; ZVZIP-NEXT: vnsrl.wi v4, v16, 8
+; ZVZIP-NEXT: vmv8r.v v16, v0
+; ZVZIP-NEXT: ret
%retval = call {<vscale x 64 x i8>, <vscale x 64 x i8>} @llvm.vector.deinterleave2.nxv128i8(<vscale x 128 x i8> %vec)
ret {<vscale x 64 x i8>, <vscale x 64 x i8>} %retval
}
@@ -255,6 +358,17 @@ define {<vscale x 32 x i16>, <vscale x 32 x i16>} @vector_deinterleave_nxv32i16_
; ZIP-NEXT: vmv8r.v v8, v24
; ZIP-NEXT: vmv8r.v v16, v0
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_deinterleave_nxv32i16_nxv64i16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVZIP-NEXT: vmv8r.v v24, v8
+; ZVZIP-NEXT: vnsrl.wi v8, v24, 0
+; ZVZIP-NEXT: vnsrl.wi v0, v24, 16
+; ZVZIP-NEXT: vnsrl.wi v12, v16, 0
+; ZVZIP-NEXT: vnsrl.wi v4, v16, 16
+; ZVZIP-NEXT: vmv8r.v v16, v0
+; ZVZIP-NEXT: ret
%retval = call {<vscale x 32 x i16>, <vscale x 32 x i16>} @llvm.vector.deinterleave2.nxv64i16(<vscale x 64 x i16> %vec)
ret {<vscale x 32 x i16>, <vscale x 32 x i16>} %retval
}
@@ -282,6 +396,18 @@ define {<vscale x 16 x i32>, <vscale x 16 x i32>} @vector_deinterleave_nxv16i32_
; ZIP-NEXT: vmv8r.v v8, v24
; ZIP-NEXT: vmv8r.v v16, v0
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_deinterleave_nxv16i32_nxvv32i32:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVZIP-NEXT: vmv8r.v v24, v16
+; ZVZIP-NEXT: li a0, 32
+; ZVZIP-NEXT: vnsrl.wx v20, v24, a0
+; ZVZIP-NEXT: vnsrl.wx v16, v8, a0
+; ZVZIP-NEXT: vnsrl.wi v0, v8, 0
+; ZVZIP-NEXT: vnsrl.wi v4, v24, 0
+; ZVZIP-NEXT: vmv8r.v v8, v0
+; ZVZIP-NEXT: ret
%retval = call {<vscale x 16 x i32>, <vscale x 16 x i32>} @llvm.vector.deinterleave2.nxv32i32(<vscale x 32 x i32> %vec)
ret {<vscale x 16 x i32>, <vscale x 16 x i32>} %retval
}
@@ -343,6 +469,52 @@ define {<vscale x 8 x i64>, <vscale x 8 x i64>} @vector_deinterleave_nxv8i64_nxv
; ZIP-NEXT: vmv8r.v v8, v24
; ZIP-NEXT: vmv8r.v v16, v0
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_deinterleave_nxv8i64_nxv16i64:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: addi sp, sp, -16
+; ZVZIP-NEXT: .cfi_def_cfa_offset 16
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 4
+; ZVZIP-NEXT: sub sp, sp, a0
+; ZVZIP-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
+; ZVZIP-NEXT: li a0, 85
+; ZVZIP-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
+; ZVZIP-NEXT: vmv.v.x v7, a0
+; ZVZIP-NEXT: li a0, 170
+; ZVZIP-NEXT: vmv.v.x v6, a0
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m8, ta, ma
+; ZVZIP-NEXT: vcompress.vm v24, v8, v7
+; ZVZIP-NEXT: vmv1r.v v28, v7
+; ZVZIP-NEXT: vmv1r.v v29, v6
+; ZVZIP-NEXT: vcompress.vm v0, v8, v29
+; ZVZIP-NEXT: vcompress.vm v8, v16, v28
+; ZVZIP-NEXT: addi a0, sp, 16
+; ZVZIP-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vcompress.vm v8, v16, v29
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 3
+; ZVZIP-NEXT: add a0, sp, a0
+; ZVZIP-NEXT: addi a0, a0, 16
+; ZVZIP-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: addi a0, sp, 16
+; ZVZIP-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vmv4r.v v28, v8
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 3
+; ZVZIP-NEXT: add a0, sp, a0
+; ZVZIP-NEXT: addi a0, a0, 16
+; ZVZIP-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vmv4r.v v4, v8
+; ZVZIP-NEXT: vmv8r.v v8, v24
+; ZVZIP-NEXT: vmv8r.v v16, v0
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 4
+; ZVZIP-NEXT: add sp, sp, a0
+; ZVZIP-NEXT: .cfi_def_cfa sp, 16
+; ZVZIP-NEXT: addi sp, sp, 16
+; ZVZIP-NEXT: .cfi_def_cfa_offset 0
+; ZVZIP-NEXT: ret
%retval = call {<vscale x 8 x i64>, <vscale x 8 x i64>} @llvm.vector.deinterleave2.nxv16i64(<vscale x 16 x i64> %vec)
ret {<vscale x 8 x i64>, <vscale x 8 x i64>} %retval
}
@@ -1592,6 +1764,14 @@ define {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>} @vector_deinterleave_nxv2b
; ZIP-NEXT: ri.vunzip2b.vv v9, v8, v11
; ZIP-NEXT: vmv.v.v v8, v10
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_deinterleave_nxv2bf16_nxv4bf16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v10, v8, 0
+; ZVZIP-NEXT: vnsrl.wi v9, v8, 16
+; ZVZIP-NEXT: vmv1r.v v8, v10
+; ZVZIP-NEXT: ret
%retval = call {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>} @llvm.vector.deinterleave2.nxv4bf16(<vscale x 4 x bfloat> %vec)
ret {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>} %retval
}
@@ -1612,6 +1792,14 @@ define {<vscale x 2 x half>, <vscale x 2 x half>} @vector_deinterleave_nxv2f16_n
; ZIP-NEXT: ri.vunzip2b.vv v9, v8, v11
; ZIP-NEXT: vmv.v.v v8, v10
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_deinterleave_nxv2f16_nxv4f16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v10, v8, 0
+; ZVZIP-NEXT: vnsrl.wi v9, v8, 16
+; ZVZIP-NEXT: vmv1r.v v8, v10
+; ZVZIP-NEXT: ret
%retval = call {<vscale x 2 x half>, <vscale x 2 x half>} @llvm.vector.deinterleave2.nxv4f16(<vscale x 4 x half> %vec)
ret {<vscale x 2 x half>, <vscale x 2 x half>} %retval
}
@@ -1634,6 +1822,15 @@ define {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>} @vector_deinterleave_nxv4b
; ZIP-NEXT: vmv.v.v v8, v10
; ZIP-NEXT: vmv.v.v v9, v11
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_deinterleave_nxv4bf16_nxv8bf16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v10, v8, 0
+; ZVZIP-NEXT: vnsrl.wi v11, v8, 16
+; ZVZIP-NEXT: vmv.v.v v8, v10
+; ZVZIP-NEXT: vmv.v.v v9, v11
+; ZVZIP-NEXT: ret
%retval = call {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>} @llvm.vector.deinterleave2.nxv8bf16(<vscale x 8 x bfloat> %vec)
ret {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>} %retval
}
@@ -1656,6 +1853,15 @@ define {<vscale x 4 x half>, <vscale x 4 x half>} @vector_deinterleave_nxv4f16_n
; ZIP-NEXT: vmv.v.v v8, v10
; ZIP-NEXT: vmv.v.v v9, v11
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_deinterleave_nxv4f16_nxv8f16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v10, v8, 0
+; ZVZIP-NEXT: vnsrl.wi v11, v8, 16
+; ZVZIP-NEXT: vmv.v.v v8, v10
+; ZVZIP-NEXT: vmv.v.v v9, v11
+; ZVZIP-NEXT: ret
%retval = call {<vscale x 4 x half>, <vscale x 4 x half>} @llvm.vector.deinterleave2.nxv8f16(<vscale x 8 x half> %vec)
ret {<vscale x 4 x half>, <vscale x 4 x half>} %retval
}
@@ -1679,6 +1885,16 @@ define {<vscale x 2 x float>, <vscale x 2 x float>} @vector_deinterleave_nxv2f32
; ZIP-NEXT: vmv.v.v v8, v10
; ZIP-NEXT: vmv.v.v v9, v11
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_deinterleave_nxv2f32_nxv4f32:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: li a0, 32
+; ZVZIP-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; ZVZIP-NEXT: vnsrl.wx v10, v8, a0
+; ZVZIP-NEXT: vnsrl.wi v11, v8, 0
+; ZVZIP-NEXT: vmv.v.v v8, v11
+; ZVZIP-NEXT: vmv.v.v v9, v10
+; ZVZIP-NEXT: ret
%retval = call {<vscale x 2 x float>, <vscale x 2 x float>} @llvm.vector.deinterleave2.nxv4f32(<vscale x 4 x float> %vec)
ret {<vscale x 2 x float>, <vscale x 2 x float>} %retval
}
@@ -1701,6 +1917,15 @@ define {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @vector_deinterleave_nxv8b
; ZIP-NEXT: vmv.v.v v8, v12
; ZIP-NEXT: vmv.v.v v10, v14
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_deinterleave_nxv8bf16_nxv16bf16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v12, v8, 0
+; ZVZIP-NEXT: vnsrl.wi v14, v8, 16
+; ZVZIP-NEXT: vmv.v.v v8, v12
+; ZVZIP-NEXT: vmv.v.v v10, v14
+; ZVZIP-NEXT: ret
%retval = call {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @llvm.vector.deinterleave2.nxv16bf16(<vscale x 16 x bfloat> %vec)
ret {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} %retval
}
@@ -1723,6 +1948,15 @@ define {<vscale x 8 x half>, <vscale x 8 x half>} @vector_deinterleave_nxv8f16_n
; ZIP-NEXT: vmv.v.v v8, v12
; ZIP-NEXT: vmv.v.v v10, v14
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_deinterleave_nxv8f16_nxv16f16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v12, v8, 0
+; ZVZIP-NEXT: vnsrl.wi v14, v8, 16
+; ZVZIP-NEXT: vmv.v.v v8, v12
+; ZVZIP-NEXT: vmv.v.v v10, v14
+; ZVZIP-NEXT: ret
%retval = call {<vscale x 8 x half>, <vscale x 8 x half>} @llvm.vector.deinterleave2.nxv16f16(<vscale x 16 x half> %vec)
ret {<vscale x 8 x half>, <vscale x 8 x half>} %retval
}
@@ -1746,6 +1980,16 @@ define {<vscale x 4 x float>, <vscale x 4 x float>} @vector_deinterleave_nxv4f32
; ZIP-NEXT: vmv.v.v v8, v12
; ZIP-NEXT: vmv.v.v v10, v14
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_deinterleave_nxv4f32_nxv8f32:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: li a0, 32
+; ZVZIP-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; ZVZIP-NEXT: vnsrl.wx v12, v8, a0
+; ZVZIP-NEXT: vnsrl.wi v14, v8, 0
+; ZVZIP-NEXT: vmv.v.v v8, v14
+; ZVZIP-NEXT: vmv.v.v v10, v12
+; ZVZIP-NEXT: ret
%retval = call {<vscale x 4 x float>, <vscale x 4 x float>} @llvm.vector.deinterleave2.nxv8f32(<vscale x 8 x float> %vec)
ret {<vscale x 4 x float>, <vscale x 4 x float>} %retval
}
@@ -1773,6 +2017,20 @@ define {<vscale x 2 x double>, <vscale x 2 x double>} @vector_deinterleave_nxv2f
; ZIP-NEXT: vmv.v.v v8, v12
; ZIP-NEXT: vmv.v.v v10, v14
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_deinterleave_nxv2f64_nxv4f64:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: li a0, 85
+; ZVZIP-NEXT: vsetvli a1, zero, e8, m1, ta, ma
+; ZVZIP-NEXT: vmv.v.x v16, a0
+; ZVZIP-NEXT: li a0, 170
+; ZVZIP-NEXT: vmv.v.x v20, a0
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m4, ta, ma
+; ZVZIP-NEXT: vcompress.vm v12, v8, v16
+; ZVZIP-NEXT: vcompress.vm v16, v8, v20
+; ZVZIP-NEXT: vmv2r.v v8, v12
+; ZVZIP-NEXT: vmv2r.v v10, v16
+; ZVZIP-NEXT: ret
%retval = call {<vscale x 2 x double>, <vscale x 2 x double>} @llvm.vector.deinterleave2.nxv4f64(<vscale x 4 x double> %vec)
ret {<vscale x 2 x double>, <vscale x 2 x double>} %retval
}
@@ -1800,6 +2058,17 @@ define {<vscale x 32 x bfloat>, <vscale x 32 x bfloat>} @vector_deinterleave_nxv
; ZIP-NEXT: vmv8r.v v8, v24
; ZIP-NEXT: vmv8r.v v16, v0
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_deinterleave_nxv32bf16_nxv64bf16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVZIP-NEXT: vmv8r.v v24, v8
+; ZVZIP-NEXT: vnsrl.wi v8, v24, 0
+; ZVZIP-NEXT: vnsrl.wi v0, v24, 16
+; ZVZIP-NEXT: vnsrl.wi v12, v16, 0
+; ZVZIP-NEXT: vnsrl.wi v4, v16, 16
+; ZVZIP-NEXT: vmv8r.v v16, v0
+; ZVZIP-NEXT: ret
%retval = call {<vscale x 32 x bfloat>, <vscale x 32 x bfloat>} @llvm.vector.deinterleave2.nxv64bf16(<vscale x 64 x bfloat> %vec)
ret {<vscale x 32 x bfloat>, <vscale x 32 x bfloat>} %retval
}
@@ -1826,6 +2095,17 @@ define {<vscale x 32 x half>, <vscale x 32 x half>} @vector_deinterleave_nxv32f1
; ZIP-NEXT: vmv8r.v v8, v24
; ZIP-NEXT: vmv8r.v v16, v0
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_deinterleave_nxv32f16_nxv64f16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVZIP-NEXT: vmv8r.v v24, v8
+; ZVZIP-NEXT: vnsrl.wi v8, v24, 0
+; ZVZIP-NEXT: vnsrl.wi v0, v24, 16
+; ZVZIP-NEXT: vnsrl.wi v12, v16, 0
+; ZVZIP-NEXT: vnsrl.wi v4, v16, 16
+; ZVZIP-NEXT: vmv8r.v v16, v0
+; ZVZIP-NEXT: ret
%retval = call {<vscale x 32 x half>, <vscale x 32 x half>} @llvm.vector.deinterleave2.nxv64f16(<vscale x 64 x half> %vec)
ret {<vscale x 32 x half>, <vscale x 32 x half>} %retval
}
@@ -1853,6 +2133,18 @@ define {<vscale x 16 x float>, <vscale x 16 x float>} @vector_deinterleave_nxv16
; ZIP-NEXT: vmv8r.v v8, v24
; ZIP-NEXT: vmv8r.v v16, v0
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_deinterleave_nxv16f32_nxv32f32:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVZIP-NEXT: vmv8r.v v24, v16
+; ZVZIP-NEXT: li a0, 32
+; ZVZIP-NEXT: vnsrl.wx v20, v24, a0
+; ZVZIP-NEXT: vnsrl.wx v16, v8, a0
+; ZVZIP-NEXT: vnsrl.wi v0, v8, 0
+; ZVZIP-NEXT: vnsrl.wi v4, v24, 0
+; ZVZIP-NEXT: vmv8r.v v8, v0
+; ZVZIP-NEXT: ret
%retval = call {<vscale x 16 x float>, <vscale x 16 x float>} @llvm.vector.deinterleave2.nxv32f32(<vscale x 32 x float> %vec)
ret {<vscale x 16 x float>, <vscale x 16 x float>} %retval
}
@@ -1914,6 +2206,52 @@ define {<vscale x 8 x double>, <vscale x 8 x double>} @vector_deinterleave_nxv8f
; ZIP-NEXT: vmv8r.v v8, v24
; ZIP-NEXT: vmv8r.v v16, v0
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_deinterleave_nxv8f64_nxv16f64:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: addi sp, sp, -16
+; ZVZIP-NEXT: .cfi_def_cfa_offset 16
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 4
+; ZVZIP-NEXT: sub sp, sp, a0
+; ZVZIP-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
+; ZVZIP-NEXT: li a0, 85
+; ZVZIP-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
+; ZVZIP-NEXT: vmv.v.x v7, a0
+; ZVZIP-NEXT: li a0, 170
+; ZVZIP-NEXT: vmv.v.x v6, a0
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m8, ta, ma
+; ZVZIP-NEXT: vcompress.vm v24, v8, v7
+; ZVZIP-NEXT: vmv1r.v v28, v7
+; ZVZIP-NEXT: vmv1r.v v29, v6
+; ZVZIP-NEXT: vcompress.vm v0, v8, v29
+; ZVZIP-NEXT: vcompress.vm v8, v16, v28
+; ZVZIP-NEXT: addi a0, sp, 16
+; ZVZIP-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: vcompress.vm v8, v16, v29
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 3
+; ZVZIP-NEXT: add a0, sp, a0
+; ZVZIP-NEXT: addi a0, a0, 16
+; ZVZIP-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; ZVZIP-NEXT: addi a0, sp, 16
+; ZVZIP-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vmv4r.v v28, v8
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 3
+; ZVZIP-NEXT: add a0, sp, a0
+; ZVZIP-NEXT: addi a0, a0, 16
+; ZVZIP-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; ZVZIP-NEXT: vmv4r.v v4, v8
+; ZVZIP-NEXT: vmv8r.v v8, v24
+; ZVZIP-NEXT: vmv8r.v v16, v0
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 4
+; ZVZIP-NEXT: add sp, sp, a0
+; ZVZIP-NEXT: .cfi_def_cfa sp, 16
+; ZVZIP-NEXT: addi sp, sp, 16
+; ZVZIP-NEXT: .cfi_def_cfa_offset 0
+; ZVZIP-NEXT: ret
%retval = call {<vscale x 8 x double>, <vscale x 8 x double>} @llvm.vector.deinterleave2.nxv16f64(<vscale x 16 x double> %vec)
ret {<vscale x 8 x double>, <vscale x 8 x double>} %retval
}
@@ -3698,6 +4036,13 @@ define <vscale x 16 x i8> @vector_deinterleave_nxv16i8_nxv32i8_oneactive(<vscale
; ZIP-NEXT: ri.vunzip2a.vv v12, v8, v10
; ZIP-NEXT: vmv.v.v v8, v12
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_deinterleave_nxv16i8_nxv32i8_oneactive:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v12, v8, 0
+; ZVZIP-NEXT: vmv.v.v v8, v12
+; ZVZIP-NEXT: ret
%retval = call {<vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> %vec)
%ext = extractvalue {<vscale x 16 x i8>, <vscale x 16 x i8>} %retval, 0
ret <vscale x 16 x i8> %ext
@@ -3771,6 +4116,17 @@ define { <8 x float>, <8 x float> } @interleave_deinterleave2(<8 x float> %a, <8
; ZIP-NEXT: vnsrl.wx v10, v16, a0
; ZIP-NEXT: vnsrl.wi v8, v16, 0
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: interleave_deinterleave2:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; ZVZIP-NEXT: vwaddu.vv v12, v8, v10
+; ZVZIP-NEXT: li a0, -1
+; ZVZIP-NEXT: vwmaccu.vx v12, a0, v10
+; ZVZIP-NEXT: li a0, 32
+; ZVZIP-NEXT: vnsrl.wx v10, v12, a0
+; ZVZIP-NEXT: vnsrl.wi v8, v12, 0
+; ZVZIP-NEXT: ret
entry:
%0 = call <16 x float> @llvm.vector.interleave2.v16f32(<8 x float> %a, <8 x float> %b)
%1 = call { <8 x float>, <8 x float> } @llvm.vector.deinterleave2.v16f32(<16 x float> %0)
@@ -3798,6 +4154,17 @@ define <16 x float> @deinterleave_interleave2(<16 x float> %arg) {
; ZIP-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; ZIP-NEXT: ri.vzip2a.vv v8, v12, v16
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: deinterleave_interleave2:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: li a0, 32
+; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v12, v8, 0
+; ZVZIP-NEXT: vnsrl.wx v14, v8, a0
+; ZVZIP-NEXT: vwaddu.vv v8, v12, v14
+; ZVZIP-NEXT: li a0, -1
+; ZVZIP-NEXT: vwmaccu.vx v8, a0, v14
+; ZVZIP-NEXT: ret
entry:
%0 = call { <8 x float>, <8 x float> } @llvm.vector.deinterleave2.v16f32(<16 x float> %arg)
%a = extractvalue { <8 x float>, <8 x float> } %0, 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
index 38d38f78c6054..cd47128c776c1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
@@ -5,6 +5,8 @@
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvbb,+zvfh | FileCheck %s --check-prefix=ZVBB
; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvbb,+zvfh,+experimental-xrivosvizip | FileCheck %s --check-prefix=ZIP
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvbb,+zvfh,+experimental-xrivosvizip | FileCheck %s --check-prefix=ZIP
+; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvbb,+zvfh,+experimental-zvzip | FileCheck %s --check-prefix=ZVZIP
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvbb,+zvfh,+experimental-zvzip | FileCheck %s --check-prefix=ZVZIP
; Integers
@@ -58,6 +60,23 @@ define <32 x i1> @vector_interleave_v32i1_v16i1(<16 x i1> %a, <16 x i1> %b) {
; ZIP-NEXT: ri.vzip2a.vv v12, v8, v10
; ZIP-NEXT: vmsne.vi v0, v12, 0
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_v32i1_v16i1:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: li a0, 32
+; ZVZIP-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; ZVZIP-NEXT: vslideup.vi v0, v8, 2
+; ZVZIP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
+; ZVZIP-NEXT: vmv.v.i v8, 0
+; ZVZIP-NEXT: vmerge.vim v8, v8, 1, v0
+; ZVZIP-NEXT: vsetivli zero, 16, e8, m2, ta, ma
+; ZVZIP-NEXT: vslidedown.vi v10, v8, 16
+; ZVZIP-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; ZVZIP-NEXT: vwsll.vi v12, v10, 8
+; ZVZIP-NEXT: vwaddu.wv v12, v12, v8
+; ZVZIP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
+; ZVZIP-NEXT: vmsne.vi v0, v12, 0
+; ZVZIP-NEXT: ret
%res = call <32 x i1> @llvm.vector.interleave2.v32i1(<16 x i1> %a, <16 x i1> %b)
ret <32 x i1> %res
}
@@ -89,6 +108,15 @@ define <16 x i16> @vector_interleave_v16i16_v8i16(<8 x i16> %a, <8 x i16> %b) {
; ZIP-NEXT: ri.vzip2a.vv v10, v8, v12
; ZIP-NEXT: vmv.v.v v8, v10
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_v16i16_v8i16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVZIP-NEXT: vmv1r.v v10, v9
+; ZVZIP-NEXT: vmv1r.v v11, v8
+; ZVZIP-NEXT: vwsll.vi v8, v10, 16
+; ZVZIP-NEXT: vwaddu.wv v8, v8, v11
+; ZVZIP-NEXT: ret
%res = call <16 x i16> @llvm.vector.interleave2.v16i16(<8 x i16> %a, <8 x i16> %b)
ret <16 x i16> %res
}
@@ -121,6 +149,16 @@ define <8 x i32> @vector_interleave_v8i32_v4i32(<4 x i32> %a, <4 x i32> %b) {
; ZIP-NEXT: ri.vzip2a.vv v10, v8, v12
; ZIP-NEXT: vmv.v.v v8, v10
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_v8i32_v4i32:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVZIP-NEXT: vmv1r.v v10, v9
+; ZVZIP-NEXT: vmv1r.v v11, v8
+; ZVZIP-NEXT: li a0, 32
+; ZVZIP-NEXT: vwsll.vx v8, v10, a0
+; ZVZIP-NEXT: vwaddu.wv v8, v8, v11
+; ZVZIP-NEXT: ret
%res = call <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32> %a, <4 x i32> %b)
ret <8 x i32> %res
}
@@ -163,6 +201,21 @@ define <4 x i64> @vector_interleave_v4i64_v2i64(<2 x i64> %a, <2 x i64> %b) {
; ZIP-NEXT: ri.vzip2a.vv v10, v8, v12
; ZIP-NEXT: vmv.v.v v8, v10
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_v4i64_v2i64:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; ZVZIP-NEXT: vmv1r.v v10, v9
+; ZVZIP-NEXT: lui a0, 12304
+; ZVZIP-NEXT: addi a0, a0, 512
+; ZVZIP-NEXT: vslideup.vi v8, v10, 2
+; ZVZIP-NEXT: vmv.s.x v10, a0
+; ZVZIP-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVZIP-NEXT: vsext.vf2 v12, v10
+; ZVZIP-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; ZVZIP-NEXT: vrgatherei16.vv v10, v8, v12
+; ZVZIP-NEXT: vmv.v.v v8, v10
+; ZVZIP-NEXT: ret
%res = call <4 x i64> @llvm.vector.interleave2.v4i64(<2 x i64> %a, <2 x i64> %b)
ret <4 x i64> %res
}
@@ -245,6 +298,32 @@ define <6 x i32> @vector_interleave3_v6i32_v2i32(<2 x i32> %a, <2 x i32> %b, <2
; ZIP-NEXT: add sp, sp, a0
; ZIP-NEXT: addi sp, sp, 16
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave3_v6i32_v2i32:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: addi sp, sp, -16
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 1
+; ZVZIP-NEXT: sub sp, sp, a0
+; ZVZIP-NEXT: addi a0, sp, 16
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: srli a1, a1, 1
+; ZVZIP-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
+; ZVZIP-NEXT: vsseg3e32.v v8, (a0)
+; ZVZIP-NEXT: add a2, a0, a1
+; ZVZIP-NEXT: vle32.v v9, (a2)
+; ZVZIP-NEXT: vle32.v v8, (a0)
+; ZVZIP-NEXT: add a1, a2, a1
+; ZVZIP-NEXT: vle32.v v10, (a1)
+; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVZIP-NEXT: vslideup.vi v8, v9, 2
+; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; ZVZIP-NEXT: vslideup.vi v8, v10, 4
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 1
+; ZVZIP-NEXT: add sp, sp, a0
+; ZVZIP-NEXT: addi sp, sp, 16
+; ZVZIP-NEXT: ret
%res = call <6 x i32> @llvm.vector.interleave3.v6i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c)
ret <6 x i32> %res
}
@@ -336,6 +415,35 @@ define <8 x i32> @vector_interleave4_v8i32_v2i32(<2 x i32> %a, <2 x i32> %b, <2
; ZIP-NEXT: add sp, sp, a0
; ZIP-NEXT: addi sp, sp, 16
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave4_v8i32_v2i32:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: addi sp, sp, -16
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 1
+; ZVZIP-NEXT: sub sp, sp, a0
+; ZVZIP-NEXT: addi a0, sp, 16
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: srli a1, a1, 1
+; ZVZIP-NEXT: add a2, a0, a1
+; ZVZIP-NEXT: vsetvli a3, zero, e32, mf2, ta, ma
+; ZVZIP-NEXT: vsseg4e32.v v8, (a0)
+; ZVZIP-NEXT: add a3, a2, a1
+; ZVZIP-NEXT: add a1, a3, a1
+; ZVZIP-NEXT: vle32.v v10, (a3)
+; ZVZIP-NEXT: vle32.v v9, (a2)
+; ZVZIP-NEXT: vle32.v v11, (a1)
+; ZVZIP-NEXT: vle32.v v8, (a0)
+; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVZIP-NEXT: vslideup.vi v10, v11, 2
+; ZVZIP-NEXT: vslideup.vi v8, v9, 2
+; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; ZVZIP-NEXT: vslideup.vi v8, v10, 4
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 1
+; ZVZIP-NEXT: add sp, sp, a0
+; ZVZIP-NEXT: addi sp, sp, 16
+; ZVZIP-NEXT: ret
%res = call <8 x i32> @llvm.vector.interleave4.v8i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 x i32> %d)
ret <8 x i32> %res
}
@@ -439,6 +547,39 @@ define <10 x i16> @vector_interleave5_v10i16_v2i16(<2 x i16> %a, <2 x i16> %b, <
; ZIP-NEXT: add sp, sp, a0
; ZIP-NEXT: addi sp, sp, 16
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave5_v10i16_v2i16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: addi sp, sp, -16
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 1
+; ZVZIP-NEXT: sub sp, sp, a0
+; ZVZIP-NEXT: addi a0, sp, 16
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: srli a1, a1, 2
+; ZVZIP-NEXT: add a2, a0, a1
+; ZVZIP-NEXT: add a3, a2, a1
+; ZVZIP-NEXT: vsetvli a4, zero, e16, mf4, ta, ma
+; ZVZIP-NEXT: vsseg5e16.v v8, (a0)
+; ZVZIP-NEXT: add a4, a3, a1
+; ZVZIP-NEXT: vle16.v v9, (a2)
+; ZVZIP-NEXT: vle16.v v11, (a4)
+; ZVZIP-NEXT: vle16.v v12, (a3)
+; ZVZIP-NEXT: vle16.v v8, (a0)
+; ZVZIP-NEXT: add a1, a4, a1
+; ZVZIP-NEXT: vle16.v v10, (a1)
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVZIP-NEXT: vslideup.vi v12, v11, 2
+; ZVZIP-NEXT: vslideup.vi v8, v9, 2
+; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVZIP-NEXT: vslideup.vi v8, v12, 4
+; ZVZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVZIP-NEXT: vslideup.vi v8, v10, 8
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 1
+; ZVZIP-NEXT: add sp, sp, a0
+; ZVZIP-NEXT: addi sp, sp, 16
+; ZVZIP-NEXT: ret
%res = call <10 x i16> @llvm.vector.interleave5.v10i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 x i16> %d, <2 x i16> %e)
ret <10 x i16> %res
}
@@ -551,6 +692,42 @@ define <12 x i16> @vector_interleave6_v12i16_v2i16(<2 x i16> %a, <2 x i16> %b, <
; ZIP-NEXT: add sp, sp, a0
; ZIP-NEXT: addi sp, sp, 16
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave6_v12i16_v2i16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: addi sp, sp, -16
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 1
+; ZVZIP-NEXT: sub sp, sp, a0
+; ZVZIP-NEXT: addi a0, sp, 16
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: srli a1, a1, 2
+; ZVZIP-NEXT: add a2, a0, a1
+; ZVZIP-NEXT: add a3, a2, a1
+; ZVZIP-NEXT: vsetvli a4, zero, e16, mf4, ta, ma
+; ZVZIP-NEXT: vsseg6e16.v v8, (a0)
+; ZVZIP-NEXT: vle16.v v9, (a2)
+; ZVZIP-NEXT: add a2, a3, a1
+; ZVZIP-NEXT: vle16.v v11, (a2)
+; ZVZIP-NEXT: add a2, a2, a1
+; ZVZIP-NEXT: vle16.v v12, (a3)
+; ZVZIP-NEXT: add a1, a2, a1
+; ZVZIP-NEXT: vle16.v v10, (a2)
+; ZVZIP-NEXT: vle16.v v8, (a0)
+; ZVZIP-NEXT: vle16.v v13, (a1)
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVZIP-NEXT: vslideup.vi v12, v11, 2
+; ZVZIP-NEXT: vslideup.vi v8, v9, 2
+; ZVZIP-NEXT: vslideup.vi v10, v13, 2
+; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVZIP-NEXT: vslideup.vi v8, v12, 4
+; ZVZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVZIP-NEXT: vslideup.vi v8, v10, 8
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 1
+; ZVZIP-NEXT: add sp, sp, a0
+; ZVZIP-NEXT: addi sp, sp, 16
+; ZVZIP-NEXT: ret
%res = call <12 x i16> @llvm.vector.interleave6.v12i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 x i16> %d, <2 x i16> %e, <2 x i16> %f)
ret <12 x i16> %res
}
@@ -669,6 +846,44 @@ define <14 x i8> @vector_interleave7_v14i8_v2i8(<2 x i8> %a, <2 x i8> %b, <2 x i
; ZIP-NEXT: add sp, sp, a0
; ZIP-NEXT: addi sp, sp, 16
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave7_v14i8_v2i8:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: addi sp, sp, -16
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: sub sp, sp, a0
+; ZVZIP-NEXT: addi a0, sp, 16
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: srli a1, a1, 3
+; ZVZIP-NEXT: add a2, a0, a1
+; ZVZIP-NEXT: add a3, a2, a1
+; ZVZIP-NEXT: add a4, a3, a1
+; ZVZIP-NEXT: vsetvli a5, zero, e8, mf8, ta, ma
+; ZVZIP-NEXT: vsseg7e8.v v8, (a0)
+; ZVZIP-NEXT: vle8.v v9, (a4)
+; ZVZIP-NEXT: add a4, a4, a1
+; ZVZIP-NEXT: vle8.v v10, (a2)
+; ZVZIP-NEXT: add a2, a4, a1
+; ZVZIP-NEXT: add a1, a2, a1
+; ZVZIP-NEXT: vle8.v v11, (a2)
+; ZVZIP-NEXT: vle8.v v12, (a4)
+; ZVZIP-NEXT: vle8.v v8, (a0)
+; ZVZIP-NEXT: vle8.v v13, (a1)
+; ZVZIP-NEXT: vle8.v v14, (a3)
+; ZVZIP-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
+; ZVZIP-NEXT: vslideup.vi v12, v11, 2
+; ZVZIP-NEXT: vslideup.vi v8, v10, 2
+; ZVZIP-NEXT: vsetivli zero, 6, e8, mf2, tu, ma
+; ZVZIP-NEXT: vslideup.vi v12, v13, 4
+; ZVZIP-NEXT: vslideup.vi v8, v14, 4
+; ZVZIP-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; ZVZIP-NEXT: vslideup.vi v8, v9, 6
+; ZVZIP-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; ZVZIP-NEXT: vslideup.vi v8, v12, 8
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: add sp, sp, a0
+; ZVZIP-NEXT: addi sp, sp, 16
+; ZVZIP-NEXT: ret
%res = call <14 x i8> @llvm.vector.interleave7.v14i8(<2 x i8> %a, <2 x i8> %b, <2 x i8> %c, <2 x i8> %d, <2 x i8> %e, <2 x i8> %f, <2 x i8> %g)
ret <14 x i8> %res
}
@@ -796,6 +1011,47 @@ define <16 x i8> @vector_interleave8_v16i8_v2i8(<2 x i8> %a, <2 x i8> %b, <2 x i
; ZIP-NEXT: add sp, sp, a0
; ZIP-NEXT: addi sp, sp, 16
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave8_v16i8_v2i8:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: addi sp, sp, -16
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: sub sp, sp, a0
+; ZVZIP-NEXT: addi a0, sp, 16
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: srli a1, a1, 3
+; ZVZIP-NEXT: add a2, a0, a1
+; ZVZIP-NEXT: add a3, a2, a1
+; ZVZIP-NEXT: add a4, a3, a1
+; ZVZIP-NEXT: add a5, a4, a1
+; ZVZIP-NEXT: add a6, a5, a1
+; ZVZIP-NEXT: vsetvli a7, zero, e8, mf8, ta, ma
+; ZVZIP-NEXT: vsseg8e8.v v8, (a0)
+; ZVZIP-NEXT: vle8.v v9, (a6)
+; ZVZIP-NEXT: add a6, a6, a1
+; ZVZIP-NEXT: vle8.v v10, (a5)
+; ZVZIP-NEXT: vle8.v v11, (a6)
+; ZVZIP-NEXT: add a1, a6, a1
+; ZVZIP-NEXT: vle8.v v12, (a2)
+; ZVZIP-NEXT: vle8.v v8, (a0)
+; ZVZIP-NEXT: vle8.v v13, (a3)
+; ZVZIP-NEXT: vle8.v v14, (a4)
+; ZVZIP-NEXT: vle8.v v15, (a1)
+; ZVZIP-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
+; ZVZIP-NEXT: vslideup.vi v10, v9, 2
+; ZVZIP-NEXT: vslideup.vi v8, v12, 2
+; ZVZIP-NEXT: vsetivli zero, 6, e8, mf2, tu, ma
+; ZVZIP-NEXT: vslideup.vi v10, v11, 4
+; ZVZIP-NEXT: vslideup.vi v8, v13, 4
+; ZVZIP-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; ZVZIP-NEXT: vslideup.vi v10, v15, 6
+; ZVZIP-NEXT: vslideup.vi v8, v14, 6
+; ZVZIP-NEXT: vsetivli zero, 16, e8, m1, ta, ma
+; ZVZIP-NEXT: vslideup.vi v8, v10, 8
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: add sp, sp, a0
+; ZVZIP-NEXT: addi sp, sp, 16
+; ZVZIP-NEXT: ret
%res = call <16 x i8> @llvm.vector.interleave8.v16i8(<2 x i8> %a, <2 x i8> %b, <2 x i8> %c, <2 x i8> %d, <2 x i8> %e, <2 x i8> %f, <2 x i8> %g, <2 x i8> %h)
ret <16 x i8> %res
}
@@ -826,6 +1082,14 @@ define <4 x half> @vector_interleave_v4f16_v2f16(<2 x half> %a, <2 x half> %b) {
; ZIP-NEXT: ri.vzip2a.vv v10, v8, v9
; ZIP-NEXT: vmv1r.v v8, v10
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_v4f16_v2f16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-NEXT: vwsll.vi v10, v9, 16
+; ZVZIP-NEXT: vwaddu.wv v10, v10, v8
+; ZVZIP-NEXT: vmv1r.v v8, v10
+; ZVZIP-NEXT: ret
%res = call <4 x half> @llvm.vector.interleave2.v4f16(<2 x half> %a, <2 x half> %b)
ret <4 x half> %res
}
@@ -854,6 +1118,14 @@ define <8 x half> @vector_interleave_v8f16_v4f16(<4 x half> %a, <4 x half> %b) {
; ZIP-NEXT: ri.vzip2a.vv v10, v8, v9
; ZIP-NEXT: vmv.v.v v8, v10
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_v8f16_v4f16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVZIP-NEXT: vwsll.vi v10, v9, 16
+; ZVZIP-NEXT: vwaddu.wv v10, v10, v8
+; ZVZIP-NEXT: vmv1r.v v8, v10
+; ZVZIP-NEXT: ret
%res = call <8 x half> @llvm.vector.interleave2.v8f16(<4 x half> %a, <4 x half> %b)
ret <8 x half> %res
}
@@ -883,6 +1155,15 @@ define <4 x float> @vector_interleave_v4f32_v2f32(<2 x float> %a, <2 x float> %b
; ZIP-NEXT: ri.vzip2a.vv v10, v8, v9
; ZIP-NEXT: vmv.v.v v8, v10
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_v4f32_v2f32:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: li a0, 32
+; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-NEXT: vwsll.vx v10, v9, a0
+; ZVZIP-NEXT: vwaddu.wv v10, v10, v8
+; ZVZIP-NEXT: vmv1r.v v8, v10
+; ZVZIP-NEXT: ret
%res = call <4 x float> @llvm.vector.interleave2.v4f32(<2 x float> %a, <2 x float> %b)
ret <4 x float> %res
}
@@ -914,6 +1195,15 @@ define <16 x half> @vector_interleave_v16f16_v8f16(<8 x half> %a, <8 x half> %b)
; ZIP-NEXT: ri.vzip2a.vv v10, v8, v12
; ZIP-NEXT: vmv.v.v v8, v10
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_v16f16_v8f16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVZIP-NEXT: vmv1r.v v10, v9
+; ZVZIP-NEXT: vmv1r.v v11, v8
+; ZVZIP-NEXT: vwsll.vi v8, v10, 16
+; ZVZIP-NEXT: vwaddu.wv v8, v8, v11
+; ZVZIP-NEXT: ret
%res = call <16 x half> @llvm.vector.interleave2.v16f16(<8 x half> %a, <8 x half> %b)
ret <16 x half> %res
}
@@ -946,6 +1236,16 @@ define <8 x float> @vector_interleave_v8f32_v4f32(<4 x float> %a, <4 x float> %b
; ZIP-NEXT: ri.vzip2a.vv v10, v8, v12
; ZIP-NEXT: vmv.v.v v8, v10
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_v8f32_v4f32:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVZIP-NEXT: vmv1r.v v10, v9
+; ZVZIP-NEXT: vmv1r.v v11, v8
+; ZVZIP-NEXT: li a0, 32
+; ZVZIP-NEXT: vwsll.vx v8, v10, a0
+; ZVZIP-NEXT: vwaddu.wv v8, v8, v11
+; ZVZIP-NEXT: ret
%res = call <8 x float> @llvm.vector.interleave2.v8f32(<4 x float> %a, <4 x float> %b)
ret <8 x float> %res
}
@@ -988,6 +1288,21 @@ define <4 x double> @vector_interleave_v4f64_v2f64(<2 x double> %a, <2 x double>
; ZIP-NEXT: ri.vzip2a.vv v10, v8, v12
; ZIP-NEXT: vmv.v.v v8, v10
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_v4f64_v2f64:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; ZVZIP-NEXT: vmv1r.v v10, v9
+; ZVZIP-NEXT: lui a0, 12304
+; ZVZIP-NEXT: addi a0, a0, 512
+; ZVZIP-NEXT: vslideup.vi v8, v10, 2
+; ZVZIP-NEXT: vmv.s.x v10, a0
+; ZVZIP-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVZIP-NEXT: vsext.vf2 v12, v10
+; ZVZIP-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; ZVZIP-NEXT: vrgatherei16.vv v10, v8, v12
+; ZVZIP-NEXT: vmv.v.v v8, v10
+; ZVZIP-NEXT: ret
%res = call <4 x double> @llvm.vector.interleave2.v4f64(<2 x double> %a, <2 x double> %b)
ret <4 x double> %res
}
@@ -1070,6 +1385,32 @@ define <6 x float> @vector_interleave3_v6f32_v2f32(<2 x float> %a, <2 x float> %
; ZIP-NEXT: add sp, sp, a0
; ZIP-NEXT: addi sp, sp, 16
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave3_v6f32_v2f32:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: addi sp, sp, -16
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 1
+; ZVZIP-NEXT: sub sp, sp, a0
+; ZVZIP-NEXT: addi a0, sp, 16
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: srli a1, a1, 1
+; ZVZIP-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
+; ZVZIP-NEXT: vsseg3e32.v v8, (a0)
+; ZVZIP-NEXT: add a2, a0, a1
+; ZVZIP-NEXT: vle32.v v9, (a2)
+; ZVZIP-NEXT: vle32.v v8, (a0)
+; ZVZIP-NEXT: add a1, a2, a1
+; ZVZIP-NEXT: vle32.v v10, (a1)
+; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVZIP-NEXT: vslideup.vi v8, v9, 2
+; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; ZVZIP-NEXT: vslideup.vi v8, v10, 4
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 1
+; ZVZIP-NEXT: add sp, sp, a0
+; ZVZIP-NEXT: addi sp, sp, 16
+; ZVZIP-NEXT: ret
%res = call <6 x float> @llvm.vector.interleave3.v6f32(<2 x float> %a, <2 x float> %b, <2 x float> %c)
ret <6 x float> %res
}
@@ -1161,6 +1502,35 @@ define <8 x float> @vector_interleave4_v8f32_v2f32(<2 x float> %a, <2 x float> %
; ZIP-NEXT: add sp, sp, a0
; ZIP-NEXT: addi sp, sp, 16
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave4_v8f32_v2f32:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: addi sp, sp, -16
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 1
+; ZVZIP-NEXT: sub sp, sp, a0
+; ZVZIP-NEXT: addi a0, sp, 16
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: srli a1, a1, 1
+; ZVZIP-NEXT: add a2, a0, a1
+; ZVZIP-NEXT: vsetvli a3, zero, e32, mf2, ta, ma
+; ZVZIP-NEXT: vsseg4e32.v v8, (a0)
+; ZVZIP-NEXT: add a3, a2, a1
+; ZVZIP-NEXT: add a1, a3, a1
+; ZVZIP-NEXT: vle32.v v10, (a3)
+; ZVZIP-NEXT: vle32.v v9, (a2)
+; ZVZIP-NEXT: vle32.v v11, (a1)
+; ZVZIP-NEXT: vle32.v v8, (a0)
+; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVZIP-NEXT: vslideup.vi v10, v11, 2
+; ZVZIP-NEXT: vslideup.vi v8, v9, 2
+; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; ZVZIP-NEXT: vslideup.vi v8, v10, 4
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 1
+; ZVZIP-NEXT: add sp, sp, a0
+; ZVZIP-NEXT: addi sp, sp, 16
+; ZVZIP-NEXT: ret
%res = call <8 x float> @llvm.vector.interleave4.v8f32(<2 x float> %a, <2 x float> %b, <2 x float> %c, <2 x float> %d)
ret <8 x float> %res
}
@@ -1264,6 +1634,39 @@ define <10 x half> @vector_interleave5_v10f16_v2f16(<2 x half> %a, <2 x half> %b
; ZIP-NEXT: add sp, sp, a0
; ZIP-NEXT: addi sp, sp, 16
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave5_v10f16_v2f16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: addi sp, sp, -16
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 1
+; ZVZIP-NEXT: sub sp, sp, a0
+; ZVZIP-NEXT: addi a0, sp, 16
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: srli a1, a1, 2
+; ZVZIP-NEXT: add a2, a0, a1
+; ZVZIP-NEXT: add a3, a2, a1
+; ZVZIP-NEXT: vsetvli a4, zero, e16, mf4, ta, ma
+; ZVZIP-NEXT: vsseg5e16.v v8, (a0)
+; ZVZIP-NEXT: add a4, a3, a1
+; ZVZIP-NEXT: vle16.v v9, (a2)
+; ZVZIP-NEXT: vle16.v v11, (a4)
+; ZVZIP-NEXT: vle16.v v12, (a3)
+; ZVZIP-NEXT: vle16.v v8, (a0)
+; ZVZIP-NEXT: add a1, a4, a1
+; ZVZIP-NEXT: vle16.v v10, (a1)
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVZIP-NEXT: vslideup.vi v12, v11, 2
+; ZVZIP-NEXT: vslideup.vi v8, v9, 2
+; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVZIP-NEXT: vslideup.vi v8, v12, 4
+; ZVZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVZIP-NEXT: vslideup.vi v8, v10, 8
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 1
+; ZVZIP-NEXT: add sp, sp, a0
+; ZVZIP-NEXT: addi sp, sp, 16
+; ZVZIP-NEXT: ret
%res = call <10 x half> @llvm.vector.interleave5.v10f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, <2 x half> %d, <2 x half> %e)
ret <10 x half> %res
}
@@ -1376,6 +1779,42 @@ define <12 x half> @vector_interleave6_v12f16_v2f16(<2 x half> %a, <2 x half> %b
; ZIP-NEXT: add sp, sp, a0
; ZIP-NEXT: addi sp, sp, 16
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave6_v12f16_v2f16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: addi sp, sp, -16
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 1
+; ZVZIP-NEXT: sub sp, sp, a0
+; ZVZIP-NEXT: addi a0, sp, 16
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: srli a1, a1, 2
+; ZVZIP-NEXT: add a2, a0, a1
+; ZVZIP-NEXT: add a3, a2, a1
+; ZVZIP-NEXT: vsetvli a4, zero, e16, mf4, ta, ma
+; ZVZIP-NEXT: vsseg6e16.v v8, (a0)
+; ZVZIP-NEXT: vle16.v v9, (a2)
+; ZVZIP-NEXT: add a2, a3, a1
+; ZVZIP-NEXT: vle16.v v11, (a2)
+; ZVZIP-NEXT: add a2, a2, a1
+; ZVZIP-NEXT: vle16.v v12, (a3)
+; ZVZIP-NEXT: add a1, a2, a1
+; ZVZIP-NEXT: vle16.v v10, (a2)
+; ZVZIP-NEXT: vle16.v v8, (a0)
+; ZVZIP-NEXT: vle16.v v13, (a1)
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVZIP-NEXT: vslideup.vi v12, v11, 2
+; ZVZIP-NEXT: vslideup.vi v8, v9, 2
+; ZVZIP-NEXT: vslideup.vi v10, v13, 2
+; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVZIP-NEXT: vslideup.vi v8, v12, 4
+; ZVZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVZIP-NEXT: vslideup.vi v8, v10, 8
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 1
+; ZVZIP-NEXT: add sp, sp, a0
+; ZVZIP-NEXT: addi sp, sp, 16
+; ZVZIP-NEXT: ret
%res = call <12 x half> @llvm.vector.interleave6.v12f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, <2 x half> %d, <2 x half> %e, <2 x half> %f)
ret <12 x half> %res
}
@@ -1500,6 +1939,46 @@ define <7 x half> @vector_interleave7_v7f16_v1f16(<1 x half> %a, <1 x half> %b,
; ZIP-NEXT: add sp, sp, a0
; ZIP-NEXT: addi sp, sp, 16
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave7_v7f16_v1f16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: addi sp, sp, -16
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 1
+; ZVZIP-NEXT: sub sp, sp, a0
+; ZVZIP-NEXT: addi a0, sp, 16
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: srli a1, a1, 2
+; ZVZIP-NEXT: add a2, a0, a1
+; ZVZIP-NEXT: add a3, a2, a1
+; ZVZIP-NEXT: add a4, a3, a1
+; ZVZIP-NEXT: vsetvli a5, zero, e16, mf4, ta, ma
+; ZVZIP-NEXT: vsseg7e16.v v8, (a0)
+; ZVZIP-NEXT: vle16.v v9, (a4)
+; ZVZIP-NEXT: add a4, a4, a1
+; ZVZIP-NEXT: vle16.v v10, (a2)
+; ZVZIP-NEXT: add a2, a4, a1
+; ZVZIP-NEXT: add a1, a2, a1
+; ZVZIP-NEXT: vle16.v v11, (a2)
+; ZVZIP-NEXT: vle16.v v12, (a4)
+; ZVZIP-NEXT: vle16.v v8, (a0)
+; ZVZIP-NEXT: vle16.v v13, (a1)
+; ZVZIP-NEXT: vle16.v v14, (a3)
+; ZVZIP-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
+; ZVZIP-NEXT: vslideup.vi v12, v11, 1
+; ZVZIP-NEXT: vslideup.vi v8, v10, 1
+; ZVZIP-NEXT: vsetivli zero, 3, e16, mf2, tu, ma
+; ZVZIP-NEXT: vslideup.vi v12, v13, 2
+; ZVZIP-NEXT: vslideup.vi v8, v14, 2
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVZIP-NEXT: vslideup.vi v8, v9, 3
+; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVZIP-NEXT: vslideup.vi v8, v12, 4
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 1
+; ZVZIP-NEXT: add sp, sp, a0
+; ZVZIP-NEXT: addi sp, sp, 16
+; ZVZIP-NEXT: ret
%res = call <7 x half> @llvm.vector.interleave7.v7f16(<1 x half> %a, <1 x half> %b, <1 x half> %c, <1 x half> %d, <1 x half> %e, <1 x half> %f, <1 x half> %g)
ret <7 x half> %res
}
@@ -1633,6 +2112,49 @@ define <8 x half> @vector_interleave8_v8f16_v1f16(<1 x half> %a, <1 x half> %b,
; ZIP-NEXT: add sp, sp, a0
; ZIP-NEXT: addi sp, sp, 16
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave8_v8f16_v1f16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: addi sp, sp, -16
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 1
+; ZVZIP-NEXT: sub sp, sp, a0
+; ZVZIP-NEXT: addi a0, sp, 16
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: srli a1, a1, 2
+; ZVZIP-NEXT: add a2, a0, a1
+; ZVZIP-NEXT: add a3, a2, a1
+; ZVZIP-NEXT: add a4, a3, a1
+; ZVZIP-NEXT: add a5, a4, a1
+; ZVZIP-NEXT: add a6, a5, a1
+; ZVZIP-NEXT: vsetvli a7, zero, e16, mf4, ta, ma
+; ZVZIP-NEXT: vsseg8e16.v v8, (a0)
+; ZVZIP-NEXT: vle16.v v9, (a6)
+; ZVZIP-NEXT: add a6, a6, a1
+; ZVZIP-NEXT: vle16.v v10, (a5)
+; ZVZIP-NEXT: vle16.v v11, (a6)
+; ZVZIP-NEXT: add a1, a6, a1
+; ZVZIP-NEXT: vle16.v v12, (a2)
+; ZVZIP-NEXT: vle16.v v8, (a0)
+; ZVZIP-NEXT: vle16.v v13, (a3)
+; ZVZIP-NEXT: vle16.v v14, (a4)
+; ZVZIP-NEXT: vle16.v v15, (a1)
+; ZVZIP-NEXT: vsetivli zero, 2, e16, mf2, tu, ma
+; ZVZIP-NEXT: vslideup.vi v10, v9, 1
+; ZVZIP-NEXT: vslideup.vi v8, v12, 1
+; ZVZIP-NEXT: vsetivli zero, 3, e16, mf2, tu, ma
+; ZVZIP-NEXT: vslideup.vi v10, v11, 2
+; ZVZIP-NEXT: vslideup.vi v8, v13, 2
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVZIP-NEXT: vslideup.vi v10, v15, 3
+; ZVZIP-NEXT: vslideup.vi v8, v14, 3
+; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVZIP-NEXT: vslideup.vi v8, v10, 4
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 1
+; ZVZIP-NEXT: add sp, sp, a0
+; ZVZIP-NEXT: addi sp, sp, 16
+; ZVZIP-NEXT: ret
%res = call <8 x half> @llvm.vector.interleave8.v8f16(<1 x half> %a, <1 x half> %b, <1 x half> %c, <1 x half> %d, <1 x half> %e, <1 x half> %f, <1 x half> %g, <1 x half> %h)
ret <8 x half> %res
}
@@ -1655,6 +2177,12 @@ define <8 x i16> @interleave4_const_splat_v8i16(<2 x i16> %a) {
; ZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZIP-NEXT: vmv.v.i v8, 3
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: interleave4_const_splat_v8i16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVZIP-NEXT: vmv.v.i v8, 3
+; ZVZIP-NEXT: ret
%retval = call <8 x i16> @llvm.vector.interleave4.v8i16(<2 x i16> splat(i16 3), <2 x i16> splat(i16 3), <2 x i16> splat(i16 3), <2 x i16> splat(i16 3))
ret <8 x i16> %retval
}
@@ -1677,6 +2205,12 @@ define <8 x i16> @interleave4_same_nonconst_splat_v8i16(i16 %a) {
; ZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZIP-NEXT: vmv.v.x v8, a0
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: interleave4_same_nonconst_splat_v8i16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVZIP-NEXT: vmv.v.x v8, a0
+; ZVZIP-NEXT: ret
%ins = insertelement <2 x i16> poison, i16 %a, i32 0
%splat = shufflevector <2 x i16> %ins, <2 x i16> poison, <2 x i32> zeroinitializer
%retval = call <8 x i16> @llvm.vector.interleave4.v8i16(<2 x i16> %splat, <2 x i16> %splat, <2 x i16> %splat, <2 x i16> %splat)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
index 0577fb1ff67bb..6bccdb0b766b1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
@@ -6,6 +6,7 @@
; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+v,+zvbb,+zvfh,+zvfbfmin | FileCheck %s --check-prefixes=ZVBB,ZVBB-RV32
; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+zvbb,+zvfh,+zvfbfmin | FileCheck %s --check-prefixes=ZVBB,ZVBB-RV64
; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+zvfhmin,+zvfbfmin,+experimental-xrivosvizip | FileCheck %s --check-prefixes=CHECK,ZIP
+; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+zvfhmin,+zvfbfmin,+experimental-zvzip | FileCheck %s --check-prefixes=CHECK,ZVZIP
; Integers
@@ -67,6 +68,26 @@ define <vscale x 32 x i1> @vector_interleave_nxv32i1_nxv16i1(<vscale x 16 x i1>
; ZIP-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
; ZIP-NEXT: vslideup.vx v0, v8, a0
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv32i1_nxv16i1:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; ZVZIP-NEXT: vmv1r.v v9, v0
+; ZVZIP-NEXT: vmv1r.v v0, v8
+; ZVZIP-NEXT: vmv.v.i v10, 0
+; ZVZIP-NEXT: li a0, -1
+; ZVZIP-NEXT: vmerge.vim v12, v10, 1, v0
+; ZVZIP-NEXT: vmv1r.v v0, v9
+; ZVZIP-NEXT: vmerge.vim v14, v10, 1, v0
+; ZVZIP-NEXT: vwaddu.vv v8, v14, v12
+; ZVZIP-NEXT: vwmaccu.vx v8, a0, v12
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: vmsne.vi v12, v10, 0
+; ZVZIP-NEXT: vmsne.vi v0, v8, 0
+; ZVZIP-NEXT: srli a0, a0, 2
+; ZVZIP-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
+; ZVZIP-NEXT: vslideup.vx v0, v12, a0
+; ZVZIP-NEXT: ret
%res = call <vscale x 32 x i1> @llvm.vector.interleave2.nxv32i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b)
ret <vscale x 32 x i1> %res
}
@@ -99,6 +120,16 @@ define <vscale x 32 x i8> @vector_interleave_nxv32i8_nxv16i8(<vscale x 16 x i8>
; ZIP-NEXT: ri.vzip2b.vv v10, v8, v12
; ZIP-NEXT: ri.vzip2a.vv v8, v14, v12
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv32i8_nxv16i8:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; ZVZIP-NEXT: vmv2r.v v12, v10
+; ZVZIP-NEXT: vmv2r.v v14, v8
+; ZVZIP-NEXT: vwaddu.vv v8, v14, v12
+; ZVZIP-NEXT: li a0, -1
+; ZVZIP-NEXT: vwmaccu.vx v8, a0, v12
+; ZVZIP-NEXT: ret
%res = call <vscale x 32 x i8> @llvm.vector.interleave2.nxv32i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
ret <vscale x 32 x i8> %res
}
@@ -131,6 +162,16 @@ define <vscale x 16 x i16> @vector_interleave_nxv16i16_nxv8i16(<vscale x 8 x i16
; ZIP-NEXT: ri.vzip2b.vv v10, v8, v12
; ZIP-NEXT: ri.vzip2a.vv v8, v14, v12
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv16i16_nxv8i16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVZIP-NEXT: vmv2r.v v12, v10
+; ZVZIP-NEXT: vmv2r.v v14, v8
+; ZVZIP-NEXT: vwaddu.vv v8, v14, v12
+; ZVZIP-NEXT: li a0, -1
+; ZVZIP-NEXT: vwmaccu.vx v8, a0, v12
+; ZVZIP-NEXT: ret
%res = call <vscale x 16 x i16> @llvm.vector.interleave2.nxv16i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)
ret <vscale x 16 x i16> %res
}
@@ -164,6 +205,16 @@ define <vscale x 8 x i32> @vector_interleave_nxv8i32_nxv4i32(<vscale x 4 x i32>
; ZIP-NEXT: ri.vzip2b.vv v10, v8, v12
; ZIP-NEXT: ri.vzip2a.vv v8, v14, v12
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv8i32_nxv4i32:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; ZVZIP-NEXT: vmv2r.v v12, v10
+; ZVZIP-NEXT: vmv2r.v v14, v8
+; ZVZIP-NEXT: vwaddu.vv v8, v14, v12
+; ZVZIP-NEXT: li a0, -1
+; ZVZIP-NEXT: vwmaccu.vx v8, a0, v12
+; ZVZIP-NEXT: ret
%res = call <vscale x 8 x i32> @llvm.vector.interleave2.nxv8i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)
ret <vscale x 8 x i32> %res
}
@@ -207,6 +258,21 @@ define <vscale x 4 x i64> @vector_interleave_nxv4i64_nxv2i64(<vscale x 2 x i64>
; ZIP-NEXT: ri.vzip2b.vv v10, v8, v12
; ZIP-NEXT: ri.vzip2a.vv v8, v14, v12
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv4i64_nxv2i64:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: vsetvli a1, zero, e16, m1, ta, mu
+; ZVZIP-NEXT: vid.v v12
+; ZVZIP-NEXT: srli a0, a0, 2
+; ZVZIP-NEXT: vand.vi v13, v12, 1
+; ZVZIP-NEXT: vmsne.vi v0, v13, 0
+; ZVZIP-NEXT: vsrl.vi v16, v12, 1
+; ZVZIP-NEXT: vadd.vx v16, v16, a0, v0.t
+; ZVZIP-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; ZVZIP-NEXT: vrgatherei16.vv v12, v8, v16
+; ZVZIP-NEXT: vmv.v.v v8, v12
+; ZVZIP-NEXT: ret
%res = call <vscale x 4 x i64> @llvm.vector.interleave2.nxv4i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)
ret <vscale x 4 x i64> %res
}
@@ -271,6 +337,27 @@ define <vscale x 128 x i1> @vector_interleave_nxv128i1_nxv64i1(<vscale x 64 x i1
; ZIP-NEXT: vmsne.vi v8, v24, 0
; ZIP-NEXT: vmv1r.v v0, v9
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv128i1_nxv64i1:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
+; ZVZIP-NEXT: vmv1r.v v9, v0
+; ZVZIP-NEXT: vmv1r.v v0, v8
+; ZVZIP-NEXT: vmv.v.i v24, 0
+; ZVZIP-NEXT: li a0, -1
+; ZVZIP-NEXT: vmerge.vim v16, v24, 1, v0
+; ZVZIP-NEXT: vmv1r.v v0, v9
+; ZVZIP-NEXT: vmerge.vim v24, v24, 1, v0
+; ZVZIP-NEXT: vsetvli a1, zero, e8, m4, ta, ma
+; ZVZIP-NEXT: vwaddu.vv v8, v24, v16
+; ZVZIP-NEXT: vwaddu.vv v0, v28, v20
+; ZVZIP-NEXT: vwmaccu.vx v8, a0, v16
+; ZVZIP-NEXT: vwmaccu.vx v0, a0, v20
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
+; ZVZIP-NEXT: vmsne.vi v16, v8, 0
+; ZVZIP-NEXT: vmsne.vi v8, v0, 0
+; ZVZIP-NEXT: vmv1r.v v0, v16
+; ZVZIP-NEXT: ret
%res = call <vscale x 128 x i1> @llvm.vector.interleave2.nxv128i1(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b)
ret <vscale x 128 x i1> %res
}
@@ -309,6 +396,18 @@ define <vscale x 128 x i8> @vector_interleave_nxv128i8_nxv64i8(<vscale x 64 x i8
; ZIP-NEXT: vmv8r.v v8, v24
; ZIP-NEXT: vmv8r.v v16, v0
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv128i8_nxv64i8:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
+; ZVZIP-NEXT: vmv8r.v v24, v8
+; ZVZIP-NEXT: vwaddu.vv v8, v24, v16
+; ZVZIP-NEXT: li a0, -1
+; ZVZIP-NEXT: vwaddu.vv v0, v28, v20
+; ZVZIP-NEXT: vwmaccu.vx v8, a0, v16
+; ZVZIP-NEXT: vwmaccu.vx v0, a0, v20
+; ZVZIP-NEXT: vmv8r.v v16, v0
+; ZVZIP-NEXT: ret
%res = call <vscale x 128 x i8> @llvm.vector.interleave2.nxv128i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b)
ret <vscale x 128 x i8> %res
}
@@ -347,6 +446,18 @@ define <vscale x 64 x i16> @vector_interleave_nxv64i16_nxv32i16(<vscale x 32 x i
; ZIP-NEXT: vmv8r.v v8, v24
; ZIP-NEXT: vmv8r.v v16, v0
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv64i16_nxv32i16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVZIP-NEXT: vmv8r.v v24, v8
+; ZVZIP-NEXT: vwaddu.vv v8, v24, v16
+; ZVZIP-NEXT: li a0, -1
+; ZVZIP-NEXT: vwaddu.vv v0, v28, v20
+; ZVZIP-NEXT: vwmaccu.vx v8, a0, v16
+; ZVZIP-NEXT: vwmaccu.vx v0, a0, v20
+; ZVZIP-NEXT: vmv8r.v v16, v0
+; ZVZIP-NEXT: ret
%res = call <vscale x 64 x i16> @llvm.vector.interleave2.nxv64i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b)
ret <vscale x 64 x i16> %res
}
@@ -386,6 +497,18 @@ define <vscale x 32 x i32> @vector_interleave_nxv32i32_nxv16i32(<vscale x 16 x i
; ZIP-NEXT: vmv8r.v v8, v24
; ZIP-NEXT: vmv8r.v v16, v0
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv32i32_nxv16i32:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVZIP-NEXT: vmv8r.v v24, v8
+; ZVZIP-NEXT: vwaddu.vv v8, v24, v16
+; ZVZIP-NEXT: li a0, -1
+; ZVZIP-NEXT: vwaddu.vv v0, v28, v20
+; ZVZIP-NEXT: vwmaccu.vx v8, a0, v16
+; ZVZIP-NEXT: vwmaccu.vx v0, a0, v20
+; ZVZIP-NEXT: vmv8r.v v16, v0
+; ZVZIP-NEXT: ret
%res = call <vscale x 32 x i32> @llvm.vector.interleave2.nxv32i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b)
ret <vscale x 32 x i32> %res
}
@@ -439,6 +562,25 @@ define <vscale x 16 x i64> @vector_interleave_nxv16i64_nxv8i64(<vscale x 8 x i64
; ZIP-NEXT: vmv8r.v v8, v24
; ZIP-NEXT: vmv8r.v v16, v0
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv16i64_nxv8i64:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: vsetvli a1, zero, e16, m2, ta, mu
+; ZVZIP-NEXT: vid.v v6
+; ZVZIP-NEXT: vmv8r.v v24, v8
+; ZVZIP-NEXT: srli a0, a0, 1
+; ZVZIP-NEXT: vmv4r.v v28, v16
+; ZVZIP-NEXT: vmv4r.v v16, v12
+; ZVZIP-NEXT: vand.vi v8, v6, 1
+; ZVZIP-NEXT: vmsne.vi v0, v8, 0
+; ZVZIP-NEXT: vsrl.vi v6, v6, 1
+; ZVZIP-NEXT: vadd.vx v6, v6, a0, v0.t
+; ZVZIP-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; ZVZIP-NEXT: vrgatherei16.vv v8, v24, v6
+; ZVZIP-NEXT: vrgatherei16.vv v24, v16, v6
+; ZVZIP-NEXT: vmv.v.v v16, v24
+; ZVZIP-NEXT: ret
%res = call <vscale x 16 x i64> @llvm.vector.interleave2.nxv16i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b)
ret <vscale x 16 x i64> %res
}
@@ -1566,6 +1708,72 @@ define <vscale x 80 x i8> @vector_interleave_nxv80i8_nxv16i8(<vscale x 16 x i8>
; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZIP-NEXT: addi sp, sp, 80
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv80i8_nxv16i8:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: addi sp, sp, -80
+; ZVZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
+; ZVZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
+; ZVZIP-NEXT: addi s0, sp, 80
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: li a1, 28
+; ZVZIP-NEXT: mul a0, a0, a1
+; ZVZIP-NEXT: sub sp, sp, a0
+; ZVZIP-NEXT: andi sp, sp, -64
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; ZVZIP-NEXT: vmv2r.v v20, v16
+; ZVZIP-NEXT: addi a0, sp, 64
+; ZVZIP-NEXT: vmv2r.v v18, v12
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a2, a1, 2
+; ZVZIP-NEXT: add a1, a2, a1
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: csrr a2, vlenb
+; ZVZIP-NEXT: vmv2r.v v16, v8
+; ZVZIP-NEXT: vmv2r.v v22, v16
+; ZVZIP-NEXT: vmv2r.v v24, v18
+; ZVZIP-NEXT: vmv1r.v v26, v20
+; ZVZIP-NEXT: add a3, a0, a2
+; ZVZIP-NEXT: vmv1r.v v23, v10
+; ZVZIP-NEXT: add a4, a1, a2
+; ZVZIP-NEXT: add a5, a4, a2
+; ZVZIP-NEXT: vmv1r.v v25, v14
+; ZVZIP-NEXT: add a6, a5, a2
+; ZVZIP-NEXT: vmv1r.v v18, v11
+; ZVZIP-NEXT: vsseg5e8.v v22, (a0)
+; ZVZIP-NEXT: vmv1r.v v20, v15
+; ZVZIP-NEXT: vsseg5e8.v v17, (a1)
+; ZVZIP-NEXT: vl1r.v v16, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1r.v v17, (a6)
+; ZVZIP-NEXT: add a6, a3, a2
+; ZVZIP-NEXT: vl1r.v v10, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1r.v v11, (a6)
+; ZVZIP-NEXT: vl1r.v v8, (a0)
+; ZVZIP-NEXT: vl1r.v v9, (a3)
+; ZVZIP-NEXT: vl1r.v v14, (a4)
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: li a3, 10
+; ZVZIP-NEXT: mul a0, a0, a3
+; ZVZIP-NEXT: add a0, sp, a0
+; ZVZIP-NEXT: addi a0, a0, 64
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1r.v v15, (a5)
+; ZVZIP-NEXT: vl1r.v v12, (a6)
+; ZVZIP-NEXT: vl1r.v v13, (a1)
+; ZVZIP-NEXT: slli a2, a2, 3
+; ZVZIP-NEXT: add a2, a0, a2
+; ZVZIP-NEXT: vs2r.v v16, (a2)
+; ZVZIP-NEXT: vs8r.v v8, (a0)
+; ZVZIP-NEXT: vl8r.v v16, (a2)
+; ZVZIP-NEXT: vl8r.v v8, (a0)
+; ZVZIP-NEXT: addi sp, s0, -80
+; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
+; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
+; ZVZIP-NEXT: addi sp, sp, 80
+; ZVZIP-NEXT: ret
%res = call <vscale x 80 x i8> @llvm.vector.interleave5.nxv80i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, <vscale x 16 x i8> %d, <vscale x 16 x i8> %e)
ret <vscale x 80 x i8> %res
}
@@ -1961,6 +2169,72 @@ define <vscale x 20 x i32> @vector_interleave_nxv20i32_nxv4i32(<vscale x 4 x i32
; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZIP-NEXT: addi sp, sp, 80
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv20i32_nxv4i32:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: addi sp, sp, -80
+; ZVZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
+; ZVZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
+; ZVZIP-NEXT: addi s0, sp, 80
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: li a1, 28
+; ZVZIP-NEXT: mul a0, a0, a1
+; ZVZIP-NEXT: sub sp, sp, a0
+; ZVZIP-NEXT: andi sp, sp, -64
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; ZVZIP-NEXT: vmv2r.v v20, v16
+; ZVZIP-NEXT: addi a0, sp, 64
+; ZVZIP-NEXT: vmv2r.v v18, v12
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a2, a1, 2
+; ZVZIP-NEXT: add a1, a2, a1
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: csrr a2, vlenb
+; ZVZIP-NEXT: vmv2r.v v16, v8
+; ZVZIP-NEXT: vmv2r.v v22, v16
+; ZVZIP-NEXT: vmv2r.v v24, v18
+; ZVZIP-NEXT: vmv1r.v v26, v20
+; ZVZIP-NEXT: add a3, a0, a2
+; ZVZIP-NEXT: vmv1r.v v23, v10
+; ZVZIP-NEXT: add a4, a1, a2
+; ZVZIP-NEXT: add a5, a4, a2
+; ZVZIP-NEXT: vmv1r.v v25, v14
+; ZVZIP-NEXT: add a6, a5, a2
+; ZVZIP-NEXT: vmv1r.v v18, v11
+; ZVZIP-NEXT: vsseg5e32.v v22, (a0)
+; ZVZIP-NEXT: vmv1r.v v20, v15
+; ZVZIP-NEXT: vsseg5e32.v v17, (a1)
+; ZVZIP-NEXT: vl1re32.v v16, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re32.v v17, (a6)
+; ZVZIP-NEXT: add a6, a3, a2
+; ZVZIP-NEXT: vl1re32.v v10, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re32.v v11, (a6)
+; ZVZIP-NEXT: vl1re32.v v8, (a0)
+; ZVZIP-NEXT: vl1re32.v v9, (a3)
+; ZVZIP-NEXT: vl1re32.v v14, (a4)
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: li a3, 10
+; ZVZIP-NEXT: mul a0, a0, a3
+; ZVZIP-NEXT: add a0, sp, a0
+; ZVZIP-NEXT: addi a0, a0, 64
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re32.v v15, (a5)
+; ZVZIP-NEXT: vl1re32.v v12, (a6)
+; ZVZIP-NEXT: vl1re32.v v13, (a1)
+; ZVZIP-NEXT: slli a2, a2, 3
+; ZVZIP-NEXT: add a2, a0, a2
+; ZVZIP-NEXT: vs2r.v v16, (a2)
+; ZVZIP-NEXT: vs8r.v v8, (a0)
+; ZVZIP-NEXT: vl8re32.v v16, (a2)
+; ZVZIP-NEXT: vl8re32.v v8, (a0)
+; ZVZIP-NEXT: addi sp, s0, -80
+; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
+; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
+; ZVZIP-NEXT: addi sp, sp, 80
+; ZVZIP-NEXT: ret
%res = call <vscale x 20 x i32> @llvm.vector.interleave5.nxv20i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, <vscale x 4 x i32> %d, <vscale x 4 x i32> %e)
ret <vscale x 20 x i32> %res
}
@@ -2297,6 +2571,72 @@ define <vscale x 10 x i64> @vector_interleave_nxv10i64_nxv2i64(<vscale x 2 x i64
; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZIP-NEXT: addi sp, sp, 80
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv10i64_nxv2i64:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: addi sp, sp, -80
+; ZVZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
+; ZVZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
+; ZVZIP-NEXT: addi s0, sp, 80
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: li a1, 28
+; ZVZIP-NEXT: mul a0, a0, a1
+; ZVZIP-NEXT: sub sp, sp, a0
+; ZVZIP-NEXT: andi sp, sp, -64
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; ZVZIP-NEXT: vmv2r.v v20, v16
+; ZVZIP-NEXT: addi a0, sp, 64
+; ZVZIP-NEXT: vmv2r.v v18, v12
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a2, a1, 2
+; ZVZIP-NEXT: add a1, a2, a1
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: csrr a2, vlenb
+; ZVZIP-NEXT: vmv2r.v v16, v8
+; ZVZIP-NEXT: vmv2r.v v22, v16
+; ZVZIP-NEXT: vmv2r.v v24, v18
+; ZVZIP-NEXT: vmv1r.v v26, v20
+; ZVZIP-NEXT: add a3, a0, a2
+; ZVZIP-NEXT: vmv1r.v v23, v10
+; ZVZIP-NEXT: add a4, a1, a2
+; ZVZIP-NEXT: add a5, a4, a2
+; ZVZIP-NEXT: vmv1r.v v25, v14
+; ZVZIP-NEXT: add a6, a5, a2
+; ZVZIP-NEXT: vmv1r.v v18, v11
+; ZVZIP-NEXT: vsseg5e64.v v22, (a0)
+; ZVZIP-NEXT: vmv1r.v v20, v15
+; ZVZIP-NEXT: vsseg5e64.v v17, (a1)
+; ZVZIP-NEXT: vl1re64.v v16, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re64.v v17, (a6)
+; ZVZIP-NEXT: add a6, a3, a2
+; ZVZIP-NEXT: vl1re64.v v10, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re64.v v11, (a6)
+; ZVZIP-NEXT: vl1re64.v v8, (a0)
+; ZVZIP-NEXT: vl1re64.v v9, (a3)
+; ZVZIP-NEXT: vl1re64.v v14, (a4)
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: li a3, 10
+; ZVZIP-NEXT: mul a0, a0, a3
+; ZVZIP-NEXT: add a0, sp, a0
+; ZVZIP-NEXT: addi a0, a0, 64
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re64.v v15, (a5)
+; ZVZIP-NEXT: vl1re64.v v12, (a6)
+; ZVZIP-NEXT: vl1re64.v v13, (a1)
+; ZVZIP-NEXT: slli a2, a2, 3
+; ZVZIP-NEXT: add a2, a0, a2
+; ZVZIP-NEXT: vs2r.v v16, (a2)
+; ZVZIP-NEXT: vs8r.v v8, (a0)
+; ZVZIP-NEXT: vl8re64.v v16, (a2)
+; ZVZIP-NEXT: vl8re64.v v8, (a0)
+; ZVZIP-NEXT: addi sp, s0, -80
+; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
+; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
+; ZVZIP-NEXT: addi sp, sp, 80
+; ZVZIP-NEXT: ret
%res = call <vscale x 10 x i64> @llvm.vector.interleave5.nxv10i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, <vscale x 2 x i64> %d, <vscale x 2 x i64> %e)
ret <vscale x 10 x i64> %res
}
@@ -2841,6 +3181,79 @@ define <vscale x 96 x i8> @vector_interleave_nxv96i8_nxv16i8(<vscale x 16 x i8>
; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZIP-NEXT: addi sp, sp, 80
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv96i8_nxv16i8:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: addi sp, sp, -80
+; ZVZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
+; ZVZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
+; ZVZIP-NEXT: addi s0, sp, 80
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: li a1, 28
+; ZVZIP-NEXT: mul a0, a0, a1
+; ZVZIP-NEXT: sub sp, sp, a0
+; ZVZIP-NEXT: andi sp, sp, -64
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; ZVZIP-NEXT: vmv2r.v v20, v14
+; ZVZIP-NEXT: vmv2r.v v22, v12
+; ZVZIP-NEXT: vmv2r.v v24, v10
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: li a0, 6
+; ZVZIP-NEXT: mul a1, a1, a0
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: vmv1r.v v10, v25
+; ZVZIP-NEXT: vmv1r.v v11, v23
+; ZVZIP-NEXT: vmv1r.v v12, v21
+; ZVZIP-NEXT: addi a0, sp, 64
+; ZVZIP-NEXT: vmv1r.v v13, v17
+; ZVZIP-NEXT: csrr a2, vlenb
+; ZVZIP-NEXT: vmv1r.v v14, v19
+; ZVZIP-NEXT: vsseg6e8.v v9, (a1)
+; ZVZIP-NEXT: vmv1r.v v9, v24
+; ZVZIP-NEXT: add a5, a1, a2
+; ZVZIP-NEXT: vmv1r.v v10, v22
+; ZVZIP-NEXT: add a3, a0, a2
+; ZVZIP-NEXT: vmv1r.v v11, v20
+; ZVZIP-NEXT: add a4, a3, a2
+; ZVZIP-NEXT: vmv1r.v v12, v16
+; ZVZIP-NEXT: add a6, a5, a2
+; ZVZIP-NEXT: vmv1r.v v13, v18
+; ZVZIP-NEXT: vsseg6e8.v v8, (a0)
+; ZVZIP-NEXT: vl1r.v v14, (a1)
+; ZVZIP-NEXT: add a1, a6, a2
+; ZVZIP-NEXT: vl1r.v v15, (a5)
+; ZVZIP-NEXT: add a5, a1, a2
+; ZVZIP-NEXT: vl1r.v v18, (a5)
+; ZVZIP-NEXT: add a5, a5, a2
+; ZVZIP-NEXT: vl1r.v v19, (a5)
+; ZVZIP-NEXT: add a5, a4, a2
+; ZVZIP-NEXT: vl1r.v v16, (a6)
+; ZVZIP-NEXT: add a6, a5, a2
+; ZVZIP-NEXT: vl1r.v v12, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1r.v v13, (a6)
+; ZVZIP-NEXT: csrr a6, vlenb
+; ZVZIP-NEXT: li a7, 12
+; ZVZIP-NEXT: mul a6, a6, a7
+; ZVZIP-NEXT: add a6, sp, a6
+; ZVZIP-NEXT: addi a6, a6, 64
+; ZVZIP-NEXT: vl1r.v v17, (a1)
+; ZVZIP-NEXT: vl1r.v v10, (a4)
+; ZVZIP-NEXT: vl1r.v v11, (a5)
+; ZVZIP-NEXT: vl1r.v v8, (a0)
+; ZVZIP-NEXT: vl1r.v v9, (a3)
+; ZVZIP-NEXT: slli a2, a2, 3
+; ZVZIP-NEXT: add a2, a6, a2
+; ZVZIP-NEXT: vs4r.v v16, (a2)
+; ZVZIP-NEXT: vs8r.v v8, (a6)
+; ZVZIP-NEXT: vl8r.v v16, (a2)
+; ZVZIP-NEXT: vl8r.v v8, (a6)
+; ZVZIP-NEXT: addi sp, s0, -80
+; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
+; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
+; ZVZIP-NEXT: addi sp, sp, 80
+; ZVZIP-NEXT: ret
%res = call <vscale x 96 x i8> @llvm.vector.interleave6.nxv96i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, <vscale x 16 x i8> %d, <vscale x 16 x i8> %e, <vscale x 16 x i8> %f)
ret <vscale x 96 x i8> %res
}
@@ -3273,6 +3686,79 @@ define <vscale x 24 x i32> @vector_interleave_nxv24i32_nxv4i32(<vscale x 4 x i32
; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZIP-NEXT: addi sp, sp, 80
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv24i32_nxv4i32:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: addi sp, sp, -80
+; ZVZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
+; ZVZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
+; ZVZIP-NEXT: addi s0, sp, 80
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: li a1, 28
+; ZVZIP-NEXT: mul a0, a0, a1
+; ZVZIP-NEXT: sub sp, sp, a0
+; ZVZIP-NEXT: andi sp, sp, -64
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; ZVZIP-NEXT: vmv2r.v v20, v14
+; ZVZIP-NEXT: vmv2r.v v22, v12
+; ZVZIP-NEXT: vmv2r.v v24, v10
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: li a0, 6
+; ZVZIP-NEXT: mul a1, a1, a0
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: vmv1r.v v10, v25
+; ZVZIP-NEXT: vmv1r.v v11, v23
+; ZVZIP-NEXT: vmv1r.v v12, v21
+; ZVZIP-NEXT: addi a0, sp, 64
+; ZVZIP-NEXT: vmv1r.v v13, v17
+; ZVZIP-NEXT: csrr a2, vlenb
+; ZVZIP-NEXT: vmv1r.v v14, v19
+; ZVZIP-NEXT: vsseg6e32.v v9, (a1)
+; ZVZIP-NEXT: vmv1r.v v9, v24
+; ZVZIP-NEXT: add a5, a1, a2
+; ZVZIP-NEXT: vmv1r.v v10, v22
+; ZVZIP-NEXT: add a3, a0, a2
+; ZVZIP-NEXT: vmv1r.v v11, v20
+; ZVZIP-NEXT: add a4, a3, a2
+; ZVZIP-NEXT: vmv1r.v v12, v16
+; ZVZIP-NEXT: add a6, a5, a2
+; ZVZIP-NEXT: vmv1r.v v13, v18
+; ZVZIP-NEXT: vsseg6e32.v v8, (a0)
+; ZVZIP-NEXT: vl1re32.v v14, (a1)
+; ZVZIP-NEXT: add a1, a6, a2
+; ZVZIP-NEXT: vl1re32.v v15, (a5)
+; ZVZIP-NEXT: add a5, a1, a2
+; ZVZIP-NEXT: vl1re32.v v18, (a5)
+; ZVZIP-NEXT: add a5, a5, a2
+; ZVZIP-NEXT: vl1re32.v v19, (a5)
+; ZVZIP-NEXT: add a5, a4, a2
+; ZVZIP-NEXT: vl1re32.v v16, (a6)
+; ZVZIP-NEXT: add a6, a5, a2
+; ZVZIP-NEXT: vl1re32.v v12, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re32.v v13, (a6)
+; ZVZIP-NEXT: csrr a6, vlenb
+; ZVZIP-NEXT: li a7, 12
+; ZVZIP-NEXT: mul a6, a6, a7
+; ZVZIP-NEXT: add a6, sp, a6
+; ZVZIP-NEXT: addi a6, a6, 64
+; ZVZIP-NEXT: vl1re32.v v17, (a1)
+; ZVZIP-NEXT: vl1re32.v v10, (a4)
+; ZVZIP-NEXT: vl1re32.v v11, (a5)
+; ZVZIP-NEXT: vl1re32.v v8, (a0)
+; ZVZIP-NEXT: vl1re32.v v9, (a3)
+; ZVZIP-NEXT: slli a2, a2, 3
+; ZVZIP-NEXT: add a2, a6, a2
+; ZVZIP-NEXT: vs4r.v v16, (a2)
+; ZVZIP-NEXT: vs8r.v v8, (a6)
+; ZVZIP-NEXT: vl8re32.v v16, (a2)
+; ZVZIP-NEXT: vl8re32.v v8, (a6)
+; ZVZIP-NEXT: addi sp, s0, -80
+; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
+; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
+; ZVZIP-NEXT: addi sp, sp, 80
+; ZVZIP-NEXT: ret
%res = call <vscale x 24 x i32> @llvm.vector.interleave6.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, <vscale x 4 x i32> %d, <vscale x 4 x i32> %e, <vscale x 4 x i32> %f)
ret <vscale x 24 x i32> %res
}
@@ -3643,6 +4129,79 @@ define <vscale x 12 x i64> @vector_interleave_nxv12i64_nxv2i64(<vscale x 2 x i64
; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZIP-NEXT: addi sp, sp, 80
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv12i64_nxv2i64:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: addi sp, sp, -80
+; ZVZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
+; ZVZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
+; ZVZIP-NEXT: addi s0, sp, 80
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: li a1, 28
+; ZVZIP-NEXT: mul a0, a0, a1
+; ZVZIP-NEXT: sub sp, sp, a0
+; ZVZIP-NEXT: andi sp, sp, -64
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; ZVZIP-NEXT: vmv2r.v v20, v14
+; ZVZIP-NEXT: vmv2r.v v22, v12
+; ZVZIP-NEXT: vmv2r.v v24, v10
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: li a0, 6
+; ZVZIP-NEXT: mul a1, a1, a0
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: vmv1r.v v10, v25
+; ZVZIP-NEXT: vmv1r.v v11, v23
+; ZVZIP-NEXT: vmv1r.v v12, v21
+; ZVZIP-NEXT: addi a0, sp, 64
+; ZVZIP-NEXT: vmv1r.v v13, v17
+; ZVZIP-NEXT: csrr a2, vlenb
+; ZVZIP-NEXT: vmv1r.v v14, v19
+; ZVZIP-NEXT: vsseg6e64.v v9, (a1)
+; ZVZIP-NEXT: vmv1r.v v9, v24
+; ZVZIP-NEXT: add a5, a1, a2
+; ZVZIP-NEXT: vmv1r.v v10, v22
+; ZVZIP-NEXT: add a3, a0, a2
+; ZVZIP-NEXT: vmv1r.v v11, v20
+; ZVZIP-NEXT: add a4, a3, a2
+; ZVZIP-NEXT: vmv1r.v v12, v16
+; ZVZIP-NEXT: add a6, a5, a2
+; ZVZIP-NEXT: vmv1r.v v13, v18
+; ZVZIP-NEXT: vsseg6e64.v v8, (a0)
+; ZVZIP-NEXT: vl1re64.v v14, (a1)
+; ZVZIP-NEXT: add a1, a6, a2
+; ZVZIP-NEXT: vl1re64.v v15, (a5)
+; ZVZIP-NEXT: add a5, a1, a2
+; ZVZIP-NEXT: vl1re64.v v18, (a5)
+; ZVZIP-NEXT: add a5, a5, a2
+; ZVZIP-NEXT: vl1re64.v v19, (a5)
+; ZVZIP-NEXT: add a5, a4, a2
+; ZVZIP-NEXT: vl1re64.v v16, (a6)
+; ZVZIP-NEXT: add a6, a5, a2
+; ZVZIP-NEXT: vl1re64.v v12, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re64.v v13, (a6)
+; ZVZIP-NEXT: csrr a6, vlenb
+; ZVZIP-NEXT: li a7, 12
+; ZVZIP-NEXT: mul a6, a6, a7
+; ZVZIP-NEXT: add a6, sp, a6
+; ZVZIP-NEXT: addi a6, a6, 64
+; ZVZIP-NEXT: vl1re64.v v17, (a1)
+; ZVZIP-NEXT: vl1re64.v v10, (a4)
+; ZVZIP-NEXT: vl1re64.v v11, (a5)
+; ZVZIP-NEXT: vl1re64.v v8, (a0)
+; ZVZIP-NEXT: vl1re64.v v9, (a3)
+; ZVZIP-NEXT: slli a2, a2, 3
+; ZVZIP-NEXT: add a2, a6, a2
+; ZVZIP-NEXT: vs4r.v v16, (a2)
+; ZVZIP-NEXT: vs8r.v v8, (a6)
+; ZVZIP-NEXT: vl8re64.v v16, (a2)
+; ZVZIP-NEXT: vl8re64.v v8, (a6)
+; ZVZIP-NEXT: addi sp, s0, -80
+; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
+; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
+; ZVZIP-NEXT: addi sp, sp, 80
+; ZVZIP-NEXT: ret
%res = call <vscale x 12 x i64> @llvm.vector.interleave6.nxv12i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, <vscale x 2 x i64> %d, <vscale x 2 x i64> %e, <vscale x 2 x i64> %f)
ret <vscale x 12 x i64> %res
}
@@ -4242,6 +4801,87 @@ define <vscale x 112 x i8> @vector_interleave_nxv112i8_nxv16i8(<vscale x 16 x i8
; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZIP-NEXT: addi sp, sp, 80
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv112i8_nxv16i8:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: addi sp, sp, -80
+; ZVZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
+; ZVZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
+; ZVZIP-NEXT: addi s0, sp, 80
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 5
+; ZVZIP-NEXT: sub sp, sp, a0
+; ZVZIP-NEXT: andi sp, sp, -64
+; ZVZIP-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; ZVZIP-NEXT: vmv2r.v v26, v20
+; ZVZIP-NEXT: addi a0, sp, 64
+; ZVZIP-NEXT: vmv2r.v v24, v16
+; ZVZIP-NEXT: vmv2r.v v22, v12
+; ZVZIP-NEXT: vmv2r.v v20, v8
+; ZVZIP-NEXT: vmv1r.v v1, v20
+; ZVZIP-NEXT: vmv1r.v v3, v22
+; ZVZIP-NEXT: vmv1r.v v5, v24
+; ZVZIP-NEXT: vmv1r.v v7, v26
+; ZVZIP-NEXT: vmv1r.v v2, v10
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a2, a1, 3
+; ZVZIP-NEXT: sub a1, a2, a1
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: csrr a2, vlenb
+; ZVZIP-NEXT: vmv1r.v v4, v14
+; ZVZIP-NEXT: add a3, a0, a2
+; ZVZIP-NEXT: add a4, a1, a2
+; ZVZIP-NEXT: vmv1r.v v6, v18
+; ZVZIP-NEXT: add a5, a4, a2
+; ZVZIP-NEXT: vmv1r.v v22, v11
+; ZVZIP-NEXT: add a6, a5, a2
+; ZVZIP-NEXT: vmv1r.v v24, v15
+; ZVZIP-NEXT: vsseg7e8.v v1, (a0)
+; ZVZIP-NEXT: vmv1r.v v26, v19
+; ZVZIP-NEXT: vsseg7e8.v v21, (a1)
+; ZVZIP-NEXT: vl1r.v v18, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1r.v v19, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1r.v v20, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1r.v v21, (a6)
+; ZVZIP-NEXT: add a6, a3, a2
+; ZVZIP-NEXT: vl1r.v v10, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1r.v v11, (a6)
+; ZVZIP-NEXT: vl1r.v v8, (a0)
+; ZVZIP-NEXT: vl1r.v v16, (a4)
+; ZVZIP-NEXT: vl1r.v v9, (a3)
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: li a3, 14
+; ZVZIP-NEXT: mul a0, a0, a3
+; ZVZIP-NEXT: add a0, sp, a0
+; ZVZIP-NEXT: addi a0, a0, 64
+; ZVZIP-NEXT: vl1r.v v17, (a5)
+; ZVZIP-NEXT: slli a3, a2, 2
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1r.v v12, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1r.v v13, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: slli a2, a2, 3
+; ZVZIP-NEXT: add a3, a2, a3
+; ZVZIP-NEXT: add a2, a0, a2
+; ZVZIP-NEXT: vl1r.v v14, (a6)
+; ZVZIP-NEXT: vl1r.v v15, (a1)
+; ZVZIP-NEXT: add a3, a0, a3
+; ZVZIP-NEXT: vs2r.v v20, (a3)
+; ZVZIP-NEXT: vs4r.v v16, (a2)
+; ZVZIP-NEXT: vs8r.v v8, (a0)
+; ZVZIP-NEXT: vl8r.v v16, (a2)
+; ZVZIP-NEXT: vl8r.v v8, (a0)
+; ZVZIP-NEXT: addi sp, s0, -80
+; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
+; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
+; ZVZIP-NEXT: addi sp, sp, 80
+; ZVZIP-NEXT: ret
%res = call <vscale x 112 x i8> @llvm.vector.interleave7.nxv112i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, <vscale x 16 x i8> %d, <vscale x 16 x i8> %e, <vscale x 16 x i8> %f, <vscale x 16 x i8> %g)
ret <vscale x 112 x i8> %res
}
@@ -4653,6 +5293,87 @@ define <vscale x 56 x i16> @vector_interleave_nxv56i16_nxv8i16(<vscale x 8 x i16
; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZIP-NEXT: addi sp, sp, 80
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv56i16_nxv8i16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: addi sp, sp, -80
+; ZVZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
+; ZVZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
+; ZVZIP-NEXT: addi s0, sp, 80
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 5
+; ZVZIP-NEXT: sub sp, sp, a0
+; ZVZIP-NEXT: andi sp, sp, -64
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vmv2r.v v26, v20
+; ZVZIP-NEXT: addi a0, sp, 64
+; ZVZIP-NEXT: vmv2r.v v24, v16
+; ZVZIP-NEXT: vmv2r.v v22, v12
+; ZVZIP-NEXT: vmv2r.v v20, v8
+; ZVZIP-NEXT: vmv1r.v v1, v20
+; ZVZIP-NEXT: vmv1r.v v3, v22
+; ZVZIP-NEXT: vmv1r.v v5, v24
+; ZVZIP-NEXT: vmv1r.v v7, v26
+; ZVZIP-NEXT: vmv1r.v v2, v10
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a2, a1, 3
+; ZVZIP-NEXT: sub a1, a2, a1
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: csrr a2, vlenb
+; ZVZIP-NEXT: vmv1r.v v4, v14
+; ZVZIP-NEXT: add a3, a0, a2
+; ZVZIP-NEXT: add a4, a1, a2
+; ZVZIP-NEXT: vmv1r.v v6, v18
+; ZVZIP-NEXT: add a5, a4, a2
+; ZVZIP-NEXT: vmv1r.v v22, v11
+; ZVZIP-NEXT: add a6, a5, a2
+; ZVZIP-NEXT: vmv1r.v v24, v15
+; ZVZIP-NEXT: vsseg7e16.v v1, (a0)
+; ZVZIP-NEXT: vmv1r.v v26, v19
+; ZVZIP-NEXT: vsseg7e16.v v21, (a1)
+; ZVZIP-NEXT: vl1re16.v v18, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re16.v v19, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re16.v v20, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re16.v v21, (a6)
+; ZVZIP-NEXT: add a6, a3, a2
+; ZVZIP-NEXT: vl1re16.v v10, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re16.v v11, (a6)
+; ZVZIP-NEXT: vl1re16.v v8, (a0)
+; ZVZIP-NEXT: vl1re16.v v16, (a4)
+; ZVZIP-NEXT: vl1re16.v v9, (a3)
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: li a3, 14
+; ZVZIP-NEXT: mul a0, a0, a3
+; ZVZIP-NEXT: add a0, sp, a0
+; ZVZIP-NEXT: addi a0, a0, 64
+; ZVZIP-NEXT: vl1re16.v v17, (a5)
+; ZVZIP-NEXT: slli a3, a2, 2
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re16.v v12, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re16.v v13, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: slli a2, a2, 3
+; ZVZIP-NEXT: add a3, a2, a3
+; ZVZIP-NEXT: add a2, a0, a2
+; ZVZIP-NEXT: vl1re16.v v14, (a6)
+; ZVZIP-NEXT: vl1re16.v v15, (a1)
+; ZVZIP-NEXT: add a3, a0, a3
+; ZVZIP-NEXT: vs2r.v v20, (a3)
+; ZVZIP-NEXT: vs4r.v v16, (a2)
+; ZVZIP-NEXT: vs8r.v v8, (a0)
+; ZVZIP-NEXT: vl8re16.v v16, (a2)
+; ZVZIP-NEXT: vl8re16.v v8, (a0)
+; ZVZIP-NEXT: addi sp, s0, -80
+; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
+; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
+; ZVZIP-NEXT: addi sp, sp, 80
+; ZVZIP-NEXT: ret
%res = call <vscale x 56 x i16> @llvm.vector.interleave7.nxv56i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c, <vscale x 8 x i16> %d, <vscale x 8 x i16> %e, <vscale x 8 x i16> %f, <vscale x 8 x i16> %g)
ret <vscale x 56 x i16> %res
}
@@ -5064,6 +5785,87 @@ define <vscale x 28 x i32> @vector_interleave_nxv28i32_nxv4i32(<vscale x 4 x i32
; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZIP-NEXT: addi sp, sp, 80
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv28i32_nxv4i32:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: addi sp, sp, -80
+; ZVZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
+; ZVZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
+; ZVZIP-NEXT: addi s0, sp, 80
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 5
+; ZVZIP-NEXT: sub sp, sp, a0
+; ZVZIP-NEXT: andi sp, sp, -64
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; ZVZIP-NEXT: vmv2r.v v26, v20
+; ZVZIP-NEXT: addi a0, sp, 64
+; ZVZIP-NEXT: vmv2r.v v24, v16
+; ZVZIP-NEXT: vmv2r.v v22, v12
+; ZVZIP-NEXT: vmv2r.v v20, v8
+; ZVZIP-NEXT: vmv1r.v v1, v20
+; ZVZIP-NEXT: vmv1r.v v3, v22
+; ZVZIP-NEXT: vmv1r.v v5, v24
+; ZVZIP-NEXT: vmv1r.v v7, v26
+; ZVZIP-NEXT: vmv1r.v v2, v10
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a2, a1, 3
+; ZVZIP-NEXT: sub a1, a2, a1
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: csrr a2, vlenb
+; ZVZIP-NEXT: vmv1r.v v4, v14
+; ZVZIP-NEXT: add a3, a0, a2
+; ZVZIP-NEXT: add a4, a1, a2
+; ZVZIP-NEXT: vmv1r.v v6, v18
+; ZVZIP-NEXT: add a5, a4, a2
+; ZVZIP-NEXT: vmv1r.v v22, v11
+; ZVZIP-NEXT: add a6, a5, a2
+; ZVZIP-NEXT: vmv1r.v v24, v15
+; ZVZIP-NEXT: vsseg7e32.v v1, (a0)
+; ZVZIP-NEXT: vmv1r.v v26, v19
+; ZVZIP-NEXT: vsseg7e32.v v21, (a1)
+; ZVZIP-NEXT: vl1re32.v v18, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re32.v v19, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re32.v v20, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re32.v v21, (a6)
+; ZVZIP-NEXT: add a6, a3, a2
+; ZVZIP-NEXT: vl1re32.v v10, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re32.v v11, (a6)
+; ZVZIP-NEXT: vl1re32.v v8, (a0)
+; ZVZIP-NEXT: vl1re32.v v16, (a4)
+; ZVZIP-NEXT: vl1re32.v v9, (a3)
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: li a3, 14
+; ZVZIP-NEXT: mul a0, a0, a3
+; ZVZIP-NEXT: add a0, sp, a0
+; ZVZIP-NEXT: addi a0, a0, 64
+; ZVZIP-NEXT: vl1re32.v v17, (a5)
+; ZVZIP-NEXT: slli a3, a2, 2
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re32.v v12, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re32.v v13, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: slli a2, a2, 3
+; ZVZIP-NEXT: add a3, a2, a3
+; ZVZIP-NEXT: add a2, a0, a2
+; ZVZIP-NEXT: vl1re32.v v14, (a6)
+; ZVZIP-NEXT: vl1re32.v v15, (a1)
+; ZVZIP-NEXT: add a3, a0, a3
+; ZVZIP-NEXT: vs2r.v v20, (a3)
+; ZVZIP-NEXT: vs4r.v v16, (a2)
+; ZVZIP-NEXT: vs8r.v v8, (a0)
+; ZVZIP-NEXT: vl8re32.v v16, (a2)
+; ZVZIP-NEXT: vl8re32.v v8, (a0)
+; ZVZIP-NEXT: addi sp, s0, -80
+; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
+; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
+; ZVZIP-NEXT: addi sp, sp, 80
+; ZVZIP-NEXT: ret
%res = call <vscale x 28 x i32> @llvm.vector.interleave7.nxv28i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, <vscale x 4 x i32> %d, <vscale x 4 x i32> %e, <vscale x 4 x i32> %f, <vscale x 4 x i32> %g)
ret <vscale x 28 x i32> %res
}
@@ -5474,6 +6276,87 @@ define <vscale x 14 x i64> @vector_interleave_nxv14i64_nxv2i64(<vscale x 2 x i64
; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZIP-NEXT: addi sp, sp, 80
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv14i64_nxv2i64:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: addi sp, sp, -80
+; ZVZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
+; ZVZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
+; ZVZIP-NEXT: addi s0, sp, 80
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 5
+; ZVZIP-NEXT: sub sp, sp, a0
+; ZVZIP-NEXT: andi sp, sp, -64
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; ZVZIP-NEXT: vmv2r.v v26, v20
+; ZVZIP-NEXT: addi a0, sp, 64
+; ZVZIP-NEXT: vmv2r.v v24, v16
+; ZVZIP-NEXT: vmv2r.v v22, v12
+; ZVZIP-NEXT: vmv2r.v v20, v8
+; ZVZIP-NEXT: vmv1r.v v1, v20
+; ZVZIP-NEXT: vmv1r.v v3, v22
+; ZVZIP-NEXT: vmv1r.v v5, v24
+; ZVZIP-NEXT: vmv1r.v v7, v26
+; ZVZIP-NEXT: vmv1r.v v2, v10
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a2, a1, 3
+; ZVZIP-NEXT: sub a1, a2, a1
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: csrr a2, vlenb
+; ZVZIP-NEXT: vmv1r.v v4, v14
+; ZVZIP-NEXT: add a3, a0, a2
+; ZVZIP-NEXT: add a4, a1, a2
+; ZVZIP-NEXT: vmv1r.v v6, v18
+; ZVZIP-NEXT: add a5, a4, a2
+; ZVZIP-NEXT: vmv1r.v v22, v11
+; ZVZIP-NEXT: add a6, a5, a2
+; ZVZIP-NEXT: vmv1r.v v24, v15
+; ZVZIP-NEXT: vsseg7e64.v v1, (a0)
+; ZVZIP-NEXT: vmv1r.v v26, v19
+; ZVZIP-NEXT: vsseg7e64.v v21, (a1)
+; ZVZIP-NEXT: vl1re64.v v18, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re64.v v19, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re64.v v20, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re64.v v21, (a6)
+; ZVZIP-NEXT: add a6, a3, a2
+; ZVZIP-NEXT: vl1re64.v v10, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re64.v v11, (a6)
+; ZVZIP-NEXT: vl1re64.v v8, (a0)
+; ZVZIP-NEXT: vl1re64.v v16, (a4)
+; ZVZIP-NEXT: vl1re64.v v9, (a3)
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: li a3, 14
+; ZVZIP-NEXT: mul a0, a0, a3
+; ZVZIP-NEXT: add a0, sp, a0
+; ZVZIP-NEXT: addi a0, a0, 64
+; ZVZIP-NEXT: vl1re64.v v17, (a5)
+; ZVZIP-NEXT: slli a3, a2, 2
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re64.v v12, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re64.v v13, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: slli a2, a2, 3
+; ZVZIP-NEXT: add a3, a2, a3
+; ZVZIP-NEXT: add a2, a0, a2
+; ZVZIP-NEXT: vl1re64.v v14, (a6)
+; ZVZIP-NEXT: vl1re64.v v15, (a1)
+; ZVZIP-NEXT: add a3, a0, a3
+; ZVZIP-NEXT: vs2r.v v20, (a3)
+; ZVZIP-NEXT: vs4r.v v16, (a2)
+; ZVZIP-NEXT: vs8r.v v8, (a0)
+; ZVZIP-NEXT: vl8re64.v v16, (a2)
+; ZVZIP-NEXT: vl8re64.v v8, (a0)
+; ZVZIP-NEXT: addi sp, s0, -80
+; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
+; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
+; ZVZIP-NEXT: addi sp, sp, 80
+; ZVZIP-NEXT: ret
%res = call <vscale x 14 x i64> @llvm.vector.interleave7.nxv14i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, <vscale x 2 x i64> %d, <vscale x 2 x i64> %e, <vscale x 2 x i64> %f, <vscale x 2 x i64> %g)
ret <vscale x 14 x i64> %res
}
@@ -6280,6 +7163,20 @@ define <vscale x 4 x bfloat> @vector_interleave_nxv4bf16_nxv2bf16(<vscale x 2 x
; ZIP-NEXT: vslideup.vx v10, v11, a0
; ZIP-NEXT: vmv.v.v v8, v10
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv4bf16_nxv2bf16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; ZVZIP-NEXT: vwaddu.vv v10, v8, v9
+; ZVZIP-NEXT: li a0, -1
+; ZVZIP-NEXT: vwmaccu.vx v10, a0, v9
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: srli a0, a0, 2
+; ZVZIP-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v8, v10, a0
+; ZVZIP-NEXT: vslideup.vx v10, v8, a0
+; ZVZIP-NEXT: vmv.v.v v8, v10
+; ZVZIP-NEXT: ret
%res = call <vscale x 4 x bfloat> @llvm.vector.interleave2.nxv4bf16(<vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b)
ret <vscale x 4 x bfloat> %res
}
@@ -6312,6 +7209,16 @@ define <vscale x 8 x bfloat> @vector_interleave_nxv8bf16_nxv4bf16(<vscale x 4 x
; ZIP-NEXT: ri.vzip2b.vv v9, v8, v10
; ZIP-NEXT: ri.vzip2a.vv v8, v11, v10
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv8bf16_nxv4bf16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vmv1r.v v10, v9
+; ZVZIP-NEXT: vmv1r.v v11, v8
+; ZVZIP-NEXT: vwaddu.vv v8, v11, v10
+; ZVZIP-NEXT: li a0, -1
+; ZVZIP-NEXT: vwmaccu.vx v8, a0, v10
+; ZVZIP-NEXT: ret
%res = call <vscale x 8 x bfloat> @llvm.vector.interleave2.nxv8bf16(<vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b)
ret <vscale x 8 x bfloat> %res
}
@@ -6355,6 +7262,20 @@ define <vscale x 4 x half> @vector_interleave_nxv4f16_nxv2f16(<vscale x 2 x half
; ZIP-NEXT: vslideup.vx v10, v11, a0
; ZIP-NEXT: vmv.v.v v8, v10
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv4f16_nxv2f16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; ZVZIP-NEXT: vwaddu.vv v10, v8, v9
+; ZVZIP-NEXT: li a0, -1
+; ZVZIP-NEXT: vwmaccu.vx v10, a0, v9
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: srli a0, a0, 2
+; ZVZIP-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v8, v10, a0
+; ZVZIP-NEXT: vslideup.vx v10, v8, a0
+; ZVZIP-NEXT: vmv.v.v v8, v10
+; ZVZIP-NEXT: ret
%res = call <vscale x 4 x half> @llvm.vector.interleave2.nxv4f16(<vscale x 2 x half> %a, <vscale x 2 x half> %b)
ret <vscale x 4 x half> %res
}
@@ -6387,6 +7308,16 @@ define <vscale x 8 x half> @vector_interleave_nxv8f16_nxv4f16(<vscale x 4 x half
; ZIP-NEXT: ri.vzip2b.vv v9, v8, v10
; ZIP-NEXT: ri.vzip2a.vv v8, v11, v10
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv8f16_nxv4f16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vmv1r.v v10, v9
+; ZVZIP-NEXT: vmv1r.v v11, v8
+; ZVZIP-NEXT: vwaddu.vv v8, v11, v10
+; ZVZIP-NEXT: li a0, -1
+; ZVZIP-NEXT: vwmaccu.vx v8, a0, v10
+; ZVZIP-NEXT: ret
%res = call <vscale x 8 x half> @llvm.vector.interleave2.nxv8f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b)
ret <vscale x 8 x half> %res
}
@@ -6420,6 +7351,16 @@ define <vscale x 4 x float> @vector_interleave_nxv4f32_nxv2f32(<vscale x 2 x flo
; ZIP-NEXT: ri.vzip2b.vv v9, v8, v10
; ZIP-NEXT: ri.vzip2a.vv v8, v11, v10
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv4f32_nxv2f32:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; ZVZIP-NEXT: vmv1r.v v10, v9
+; ZVZIP-NEXT: vmv1r.v v11, v8
+; ZVZIP-NEXT: vwaddu.vv v8, v11, v10
+; ZVZIP-NEXT: li a0, -1
+; ZVZIP-NEXT: vwmaccu.vx v8, a0, v10
+; ZVZIP-NEXT: ret
%res = call <vscale x 4 x float> @llvm.vector.interleave2.nxv4f32(<vscale x 2 x float> %a, <vscale x 2 x float> %b)
ret <vscale x 4 x float> %res
}
@@ -6452,6 +7393,16 @@ define <vscale x 16 x bfloat> @vector_interleave_nxv16bf16_nxv8bf16(<vscale x 8
; ZIP-NEXT: ri.vzip2b.vv v10, v8, v12
; ZIP-NEXT: ri.vzip2a.vv v8, v14, v12
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv16bf16_nxv8bf16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVZIP-NEXT: vmv2r.v v12, v10
+; ZVZIP-NEXT: vmv2r.v v14, v8
+; ZVZIP-NEXT: vwaddu.vv v8, v14, v12
+; ZVZIP-NEXT: li a0, -1
+; ZVZIP-NEXT: vwmaccu.vx v8, a0, v12
+; ZVZIP-NEXT: ret
%res = call <vscale x 16 x bfloat> @llvm.vector.interleave2.nxv16bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b)
ret <vscale x 16 x bfloat> %res
}
@@ -6484,6 +7435,16 @@ define <vscale x 16 x half> @vector_interleave_nxv16f16_nxv8f16(<vscale x 8 x ha
; ZIP-NEXT: ri.vzip2b.vv v10, v8, v12
; ZIP-NEXT: ri.vzip2a.vv v8, v14, v12
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv16f16_nxv8f16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVZIP-NEXT: vmv2r.v v12, v10
+; ZVZIP-NEXT: vmv2r.v v14, v8
+; ZVZIP-NEXT: vwaddu.vv v8, v14, v12
+; ZVZIP-NEXT: li a0, -1
+; ZVZIP-NEXT: vwmaccu.vx v8, a0, v12
+; ZVZIP-NEXT: ret
%res = call <vscale x 16 x half> @llvm.vector.interleave2.nxv16f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b)
ret <vscale x 16 x half> %res
}
@@ -6517,6 +7478,16 @@ define <vscale x 8 x float> @vector_interleave_nxv8f32_nxv4f32(<vscale x 4 x flo
; ZIP-NEXT: ri.vzip2b.vv v10, v8, v12
; ZIP-NEXT: ri.vzip2a.vv v8, v14, v12
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv8f32_nxv4f32:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; ZVZIP-NEXT: vmv2r.v v12, v10
+; ZVZIP-NEXT: vmv2r.v v14, v8
+; ZVZIP-NEXT: vwaddu.vv v8, v14, v12
+; ZVZIP-NEXT: li a0, -1
+; ZVZIP-NEXT: vwmaccu.vx v8, a0, v12
+; ZVZIP-NEXT: ret
%res = call <vscale x 8 x float> @llvm.vector.interleave2.nxv8f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b)
ret <vscale x 8 x float> %res
}
@@ -6560,6 +7531,21 @@ define <vscale x 4 x double> @vector_interleave_nxv4f64_nxv2f64(<vscale x 2 x do
; ZIP-NEXT: ri.vzip2b.vv v10, v8, v12
; ZIP-NEXT: ri.vzip2a.vv v8, v14, v12
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv4f64_nxv2f64:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: vsetvli a1, zero, e16, m1, ta, mu
+; ZVZIP-NEXT: vid.v v12
+; ZVZIP-NEXT: srli a0, a0, 2
+; ZVZIP-NEXT: vand.vi v13, v12, 1
+; ZVZIP-NEXT: vmsne.vi v0, v13, 0
+; ZVZIP-NEXT: vsrl.vi v16, v12, 1
+; ZVZIP-NEXT: vadd.vx v16, v16, a0, v0.t
+; ZVZIP-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; ZVZIP-NEXT: vrgatherei16.vv v12, v8, v16
+; ZVZIP-NEXT: vmv.v.v v8, v12
+; ZVZIP-NEXT: ret
%res = call <vscale x 4 x double> @llvm.vector.interleave2.nxv4f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b)
ret <vscale x 4 x double> %res
}
@@ -6600,6 +7586,18 @@ define <vscale x 64 x bfloat> @vector_interleave_nxv64bf16_nxv32bf16(<vscale x 3
; ZIP-NEXT: vmv8r.v v8, v24
; ZIP-NEXT: vmv8r.v v16, v0
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv64bf16_nxv32bf16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVZIP-NEXT: vmv8r.v v24, v8
+; ZVZIP-NEXT: vwaddu.vv v8, v24, v16
+; ZVZIP-NEXT: li a0, -1
+; ZVZIP-NEXT: vwaddu.vv v0, v28, v20
+; ZVZIP-NEXT: vwmaccu.vx v8, a0, v16
+; ZVZIP-NEXT: vwmaccu.vx v0, a0, v20
+; ZVZIP-NEXT: vmv8r.v v16, v0
+; ZVZIP-NEXT: ret
%res = call <vscale x 64 x bfloat> @llvm.vector.interleave2.nxv64bf16(<vscale x 32 x bfloat> %a, <vscale x 32 x bfloat> %b)
ret <vscale x 64 x bfloat> %res
}
@@ -6638,6 +7636,18 @@ define <vscale x 64 x half> @vector_interleave_nxv64f16_nxv32f16(<vscale x 32 x
; ZIP-NEXT: vmv8r.v v8, v24
; ZIP-NEXT: vmv8r.v v16, v0
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv64f16_nxv32f16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVZIP-NEXT: vmv8r.v v24, v8
+; ZVZIP-NEXT: vwaddu.vv v8, v24, v16
+; ZVZIP-NEXT: li a0, -1
+; ZVZIP-NEXT: vwaddu.vv v0, v28, v20
+; ZVZIP-NEXT: vwmaccu.vx v8, a0, v16
+; ZVZIP-NEXT: vwmaccu.vx v0, a0, v20
+; ZVZIP-NEXT: vmv8r.v v16, v0
+; ZVZIP-NEXT: ret
%res = call <vscale x 64 x half> @llvm.vector.interleave2.nxv64f16(<vscale x 32 x half> %a, <vscale x 32 x half> %b)
ret <vscale x 64 x half> %res
}
@@ -6677,6 +7687,18 @@ define <vscale x 32 x float> @vector_interleave_nxv32f32_nxv16f32(<vscale x 16 x
; ZIP-NEXT: vmv8r.v v8, v24
; ZIP-NEXT: vmv8r.v v16, v0
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv32f32_nxv16f32:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVZIP-NEXT: vmv8r.v v24, v8
+; ZVZIP-NEXT: vwaddu.vv v8, v24, v16
+; ZVZIP-NEXT: li a0, -1
+; ZVZIP-NEXT: vwaddu.vv v0, v28, v20
+; ZVZIP-NEXT: vwmaccu.vx v8, a0, v16
+; ZVZIP-NEXT: vwmaccu.vx v0, a0, v20
+; ZVZIP-NEXT: vmv8r.v v16, v0
+; ZVZIP-NEXT: ret
%res = call <vscale x 32 x float> @llvm.vector.interleave2.nxv32f32(<vscale x 16 x float> %a, <vscale x 16 x float> %b)
ret <vscale x 32 x float> %res
}
@@ -6730,6 +7752,25 @@ define <vscale x 16 x double> @vector_interleave_nxv16f64_nxv8f64(<vscale x 8 x
; ZIP-NEXT: vmv8r.v v8, v24
; ZIP-NEXT: vmv8r.v v16, v0
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv16f64_nxv8f64:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: vsetvli a1, zero, e16, m2, ta, mu
+; ZVZIP-NEXT: vid.v v6
+; ZVZIP-NEXT: vmv8r.v v24, v8
+; ZVZIP-NEXT: srli a0, a0, 1
+; ZVZIP-NEXT: vmv4r.v v28, v16
+; ZVZIP-NEXT: vmv4r.v v16, v12
+; ZVZIP-NEXT: vand.vi v8, v6, 1
+; ZVZIP-NEXT: vmsne.vi v0, v8, 0
+; ZVZIP-NEXT: vsrl.vi v6, v6, 1
+; ZVZIP-NEXT: vadd.vx v6, v6, a0, v0.t
+; ZVZIP-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; ZVZIP-NEXT: vrgatherei16.vv v8, v24, v6
+; ZVZIP-NEXT: vrgatherei16.vv v24, v16, v6
+; ZVZIP-NEXT: vmv.v.v v16, v24
+; ZVZIP-NEXT: ret
%res = call <vscale x 16 x double> @llvm.vector.interleave2.nxv16f64(<vscale x 8 x double> %a, <vscale x 8 x double> %b)
ret <vscale x 16 x double> %res
}
@@ -8372,6 +9413,72 @@ define <vscale x 40 x half> @vector_interleave_nxv40f16_nxv8f16(<vscale x 8 x ha
; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZIP-NEXT: addi sp, sp, 80
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv40f16_nxv8f16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: addi sp, sp, -80
+; ZVZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
+; ZVZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
+; ZVZIP-NEXT: addi s0, sp, 80
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: li a1, 28
+; ZVZIP-NEXT: mul a0, a0, a1
+; ZVZIP-NEXT: sub sp, sp, a0
+; ZVZIP-NEXT: andi sp, sp, -64
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vmv2r.v v20, v16
+; ZVZIP-NEXT: addi a0, sp, 64
+; ZVZIP-NEXT: vmv2r.v v18, v12
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a2, a1, 2
+; ZVZIP-NEXT: add a1, a2, a1
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: csrr a2, vlenb
+; ZVZIP-NEXT: vmv2r.v v16, v8
+; ZVZIP-NEXT: vmv2r.v v22, v16
+; ZVZIP-NEXT: vmv2r.v v24, v18
+; ZVZIP-NEXT: vmv1r.v v26, v20
+; ZVZIP-NEXT: add a3, a0, a2
+; ZVZIP-NEXT: vmv1r.v v23, v10
+; ZVZIP-NEXT: add a4, a1, a2
+; ZVZIP-NEXT: add a5, a4, a2
+; ZVZIP-NEXT: vmv1r.v v25, v14
+; ZVZIP-NEXT: add a6, a5, a2
+; ZVZIP-NEXT: vmv1r.v v18, v11
+; ZVZIP-NEXT: vsseg5e16.v v22, (a0)
+; ZVZIP-NEXT: vmv1r.v v20, v15
+; ZVZIP-NEXT: vsseg5e16.v v17, (a1)
+; ZVZIP-NEXT: vl1re16.v v16, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re16.v v17, (a6)
+; ZVZIP-NEXT: add a6, a3, a2
+; ZVZIP-NEXT: vl1re16.v v10, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re16.v v11, (a6)
+; ZVZIP-NEXT: vl1re16.v v8, (a0)
+; ZVZIP-NEXT: vl1re16.v v9, (a3)
+; ZVZIP-NEXT: vl1re16.v v14, (a4)
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: li a3, 10
+; ZVZIP-NEXT: mul a0, a0, a3
+; ZVZIP-NEXT: add a0, sp, a0
+; ZVZIP-NEXT: addi a0, a0, 64
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re16.v v15, (a5)
+; ZVZIP-NEXT: vl1re16.v v12, (a6)
+; ZVZIP-NEXT: vl1re16.v v13, (a1)
+; ZVZIP-NEXT: slli a2, a2, 3
+; ZVZIP-NEXT: add a2, a0, a2
+; ZVZIP-NEXT: vs2r.v v16, (a2)
+; ZVZIP-NEXT: vs8r.v v8, (a0)
+; ZVZIP-NEXT: vl8re16.v v16, (a2)
+; ZVZIP-NEXT: vl8re16.v v8, (a0)
+; ZVZIP-NEXT: addi sp, s0, -80
+; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
+; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
+; ZVZIP-NEXT: addi sp, sp, 80
+; ZVZIP-NEXT: ret
%res = call <vscale x 40 x half> @llvm.vector.interleave5.nxv40f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x half> %v3, <vscale x 8 x half> %v4)
ret <vscale x 40 x half> %res
}
@@ -8838,6 +9945,72 @@ define <vscale x 40 x bfloat> @vector_interleave_nxv40bf16_nxv8bf16(<vscale x 8
; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZIP-NEXT: addi sp, sp, 80
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv40bf16_nxv8bf16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: addi sp, sp, -80
+; ZVZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
+; ZVZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
+; ZVZIP-NEXT: addi s0, sp, 80
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: li a1, 28
+; ZVZIP-NEXT: mul a0, a0, a1
+; ZVZIP-NEXT: sub sp, sp, a0
+; ZVZIP-NEXT: andi sp, sp, -64
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vmv2r.v v20, v16
+; ZVZIP-NEXT: addi a0, sp, 64
+; ZVZIP-NEXT: vmv2r.v v18, v12
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a2, a1, 2
+; ZVZIP-NEXT: add a1, a2, a1
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: csrr a2, vlenb
+; ZVZIP-NEXT: vmv2r.v v16, v8
+; ZVZIP-NEXT: vmv2r.v v22, v16
+; ZVZIP-NEXT: vmv2r.v v24, v18
+; ZVZIP-NEXT: vmv1r.v v26, v20
+; ZVZIP-NEXT: add a3, a0, a2
+; ZVZIP-NEXT: vmv1r.v v23, v10
+; ZVZIP-NEXT: add a4, a1, a2
+; ZVZIP-NEXT: add a5, a4, a2
+; ZVZIP-NEXT: vmv1r.v v25, v14
+; ZVZIP-NEXT: add a6, a5, a2
+; ZVZIP-NEXT: vmv1r.v v18, v11
+; ZVZIP-NEXT: vsseg5e16.v v22, (a0)
+; ZVZIP-NEXT: vmv1r.v v20, v15
+; ZVZIP-NEXT: vsseg5e16.v v17, (a1)
+; ZVZIP-NEXT: vl1re16.v v16, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re16.v v17, (a6)
+; ZVZIP-NEXT: add a6, a3, a2
+; ZVZIP-NEXT: vl1re16.v v10, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re16.v v11, (a6)
+; ZVZIP-NEXT: vl1re16.v v8, (a0)
+; ZVZIP-NEXT: vl1re16.v v9, (a3)
+; ZVZIP-NEXT: vl1re16.v v14, (a4)
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: li a3, 10
+; ZVZIP-NEXT: mul a0, a0, a3
+; ZVZIP-NEXT: add a0, sp, a0
+; ZVZIP-NEXT: addi a0, a0, 64
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re16.v v15, (a5)
+; ZVZIP-NEXT: vl1re16.v v12, (a6)
+; ZVZIP-NEXT: vl1re16.v v13, (a1)
+; ZVZIP-NEXT: slli a2, a2, 3
+; ZVZIP-NEXT: add a2, a0, a2
+; ZVZIP-NEXT: vs2r.v v16, (a2)
+; ZVZIP-NEXT: vs8r.v v8, (a0)
+; ZVZIP-NEXT: vl8re16.v v16, (a2)
+; ZVZIP-NEXT: vl8re16.v v8, (a0)
+; ZVZIP-NEXT: addi sp, s0, -80
+; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
+; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
+; ZVZIP-NEXT: addi sp, sp, 80
+; ZVZIP-NEXT: ret
%res = call <vscale x 40 x bfloat> @llvm.vector.interleave5.nxv40bf16(<vscale x 8 x bfloat> %v0, <vscale x 8 x bfloat> %v1, <vscale x 8 x bfloat> %v2, <vscale x 8 x bfloat> %v3, <vscale x 8 x bfloat> %v4)
ret <vscale x 40 x bfloat> %res
}
@@ -9304,6 +10477,72 @@ define <vscale x 20 x float> @vector_interleave_nxv20f32_nxv4f32(<vscale x 4 x f
; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZIP-NEXT: addi sp, sp, 80
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv20f32_nxv4f32:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: addi sp, sp, -80
+; ZVZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
+; ZVZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
+; ZVZIP-NEXT: addi s0, sp, 80
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: li a1, 28
+; ZVZIP-NEXT: mul a0, a0, a1
+; ZVZIP-NEXT: sub sp, sp, a0
+; ZVZIP-NEXT: andi sp, sp, -64
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; ZVZIP-NEXT: vmv2r.v v20, v16
+; ZVZIP-NEXT: addi a0, sp, 64
+; ZVZIP-NEXT: vmv2r.v v18, v12
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a2, a1, 2
+; ZVZIP-NEXT: add a1, a2, a1
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: csrr a2, vlenb
+; ZVZIP-NEXT: vmv2r.v v16, v8
+; ZVZIP-NEXT: vmv2r.v v22, v16
+; ZVZIP-NEXT: vmv2r.v v24, v18
+; ZVZIP-NEXT: vmv1r.v v26, v20
+; ZVZIP-NEXT: add a3, a0, a2
+; ZVZIP-NEXT: vmv1r.v v23, v10
+; ZVZIP-NEXT: add a4, a1, a2
+; ZVZIP-NEXT: add a5, a4, a2
+; ZVZIP-NEXT: vmv1r.v v25, v14
+; ZVZIP-NEXT: add a6, a5, a2
+; ZVZIP-NEXT: vmv1r.v v18, v11
+; ZVZIP-NEXT: vsseg5e32.v v22, (a0)
+; ZVZIP-NEXT: vmv1r.v v20, v15
+; ZVZIP-NEXT: vsseg5e32.v v17, (a1)
+; ZVZIP-NEXT: vl1re32.v v16, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re32.v v17, (a6)
+; ZVZIP-NEXT: add a6, a3, a2
+; ZVZIP-NEXT: vl1re32.v v10, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re32.v v11, (a6)
+; ZVZIP-NEXT: vl1re32.v v8, (a0)
+; ZVZIP-NEXT: vl1re32.v v9, (a3)
+; ZVZIP-NEXT: vl1re32.v v14, (a4)
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: li a3, 10
+; ZVZIP-NEXT: mul a0, a0, a3
+; ZVZIP-NEXT: add a0, sp, a0
+; ZVZIP-NEXT: addi a0, a0, 64
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re32.v v15, (a5)
+; ZVZIP-NEXT: vl1re32.v v12, (a6)
+; ZVZIP-NEXT: vl1re32.v v13, (a1)
+; ZVZIP-NEXT: slli a2, a2, 3
+; ZVZIP-NEXT: add a2, a0, a2
+; ZVZIP-NEXT: vs2r.v v16, (a2)
+; ZVZIP-NEXT: vs8r.v v8, (a0)
+; ZVZIP-NEXT: vl8re32.v v16, (a2)
+; ZVZIP-NEXT: vl8re32.v v8, (a0)
+; ZVZIP-NEXT: addi sp, s0, -80
+; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
+; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
+; ZVZIP-NEXT: addi sp, sp, 80
+; ZVZIP-NEXT: ret
%res = call <vscale x 20 x float> @llvm.vector.interleave5.nxv20f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, <vscale x 4 x float> %v3, <vscale x 4 x float> %v4)
ret <vscale x 20 x float> %res
}
@@ -9696,6 +10935,72 @@ define <vscale x 10 x double> @vector_interleave_nxv10f64_nxv2f64(<vscale x 2 x
; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZIP-NEXT: addi sp, sp, 80
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv10f64_nxv2f64:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: addi sp, sp, -80
+; ZVZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
+; ZVZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
+; ZVZIP-NEXT: addi s0, sp, 80
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: li a1, 28
+; ZVZIP-NEXT: mul a0, a0, a1
+; ZVZIP-NEXT: sub sp, sp, a0
+; ZVZIP-NEXT: andi sp, sp, -64
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; ZVZIP-NEXT: vmv2r.v v20, v16
+; ZVZIP-NEXT: addi a0, sp, 64
+; ZVZIP-NEXT: vmv2r.v v18, v12
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a2, a1, 2
+; ZVZIP-NEXT: add a1, a2, a1
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: csrr a2, vlenb
+; ZVZIP-NEXT: vmv2r.v v16, v8
+; ZVZIP-NEXT: vmv2r.v v22, v16
+; ZVZIP-NEXT: vmv2r.v v24, v18
+; ZVZIP-NEXT: vmv1r.v v26, v20
+; ZVZIP-NEXT: add a3, a0, a2
+; ZVZIP-NEXT: vmv1r.v v23, v10
+; ZVZIP-NEXT: add a4, a1, a2
+; ZVZIP-NEXT: add a5, a4, a2
+; ZVZIP-NEXT: vmv1r.v v25, v14
+; ZVZIP-NEXT: add a6, a5, a2
+; ZVZIP-NEXT: vmv1r.v v18, v11
+; ZVZIP-NEXT: vsseg5e64.v v22, (a0)
+; ZVZIP-NEXT: vmv1r.v v20, v15
+; ZVZIP-NEXT: vsseg5e64.v v17, (a1)
+; ZVZIP-NEXT: vl1re64.v v16, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re64.v v17, (a6)
+; ZVZIP-NEXT: add a6, a3, a2
+; ZVZIP-NEXT: vl1re64.v v10, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re64.v v11, (a6)
+; ZVZIP-NEXT: vl1re64.v v8, (a0)
+; ZVZIP-NEXT: vl1re64.v v9, (a3)
+; ZVZIP-NEXT: vl1re64.v v14, (a4)
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: li a3, 10
+; ZVZIP-NEXT: mul a0, a0, a3
+; ZVZIP-NEXT: add a0, sp, a0
+; ZVZIP-NEXT: addi a0, a0, 64
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re64.v v15, (a5)
+; ZVZIP-NEXT: vl1re64.v v12, (a6)
+; ZVZIP-NEXT: vl1re64.v v13, (a1)
+; ZVZIP-NEXT: slli a2, a2, 3
+; ZVZIP-NEXT: add a2, a0, a2
+; ZVZIP-NEXT: vs2r.v v16, (a2)
+; ZVZIP-NEXT: vs8r.v v8, (a0)
+; ZVZIP-NEXT: vl8re64.v v16, (a2)
+; ZVZIP-NEXT: vl8re64.v v8, (a0)
+; ZVZIP-NEXT: addi sp, s0, -80
+; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
+; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
+; ZVZIP-NEXT: addi sp, sp, 80
+; ZVZIP-NEXT: ret
%res = call <vscale x 10 x double> @llvm.vector.interleave5.nxv10f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2, <vscale x 2 x double> %v3, <vscale x 2 x double> %v4)
ret <vscale x 10 x double> %res
}
@@ -10209,6 +11514,79 @@ define <vscale x 48 x half> @vector_interleave_nxv48f16_nxv8f16(<vscale x 8 x ha
; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZIP-NEXT: addi sp, sp, 80
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv48f16_nxv8f16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: addi sp, sp, -80
+; ZVZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
+; ZVZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
+; ZVZIP-NEXT: addi s0, sp, 80
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: li a1, 28
+; ZVZIP-NEXT: mul a0, a0, a1
+; ZVZIP-NEXT: sub sp, sp, a0
+; ZVZIP-NEXT: andi sp, sp, -64
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vmv2r.v v20, v14
+; ZVZIP-NEXT: vmv2r.v v22, v12
+; ZVZIP-NEXT: vmv2r.v v24, v10
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: li a0, 6
+; ZVZIP-NEXT: mul a1, a1, a0
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: vmv1r.v v10, v25
+; ZVZIP-NEXT: vmv1r.v v11, v23
+; ZVZIP-NEXT: vmv1r.v v12, v21
+; ZVZIP-NEXT: addi a0, sp, 64
+; ZVZIP-NEXT: vmv1r.v v13, v17
+; ZVZIP-NEXT: csrr a2, vlenb
+; ZVZIP-NEXT: vmv1r.v v14, v19
+; ZVZIP-NEXT: vsseg6e16.v v9, (a1)
+; ZVZIP-NEXT: vmv1r.v v9, v24
+; ZVZIP-NEXT: add a5, a1, a2
+; ZVZIP-NEXT: vmv1r.v v10, v22
+; ZVZIP-NEXT: add a3, a0, a2
+; ZVZIP-NEXT: vmv1r.v v11, v20
+; ZVZIP-NEXT: add a4, a3, a2
+; ZVZIP-NEXT: vmv1r.v v12, v16
+; ZVZIP-NEXT: add a6, a5, a2
+; ZVZIP-NEXT: vmv1r.v v13, v18
+; ZVZIP-NEXT: vsseg6e16.v v8, (a0)
+; ZVZIP-NEXT: vl1re16.v v14, (a1)
+; ZVZIP-NEXT: add a1, a6, a2
+; ZVZIP-NEXT: vl1re16.v v15, (a5)
+; ZVZIP-NEXT: add a5, a1, a2
+; ZVZIP-NEXT: vl1re16.v v18, (a5)
+; ZVZIP-NEXT: add a5, a5, a2
+; ZVZIP-NEXT: vl1re16.v v19, (a5)
+; ZVZIP-NEXT: add a5, a4, a2
+; ZVZIP-NEXT: vl1re16.v v16, (a6)
+; ZVZIP-NEXT: add a6, a5, a2
+; ZVZIP-NEXT: vl1re16.v v12, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re16.v v13, (a6)
+; ZVZIP-NEXT: csrr a6, vlenb
+; ZVZIP-NEXT: li a7, 12
+; ZVZIP-NEXT: mul a6, a6, a7
+; ZVZIP-NEXT: add a6, sp, a6
+; ZVZIP-NEXT: addi a6, a6, 64
+; ZVZIP-NEXT: vl1re16.v v17, (a1)
+; ZVZIP-NEXT: vl1re16.v v10, (a4)
+; ZVZIP-NEXT: vl1re16.v v11, (a5)
+; ZVZIP-NEXT: vl1re16.v v8, (a0)
+; ZVZIP-NEXT: vl1re16.v v9, (a3)
+; ZVZIP-NEXT: slli a2, a2, 3
+; ZVZIP-NEXT: add a2, a6, a2
+; ZVZIP-NEXT: vs4r.v v16, (a2)
+; ZVZIP-NEXT: vs8r.v v8, (a6)
+; ZVZIP-NEXT: vl8re16.v v16, (a2)
+; ZVZIP-NEXT: vl8re16.v v8, (a6)
+; ZVZIP-NEXT: addi sp, s0, -80
+; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
+; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
+; ZVZIP-NEXT: addi sp, sp, 80
+; ZVZIP-NEXT: ret
%res = call <vscale x 48 x half> @llvm.vector.interleave6.nxv48f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x half> %v3, <vscale x 8 x half> %v4, <vscale x 8 x half> %v5)
ret <vscale x 48 x half> %res
}
@@ -10722,6 +12100,79 @@ define <vscale x 48 x bfloat> @vector_interleave_nxv48bf16_nxv8bf16(<vscale x 8
; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZIP-NEXT: addi sp, sp, 80
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv48bf16_nxv8bf16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: addi sp, sp, -80
+; ZVZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
+; ZVZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
+; ZVZIP-NEXT: addi s0, sp, 80
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: li a1, 28
+; ZVZIP-NEXT: mul a0, a0, a1
+; ZVZIP-NEXT: sub sp, sp, a0
+; ZVZIP-NEXT: andi sp, sp, -64
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vmv2r.v v20, v14
+; ZVZIP-NEXT: vmv2r.v v22, v12
+; ZVZIP-NEXT: vmv2r.v v24, v10
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: li a0, 6
+; ZVZIP-NEXT: mul a1, a1, a0
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: vmv1r.v v10, v25
+; ZVZIP-NEXT: vmv1r.v v11, v23
+; ZVZIP-NEXT: vmv1r.v v12, v21
+; ZVZIP-NEXT: addi a0, sp, 64
+; ZVZIP-NEXT: vmv1r.v v13, v17
+; ZVZIP-NEXT: csrr a2, vlenb
+; ZVZIP-NEXT: vmv1r.v v14, v19
+; ZVZIP-NEXT: vsseg6e16.v v9, (a1)
+; ZVZIP-NEXT: vmv1r.v v9, v24
+; ZVZIP-NEXT: add a5, a1, a2
+; ZVZIP-NEXT: vmv1r.v v10, v22
+; ZVZIP-NEXT: add a3, a0, a2
+; ZVZIP-NEXT: vmv1r.v v11, v20
+; ZVZIP-NEXT: add a4, a3, a2
+; ZVZIP-NEXT: vmv1r.v v12, v16
+; ZVZIP-NEXT: add a6, a5, a2
+; ZVZIP-NEXT: vmv1r.v v13, v18
+; ZVZIP-NEXT: vsseg6e16.v v8, (a0)
+; ZVZIP-NEXT: vl1re16.v v14, (a1)
+; ZVZIP-NEXT: add a1, a6, a2
+; ZVZIP-NEXT: vl1re16.v v15, (a5)
+; ZVZIP-NEXT: add a5, a1, a2
+; ZVZIP-NEXT: vl1re16.v v18, (a5)
+; ZVZIP-NEXT: add a5, a5, a2
+; ZVZIP-NEXT: vl1re16.v v19, (a5)
+; ZVZIP-NEXT: add a5, a4, a2
+; ZVZIP-NEXT: vl1re16.v v16, (a6)
+; ZVZIP-NEXT: add a6, a5, a2
+; ZVZIP-NEXT: vl1re16.v v12, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re16.v v13, (a6)
+; ZVZIP-NEXT: csrr a6, vlenb
+; ZVZIP-NEXT: li a7, 12
+; ZVZIP-NEXT: mul a6, a6, a7
+; ZVZIP-NEXT: add a6, sp, a6
+; ZVZIP-NEXT: addi a6, a6, 64
+; ZVZIP-NEXT: vl1re16.v v17, (a1)
+; ZVZIP-NEXT: vl1re16.v v10, (a4)
+; ZVZIP-NEXT: vl1re16.v v11, (a5)
+; ZVZIP-NEXT: vl1re16.v v8, (a0)
+; ZVZIP-NEXT: vl1re16.v v9, (a3)
+; ZVZIP-NEXT: slli a2, a2, 3
+; ZVZIP-NEXT: add a2, a6, a2
+; ZVZIP-NEXT: vs4r.v v16, (a2)
+; ZVZIP-NEXT: vs8r.v v8, (a6)
+; ZVZIP-NEXT: vl8re16.v v16, (a2)
+; ZVZIP-NEXT: vl8re16.v v8, (a6)
+; ZVZIP-NEXT: addi sp, s0, -80
+; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
+; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
+; ZVZIP-NEXT: addi sp, sp, 80
+; ZVZIP-NEXT: ret
%res = call <vscale x 48 x bfloat> @llvm.vector.interleave6.nxv48bf16(<vscale x 8 x bfloat> %v0, <vscale x 8 x bfloat> %v1, <vscale x 8 x bfloat> %v2, <vscale x 8 x bfloat> %v3, <vscale x 8 x bfloat> %v4, <vscale x 8 x bfloat> %v5)
ret <vscale x 48 x bfloat> %res
}
@@ -11235,6 +12686,79 @@ define <vscale x 24 x float> @vector_interleave_nxv24f32_nxv4f32(<vscale x 4 x f
; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZIP-NEXT: addi sp, sp, 80
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv24f32_nxv4f32:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: addi sp, sp, -80
+; ZVZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
+; ZVZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
+; ZVZIP-NEXT: addi s0, sp, 80
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: li a1, 28
+; ZVZIP-NEXT: mul a0, a0, a1
+; ZVZIP-NEXT: sub sp, sp, a0
+; ZVZIP-NEXT: andi sp, sp, -64
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; ZVZIP-NEXT: vmv2r.v v20, v14
+; ZVZIP-NEXT: vmv2r.v v22, v12
+; ZVZIP-NEXT: vmv2r.v v24, v10
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: li a0, 6
+; ZVZIP-NEXT: mul a1, a1, a0
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: vmv1r.v v10, v25
+; ZVZIP-NEXT: vmv1r.v v11, v23
+; ZVZIP-NEXT: vmv1r.v v12, v21
+; ZVZIP-NEXT: addi a0, sp, 64
+; ZVZIP-NEXT: vmv1r.v v13, v17
+; ZVZIP-NEXT: csrr a2, vlenb
+; ZVZIP-NEXT: vmv1r.v v14, v19
+; ZVZIP-NEXT: vsseg6e32.v v9, (a1)
+; ZVZIP-NEXT: vmv1r.v v9, v24
+; ZVZIP-NEXT: add a5, a1, a2
+; ZVZIP-NEXT: vmv1r.v v10, v22
+; ZVZIP-NEXT: add a3, a0, a2
+; ZVZIP-NEXT: vmv1r.v v11, v20
+; ZVZIP-NEXT: add a4, a3, a2
+; ZVZIP-NEXT: vmv1r.v v12, v16
+; ZVZIP-NEXT: add a6, a5, a2
+; ZVZIP-NEXT: vmv1r.v v13, v18
+; ZVZIP-NEXT: vsseg6e32.v v8, (a0)
+; ZVZIP-NEXT: vl1re32.v v14, (a1)
+; ZVZIP-NEXT: add a1, a6, a2
+; ZVZIP-NEXT: vl1re32.v v15, (a5)
+; ZVZIP-NEXT: add a5, a1, a2
+; ZVZIP-NEXT: vl1re32.v v18, (a5)
+; ZVZIP-NEXT: add a5, a5, a2
+; ZVZIP-NEXT: vl1re32.v v19, (a5)
+; ZVZIP-NEXT: add a5, a4, a2
+; ZVZIP-NEXT: vl1re32.v v16, (a6)
+; ZVZIP-NEXT: add a6, a5, a2
+; ZVZIP-NEXT: vl1re32.v v12, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re32.v v13, (a6)
+; ZVZIP-NEXT: csrr a6, vlenb
+; ZVZIP-NEXT: li a7, 12
+; ZVZIP-NEXT: mul a6, a6, a7
+; ZVZIP-NEXT: add a6, sp, a6
+; ZVZIP-NEXT: addi a6, a6, 64
+; ZVZIP-NEXT: vl1re32.v v17, (a1)
+; ZVZIP-NEXT: vl1re32.v v10, (a4)
+; ZVZIP-NEXT: vl1re32.v v11, (a5)
+; ZVZIP-NEXT: vl1re32.v v8, (a0)
+; ZVZIP-NEXT: vl1re32.v v9, (a3)
+; ZVZIP-NEXT: slli a2, a2, 3
+; ZVZIP-NEXT: add a2, a6, a2
+; ZVZIP-NEXT: vs4r.v v16, (a2)
+; ZVZIP-NEXT: vs8r.v v8, (a6)
+; ZVZIP-NEXT: vl8re32.v v16, (a2)
+; ZVZIP-NEXT: vl8re32.v v8, (a6)
+; ZVZIP-NEXT: addi sp, s0, -80
+; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
+; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
+; ZVZIP-NEXT: addi sp, sp, 80
+; ZVZIP-NEXT: ret
%res = call <vscale x 24 x float> @llvm.vector.interleave6.nxv24f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, <vscale x 4 x float> %v3, <vscale x 4 x float> %v4, <vscale x 4 x float> %v5)
ret <vscale x 24 x float> %res
}
@@ -11666,6 +13190,79 @@ define <vscale x 12 x double> @vector_interleave_nxv12f64_nxv2f64(<vscale x 2 x
; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZIP-NEXT: addi sp, sp, 80
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv12f64_nxv2f64:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: addi sp, sp, -80
+; ZVZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
+; ZVZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
+; ZVZIP-NEXT: addi s0, sp, 80
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: li a1, 28
+; ZVZIP-NEXT: mul a0, a0, a1
+; ZVZIP-NEXT: sub sp, sp, a0
+; ZVZIP-NEXT: andi sp, sp, -64
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; ZVZIP-NEXT: vmv2r.v v20, v14
+; ZVZIP-NEXT: vmv2r.v v22, v12
+; ZVZIP-NEXT: vmv2r.v v24, v10
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: li a0, 6
+; ZVZIP-NEXT: mul a1, a1, a0
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: vmv1r.v v10, v25
+; ZVZIP-NEXT: vmv1r.v v11, v23
+; ZVZIP-NEXT: vmv1r.v v12, v21
+; ZVZIP-NEXT: addi a0, sp, 64
+; ZVZIP-NEXT: vmv1r.v v13, v17
+; ZVZIP-NEXT: csrr a2, vlenb
+; ZVZIP-NEXT: vmv1r.v v14, v19
+; ZVZIP-NEXT: vsseg6e64.v v9, (a1)
+; ZVZIP-NEXT: vmv1r.v v9, v24
+; ZVZIP-NEXT: add a5, a1, a2
+; ZVZIP-NEXT: vmv1r.v v10, v22
+; ZVZIP-NEXT: add a3, a0, a2
+; ZVZIP-NEXT: vmv1r.v v11, v20
+; ZVZIP-NEXT: add a4, a3, a2
+; ZVZIP-NEXT: vmv1r.v v12, v16
+; ZVZIP-NEXT: add a6, a5, a2
+; ZVZIP-NEXT: vmv1r.v v13, v18
+; ZVZIP-NEXT: vsseg6e64.v v8, (a0)
+; ZVZIP-NEXT: vl1re64.v v14, (a1)
+; ZVZIP-NEXT: add a1, a6, a2
+; ZVZIP-NEXT: vl1re64.v v15, (a5)
+; ZVZIP-NEXT: add a5, a1, a2
+; ZVZIP-NEXT: vl1re64.v v18, (a5)
+; ZVZIP-NEXT: add a5, a5, a2
+; ZVZIP-NEXT: vl1re64.v v19, (a5)
+; ZVZIP-NEXT: add a5, a4, a2
+; ZVZIP-NEXT: vl1re64.v v16, (a6)
+; ZVZIP-NEXT: add a6, a5, a2
+; ZVZIP-NEXT: vl1re64.v v12, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re64.v v13, (a6)
+; ZVZIP-NEXT: csrr a6, vlenb
+; ZVZIP-NEXT: li a7, 12
+; ZVZIP-NEXT: mul a6, a6, a7
+; ZVZIP-NEXT: add a6, sp, a6
+; ZVZIP-NEXT: addi a6, a6, 64
+; ZVZIP-NEXT: vl1re64.v v17, (a1)
+; ZVZIP-NEXT: vl1re64.v v10, (a4)
+; ZVZIP-NEXT: vl1re64.v v11, (a5)
+; ZVZIP-NEXT: vl1re64.v v8, (a0)
+; ZVZIP-NEXT: vl1re64.v v9, (a3)
+; ZVZIP-NEXT: slli a2, a2, 3
+; ZVZIP-NEXT: add a2, a6, a2
+; ZVZIP-NEXT: vs4r.v v16, (a2)
+; ZVZIP-NEXT: vs8r.v v8, (a6)
+; ZVZIP-NEXT: vl8re64.v v16, (a2)
+; ZVZIP-NEXT: vl8re64.v v8, (a6)
+; ZVZIP-NEXT: addi sp, s0, -80
+; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
+; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
+; ZVZIP-NEXT: addi sp, sp, 80
+; ZVZIP-NEXT: ret
%res = call <vscale x 12 x double> @llvm.vector.interleave6.nxv12f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2, <vscale x 2 x double> %v3, <vscale x 2 x double> %v4, <vscale x 2 x double> %v5)
ret <vscale x 12 x double> %res
}
@@ -12223,6 +13820,87 @@ define <vscale x 56 x half> @vector_interleave_nxv56f16_nxv8f16(<vscale x 8 x ha
; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZIP-NEXT: addi sp, sp, 80
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv56f16_nxv8f16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: addi sp, sp, -80
+; ZVZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
+; ZVZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
+; ZVZIP-NEXT: addi s0, sp, 80
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 5
+; ZVZIP-NEXT: sub sp, sp, a0
+; ZVZIP-NEXT: andi sp, sp, -64
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vmv2r.v v26, v20
+; ZVZIP-NEXT: addi a0, sp, 64
+; ZVZIP-NEXT: vmv2r.v v24, v16
+; ZVZIP-NEXT: vmv2r.v v22, v12
+; ZVZIP-NEXT: vmv2r.v v20, v8
+; ZVZIP-NEXT: vmv1r.v v1, v20
+; ZVZIP-NEXT: vmv1r.v v3, v22
+; ZVZIP-NEXT: vmv1r.v v5, v24
+; ZVZIP-NEXT: vmv1r.v v7, v26
+; ZVZIP-NEXT: vmv1r.v v2, v10
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a2, a1, 3
+; ZVZIP-NEXT: sub a1, a2, a1
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: csrr a2, vlenb
+; ZVZIP-NEXT: vmv1r.v v4, v14
+; ZVZIP-NEXT: add a3, a0, a2
+; ZVZIP-NEXT: add a4, a1, a2
+; ZVZIP-NEXT: vmv1r.v v6, v18
+; ZVZIP-NEXT: add a5, a4, a2
+; ZVZIP-NEXT: vmv1r.v v22, v11
+; ZVZIP-NEXT: add a6, a5, a2
+; ZVZIP-NEXT: vmv1r.v v24, v15
+; ZVZIP-NEXT: vsseg7e16.v v1, (a0)
+; ZVZIP-NEXT: vmv1r.v v26, v19
+; ZVZIP-NEXT: vsseg7e16.v v21, (a1)
+; ZVZIP-NEXT: vl1re16.v v18, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re16.v v19, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re16.v v20, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re16.v v21, (a6)
+; ZVZIP-NEXT: add a6, a3, a2
+; ZVZIP-NEXT: vl1re16.v v10, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re16.v v11, (a6)
+; ZVZIP-NEXT: vl1re16.v v8, (a0)
+; ZVZIP-NEXT: vl1re16.v v16, (a4)
+; ZVZIP-NEXT: vl1re16.v v9, (a3)
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: li a3, 14
+; ZVZIP-NEXT: mul a0, a0, a3
+; ZVZIP-NEXT: add a0, sp, a0
+; ZVZIP-NEXT: addi a0, a0, 64
+; ZVZIP-NEXT: vl1re16.v v17, (a5)
+; ZVZIP-NEXT: slli a3, a2, 2
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re16.v v12, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re16.v v13, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: slli a2, a2, 3
+; ZVZIP-NEXT: add a3, a2, a3
+; ZVZIP-NEXT: add a2, a0, a2
+; ZVZIP-NEXT: vl1re16.v v14, (a6)
+; ZVZIP-NEXT: vl1re16.v v15, (a1)
+; ZVZIP-NEXT: add a3, a0, a3
+; ZVZIP-NEXT: vs2r.v v20, (a3)
+; ZVZIP-NEXT: vs4r.v v16, (a2)
+; ZVZIP-NEXT: vs8r.v v8, (a0)
+; ZVZIP-NEXT: vl8re16.v v16, (a2)
+; ZVZIP-NEXT: vl8re16.v v8, (a0)
+; ZVZIP-NEXT: addi sp, s0, -80
+; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
+; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
+; ZVZIP-NEXT: addi sp, sp, 80
+; ZVZIP-NEXT: ret
%res = call <vscale x 56 x half> @llvm.vector.interleave7.nxv56f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x half> %v3, <vscale x 8 x half> %v4, <vscale x 8 x half> %v5, <vscale x 8 x half> %v6)
ret <vscale x 56 x half> %res
}
@@ -12780,6 +14458,87 @@ define <vscale x 56 x bfloat> @vector_interleave_nxv56bf16_nxv8bf16(<vscale x 8
; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZIP-NEXT: addi sp, sp, 80
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv56bf16_nxv8bf16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: addi sp, sp, -80
+; ZVZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
+; ZVZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
+; ZVZIP-NEXT: addi s0, sp, 80
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 5
+; ZVZIP-NEXT: sub sp, sp, a0
+; ZVZIP-NEXT: andi sp, sp, -64
+; ZVZIP-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vmv2r.v v26, v20
+; ZVZIP-NEXT: addi a0, sp, 64
+; ZVZIP-NEXT: vmv2r.v v24, v16
+; ZVZIP-NEXT: vmv2r.v v22, v12
+; ZVZIP-NEXT: vmv2r.v v20, v8
+; ZVZIP-NEXT: vmv1r.v v1, v20
+; ZVZIP-NEXT: vmv1r.v v3, v22
+; ZVZIP-NEXT: vmv1r.v v5, v24
+; ZVZIP-NEXT: vmv1r.v v7, v26
+; ZVZIP-NEXT: vmv1r.v v2, v10
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a2, a1, 3
+; ZVZIP-NEXT: sub a1, a2, a1
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: csrr a2, vlenb
+; ZVZIP-NEXT: vmv1r.v v4, v14
+; ZVZIP-NEXT: add a3, a0, a2
+; ZVZIP-NEXT: add a4, a1, a2
+; ZVZIP-NEXT: vmv1r.v v6, v18
+; ZVZIP-NEXT: add a5, a4, a2
+; ZVZIP-NEXT: vmv1r.v v22, v11
+; ZVZIP-NEXT: add a6, a5, a2
+; ZVZIP-NEXT: vmv1r.v v24, v15
+; ZVZIP-NEXT: vsseg7e16.v v1, (a0)
+; ZVZIP-NEXT: vmv1r.v v26, v19
+; ZVZIP-NEXT: vsseg7e16.v v21, (a1)
+; ZVZIP-NEXT: vl1re16.v v18, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re16.v v19, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re16.v v20, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re16.v v21, (a6)
+; ZVZIP-NEXT: add a6, a3, a2
+; ZVZIP-NEXT: vl1re16.v v10, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re16.v v11, (a6)
+; ZVZIP-NEXT: vl1re16.v v8, (a0)
+; ZVZIP-NEXT: vl1re16.v v16, (a4)
+; ZVZIP-NEXT: vl1re16.v v9, (a3)
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: li a3, 14
+; ZVZIP-NEXT: mul a0, a0, a3
+; ZVZIP-NEXT: add a0, sp, a0
+; ZVZIP-NEXT: addi a0, a0, 64
+; ZVZIP-NEXT: vl1re16.v v17, (a5)
+; ZVZIP-NEXT: slli a3, a2, 2
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re16.v v12, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re16.v v13, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: slli a2, a2, 3
+; ZVZIP-NEXT: add a3, a2, a3
+; ZVZIP-NEXT: add a2, a0, a2
+; ZVZIP-NEXT: vl1re16.v v14, (a6)
+; ZVZIP-NEXT: vl1re16.v v15, (a1)
+; ZVZIP-NEXT: add a3, a0, a3
+; ZVZIP-NEXT: vs2r.v v20, (a3)
+; ZVZIP-NEXT: vs4r.v v16, (a2)
+; ZVZIP-NEXT: vs8r.v v8, (a0)
+; ZVZIP-NEXT: vl8re16.v v16, (a2)
+; ZVZIP-NEXT: vl8re16.v v8, (a0)
+; ZVZIP-NEXT: addi sp, s0, -80
+; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
+; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
+; ZVZIP-NEXT: addi sp, sp, 80
+; ZVZIP-NEXT: ret
%res = call <vscale x 56 x bfloat> @llvm.vector.interleave7.nxv56bf16(<vscale x 8 x bfloat> %v0, <vscale x 8 x bfloat> %v1, <vscale x 8 x bfloat> %v2, <vscale x 8 x bfloat> %v3, <vscale x 8 x bfloat> %v4, <vscale x 8 x bfloat> %v5, <vscale x 8 x bfloat> %v6)
ret <vscale x 56 x bfloat> %res
}
@@ -13337,6 +15096,87 @@ define <vscale x 28 x float> @vector_interleave_nxv28f32_nxv4f32(<vscale x 4 x f
; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZIP-NEXT: addi sp, sp, 80
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv28f32_nxv4f32:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: addi sp, sp, -80
+; ZVZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
+; ZVZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
+; ZVZIP-NEXT: addi s0, sp, 80
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 5
+; ZVZIP-NEXT: sub sp, sp, a0
+; ZVZIP-NEXT: andi sp, sp, -64
+; ZVZIP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; ZVZIP-NEXT: vmv2r.v v26, v20
+; ZVZIP-NEXT: addi a0, sp, 64
+; ZVZIP-NEXT: vmv2r.v v24, v16
+; ZVZIP-NEXT: vmv2r.v v22, v12
+; ZVZIP-NEXT: vmv2r.v v20, v8
+; ZVZIP-NEXT: vmv1r.v v1, v20
+; ZVZIP-NEXT: vmv1r.v v3, v22
+; ZVZIP-NEXT: vmv1r.v v5, v24
+; ZVZIP-NEXT: vmv1r.v v7, v26
+; ZVZIP-NEXT: vmv1r.v v2, v10
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a2, a1, 3
+; ZVZIP-NEXT: sub a1, a2, a1
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: csrr a2, vlenb
+; ZVZIP-NEXT: vmv1r.v v4, v14
+; ZVZIP-NEXT: add a3, a0, a2
+; ZVZIP-NEXT: add a4, a1, a2
+; ZVZIP-NEXT: vmv1r.v v6, v18
+; ZVZIP-NEXT: add a5, a4, a2
+; ZVZIP-NEXT: vmv1r.v v22, v11
+; ZVZIP-NEXT: add a6, a5, a2
+; ZVZIP-NEXT: vmv1r.v v24, v15
+; ZVZIP-NEXT: vsseg7e32.v v1, (a0)
+; ZVZIP-NEXT: vmv1r.v v26, v19
+; ZVZIP-NEXT: vsseg7e32.v v21, (a1)
+; ZVZIP-NEXT: vl1re32.v v18, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re32.v v19, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re32.v v20, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re32.v v21, (a6)
+; ZVZIP-NEXT: add a6, a3, a2
+; ZVZIP-NEXT: vl1re32.v v10, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re32.v v11, (a6)
+; ZVZIP-NEXT: vl1re32.v v8, (a0)
+; ZVZIP-NEXT: vl1re32.v v16, (a4)
+; ZVZIP-NEXT: vl1re32.v v9, (a3)
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: li a3, 14
+; ZVZIP-NEXT: mul a0, a0, a3
+; ZVZIP-NEXT: add a0, sp, a0
+; ZVZIP-NEXT: addi a0, a0, 64
+; ZVZIP-NEXT: vl1re32.v v17, (a5)
+; ZVZIP-NEXT: slli a3, a2, 2
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re32.v v12, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re32.v v13, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: slli a2, a2, 3
+; ZVZIP-NEXT: add a3, a2, a3
+; ZVZIP-NEXT: add a2, a0, a2
+; ZVZIP-NEXT: vl1re32.v v14, (a6)
+; ZVZIP-NEXT: vl1re32.v v15, (a1)
+; ZVZIP-NEXT: add a3, a0, a3
+; ZVZIP-NEXT: vs2r.v v20, (a3)
+; ZVZIP-NEXT: vs4r.v v16, (a2)
+; ZVZIP-NEXT: vs8r.v v8, (a0)
+; ZVZIP-NEXT: vl8re32.v v16, (a2)
+; ZVZIP-NEXT: vl8re32.v v8, (a0)
+; ZVZIP-NEXT: addi sp, s0, -80
+; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
+; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
+; ZVZIP-NEXT: addi sp, sp, 80
+; ZVZIP-NEXT: ret
%res = call <vscale x 28 x float> @llvm.vector.interleave7.nxv28f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, <vscale x 4 x float> %v3, <vscale x 4 x float> %v4, <vscale x 4 x float> %v5, <vscale x 4 x float> %v6)
ret <vscale x 28 x float> %res
}
@@ -13812,6 +15652,87 @@ define <vscale x 14 x double> @vector_interleave_nxv14f64_nxv2f64(<vscale x 2 x
; ZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; ZIP-NEXT: addi sp, sp, 80
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vector_interleave_nxv14f64_nxv2f64:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: addi sp, sp, -80
+; ZVZIP-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
+; ZVZIP-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
+; ZVZIP-NEXT: addi s0, sp, 80
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: slli a0, a0, 5
+; ZVZIP-NEXT: sub sp, sp, a0
+; ZVZIP-NEXT: andi sp, sp, -64
+; ZVZIP-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; ZVZIP-NEXT: vmv2r.v v26, v20
+; ZVZIP-NEXT: addi a0, sp, 64
+; ZVZIP-NEXT: vmv2r.v v24, v16
+; ZVZIP-NEXT: vmv2r.v v22, v12
+; ZVZIP-NEXT: vmv2r.v v20, v8
+; ZVZIP-NEXT: vmv1r.v v1, v20
+; ZVZIP-NEXT: vmv1r.v v3, v22
+; ZVZIP-NEXT: vmv1r.v v5, v24
+; ZVZIP-NEXT: vmv1r.v v7, v26
+; ZVZIP-NEXT: vmv1r.v v2, v10
+; ZVZIP-NEXT: csrr a1, vlenb
+; ZVZIP-NEXT: slli a2, a1, 3
+; ZVZIP-NEXT: sub a1, a2, a1
+; ZVZIP-NEXT: add a1, sp, a1
+; ZVZIP-NEXT: addi a1, a1, 64
+; ZVZIP-NEXT: csrr a2, vlenb
+; ZVZIP-NEXT: vmv1r.v v4, v14
+; ZVZIP-NEXT: add a3, a0, a2
+; ZVZIP-NEXT: add a4, a1, a2
+; ZVZIP-NEXT: vmv1r.v v6, v18
+; ZVZIP-NEXT: add a5, a4, a2
+; ZVZIP-NEXT: vmv1r.v v22, v11
+; ZVZIP-NEXT: add a6, a5, a2
+; ZVZIP-NEXT: vmv1r.v v24, v15
+; ZVZIP-NEXT: vsseg7e64.v v1, (a0)
+; ZVZIP-NEXT: vmv1r.v v26, v19
+; ZVZIP-NEXT: vsseg7e64.v v21, (a1)
+; ZVZIP-NEXT: vl1re64.v v18, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re64.v v19, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re64.v v20, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re64.v v21, (a6)
+; ZVZIP-NEXT: add a6, a3, a2
+; ZVZIP-NEXT: vl1re64.v v10, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re64.v v11, (a6)
+; ZVZIP-NEXT: vl1re64.v v8, (a0)
+; ZVZIP-NEXT: vl1re64.v v16, (a4)
+; ZVZIP-NEXT: vl1re64.v v9, (a3)
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: li a3, 14
+; ZVZIP-NEXT: mul a0, a0, a3
+; ZVZIP-NEXT: add a0, sp, a0
+; ZVZIP-NEXT: addi a0, a0, 64
+; ZVZIP-NEXT: vl1re64.v v17, (a5)
+; ZVZIP-NEXT: slli a3, a2, 2
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re64.v v12, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: vl1re64.v v13, (a6)
+; ZVZIP-NEXT: add a6, a6, a2
+; ZVZIP-NEXT: slli a2, a2, 3
+; ZVZIP-NEXT: add a3, a2, a3
+; ZVZIP-NEXT: add a2, a0, a2
+; ZVZIP-NEXT: vl1re64.v v14, (a6)
+; ZVZIP-NEXT: vl1re64.v v15, (a1)
+; ZVZIP-NEXT: add a3, a0, a3
+; ZVZIP-NEXT: vs2r.v v20, (a3)
+; ZVZIP-NEXT: vs4r.v v16, (a2)
+; ZVZIP-NEXT: vs8r.v v8, (a0)
+; ZVZIP-NEXT: vl8re64.v v16, (a2)
+; ZVZIP-NEXT: vl8re64.v v8, (a0)
+; ZVZIP-NEXT: addi sp, s0, -80
+; ZVZIP-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
+; ZVZIP-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
+; ZVZIP-NEXT: addi sp, sp, 80
+; ZVZIP-NEXT: ret
%res = call <vscale x 14 x double> @llvm.vector.interleave7.nxv14f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2, <vscale x 2 x double> %v3, <vscale x 2 x double> %v4, <vscale x 2 x double> %v5, <vscale x 2 x double> %v6)
ret <vscale x 14 x double> %res
}
@@ -14966,6 +16887,21 @@ define <vscale x 4 x i16> @interleave2_
diff _const_splat_nxv4i16() {
; ZIP-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; ZIP-NEXT: vslideup.vx v8, v11, a0
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: interleave2_
diff _const_splat_nxv4i16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; ZVZIP-NEXT: vmv.v.i v9, 3
+; ZVZIP-NEXT: li a0, 4
+; ZVZIP-NEXT: vmv.v.i v10, -1
+; ZVZIP-NEXT: vwaddu.vx v8, v9, a0
+; ZVZIP-NEXT: vwmaccu.vx v8, a0, v10
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: srli a0, a0, 2
+; ZVZIP-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v9, v8, a0
+; ZVZIP-NEXT: vslideup.vx v8, v9, a0
+; ZVZIP-NEXT: ret
%retval = call <vscale x 4 x i16> @llvm.vector.interleave2.v4i16(<vscale x 2 x i16> splat(i16 3), <vscale x 2 x i16> splat(i16 4))
ret <vscale x 4 x i16> %retval
}
@@ -15028,6 +16964,20 @@ define <vscale x 4 x i16> @interleave2_
diff _nonconst_splat_nxv4i16(i16 %a, i16 %
; ZIP-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; ZIP-NEXT: vslideup.vx v8, v11, a0
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: interleave2_
diff _nonconst_splat_nxv4i16:
+; ZVZIP: # %bb.0:
+; ZVZIP-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
+; ZVZIP-NEXT: vmv.v.x v9, a0
+; ZVZIP-NEXT: vmv.v.i v10, -1
+; ZVZIP-NEXT: csrr a0, vlenb
+; ZVZIP-NEXT: vwaddu.vx v8, v9, a1
+; ZVZIP-NEXT: vwmaccu.vx v8, a1, v10
+; ZVZIP-NEXT: srli a0, a0, 2
+; ZVZIP-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; ZVZIP-NEXT: vslidedown.vx v9, v8, a0
+; ZVZIP-NEXT: vslideup.vx v8, v9, a0
+; ZVZIP-NEXT: ret
%ins1 = insertelement <vscale x 2 x i16> poison, i16 %a, i32 0
%splat1 = shufflevector <vscale x 2 x i16> %ins1, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
%ins2 = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
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