[llvm] cb5445f - [RISCV] Lower masked_{u, s}{div, rem} and update TTI (#192543)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 17 03:07:27 PDT 2026
Author: Luke Lau
Date: 2026-04-17T10:07:22Z
New Revision: cb5445f0797b01fee6410319df09813bfc8021f6
URL: https://github.com/llvm/llvm-project/commit/cb5445f0797b01fee6410319df09813bfc8021f6
DIFF: https://github.com/llvm/llvm-project/commit/cb5445f0797b01fee6410319df09813bfc8021f6.diff
LOG: [RISCV] Lower masked_{u,s}{div,rem} and update TTI (#192543)
The loop vectorizer will soon emit llvm.masked.udiv intrinsics and
friends. The vast majority of the time these will be transformed to
vp.udiv on RISC-V thanks to tail folding, but if it doesn't tail fold or
uses a fixed VF then it will reach instruction selection.
This patch lowers the nodes to the masked pseudo for scalable and fixed
vectors, and updates the TTI to account for it.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
llvm/test/Analysis/CostModel/RISCV/masked-divrem.ll
llvm/test/CodeGen/RISCV/rvv/masked-sdiv.ll
llvm/test/CodeGen/RISCV/rvv/masked-srem.ll
llvm/test/CodeGen/RISCV/rvv/masked-udiv.ll
llvm/test/CodeGen/RISCV/rvv/masked-urem.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 2a2521c62b8b9..4dc2e1c03b7f3 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1123,6 +1123,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
}
setOperationAction(ISD::VECTOR_COMPRESS, VT, Custom);
+ setOperationAction({ISD::MASKED_UDIV, ISD::MASKED_SDIV, ISD::MASKED_UREM,
+ ISD::MASKED_SREM},
+ VT, Legal);
}
for (MVT VT : VecTupleVTs) {
@@ -1616,6 +1619,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
}
setOperationAction(ISD::VECTOR_COMPRESS, VT, Custom);
+ setOperationAction({ISD::MASKED_UDIV, ISD::MASKED_SDIV,
+ ISD::MASKED_UREM, ISD::MASKED_SREM},
+ VT, Custom);
}
for (MVT VT : MVT::fp_fixedlen_vector_valuetypes()) {
@@ -7603,6 +7609,14 @@ static unsigned getRISCVVLOp(SDValue Op) {
case ISD::LRINT:
case ISD::LLRINT:
return RISCVISD::VFCVT_RM_X_F_VL;
+ case ISD::MASKED_UDIV:
+ return RISCVISD::UDIV_VL;
+ case ISD::MASKED_UREM:
+ return RISCVISD::UREM_VL;
+ case ISD::MASKED_SDIV:
+ return RISCVISD::SDIV_VL;
+ case ISD::MASKED_SREM:
+ return RISCVISD::SREM_VL;
}
// clang-format on
#undef OP_CASE
@@ -8796,6 +8810,18 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
return DAG.getNode(RISCVISD::PSSLAI, DL, VT, Op.getOperand(0),
DAG.getTargetConstant(ShAmt, DL, Subtarget.getXLenVT()));
}
+ case ISD::MASKED_UDIV:
+ case ISD::MASKED_SDIV:
+ case ISD::MASKED_UREM:
+ case ISD::MASKED_SREM: {
+ SDLoc DL(Op);
+ MVT VT = Op.getSimpleValueType();
+ MVT ContainerVT = getContainerForFixedLengthVector(VT);
+ SDValue VL = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget).second;
+ return DAG.getNode(getRISCVVLOp(Op), DL, ContainerVT, Op.getOperand(0),
+ Op.getOperand(1), DAG.getUNDEF(ContainerVT),
+ Op.getOperand(2), VL);
+ }
case ISD::FABS:
case ISD::FNEG:
if (Op.getValueType() == MVT::f16 || Op.getValueType() == MVT::bf16)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
index 4c558c4524c5b..01d259c393eea 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -168,6 +168,27 @@ multiclass VPatBinarySDNode_VV_VX_VI<SDPatternOperator vop, string instruction_n
}
}
+multiclass VPatBinaryMaskedSDNode_VV<SDPatternOperator vop, string instruction_name> {
+ foreach vti = AllIntegerVectors in {
+ def : Pat<(vti.Vector (vop vti.RegClass:$vs2, vti.RegClass:$vs1, VMV0:$vm)),
+ (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX#"_E"#!shl(1, vti.Log2SEW)#"_MASK")
+ (IMPLICIT_DEF), vti.RegClass:$vs2, vti.RegClass:$vs1, VMV0:$vm,
+ vti.AVL, vti.Log2SEW, TA_MA)>;
+ }
+}
+
+multiclass VPatBinaryMaskedSDNode_VV_VX<SDPatternOperator vop, string instruction_name>
+ : VPatBinaryMaskedSDNode_VV<vop, instruction_name> {
+ foreach vti = AllIntegerVectors in {
+ def : Pat<(vti.Vector (vop vti.RegClass:$vs2,
+ (SplatPat (XLenVT GPR:$rs1)),
+ VMV0:$vm)),
+ (!cast<Instruction>(instruction_name#"_VX_"#vti.LMul.MX#"_E"#!shl(1, vti.Log2SEW)#"_MASK")
+ (IMPLICIT_DEF), vti.RegClass:$vs2, GPR:$rs1, VMV0:$vm,
+ vti.AVL, vti.Log2SEW, TA_MA)>;
+ }
+}
+
class VPatBinarySDNode_VF<SDPatternOperator vop,
string instruction_name,
ValueType result_type,
@@ -1100,6 +1121,10 @@ defm : VPatBinarySDNode_VV_VX<udiv, "PseudoVDIVU", isSEWAware=1>;
defm : VPatBinarySDNode_VV_VX<sdiv, "PseudoVDIV", isSEWAware=1>;
defm : VPatBinarySDNode_VV_VX<urem, "PseudoVREMU", isSEWAware=1>;
defm : VPatBinarySDNode_VV_VX<srem, "PseudoVREM", isSEWAware=1>;
+defm : VPatBinaryMaskedSDNode_VV_VX<masked_udiv, "PseudoVDIVU">;
+defm : VPatBinaryMaskedSDNode_VV_VX<masked_sdiv, "PseudoVDIV">;
+defm : VPatBinaryMaskedSDNode_VV_VX<masked_urem, "PseudoVREMU">;
+defm : VPatBinaryMaskedSDNode_VV_VX<masked_srem, "PseudoVREM">;
foreach vtiTowti = AllWidenableIntVectors in {
defvar vti = vtiTowti.Vti;
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index fd762f35124b5..ad1a2c4d013fa 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -1615,6 +1615,18 @@ RISCVTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
}
break;
}
+ case Intrinsic::masked_udiv:
+ return getArithmeticInstrCost(Instruction::UDiv, ICA.getReturnType(),
+ CostKind);
+ case Intrinsic::masked_sdiv:
+ return getArithmeticInstrCost(Instruction::SDiv, ICA.getReturnType(),
+ CostKind);
+ case Intrinsic::masked_urem:
+ return getArithmeticInstrCost(Instruction::URem, ICA.getReturnType(),
+ CostKind);
+ case Intrinsic::masked_srem:
+ return getArithmeticInstrCost(Instruction::SRem, ICA.getReturnType(),
+ CostKind);
case Intrinsic::get_active_lane_mask: {
if (ST->hasVInstructions()) {
Type *ExpRetTy = VectorType::get(
diff --git a/llvm/test/Analysis/CostModel/RISCV/masked-divrem.ll b/llvm/test/Analysis/CostModel/RISCV/masked-divrem.ll
index 6846a4f282782..3fa305a00f218 100644
--- a/llvm/test/Analysis/CostModel/RISCV/masked-divrem.ll
+++ b/llvm/test/Analysis/CostModel/RISCV/masked-divrem.ll
@@ -4,36 +4,36 @@
define void @udiv() {
; CHECK-LABEL: 'udiv'
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %V1I16 = call <1 x i16> @llvm.masked.udiv.v1i16(<1 x i16> poison, <1 x i16> poison, <1 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %V2I16 = call <2 x i16> @llvm.masked.udiv.v2i16(<2 x i16> poison, <2 x i16> poison, <2 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %V4I16 = call <4 x i16> @llvm.masked.udiv.v4i16(<4 x i16> poison, <4 x i16> poison, <4 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %V8I16 = call <8 x i16> @llvm.masked.udiv.v8i16(<8 x i16> poison, <8 x i16> poison, <8 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:10 CodeSize:5 Lat:5 SizeLat:5 for: %V16I16 = call <16 x i16> @llvm.masked.udiv.v16i16(<16 x i16> poison, <16 x i16> poison, <16 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:20 CodeSize:5 Lat:5 SizeLat:5 for: %V32I16 = call <32 x i16> @llvm.masked.udiv.v32i16(<32 x i16> poison, <32 x i16> poison, <32 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %NXV1I16 = call <vscale x 1 x i16> @llvm.masked.udiv.nxv1i16(<vscale x 1 x i16> poison, <vscale x 1 x i16> poison, <vscale x 1 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %NXV2I16 = call <vscale x 2 x i16> @llvm.masked.udiv.nxv2i16(<vscale x 2 x i16> poison, <vscale x 2 x i16> poison, <vscale x 2 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %NXV4I16 = call <vscale x 4 x i16> @llvm.masked.udiv.nxv4i16(<vscale x 4 x i16> poison, <vscale x 4 x i16> poison, <vscale x 4 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:10 CodeSize:5 Lat:5 SizeLat:5 for: %NXV8I16 = call <vscale x 8 x i16> @llvm.masked.udiv.nxv8i16(<vscale x 8 x i16> poison, <vscale x 8 x i16> poison, <vscale x 8 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:20 CodeSize:5 Lat:5 SizeLat:5 for: %NXV16I16 = call <vscale x 16 x i16> @llvm.masked.udiv.nxv16i16(<vscale x 16 x i16> poison, <vscale x 16 x i16> poison, <vscale x 16 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:40 CodeSize:5 Lat:5 SizeLat:5 for: %NXV32I16 = call <vscale x 32 x i16> @llvm.masked.udiv.nxv32i16(<vscale x 32 x i16> poison, <vscale x 32 x i16> poison, <vscale x 32 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %V1I32 = call <1 x i32> @llvm.masked.udiv.v1i32(<1 x i32> poison, <1 x i32> poison, <1 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %V2I32 = call <2 x i32> @llvm.masked.udiv.v2i32(<2 x i32> poison, <2 x i32> poison, <2 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %V4I32 = call <4 x i32> @llvm.masked.udiv.v4i32(<4 x i32> poison, <4 x i32> poison, <4 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:10 CodeSize:5 Lat:5 SizeLat:5 for: %V8I32 = call <8 x i32> @llvm.masked.udiv.v8i32(<8 x i32> poison, <8 x i32> poison, <8 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:20 CodeSize:5 Lat:5 SizeLat:5 for: %V16I32 = call <16 x i32> @llvm.masked.udiv.v16i32(<16 x i32> poison, <16 x i32> poison, <16 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %NXV1I32 = call <vscale x 1 x i32> @llvm.masked.udiv.nxv1i32(<vscale x 1 x i32> poison, <vscale x 1 x i32> poison, <vscale x 1 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %NXV2I32 = call <vscale x 2 x i32> @llvm.masked.udiv.nxv2i32(<vscale x 2 x i32> poison, <vscale x 2 x i32> poison, <vscale x 2 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:10 CodeSize:5 Lat:5 SizeLat:5 for: %NXV4I32 = call <vscale x 4 x i32> @llvm.masked.udiv.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> poison, <vscale x 4 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:20 CodeSize:5 Lat:5 SizeLat:5 for: %NXV8I32 = call <vscale x 8 x i32> @llvm.masked.udiv.nxv8i32(<vscale x 8 x i32> poison, <vscale x 8 x i32> poison, <vscale x 8 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:40 CodeSize:5 Lat:5 SizeLat:5 for: %NXV16I32 = call <vscale x 16 x i32> @llvm.masked.udiv.nxv16i32(<vscale x 16 x i32> poison, <vscale x 16 x i32> poison, <vscale x 16 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %V1I64 = call <1 x i64> @llvm.masked.udiv.v1i64(<1 x i64> poison, <1 x i64> poison, <1 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %V2I64 = call <2 x i64> @llvm.masked.udiv.v2i64(<2 x i64> poison, <2 x i64> poison, <2 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:10 CodeSize:5 Lat:5 SizeLat:5 for: %V4I64 = call <4 x i64> @llvm.masked.udiv.v4i64(<4 x i64> poison, <4 x i64> poison, <4 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:20 CodeSize:5 Lat:5 SizeLat:5 for: %V8I64 = call <8 x i64> @llvm.masked.udiv.v8i64(<8 x i64> poison, <8 x i64> poison, <8 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %NXV1I64 = call <vscale x 1 x i64> @llvm.masked.udiv.nxv1i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> poison, <vscale x 1 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:10 CodeSize:5 Lat:5 SizeLat:5 for: %NXV2I64 = call <vscale x 2 x i64> @llvm.masked.udiv.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> poison, <vscale x 2 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:20 CodeSize:5 Lat:5 SizeLat:5 for: %NXV4I64 = call <vscale x 4 x i64> @llvm.masked.udiv.nxv4i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> poison, <vscale x 4 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:40 CodeSize:5 Lat:5 SizeLat:5 for: %NXV8I64 = call <vscale x 8 x i64> @llvm.masked.udiv.nxv8i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> poison, <vscale x 8 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V1I16 = call <1 x i16> @llvm.masked.udiv.v1i16(<1 x i16> poison, <1 x i16> poison, <1 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V2I16 = call <2 x i16> @llvm.masked.udiv.v2i16(<2 x i16> poison, <2 x i16> poison, <2 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V4I16 = call <4 x i16> @llvm.masked.udiv.v4i16(<4 x i16> poison, <4 x i16> poison, <4 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V8I16 = call <8 x i16> @llvm.masked.udiv.v8i16(<8 x i16> poison, <8 x i16> poison, <8 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V16I16 = call <16 x i16> @llvm.masked.udiv.v16i16(<16 x i16> poison, <16 x i16> poison, <16 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V32I16 = call <32 x i16> @llvm.masked.udiv.v32i16(<32 x i16> poison, <32 x i16> poison, <32 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NXV1I16 = call <vscale x 1 x i16> @llvm.masked.udiv.nxv1i16(<vscale x 1 x i16> poison, <vscale x 1 x i16> poison, <vscale x 1 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NXV2I16 = call <vscale x 2 x i16> @llvm.masked.udiv.nxv2i16(<vscale x 2 x i16> poison, <vscale x 2 x i16> poison, <vscale x 2 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NXV4I16 = call <vscale x 4 x i16> @llvm.masked.udiv.nxv4i16(<vscale x 4 x i16> poison, <vscale x 4 x i16> poison, <vscale x 4 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %NXV8I16 = call <vscale x 8 x i16> @llvm.masked.udiv.nxv8i16(<vscale x 8 x i16> poison, <vscale x 8 x i16> poison, <vscale x 8 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %NXV16I16 = call <vscale x 16 x i16> @llvm.masked.udiv.nxv16i16(<vscale x 16 x i16> poison, <vscale x 16 x i16> poison, <vscale x 16 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %NXV32I16 = call <vscale x 32 x i16> @llvm.masked.udiv.nxv32i16(<vscale x 32 x i16> poison, <vscale x 32 x i16> poison, <vscale x 32 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V1I32 = call <1 x i32> @llvm.masked.udiv.v1i32(<1 x i32> poison, <1 x i32> poison, <1 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V2I32 = call <2 x i32> @llvm.masked.udiv.v2i32(<2 x i32> poison, <2 x i32> poison, <2 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V4I32 = call <4 x i32> @llvm.masked.udiv.v4i32(<4 x i32> poison, <4 x i32> poison, <4 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V8I32 = call <8 x i32> @llvm.masked.udiv.v8i32(<8 x i32> poison, <8 x i32> poison, <8 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V16I32 = call <16 x i32> @llvm.masked.udiv.v16i32(<16 x i32> poison, <16 x i32> poison, <16 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NXV1I32 = call <vscale x 1 x i32> @llvm.masked.udiv.nxv1i32(<vscale x 1 x i32> poison, <vscale x 1 x i32> poison, <vscale x 1 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NXV2I32 = call <vscale x 2 x i32> @llvm.masked.udiv.nxv2i32(<vscale x 2 x i32> poison, <vscale x 2 x i32> poison, <vscale x 2 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %NXV4I32 = call <vscale x 4 x i32> @llvm.masked.udiv.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> poison, <vscale x 4 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %NXV8I32 = call <vscale x 8 x i32> @llvm.masked.udiv.nxv8i32(<vscale x 8 x i32> poison, <vscale x 8 x i32> poison, <vscale x 8 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %NXV16I32 = call <vscale x 16 x i32> @llvm.masked.udiv.nxv16i32(<vscale x 16 x i32> poison, <vscale x 16 x i32> poison, <vscale x 16 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V1I64 = call <1 x i64> @llvm.masked.udiv.v1i64(<1 x i64> poison, <1 x i64> poison, <1 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V2I64 = call <2 x i64> @llvm.masked.udiv.v2i64(<2 x i64> poison, <2 x i64> poison, <2 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V4I64 = call <4 x i64> @llvm.masked.udiv.v4i64(<4 x i64> poison, <4 x i64> poison, <4 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V8I64 = call <8 x i64> @llvm.masked.udiv.v8i64(<8 x i64> poison, <8 x i64> poison, <8 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NXV1I64 = call <vscale x 1 x i64> @llvm.masked.udiv.nxv1i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> poison, <vscale x 1 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %NXV2I64 = call <vscale x 2 x i64> @llvm.masked.udiv.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> poison, <vscale x 2 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %NXV4I64 = call <vscale x 4 x i64> @llvm.masked.udiv.nxv4i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> poison, <vscale x 4 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %NXV8I64 = call <vscale x 8 x i64> @llvm.masked.udiv.nxv8i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> poison, <vscale x 8 x i1> poison)
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
%V1I16 = call <1 x i16> @llvm.masked.udiv(<1 x i16> poison, <1 x i16> poison, <1 x i1> poison)
@@ -77,36 +77,36 @@ define void @udiv() {
define void @sdiv() {
; CHECK-LABEL: 'sdiv'
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %V1I16 = call <1 x i16> @llvm.masked.sdiv.v1i16(<1 x i16> poison, <1 x i16> poison, <1 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %V2I16 = call <2 x i16> @llvm.masked.sdiv.v2i16(<2 x i16> poison, <2 x i16> poison, <2 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %V4I16 = call <4 x i16> @llvm.masked.sdiv.v4i16(<4 x i16> poison, <4 x i16> poison, <4 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %V8I16 = call <8 x i16> @llvm.masked.sdiv.v8i16(<8 x i16> poison, <8 x i16> poison, <8 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:10 CodeSize:5 Lat:5 SizeLat:5 for: %V16I16 = call <16 x i16> @llvm.masked.sdiv.v16i16(<16 x i16> poison, <16 x i16> poison, <16 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:20 CodeSize:5 Lat:5 SizeLat:5 for: %V32I16 = call <32 x i16> @llvm.masked.sdiv.v32i16(<32 x i16> poison, <32 x i16> poison, <32 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %NXV1I16 = call <vscale x 1 x i16> @llvm.masked.sdiv.nxv1i16(<vscale x 1 x i16> poison, <vscale x 1 x i16> poison, <vscale x 1 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %NXV2I16 = call <vscale x 2 x i16> @llvm.masked.sdiv.nxv2i16(<vscale x 2 x i16> poison, <vscale x 2 x i16> poison, <vscale x 2 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %NXV4I16 = call <vscale x 4 x i16> @llvm.masked.sdiv.nxv4i16(<vscale x 4 x i16> poison, <vscale x 4 x i16> poison, <vscale x 4 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:10 CodeSize:5 Lat:5 SizeLat:5 for: %NXV8I16 = call <vscale x 8 x i16> @llvm.masked.sdiv.nxv8i16(<vscale x 8 x i16> poison, <vscale x 8 x i16> poison, <vscale x 8 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:20 CodeSize:5 Lat:5 SizeLat:5 for: %NXV16I16 = call <vscale x 16 x i16> @llvm.masked.sdiv.nxv16i16(<vscale x 16 x i16> poison, <vscale x 16 x i16> poison, <vscale x 16 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:40 CodeSize:5 Lat:5 SizeLat:5 for: %NXV32I16 = call <vscale x 32 x i16> @llvm.masked.sdiv.nxv32i16(<vscale x 32 x i16> poison, <vscale x 32 x i16> poison, <vscale x 32 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %V1I32 = call <1 x i32> @llvm.masked.sdiv.v1i32(<1 x i32> poison, <1 x i32> poison, <1 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %V2I32 = call <2 x i32> @llvm.masked.sdiv.v2i32(<2 x i32> poison, <2 x i32> poison, <2 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %V4I32 = call <4 x i32> @llvm.masked.sdiv.v4i32(<4 x i32> poison, <4 x i32> poison, <4 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:10 CodeSize:5 Lat:5 SizeLat:5 for: %V8I32 = call <8 x i32> @llvm.masked.sdiv.v8i32(<8 x i32> poison, <8 x i32> poison, <8 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:20 CodeSize:5 Lat:5 SizeLat:5 for: %V16I32 = call <16 x i32> @llvm.masked.sdiv.v16i32(<16 x i32> poison, <16 x i32> poison, <16 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %NXV1I32 = call <vscale x 1 x i32> @llvm.masked.sdiv.nxv1i32(<vscale x 1 x i32> poison, <vscale x 1 x i32> poison, <vscale x 1 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %NXV2I32 = call <vscale x 2 x i32> @llvm.masked.sdiv.nxv2i32(<vscale x 2 x i32> poison, <vscale x 2 x i32> poison, <vscale x 2 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:10 CodeSize:5 Lat:5 SizeLat:5 for: %NXV4I32 = call <vscale x 4 x i32> @llvm.masked.sdiv.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> poison, <vscale x 4 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:20 CodeSize:5 Lat:5 SizeLat:5 for: %NXV8I32 = call <vscale x 8 x i32> @llvm.masked.sdiv.nxv8i32(<vscale x 8 x i32> poison, <vscale x 8 x i32> poison, <vscale x 8 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:40 CodeSize:5 Lat:5 SizeLat:5 for: %NXV16I32 = call <vscale x 16 x i32> @llvm.masked.sdiv.nxv16i32(<vscale x 16 x i32> poison, <vscale x 16 x i32> poison, <vscale x 16 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %V1I64 = call <1 x i64> @llvm.masked.sdiv.v1i64(<1 x i64> poison, <1 x i64> poison, <1 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %V2I64 = call <2 x i64> @llvm.masked.sdiv.v2i64(<2 x i64> poison, <2 x i64> poison, <2 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:10 CodeSize:5 Lat:5 SizeLat:5 for: %V4I64 = call <4 x i64> @llvm.masked.sdiv.v4i64(<4 x i64> poison, <4 x i64> poison, <4 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:20 CodeSize:5 Lat:5 SizeLat:5 for: %V8I64 = call <8 x i64> @llvm.masked.sdiv.v8i64(<8 x i64> poison, <8 x i64> poison, <8 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %NXV1I64 = call <vscale x 1 x i64> @llvm.masked.sdiv.nxv1i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> poison, <vscale x 1 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:10 CodeSize:5 Lat:5 SizeLat:5 for: %NXV2I64 = call <vscale x 2 x i64> @llvm.masked.sdiv.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> poison, <vscale x 2 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:20 CodeSize:5 Lat:5 SizeLat:5 for: %NXV4I64 = call <vscale x 4 x i64> @llvm.masked.sdiv.nxv4i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> poison, <vscale x 4 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:40 CodeSize:5 Lat:5 SizeLat:5 for: %NXV8I64 = call <vscale x 8 x i64> @llvm.masked.sdiv.nxv8i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> poison, <vscale x 8 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V1I16 = call <1 x i16> @llvm.masked.sdiv.v1i16(<1 x i16> poison, <1 x i16> poison, <1 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V2I16 = call <2 x i16> @llvm.masked.sdiv.v2i16(<2 x i16> poison, <2 x i16> poison, <2 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V4I16 = call <4 x i16> @llvm.masked.sdiv.v4i16(<4 x i16> poison, <4 x i16> poison, <4 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V8I16 = call <8 x i16> @llvm.masked.sdiv.v8i16(<8 x i16> poison, <8 x i16> poison, <8 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V16I16 = call <16 x i16> @llvm.masked.sdiv.v16i16(<16 x i16> poison, <16 x i16> poison, <16 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V32I16 = call <32 x i16> @llvm.masked.sdiv.v32i16(<32 x i16> poison, <32 x i16> poison, <32 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NXV1I16 = call <vscale x 1 x i16> @llvm.masked.sdiv.nxv1i16(<vscale x 1 x i16> poison, <vscale x 1 x i16> poison, <vscale x 1 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NXV2I16 = call <vscale x 2 x i16> @llvm.masked.sdiv.nxv2i16(<vscale x 2 x i16> poison, <vscale x 2 x i16> poison, <vscale x 2 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NXV4I16 = call <vscale x 4 x i16> @llvm.masked.sdiv.nxv4i16(<vscale x 4 x i16> poison, <vscale x 4 x i16> poison, <vscale x 4 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %NXV8I16 = call <vscale x 8 x i16> @llvm.masked.sdiv.nxv8i16(<vscale x 8 x i16> poison, <vscale x 8 x i16> poison, <vscale x 8 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %NXV16I16 = call <vscale x 16 x i16> @llvm.masked.sdiv.nxv16i16(<vscale x 16 x i16> poison, <vscale x 16 x i16> poison, <vscale x 16 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %NXV32I16 = call <vscale x 32 x i16> @llvm.masked.sdiv.nxv32i16(<vscale x 32 x i16> poison, <vscale x 32 x i16> poison, <vscale x 32 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V1I32 = call <1 x i32> @llvm.masked.sdiv.v1i32(<1 x i32> poison, <1 x i32> poison, <1 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V2I32 = call <2 x i32> @llvm.masked.sdiv.v2i32(<2 x i32> poison, <2 x i32> poison, <2 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V4I32 = call <4 x i32> @llvm.masked.sdiv.v4i32(<4 x i32> poison, <4 x i32> poison, <4 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V8I32 = call <8 x i32> @llvm.masked.sdiv.v8i32(<8 x i32> poison, <8 x i32> poison, <8 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V16I32 = call <16 x i32> @llvm.masked.sdiv.v16i32(<16 x i32> poison, <16 x i32> poison, <16 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NXV1I32 = call <vscale x 1 x i32> @llvm.masked.sdiv.nxv1i32(<vscale x 1 x i32> poison, <vscale x 1 x i32> poison, <vscale x 1 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NXV2I32 = call <vscale x 2 x i32> @llvm.masked.sdiv.nxv2i32(<vscale x 2 x i32> poison, <vscale x 2 x i32> poison, <vscale x 2 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %NXV4I32 = call <vscale x 4 x i32> @llvm.masked.sdiv.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> poison, <vscale x 4 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %NXV8I32 = call <vscale x 8 x i32> @llvm.masked.sdiv.nxv8i32(<vscale x 8 x i32> poison, <vscale x 8 x i32> poison, <vscale x 8 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %NXV16I32 = call <vscale x 16 x i32> @llvm.masked.sdiv.nxv16i32(<vscale x 16 x i32> poison, <vscale x 16 x i32> poison, <vscale x 16 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V1I64 = call <1 x i64> @llvm.masked.sdiv.v1i64(<1 x i64> poison, <1 x i64> poison, <1 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V2I64 = call <2 x i64> @llvm.masked.sdiv.v2i64(<2 x i64> poison, <2 x i64> poison, <2 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V4I64 = call <4 x i64> @llvm.masked.sdiv.v4i64(<4 x i64> poison, <4 x i64> poison, <4 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V8I64 = call <8 x i64> @llvm.masked.sdiv.v8i64(<8 x i64> poison, <8 x i64> poison, <8 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NXV1I64 = call <vscale x 1 x i64> @llvm.masked.sdiv.nxv1i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> poison, <vscale x 1 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %NXV2I64 = call <vscale x 2 x i64> @llvm.masked.sdiv.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> poison, <vscale x 2 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %NXV4I64 = call <vscale x 4 x i64> @llvm.masked.sdiv.nxv4i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> poison, <vscale x 4 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %NXV8I64 = call <vscale x 8 x i64> @llvm.masked.sdiv.nxv8i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> poison, <vscale x 8 x i1> poison)
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
%V1I16 = call <1 x i16> @llvm.masked.sdiv(<1 x i16> poison, <1 x i16> poison, <1 x i1> poison)
@@ -150,36 +150,36 @@ define void @sdiv() {
define void @urem() {
; CHECK-LABEL: 'urem'
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %V1I16 = call <1 x i16> @llvm.masked.urem.v1i16(<1 x i16> poison, <1 x i16> poison, <1 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %V2I16 = call <2 x i16> @llvm.masked.urem.v2i16(<2 x i16> poison, <2 x i16> poison, <2 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %V4I16 = call <4 x i16> @llvm.masked.urem.v4i16(<4 x i16> poison, <4 x i16> poison, <4 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %V8I16 = call <8 x i16> @llvm.masked.urem.v8i16(<8 x i16> poison, <8 x i16> poison, <8 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:10 CodeSize:5 Lat:5 SizeLat:5 for: %V16I16 = call <16 x i16> @llvm.masked.urem.v16i16(<16 x i16> poison, <16 x i16> poison, <16 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:20 CodeSize:5 Lat:5 SizeLat:5 for: %V32I16 = call <32 x i16> @llvm.masked.urem.v32i16(<32 x i16> poison, <32 x i16> poison, <32 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %NXV1I16 = call <vscale x 1 x i16> @llvm.masked.urem.nxv1i16(<vscale x 1 x i16> poison, <vscale x 1 x i16> poison, <vscale x 1 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %NXV2I16 = call <vscale x 2 x i16> @llvm.masked.urem.nxv2i16(<vscale x 2 x i16> poison, <vscale x 2 x i16> poison, <vscale x 2 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %NXV4I16 = call <vscale x 4 x i16> @llvm.masked.urem.nxv4i16(<vscale x 4 x i16> poison, <vscale x 4 x i16> poison, <vscale x 4 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:10 CodeSize:5 Lat:5 SizeLat:5 for: %NXV8I16 = call <vscale x 8 x i16> @llvm.masked.urem.nxv8i16(<vscale x 8 x i16> poison, <vscale x 8 x i16> poison, <vscale x 8 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:20 CodeSize:5 Lat:5 SizeLat:5 for: %NXV16I16 = call <vscale x 16 x i16> @llvm.masked.urem.nxv16i16(<vscale x 16 x i16> poison, <vscale x 16 x i16> poison, <vscale x 16 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:40 CodeSize:5 Lat:5 SizeLat:5 for: %NXV32I16 = call <vscale x 32 x i16> @llvm.masked.urem.nxv32i16(<vscale x 32 x i16> poison, <vscale x 32 x i16> poison, <vscale x 32 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %V1I32 = call <1 x i32> @llvm.masked.urem.v1i32(<1 x i32> poison, <1 x i32> poison, <1 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %V2I32 = call <2 x i32> @llvm.masked.urem.v2i32(<2 x i32> poison, <2 x i32> poison, <2 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %V4I32 = call <4 x i32> @llvm.masked.urem.v4i32(<4 x i32> poison, <4 x i32> poison, <4 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:10 CodeSize:5 Lat:5 SizeLat:5 for: %V8I32 = call <8 x i32> @llvm.masked.urem.v8i32(<8 x i32> poison, <8 x i32> poison, <8 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:20 CodeSize:5 Lat:5 SizeLat:5 for: %V16I32 = call <16 x i32> @llvm.masked.urem.v16i32(<16 x i32> poison, <16 x i32> poison, <16 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %NXV1I32 = call <vscale x 1 x i32> @llvm.masked.urem.nxv1i32(<vscale x 1 x i32> poison, <vscale x 1 x i32> poison, <vscale x 1 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %NXV2I32 = call <vscale x 2 x i32> @llvm.masked.urem.nxv2i32(<vscale x 2 x i32> poison, <vscale x 2 x i32> poison, <vscale x 2 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:10 CodeSize:5 Lat:5 SizeLat:5 for: %NXV4I32 = call <vscale x 4 x i32> @llvm.masked.urem.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> poison, <vscale x 4 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:20 CodeSize:5 Lat:5 SizeLat:5 for: %NXV8I32 = call <vscale x 8 x i32> @llvm.masked.urem.nxv8i32(<vscale x 8 x i32> poison, <vscale x 8 x i32> poison, <vscale x 8 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:40 CodeSize:5 Lat:5 SizeLat:5 for: %NXV16I32 = call <vscale x 16 x i32> @llvm.masked.urem.nxv16i32(<vscale x 16 x i32> poison, <vscale x 16 x i32> poison, <vscale x 16 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %V1I64 = call <1 x i64> @llvm.masked.urem.v1i64(<1 x i64> poison, <1 x i64> poison, <1 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %V2I64 = call <2 x i64> @llvm.masked.urem.v2i64(<2 x i64> poison, <2 x i64> poison, <2 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:10 CodeSize:5 Lat:5 SizeLat:5 for: %V4I64 = call <4 x i64> @llvm.masked.urem.v4i64(<4 x i64> poison, <4 x i64> poison, <4 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:20 CodeSize:5 Lat:5 SizeLat:5 for: %V8I64 = call <8 x i64> @llvm.masked.urem.v8i64(<8 x i64> poison, <8 x i64> poison, <8 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %NXV1I64 = call <vscale x 1 x i64> @llvm.masked.urem.nxv1i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> poison, <vscale x 1 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:10 CodeSize:5 Lat:5 SizeLat:5 for: %NXV2I64 = call <vscale x 2 x i64> @llvm.masked.urem.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> poison, <vscale x 2 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:20 CodeSize:5 Lat:5 SizeLat:5 for: %NXV4I64 = call <vscale x 4 x i64> @llvm.masked.urem.nxv4i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> poison, <vscale x 4 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:40 CodeSize:5 Lat:5 SizeLat:5 for: %NXV8I64 = call <vscale x 8 x i64> @llvm.masked.urem.nxv8i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> poison, <vscale x 8 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V1I16 = call <1 x i16> @llvm.masked.urem.v1i16(<1 x i16> poison, <1 x i16> poison, <1 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V2I16 = call <2 x i16> @llvm.masked.urem.v2i16(<2 x i16> poison, <2 x i16> poison, <2 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V4I16 = call <4 x i16> @llvm.masked.urem.v4i16(<4 x i16> poison, <4 x i16> poison, <4 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V8I16 = call <8 x i16> @llvm.masked.urem.v8i16(<8 x i16> poison, <8 x i16> poison, <8 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V16I16 = call <16 x i16> @llvm.masked.urem.v16i16(<16 x i16> poison, <16 x i16> poison, <16 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V32I16 = call <32 x i16> @llvm.masked.urem.v32i16(<32 x i16> poison, <32 x i16> poison, <32 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NXV1I16 = call <vscale x 1 x i16> @llvm.masked.urem.nxv1i16(<vscale x 1 x i16> poison, <vscale x 1 x i16> poison, <vscale x 1 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NXV2I16 = call <vscale x 2 x i16> @llvm.masked.urem.nxv2i16(<vscale x 2 x i16> poison, <vscale x 2 x i16> poison, <vscale x 2 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NXV4I16 = call <vscale x 4 x i16> @llvm.masked.urem.nxv4i16(<vscale x 4 x i16> poison, <vscale x 4 x i16> poison, <vscale x 4 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %NXV8I16 = call <vscale x 8 x i16> @llvm.masked.urem.nxv8i16(<vscale x 8 x i16> poison, <vscale x 8 x i16> poison, <vscale x 8 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %NXV16I16 = call <vscale x 16 x i16> @llvm.masked.urem.nxv16i16(<vscale x 16 x i16> poison, <vscale x 16 x i16> poison, <vscale x 16 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %NXV32I16 = call <vscale x 32 x i16> @llvm.masked.urem.nxv32i16(<vscale x 32 x i16> poison, <vscale x 32 x i16> poison, <vscale x 32 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V1I32 = call <1 x i32> @llvm.masked.urem.v1i32(<1 x i32> poison, <1 x i32> poison, <1 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V2I32 = call <2 x i32> @llvm.masked.urem.v2i32(<2 x i32> poison, <2 x i32> poison, <2 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V4I32 = call <4 x i32> @llvm.masked.urem.v4i32(<4 x i32> poison, <4 x i32> poison, <4 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V8I32 = call <8 x i32> @llvm.masked.urem.v8i32(<8 x i32> poison, <8 x i32> poison, <8 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V16I32 = call <16 x i32> @llvm.masked.urem.v16i32(<16 x i32> poison, <16 x i32> poison, <16 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NXV1I32 = call <vscale x 1 x i32> @llvm.masked.urem.nxv1i32(<vscale x 1 x i32> poison, <vscale x 1 x i32> poison, <vscale x 1 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NXV2I32 = call <vscale x 2 x i32> @llvm.masked.urem.nxv2i32(<vscale x 2 x i32> poison, <vscale x 2 x i32> poison, <vscale x 2 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %NXV4I32 = call <vscale x 4 x i32> @llvm.masked.urem.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> poison, <vscale x 4 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %NXV8I32 = call <vscale x 8 x i32> @llvm.masked.urem.nxv8i32(<vscale x 8 x i32> poison, <vscale x 8 x i32> poison, <vscale x 8 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %NXV16I32 = call <vscale x 16 x i32> @llvm.masked.urem.nxv16i32(<vscale x 16 x i32> poison, <vscale x 16 x i32> poison, <vscale x 16 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V1I64 = call <1 x i64> @llvm.masked.urem.v1i64(<1 x i64> poison, <1 x i64> poison, <1 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V2I64 = call <2 x i64> @llvm.masked.urem.v2i64(<2 x i64> poison, <2 x i64> poison, <2 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V4I64 = call <4 x i64> @llvm.masked.urem.v4i64(<4 x i64> poison, <4 x i64> poison, <4 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V8I64 = call <8 x i64> @llvm.masked.urem.v8i64(<8 x i64> poison, <8 x i64> poison, <8 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NXV1I64 = call <vscale x 1 x i64> @llvm.masked.urem.nxv1i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> poison, <vscale x 1 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %NXV2I64 = call <vscale x 2 x i64> @llvm.masked.urem.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> poison, <vscale x 2 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %NXV4I64 = call <vscale x 4 x i64> @llvm.masked.urem.nxv4i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> poison, <vscale x 4 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %NXV8I64 = call <vscale x 8 x i64> @llvm.masked.urem.nxv8i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> poison, <vscale x 8 x i1> poison)
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
%V1I16 = call <1 x i16> @llvm.masked.urem(<1 x i16> poison, <1 x i16> poison, <1 x i1> poison)
@@ -223,36 +223,36 @@ define void @urem() {
define void @srem() {
; CHECK-LABEL: 'srem'
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %V1I16 = call <1 x i16> @llvm.masked.srem.v1i16(<1 x i16> poison, <1 x i16> poison, <1 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %V2I16 = call <2 x i16> @llvm.masked.srem.v2i16(<2 x i16> poison, <2 x i16> poison, <2 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %V4I16 = call <4 x i16> @llvm.masked.srem.v4i16(<4 x i16> poison, <4 x i16> poison, <4 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %V8I16 = call <8 x i16> @llvm.masked.srem.v8i16(<8 x i16> poison, <8 x i16> poison, <8 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:10 CodeSize:5 Lat:5 SizeLat:5 for: %V16I16 = call <16 x i16> @llvm.masked.srem.v16i16(<16 x i16> poison, <16 x i16> poison, <16 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:20 CodeSize:5 Lat:5 SizeLat:5 for: %V32I16 = call <32 x i16> @llvm.masked.srem.v32i16(<32 x i16> poison, <32 x i16> poison, <32 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %NXV1I16 = call <vscale x 1 x i16> @llvm.masked.srem.nxv1i16(<vscale x 1 x i16> poison, <vscale x 1 x i16> poison, <vscale x 1 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %NXV2I16 = call <vscale x 2 x i16> @llvm.masked.srem.nxv2i16(<vscale x 2 x i16> poison, <vscale x 2 x i16> poison, <vscale x 2 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %NXV4I16 = call <vscale x 4 x i16> @llvm.masked.srem.nxv4i16(<vscale x 4 x i16> poison, <vscale x 4 x i16> poison, <vscale x 4 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:10 CodeSize:5 Lat:5 SizeLat:5 for: %NXV8I16 = call <vscale x 8 x i16> @llvm.masked.srem.nxv8i16(<vscale x 8 x i16> poison, <vscale x 8 x i16> poison, <vscale x 8 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:20 CodeSize:5 Lat:5 SizeLat:5 for: %NXV16I16 = call <vscale x 16 x i16> @llvm.masked.srem.nxv16i16(<vscale x 16 x i16> poison, <vscale x 16 x i16> poison, <vscale x 16 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:40 CodeSize:5 Lat:5 SizeLat:5 for: %NXV32I16 = call <vscale x 32 x i16> @llvm.masked.srem.nxv32i16(<vscale x 32 x i16> poison, <vscale x 32 x i16> poison, <vscale x 32 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %V1I32 = call <1 x i32> @llvm.masked.srem.v1i32(<1 x i32> poison, <1 x i32> poison, <1 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %V2I32 = call <2 x i32> @llvm.masked.srem.v2i32(<2 x i32> poison, <2 x i32> poison, <2 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %V4I32 = call <4 x i32> @llvm.masked.srem.v4i32(<4 x i32> poison, <4 x i32> poison, <4 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:10 CodeSize:5 Lat:5 SizeLat:5 for: %V8I32 = call <8 x i32> @llvm.masked.srem.v8i32(<8 x i32> poison, <8 x i32> poison, <8 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:20 CodeSize:5 Lat:5 SizeLat:5 for: %V16I32 = call <16 x i32> @llvm.masked.srem.v16i32(<16 x i32> poison, <16 x i32> poison, <16 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %NXV1I32 = call <vscale x 1 x i32> @llvm.masked.srem.nxv1i32(<vscale x 1 x i32> poison, <vscale x 1 x i32> poison, <vscale x 1 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %NXV2I32 = call <vscale x 2 x i32> @llvm.masked.srem.nxv2i32(<vscale x 2 x i32> poison, <vscale x 2 x i32> poison, <vscale x 2 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:10 CodeSize:5 Lat:5 SizeLat:5 for: %NXV4I32 = call <vscale x 4 x i32> @llvm.masked.srem.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> poison, <vscale x 4 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:20 CodeSize:5 Lat:5 SizeLat:5 for: %NXV8I32 = call <vscale x 8 x i32> @llvm.masked.srem.nxv8i32(<vscale x 8 x i32> poison, <vscale x 8 x i32> poison, <vscale x 8 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:40 CodeSize:5 Lat:5 SizeLat:5 for: %NXV16I32 = call <vscale x 16 x i32> @llvm.masked.srem.nxv16i32(<vscale x 16 x i32> poison, <vscale x 16 x i32> poison, <vscale x 16 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %V1I64 = call <1 x i64> @llvm.masked.srem.v1i64(<1 x i64> poison, <1 x i64> poison, <1 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %V2I64 = call <2 x i64> @llvm.masked.srem.v2i64(<2 x i64> poison, <2 x i64> poison, <2 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:10 CodeSize:5 Lat:5 SizeLat:5 for: %V4I64 = call <4 x i64> @llvm.masked.srem.v4i64(<4 x i64> poison, <4 x i64> poison, <4 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:20 CodeSize:5 Lat:5 SizeLat:5 for: %V8I64 = call <8 x i64> @llvm.masked.srem.v8i64(<8 x i64> poison, <8 x i64> poison, <8 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of 5 for: %NXV1I64 = call <vscale x 1 x i64> @llvm.masked.srem.nxv1i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> poison, <vscale x 1 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:10 CodeSize:5 Lat:5 SizeLat:5 for: %NXV2I64 = call <vscale x 2 x i64> @llvm.masked.srem.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> poison, <vscale x 2 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:20 CodeSize:5 Lat:5 SizeLat:5 for: %NXV4I64 = call <vscale x 4 x i64> @llvm.masked.srem.nxv4i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> poison, <vscale x 4 x i1> poison)
-; CHECK-NEXT: Cost Model: Found costs of RThru:40 CodeSize:5 Lat:5 SizeLat:5 for: %NXV8I64 = call <vscale x 8 x i64> @llvm.masked.srem.nxv8i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> poison, <vscale x 8 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V1I16 = call <1 x i16> @llvm.masked.srem.v1i16(<1 x i16> poison, <1 x i16> poison, <1 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V2I16 = call <2 x i16> @llvm.masked.srem.v2i16(<2 x i16> poison, <2 x i16> poison, <2 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V4I16 = call <4 x i16> @llvm.masked.srem.v4i16(<4 x i16> poison, <4 x i16> poison, <4 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V8I16 = call <8 x i16> @llvm.masked.srem.v8i16(<8 x i16> poison, <8 x i16> poison, <8 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V16I16 = call <16 x i16> @llvm.masked.srem.v16i16(<16 x i16> poison, <16 x i16> poison, <16 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V32I16 = call <32 x i16> @llvm.masked.srem.v32i16(<32 x i16> poison, <32 x i16> poison, <32 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NXV1I16 = call <vscale x 1 x i16> @llvm.masked.srem.nxv1i16(<vscale x 1 x i16> poison, <vscale x 1 x i16> poison, <vscale x 1 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NXV2I16 = call <vscale x 2 x i16> @llvm.masked.srem.nxv2i16(<vscale x 2 x i16> poison, <vscale x 2 x i16> poison, <vscale x 2 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NXV4I16 = call <vscale x 4 x i16> @llvm.masked.srem.nxv4i16(<vscale x 4 x i16> poison, <vscale x 4 x i16> poison, <vscale x 4 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %NXV8I16 = call <vscale x 8 x i16> @llvm.masked.srem.nxv8i16(<vscale x 8 x i16> poison, <vscale x 8 x i16> poison, <vscale x 8 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %NXV16I16 = call <vscale x 16 x i16> @llvm.masked.srem.nxv16i16(<vscale x 16 x i16> poison, <vscale x 16 x i16> poison, <vscale x 16 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %NXV32I16 = call <vscale x 32 x i16> @llvm.masked.srem.nxv32i16(<vscale x 32 x i16> poison, <vscale x 32 x i16> poison, <vscale x 32 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V1I32 = call <1 x i32> @llvm.masked.srem.v1i32(<1 x i32> poison, <1 x i32> poison, <1 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V2I32 = call <2 x i32> @llvm.masked.srem.v2i32(<2 x i32> poison, <2 x i32> poison, <2 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V4I32 = call <4 x i32> @llvm.masked.srem.v4i32(<4 x i32> poison, <4 x i32> poison, <4 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V8I32 = call <8 x i32> @llvm.masked.srem.v8i32(<8 x i32> poison, <8 x i32> poison, <8 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V16I32 = call <16 x i32> @llvm.masked.srem.v16i32(<16 x i32> poison, <16 x i32> poison, <16 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NXV1I32 = call <vscale x 1 x i32> @llvm.masked.srem.nxv1i32(<vscale x 1 x i32> poison, <vscale x 1 x i32> poison, <vscale x 1 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NXV2I32 = call <vscale x 2 x i32> @llvm.masked.srem.nxv2i32(<vscale x 2 x i32> poison, <vscale x 2 x i32> poison, <vscale x 2 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %NXV4I32 = call <vscale x 4 x i32> @llvm.masked.srem.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> poison, <vscale x 4 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %NXV8I32 = call <vscale x 8 x i32> @llvm.masked.srem.nxv8i32(<vscale x 8 x i32> poison, <vscale x 8 x i32> poison, <vscale x 8 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %NXV16I32 = call <vscale x 16 x i32> @llvm.masked.srem.nxv16i32(<vscale x 16 x i32> poison, <vscale x 16 x i32> poison, <vscale x 16 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V1I64 = call <1 x i64> @llvm.masked.srem.v1i64(<1 x i64> poison, <1 x i64> poison, <1 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %V2I64 = call <2 x i64> @llvm.masked.srem.v2i64(<2 x i64> poison, <2 x i64> poison, <2 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %V4I64 = call <4 x i64> @llvm.masked.srem.v4i64(<4 x i64> poison, <4 x i64> poison, <4 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %V8I64 = call <8 x i64> @llvm.masked.srem.v8i64(<8 x i64> poison, <8 x i64> poison, <8 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of 4 for: %NXV1I64 = call <vscale x 1 x i64> @llvm.masked.srem.nxv1i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> poison, <vscale x 1 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:4 SizeLat:4 for: %NXV2I64 = call <vscale x 2 x i64> @llvm.masked.srem.nxv2i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> poison, <vscale x 2 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:16 CodeSize:4 Lat:4 SizeLat:4 for: %NXV4I64 = call <vscale x 4 x i64> @llvm.masked.srem.nxv4i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> poison, <vscale x 4 x i1> poison)
+; CHECK-NEXT: Cost Model: Found costs of RThru:32 CodeSize:4 Lat:4 SizeLat:4 for: %NXV8I64 = call <vscale x 8 x i64> @llvm.masked.srem.nxv8i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> poison, <vscale x 8 x i1> poison)
; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
%V1I16 = call <1 x i16> @llvm.masked.srem(<1 x i16> poison, <1 x i16> poison, <1 x i1> poison)
diff --git a/llvm/test/CodeGen/RISCV/rvv/masked-sdiv.ll b/llvm/test/CodeGen/RISCV/rvv/masked-sdiv.ll
index a08dd50a39a38..1638d026a01f8 100644
--- a/llvm/test/CodeGen/RISCV/rvv/masked-sdiv.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/masked-sdiv.ll
@@ -5,9 +5,7 @@ define <vscale x 8 x i8> @sdiv_nxv8i8(<vscale x 8 x i8> %x, <vscale x 8 x i8> %y
; CHECK-LABEL: sdiv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 1
-; CHECK-NEXT: vmerge.vvm v9, v10, v9, v0
-; CHECK-NEXT: vdiv.vv v8, v8, v9
+; CHECK-NEXT: vdiv.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 8 x i8> @llvm.masked.sdiv(<vscale x 8 x i8> %x, <vscale x 8 x i8> %y, <vscale x 8 x i1> %m)
ret <vscale x 8 x i8> %res
@@ -17,9 +15,7 @@ define <vscale x 4 x i16> @sdiv_nxv4i16(<vscale x 4 x i16> %x, <vscale x 4 x i16
; CHECK-LABEL: sdiv_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 1
-; CHECK-NEXT: vmerge.vvm v9, v10, v9, v0
-; CHECK-NEXT: vdiv.vv v8, v8, v9
+; CHECK-NEXT: vdiv.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 4 x i16> @llvm.masked.sdiv(<vscale x 4 x i16> %x, <vscale x 4 x i16> %y, <vscale x 4 x i1> %m)
ret <vscale x 4 x i16> %res
@@ -29,9 +25,7 @@ define <vscale x 4 x i32> @sdiv_nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32
; CHECK-LABEL: sdiv_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 1
-; CHECK-NEXT: vmerge.vvm v10, v12, v10, v0
-; CHECK-NEXT: vdiv.vv v8, v8, v10
+; CHECK-NEXT: vdiv.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 4 x i32> @llvm.masked.sdiv(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i1> %m)
ret <vscale x 4 x i32> %res
@@ -41,9 +35,7 @@ define <vscale x 8 x i32> @sdiv_nxv8i32(<vscale x 8 x i32> %x, <vscale x 8 x i32
; CHECK-LABEL: sdiv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v16, 1
-; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
-; CHECK-NEXT: vdiv.vv v8, v8, v12
+; CHECK-NEXT: vdiv.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 8 x i32> @llvm.masked.sdiv(<vscale x 8 x i32> %x, <vscale x 8 x i32> %y, <vscale x 8 x i1> %m)
ret <vscale x 8 x i32> %res
@@ -53,9 +45,7 @@ define <vscale x 8 x i32> @sdiv_nxv8i32_splat_rhs(<vscale x 8 x i32> %x, i32 %y,
; CHECK-LABEL: sdiv_nxv8i32_splat_rhs:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 1
-; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
-; CHECK-NEXT: vdiv.vv v8, v8, v12
+; CHECK-NEXT: vdiv.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %y, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
@@ -67,9 +57,7 @@ define <vscale x 8 x i16> @sdiv_nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16
; CHECK-LABEL: sdiv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 1
-; CHECK-NEXT: vmerge.vvm v10, v12, v10, v0
-; CHECK-NEXT: vdiv.vv v8, v8, v10
+; CHECK-NEXT: vdiv.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 8 x i16> @llvm.masked.sdiv(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i1> %m)
ret <vscale x 8 x i16> %res
@@ -79,9 +67,7 @@ define <vscale x 2 x i64> @sdiv_nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64
; CHECK-LABEL: sdiv_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 1
-; CHECK-NEXT: vmerge.vvm v10, v12, v10, v0
-; CHECK-NEXT: vdiv.vv v8, v8, v10
+; CHECK-NEXT: vdiv.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 2 x i64> @llvm.masked.sdiv(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i1> %m)
ret <vscale x 2 x i64> %res
@@ -91,9 +77,7 @@ define <4 x i32> @sdiv_v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i1> %m) {
; CHECK-LABEL: sdiv_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 1
-; CHECK-NEXT: vmerge.vvm v9, v10, v9, v0
-; CHECK-NEXT: vdiv.vv v8, v8, v9
+; CHECK-NEXT: vdiv.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <4 x i32> @llvm.masked.sdiv(<4 x i32> %x, <4 x i32> %y, <4 x i1> %m)
ret <4 x i32> %res
@@ -103,9 +87,7 @@ define <2 x i64> @sdiv_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i1> %m) {
; CHECK-LABEL: sdiv_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 1
-; CHECK-NEXT: vmerge.vvm v9, v10, v9, v0
-; CHECK-NEXT: vdiv.vv v8, v8, v9
+; CHECK-NEXT: vdiv.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <2 x i64> @llvm.masked.sdiv(<2 x i64> %x, <2 x i64> %y, <2 x i1> %m)
ret <2 x i64> %res
@@ -115,9 +97,7 @@ define <4 x i64> @sdiv_v4i64(<4 x i64> %x, <4 x i64> %y, <4 x i1> %m) {
; CHECK-LABEL: sdiv_v4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 1
-; CHECK-NEXT: vmerge.vvm v10, v12, v10, v0
-; CHECK-NEXT: vdiv.vv v8, v8, v10
+; CHECK-NEXT: vdiv.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%res = call <4 x i64> @llvm.masked.sdiv(<4 x i64> %x, <4 x i64> %y, <4 x i1> %m)
ret <4 x i64> %res
@@ -127,9 +107,7 @@ define <2 x i32> @sdiv_v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i1> %m) {
; CHECK-LABEL: sdiv_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 1
-; CHECK-NEXT: vmerge.vvm v9, v10, v9, v0
-; CHECK-NEXT: vdiv.vv v8, v8, v9
+; CHECK-NEXT: vdiv.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <2 x i32> @llvm.masked.sdiv(<2 x i32> %x, <2 x i32> %y, <2 x i1> %m)
ret <2 x i32> %res
@@ -139,9 +117,7 @@ define <4 x i16> @sdiv_v4i16(<4 x i16> %x, <4 x i16> %y, <4 x i1> %m) {
; CHECK-LABEL: sdiv_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 1
-; CHECK-NEXT: vmerge.vvm v9, v10, v9, v0
-; CHECK-NEXT: vdiv.vv v8, v8, v9
+; CHECK-NEXT: vdiv.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <4 x i16> @llvm.masked.sdiv(<4 x i16> %x, <4 x i16> %y, <4 x i1> %m)
ret <4 x i16> %res
@@ -151,9 +127,7 @@ define <1 x i64> @sdiv_v1i64(<1 x i64> %x, <1 x i64> %y, <1 x i1> %m) {
; CHECK-LABEL: sdiv_v1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 1
-; CHECK-NEXT: vmerge.vvm v9, v10, v9, v0
-; CHECK-NEXT: vdiv.vv v8, v8, v9
+; CHECK-NEXT: vdiv.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <1 x i64> @llvm.masked.sdiv(<1 x i64> %x, <1 x i64> %y, <1 x i1> %m)
ret <1 x i64> %res
@@ -242,29 +216,28 @@ define <2 x i128> @sdiv_v2i128(<2 x i128> %x, <2 x i128> %y, <2 x i1> %m) nounwi
define <3 x i10> @sdiv_v3i10(<3 x i10> %x, <3 x i10> %y, <3 x i1> %m) {
; CHECK-LABEL: sdiv_v3i10:
; CHECK: # %bb.0:
+; CHECK-NEXT: ld a3, 0(a2)
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 7
+; CHECK-NEXT: ld a4, 8(a2)
+; CHECK-NEXT: ld a2, 16(a2)
+; CHECK-NEXT: vmv.v.x v9, a3
; CHECK-NEXT: ld a3, 0(a1)
-; CHECK-NEXT: ld a4, 8(a1)
+; CHECK-NEXT: ld a5, 8(a1)
; CHECK-NEXT: ld a1, 16(a1)
-; CHECK-NEXT: ld a5, 0(a2)
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
+; CHECK-NEXT: vmand.mm v0, v0, v8
; CHECK-NEXT: vmv.v.x v8, a3
-; CHECK-NEXT: ld a3, 8(a2)
-; CHECK-NEXT: ld a2, 16(a2)
-; CHECK-NEXT: vmv.v.x v9, a5
-; CHECK-NEXT: vmv.v.i v10, 7
-; CHECK-NEXT: vmand.mm v0, v0, v10
-; CHECK-NEXT: vmv.v.i v10, 1
-; CHECK-NEXT: vslide1down.vx v8, v8, a4
-; CHECK-NEXT: vslide1down.vx v9, v9, a3
-; CHECK-NEXT: vslide1down.vx v8, v8, a1
+; CHECK-NEXT: vslide1down.vx v9, v9, a4
+; CHECK-NEXT: vslide1down.vx v8, v8, a5
; CHECK-NEXT: vslide1down.vx v9, v9, a2
-; CHECK-NEXT: vslidedown.vi v8, v8, 1
+; CHECK-NEXT: vslide1down.vx v8, v8, a1
; CHECK-NEXT: vslidedown.vi v9, v9, 1
-; CHECK-NEXT: vsll.vi v8, v8, 6
+; CHECK-NEXT: vslidedown.vi v8, v8, 1
; CHECK-NEXT: vsll.vi v9, v9, 6
+; CHECK-NEXT: vsll.vi v8, v8, 6
+; CHECK-NEXT: vsra.vi v9, v9, 6
; CHECK-NEXT: vsra.vi v8, v8, 6
-; CHECK-NEXT: vsra.vi v10, v9, 6, v0.t
-; CHECK-NEXT: vdiv.vv v8, v8, v10
+; CHECK-NEXT: vdiv.vv v8, v8, v9, v0.t
; CHECK-NEXT: vmv.x.s a1, v8
; CHECK-NEXT: vslidedown.vi v9, v8, 1
; CHECK-NEXT: vslidedown.vi v8, v8, 2
diff --git a/llvm/test/CodeGen/RISCV/rvv/masked-srem.ll b/llvm/test/CodeGen/RISCV/rvv/masked-srem.ll
index f8e5d35a3661b..b76afe8ec377c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/masked-srem.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/masked-srem.ll
@@ -5,9 +5,7 @@ define <vscale x 8 x i8> @srem_nxv8i8(<vscale x 8 x i8> %x, <vscale x 8 x i8> %y
; CHECK-LABEL: srem_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 1
-; CHECK-NEXT: vmerge.vvm v9, v10, v9, v0
-; CHECK-NEXT: vrem.vv v8, v8, v9
+; CHECK-NEXT: vrem.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 8 x i8> @llvm.masked.srem(<vscale x 8 x i8> %x, <vscale x 8 x i8> %y, <vscale x 8 x i1> %m)
ret <vscale x 8 x i8> %res
@@ -17,9 +15,7 @@ define <vscale x 4 x i16> @srem_nxv4i16(<vscale x 4 x i16> %x, <vscale x 4 x i16
; CHECK-LABEL: srem_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 1
-; CHECK-NEXT: vmerge.vvm v9, v10, v9, v0
-; CHECK-NEXT: vrem.vv v8, v8, v9
+; CHECK-NEXT: vrem.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 4 x i16> @llvm.masked.srem(<vscale x 4 x i16> %x, <vscale x 4 x i16> %y, <vscale x 4 x i1> %m)
ret <vscale x 4 x i16> %res
@@ -29,9 +25,7 @@ define <vscale x 4 x i32> @srem_nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32
; CHECK-LABEL: srem_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 1
-; CHECK-NEXT: vmerge.vvm v10, v12, v10, v0
-; CHECK-NEXT: vrem.vv v8, v8, v10
+; CHECK-NEXT: vrem.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 4 x i32> @llvm.masked.srem(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i1> %m)
ret <vscale x 4 x i32> %res
@@ -41,9 +35,7 @@ define <vscale x 8 x i32> @srem_nxv8i32(<vscale x 8 x i32> %x, <vscale x 8 x i32
; CHECK-LABEL: srem_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v16, 1
-; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
-; CHECK-NEXT: vrem.vv v8, v8, v12
+; CHECK-NEXT: vrem.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 8 x i32> @llvm.masked.srem(<vscale x 8 x i32> %x, <vscale x 8 x i32> %y, <vscale x 8 x i1> %m)
ret <vscale x 8 x i32> %res
@@ -53,9 +45,7 @@ define <vscale x 8 x i32> @srem_nxv8i32_splat_rhs(<vscale x 8 x i32> %x, i32 %y,
; CHECK-LABEL: srem_nxv8i32_splat_rhs:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 1
-; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
-; CHECK-NEXT: vrem.vv v8, v8, v12
+; CHECK-NEXT: vrem.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %y, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
@@ -67,9 +57,7 @@ define <vscale x 8 x i16> @srem_nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16
; CHECK-LABEL: srem_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 1
-; CHECK-NEXT: vmerge.vvm v10, v12, v10, v0
-; CHECK-NEXT: vrem.vv v8, v8, v10
+; CHECK-NEXT: vrem.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 8 x i16> @llvm.masked.srem(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i1> %m)
ret <vscale x 8 x i16> %res
@@ -79,9 +67,7 @@ define <vscale x 2 x i64> @srem_nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64
; CHECK-LABEL: srem_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 1
-; CHECK-NEXT: vmerge.vvm v10, v12, v10, v0
-; CHECK-NEXT: vrem.vv v8, v8, v10
+; CHECK-NEXT: vrem.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 2 x i64> @llvm.masked.srem(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i1> %m)
ret <vscale x 2 x i64> %res
@@ -91,9 +77,7 @@ define <4 x i32> @srem_v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i1> %m) {
; CHECK-LABEL: srem_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 1
-; CHECK-NEXT: vmerge.vvm v9, v10, v9, v0
-; CHECK-NEXT: vrem.vv v8, v8, v9
+; CHECK-NEXT: vrem.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <4 x i32> @llvm.masked.srem(<4 x i32> %x, <4 x i32> %y, <4 x i1> %m)
ret <4 x i32> %res
@@ -103,9 +87,7 @@ define <2 x i64> @srem_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i1> %m) {
; CHECK-LABEL: srem_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 1
-; CHECK-NEXT: vmerge.vvm v9, v10, v9, v0
-; CHECK-NEXT: vrem.vv v8, v8, v9
+; CHECK-NEXT: vrem.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <2 x i64> @llvm.masked.srem(<2 x i64> %x, <2 x i64> %y, <2 x i1> %m)
ret <2 x i64> %res
@@ -115,9 +97,7 @@ define <4 x i64> @srem_v4i64(<4 x i64> %x, <4 x i64> %y, <4 x i1> %m) {
; CHECK-LABEL: srem_v4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 1
-; CHECK-NEXT: vmerge.vvm v10, v12, v10, v0
-; CHECK-NEXT: vrem.vv v8, v8, v10
+; CHECK-NEXT: vrem.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%res = call <4 x i64> @llvm.masked.srem(<4 x i64> %x, <4 x i64> %y, <4 x i1> %m)
ret <4 x i64> %res
@@ -127,9 +107,7 @@ define <2 x i32> @srem_v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i1> %m) {
; CHECK-LABEL: srem_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 1
-; CHECK-NEXT: vmerge.vvm v9, v10, v9, v0
-; CHECK-NEXT: vrem.vv v8, v8, v9
+; CHECK-NEXT: vrem.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <2 x i32> @llvm.masked.srem(<2 x i32> %x, <2 x i32> %y, <2 x i1> %m)
ret <2 x i32> %res
@@ -139,9 +117,7 @@ define <4 x i16> @srem_v4i16(<4 x i16> %x, <4 x i16> %y, <4 x i1> %m) {
; CHECK-LABEL: srem_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 1
-; CHECK-NEXT: vmerge.vvm v9, v10, v9, v0
-; CHECK-NEXT: vrem.vv v8, v8, v9
+; CHECK-NEXT: vrem.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <4 x i16> @llvm.masked.srem(<4 x i16> %x, <4 x i16> %y, <4 x i1> %m)
ret <4 x i16> %res
@@ -151,9 +127,7 @@ define <1 x i64> @srem_v1i64(<1 x i64> %x, <1 x i64> %y, <1 x i1> %m) {
; CHECK-LABEL: srem_v1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 1
-; CHECK-NEXT: vmerge.vvm v9, v10, v9, v0
-; CHECK-NEXT: vrem.vv v8, v8, v9
+; CHECK-NEXT: vrem.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <1 x i64> @llvm.masked.srem(<1 x i64> %x, <1 x i64> %y, <1 x i1> %m)
ret <1 x i64> %res
@@ -242,29 +216,28 @@ define <2 x i128> @srem_v2i128(<2 x i128> %x, <2 x i128> %y, <2 x i1> %m) nounwi
define <3 x i10> @srem_v3i10(<3 x i10> %x, <3 x i10> %y, <3 x i1> %m) {
; CHECK-LABEL: srem_v3i10:
; CHECK: # %bb.0:
+; CHECK-NEXT: ld a3, 0(a2)
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 7
+; CHECK-NEXT: ld a4, 8(a2)
+; CHECK-NEXT: ld a2, 16(a2)
+; CHECK-NEXT: vmv.v.x v9, a3
; CHECK-NEXT: ld a3, 0(a1)
-; CHECK-NEXT: ld a4, 8(a1)
+; CHECK-NEXT: ld a5, 8(a1)
; CHECK-NEXT: ld a1, 16(a1)
-; CHECK-NEXT: ld a5, 0(a2)
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
+; CHECK-NEXT: vmand.mm v0, v0, v8
; CHECK-NEXT: vmv.v.x v8, a3
-; CHECK-NEXT: ld a3, 8(a2)
-; CHECK-NEXT: ld a2, 16(a2)
-; CHECK-NEXT: vmv.v.x v9, a5
-; CHECK-NEXT: vmv.v.i v10, 7
-; CHECK-NEXT: vmand.mm v0, v0, v10
-; CHECK-NEXT: vmv.v.i v10, 1
-; CHECK-NEXT: vslide1down.vx v8, v8, a4
-; CHECK-NEXT: vslide1down.vx v9, v9, a3
-; CHECK-NEXT: vslide1down.vx v8, v8, a1
+; CHECK-NEXT: vslide1down.vx v9, v9, a4
+; CHECK-NEXT: vslide1down.vx v8, v8, a5
; CHECK-NEXT: vslide1down.vx v9, v9, a2
-; CHECK-NEXT: vslidedown.vi v8, v8, 1
+; CHECK-NEXT: vslide1down.vx v8, v8, a1
; CHECK-NEXT: vslidedown.vi v9, v9, 1
-; CHECK-NEXT: vsll.vi v8, v8, 6
+; CHECK-NEXT: vslidedown.vi v8, v8, 1
; CHECK-NEXT: vsll.vi v9, v9, 6
+; CHECK-NEXT: vsll.vi v8, v8, 6
+; CHECK-NEXT: vsra.vi v9, v9, 6
; CHECK-NEXT: vsra.vi v8, v8, 6
-; CHECK-NEXT: vsra.vi v10, v9, 6, v0.t
-; CHECK-NEXT: vrem.vv v8, v8, v10
+; CHECK-NEXT: vrem.vv v8, v8, v9, v0.t
; CHECK-NEXT: vmv.x.s a1, v8
; CHECK-NEXT: vslidedown.vi v9, v8, 1
; CHECK-NEXT: vslidedown.vi v8, v8, 2
diff --git a/llvm/test/CodeGen/RISCV/rvv/masked-udiv.ll b/llvm/test/CodeGen/RISCV/rvv/masked-udiv.ll
index 79872fd31ba23..f4317244a600f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/masked-udiv.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/masked-udiv.ll
@@ -5,9 +5,7 @@ define <vscale x 8 x i8> @udiv_nxv8i8(<vscale x 8 x i8> %x, <vscale x 8 x i8> %y
; CHECK-LABEL: udiv_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 1
-; CHECK-NEXT: vmerge.vvm v9, v10, v9, v0
-; CHECK-NEXT: vdivu.vv v8, v8, v9
+; CHECK-NEXT: vdivu.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 8 x i8> @llvm.masked.udiv(<vscale x 8 x i8> %x, <vscale x 8 x i8> %y, <vscale x 8 x i1> %m)
ret <vscale x 8 x i8> %res
@@ -17,9 +15,7 @@ define <vscale x 4 x i16> @udiv_nxv4i16(<vscale x 4 x i16> %x, <vscale x 4 x i16
; CHECK-LABEL: udiv_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 1
-; CHECK-NEXT: vmerge.vvm v9, v10, v9, v0
-; CHECK-NEXT: vdivu.vv v8, v8, v9
+; CHECK-NEXT: vdivu.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 4 x i16> @llvm.masked.udiv(<vscale x 4 x i16> %x, <vscale x 4 x i16> %y, <vscale x 4 x i1> %m)
ret <vscale x 4 x i16> %res
@@ -29,9 +25,7 @@ define <vscale x 4 x i32> @udiv_nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32
; CHECK-LABEL: udiv_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 1
-; CHECK-NEXT: vmerge.vvm v10, v12, v10, v0
-; CHECK-NEXT: vdivu.vv v8, v8, v10
+; CHECK-NEXT: vdivu.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 4 x i32> @llvm.masked.udiv(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i1> %m)
ret <vscale x 4 x i32> %res
@@ -41,9 +35,7 @@ define <vscale x 8 x i32> @udiv_nxv8i32(<vscale x 8 x i32> %x, <vscale x 8 x i32
; CHECK-LABEL: udiv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v16, 1
-; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
-; CHECK-NEXT: vdivu.vv v8, v8, v12
+; CHECK-NEXT: vdivu.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 8 x i32> @llvm.masked.udiv(<vscale x 8 x i32> %x, <vscale x 8 x i32> %y, <vscale x 8 x i1> %m)
ret <vscale x 8 x i32> %res
@@ -53,9 +45,7 @@ define <vscale x 8 x i32> @udiv_nxv8i32_splat_rhs(<vscale x 8 x i32> %x, i32 %y,
; CHECK-LABEL: udiv_nxv8i32_splat_rhs:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 1
-; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
-; CHECK-NEXT: vdivu.vv v8, v8, v12
+; CHECK-NEXT: vdivu.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %y, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
@@ -67,9 +57,7 @@ define <vscale x 8 x i16> @udiv_nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16
; CHECK-LABEL: udiv_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 1
-; CHECK-NEXT: vmerge.vvm v10, v12, v10, v0
-; CHECK-NEXT: vdivu.vv v8, v8, v10
+; CHECK-NEXT: vdivu.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 8 x i16> @llvm.masked.udiv(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i1> %m)
ret <vscale x 8 x i16> %res
@@ -79,9 +67,7 @@ define <vscale x 2 x i64> @udiv_nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64
; CHECK-LABEL: udiv_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 1
-; CHECK-NEXT: vmerge.vvm v10, v12, v10, v0
-; CHECK-NEXT: vdivu.vv v8, v8, v10
+; CHECK-NEXT: vdivu.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 2 x i64> @llvm.masked.udiv(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i1> %m)
ret <vscale x 2 x i64> %res
@@ -91,9 +77,7 @@ define <4 x i32> @udiv_v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i1> %m) {
; CHECK-LABEL: udiv_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 1
-; CHECK-NEXT: vmerge.vvm v9, v10, v9, v0
-; CHECK-NEXT: vdivu.vv v8, v8, v9
+; CHECK-NEXT: vdivu.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <4 x i32> @llvm.masked.udiv(<4 x i32> %x, <4 x i32> %y, <4 x i1> %m)
ret <4 x i32> %res
@@ -103,9 +87,7 @@ define <2 x i64> @udiv_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i1> %m) {
; CHECK-LABEL: udiv_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 1
-; CHECK-NEXT: vmerge.vvm v9, v10, v9, v0
-; CHECK-NEXT: vdivu.vv v8, v8, v9
+; CHECK-NEXT: vdivu.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <2 x i64> @llvm.masked.udiv(<2 x i64> %x, <2 x i64> %y, <2 x i1> %m)
ret <2 x i64> %res
@@ -115,9 +97,7 @@ define <4 x i64> @udiv_v4i64(<4 x i64> %x, <4 x i64> %y, <4 x i1> %m) {
; CHECK-LABEL: udiv_v4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 1
-; CHECK-NEXT: vmerge.vvm v10, v12, v10, v0
-; CHECK-NEXT: vdivu.vv v8, v8, v10
+; CHECK-NEXT: vdivu.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%res = call <4 x i64> @llvm.masked.udiv(<4 x i64> %x, <4 x i64> %y, <4 x i1> %m)
ret <4 x i64> %res
@@ -127,9 +107,7 @@ define <2 x i32> @udiv_v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i1> %m) {
; CHECK-LABEL: udiv_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 1
-; CHECK-NEXT: vmerge.vvm v9, v10, v9, v0
-; CHECK-NEXT: vdivu.vv v8, v8, v9
+; CHECK-NEXT: vdivu.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <2 x i32> @llvm.masked.udiv(<2 x i32> %x, <2 x i32> %y, <2 x i1> %m)
ret <2 x i32> %res
@@ -139,9 +117,7 @@ define <4 x i16> @udiv_v4i16(<4 x i16> %x, <4 x i16> %y, <4 x i1> %m) {
; CHECK-LABEL: udiv_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 1
-; CHECK-NEXT: vmerge.vvm v9, v10, v9, v0
-; CHECK-NEXT: vdivu.vv v8, v8, v9
+; CHECK-NEXT: vdivu.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <4 x i16> @llvm.masked.udiv(<4 x i16> %x, <4 x i16> %y, <4 x i1> %m)
ret <4 x i16> %res
@@ -151,9 +127,7 @@ define <1 x i64> @udiv_v1i64(<1 x i64> %x, <1 x i64> %y, <1 x i1> %m) {
; CHECK-LABEL: udiv_v1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 1
-; CHECK-NEXT: vmerge.vvm v9, v10, v9, v0
-; CHECK-NEXT: vdivu.vv v8, v8, v9
+; CHECK-NEXT: vdivu.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <1 x i64> @llvm.masked.udiv(<1 x i64> %x, <1 x i64> %y, <1 x i1> %m)
ret <1 x i64> %res
@@ -242,28 +216,27 @@ define <2 x i128> @udiv_v2i128(<2 x i128> %x, <2 x i128> %y, <2 x i1> %m) nounwi
define <3 x i10> @udiv_v3i10(<3 x i10> %x, <3 x i10> %y, <3 x i1> %m) {
; CHECK-LABEL: udiv_v3i10:
; CHECK: # %bb.0:
+; CHECK-NEXT: ld a3, 0(a2)
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 7
+; CHECK-NEXT: ld a4, 8(a2)
+; CHECK-NEXT: ld a2, 16(a2)
+; CHECK-NEXT: vmv.v.x v9, a3
; CHECK-NEXT: ld a3, 0(a1)
-; CHECK-NEXT: ld a4, 8(a1)
+; CHECK-NEXT: ld a5, 8(a1)
; CHECK-NEXT: ld a1, 16(a1)
-; CHECK-NEXT: ld a5, 0(a2)
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
+; CHECK-NEXT: vmand.mm v0, v0, v8
; CHECK-NEXT: vmv.v.x v8, a3
-; CHECK-NEXT: ld a3, 8(a2)
-; CHECK-NEXT: ld a2, 16(a2)
-; CHECK-NEXT: vmv.v.x v9, a5
-; CHECK-NEXT: vslide1down.vx v8, v8, a4
-; CHECK-NEXT: li a4, 1023
-; CHECK-NEXT: vmv.v.i v10, 7
-; CHECK-NEXT: vmand.mm v0, v0, v10
-; CHECK-NEXT: vmv.v.i v10, 1
-; CHECK-NEXT: vslide1down.vx v9, v9, a3
-; CHECK-NEXT: vslide1down.vx v8, v8, a1
+; CHECK-NEXT: vslide1down.vx v9, v9, a4
+; CHECK-NEXT: li a3, 1023
+; CHECK-NEXT: vslide1down.vx v8, v8, a5
; CHECK-NEXT: vslide1down.vx v9, v9, a2
-; CHECK-NEXT: vslidedown.vi v8, v8, 1
+; CHECK-NEXT: vslide1down.vx v8, v8, a1
; CHECK-NEXT: vslidedown.vi v9, v9, 1
-; CHECK-NEXT: vand.vx v8, v8, a4
-; CHECK-NEXT: vand.vx v10, v9, a4, v0.t
-; CHECK-NEXT: vdivu.vv v8, v8, v10
+; CHECK-NEXT: vslidedown.vi v8, v8, 1
+; CHECK-NEXT: vand.vx v9, v9, a3
+; CHECK-NEXT: vand.vx v8, v8, a3
+; CHECK-NEXT: vdivu.vv v8, v8, v9, v0.t
; CHECK-NEXT: vmv.x.s a1, v8
; CHECK-NEXT: vslidedown.vi v9, v8, 1
; CHECK-NEXT: vslidedown.vi v8, v8, 2
diff --git a/llvm/test/CodeGen/RISCV/rvv/masked-urem.ll b/llvm/test/CodeGen/RISCV/rvv/masked-urem.ll
index 06e0a98daecba..446f26d040bd5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/masked-urem.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/masked-urem.ll
@@ -5,9 +5,7 @@ define <vscale x 8 x i8> @urem_nxv8i8(<vscale x 8 x i8> %x, <vscale x 8 x i8> %y
; CHECK-LABEL: urem_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 1
-; CHECK-NEXT: vmerge.vvm v9, v10, v9, v0
-; CHECK-NEXT: vremu.vv v8, v8, v9
+; CHECK-NEXT: vremu.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 8 x i8> @llvm.masked.urem(<vscale x 8 x i8> %x, <vscale x 8 x i8> %y, <vscale x 8 x i1> %m)
ret <vscale x 8 x i8> %res
@@ -17,9 +15,7 @@ define <vscale x 4 x i16> @urem_nxv4i16(<vscale x 4 x i16> %x, <vscale x 4 x i16
; CHECK-LABEL: urem_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 1
-; CHECK-NEXT: vmerge.vvm v9, v10, v9, v0
-; CHECK-NEXT: vremu.vv v8, v8, v9
+; CHECK-NEXT: vremu.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 4 x i16> @llvm.masked.urem(<vscale x 4 x i16> %x, <vscale x 4 x i16> %y, <vscale x 4 x i1> %m)
ret <vscale x 4 x i16> %res
@@ -29,9 +25,7 @@ define <vscale x 4 x i32> @urem_nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32
; CHECK-LABEL: urem_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 1
-; CHECK-NEXT: vmerge.vvm v10, v12, v10, v0
-; CHECK-NEXT: vremu.vv v8, v8, v10
+; CHECK-NEXT: vremu.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 4 x i32> @llvm.masked.urem(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i1> %m)
ret <vscale x 4 x i32> %res
@@ -41,9 +35,7 @@ define <vscale x 8 x i32> @urem_nxv8i32(<vscale x 8 x i32> %x, <vscale x 8 x i32
; CHECK-LABEL: urem_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v16, 1
-; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
-; CHECK-NEXT: vremu.vv v8, v8, v12
+; CHECK-NEXT: vremu.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 8 x i32> @llvm.masked.urem(<vscale x 8 x i32> %x, <vscale x 8 x i32> %y, <vscale x 8 x i1> %m)
ret <vscale x 8 x i32> %res
@@ -53,9 +45,7 @@ define <vscale x 8 x i32> @urem_nxv8i32_splat_rhs(<vscale x 8 x i32> %x, i32 %y,
; CHECK-LABEL: urem_nxv8i32_splat_rhs:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 1
-; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0
-; CHECK-NEXT: vremu.vv v8, v8, v12
+; CHECK-NEXT: vremu.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %y, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
@@ -67,9 +57,7 @@ define <vscale x 8 x i16> @urem_nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16
; CHECK-LABEL: urem_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 1
-; CHECK-NEXT: vmerge.vvm v10, v12, v10, v0
-; CHECK-NEXT: vremu.vv v8, v8, v10
+; CHECK-NEXT: vremu.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 8 x i16> @llvm.masked.urem(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i1> %m)
ret <vscale x 8 x i16> %res
@@ -79,9 +67,7 @@ define <vscale x 2 x i64> @urem_nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64
; CHECK-LABEL: urem_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 1
-; CHECK-NEXT: vmerge.vvm v10, v12, v10, v0
-; CHECK-NEXT: vremu.vv v8, v8, v10
+; CHECK-NEXT: vremu.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 2 x i64> @llvm.masked.urem(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i1> %m)
ret <vscale x 2 x i64> %res
@@ -91,9 +77,7 @@ define <4 x i32> @urem_v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i1> %m) {
; CHECK-LABEL: urem_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 1
-; CHECK-NEXT: vmerge.vvm v9, v10, v9, v0
-; CHECK-NEXT: vremu.vv v8, v8, v9
+; CHECK-NEXT: vremu.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <4 x i32> @llvm.masked.urem(<4 x i32> %x, <4 x i32> %y, <4 x i1> %m)
ret <4 x i32> %res
@@ -103,9 +87,7 @@ define <2 x i64> @urem_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i1> %m) {
; CHECK-LABEL: urem_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 1
-; CHECK-NEXT: vmerge.vvm v9, v10, v9, v0
-; CHECK-NEXT: vremu.vv v8, v8, v9
+; CHECK-NEXT: vremu.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <2 x i64> @llvm.masked.urem(<2 x i64> %x, <2 x i64> %y, <2 x i1> %m)
ret <2 x i64> %res
@@ -115,9 +97,7 @@ define <4 x i64> @urem_v4i64(<4 x i64> %x, <4 x i64> %y, <4 x i1> %m) {
; CHECK-LABEL: urem_v4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 1
-; CHECK-NEXT: vmerge.vvm v10, v12, v10, v0
-; CHECK-NEXT: vremu.vv v8, v8, v10
+; CHECK-NEXT: vremu.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%res = call <4 x i64> @llvm.masked.urem(<4 x i64> %x, <4 x i64> %y, <4 x i1> %m)
ret <4 x i64> %res
@@ -127,9 +107,7 @@ define <2 x i32> @urem_v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i1> %m) {
; CHECK-LABEL: urem_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 1
-; CHECK-NEXT: vmerge.vvm v9, v10, v9, v0
-; CHECK-NEXT: vremu.vv v8, v8, v9
+; CHECK-NEXT: vremu.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <2 x i32> @llvm.masked.urem(<2 x i32> %x, <2 x i32> %y, <2 x i1> %m)
ret <2 x i32> %res
@@ -139,9 +117,7 @@ define <4 x i16> @urem_v4i16(<4 x i16> %x, <4 x i16> %y, <4 x i1> %m) {
; CHECK-LABEL: urem_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 1
-; CHECK-NEXT: vmerge.vvm v9, v10, v9, v0
-; CHECK-NEXT: vremu.vv v8, v8, v9
+; CHECK-NEXT: vremu.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <4 x i16> @llvm.masked.urem(<4 x i16> %x, <4 x i16> %y, <4 x i1> %m)
ret <4 x i16> %res
@@ -151,9 +127,7 @@ define <1 x i64> @urem_v1i64(<1 x i64> %x, <1 x i64> %y, <1 x i1> %m) {
; CHECK-LABEL: urem_v1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 1
-; CHECK-NEXT: vmerge.vvm v9, v10, v9, v0
-; CHECK-NEXT: vremu.vv v8, v8, v9
+; CHECK-NEXT: vremu.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <1 x i64> @llvm.masked.urem(<1 x i64> %x, <1 x i64> %y, <1 x i1> %m)
ret <1 x i64> %res
@@ -242,28 +216,27 @@ define <2 x i128> @urem_v2i128(<2 x i128> %x, <2 x i128> %y, <2 x i1> %m) nounwi
define <3 x i10> @urem_v3i10(<3 x i10> %x, <3 x i10> %y, <3 x i1> %m) {
; CHECK-LABEL: urem_v3i10:
; CHECK: # %bb.0:
+; CHECK-NEXT: ld a3, 0(a2)
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 7
+; CHECK-NEXT: ld a4, 8(a2)
+; CHECK-NEXT: ld a2, 16(a2)
+; CHECK-NEXT: vmv.v.x v9, a3
; CHECK-NEXT: ld a3, 0(a1)
-; CHECK-NEXT: ld a4, 8(a1)
+; CHECK-NEXT: ld a5, 8(a1)
; CHECK-NEXT: ld a1, 16(a1)
-; CHECK-NEXT: ld a5, 0(a2)
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
+; CHECK-NEXT: vmand.mm v0, v0, v8
; CHECK-NEXT: vmv.v.x v8, a3
-; CHECK-NEXT: ld a3, 8(a2)
-; CHECK-NEXT: ld a2, 16(a2)
-; CHECK-NEXT: vmv.v.x v9, a5
-; CHECK-NEXT: vslide1down.vx v8, v8, a4
-; CHECK-NEXT: li a4, 1023
-; CHECK-NEXT: vmv.v.i v10, 7
-; CHECK-NEXT: vmand.mm v0, v0, v10
-; CHECK-NEXT: vmv.v.i v10, 1
-; CHECK-NEXT: vslide1down.vx v9, v9, a3
-; CHECK-NEXT: vslide1down.vx v8, v8, a1
+; CHECK-NEXT: vslide1down.vx v9, v9, a4
+; CHECK-NEXT: li a3, 1023
+; CHECK-NEXT: vslide1down.vx v8, v8, a5
; CHECK-NEXT: vslide1down.vx v9, v9, a2
-; CHECK-NEXT: vslidedown.vi v8, v8, 1
+; CHECK-NEXT: vslide1down.vx v8, v8, a1
; CHECK-NEXT: vslidedown.vi v9, v9, 1
-; CHECK-NEXT: vand.vx v8, v8, a4
-; CHECK-NEXT: vand.vx v10, v9, a4, v0.t
-; CHECK-NEXT: vremu.vv v8, v8, v10
+; CHECK-NEXT: vslidedown.vi v8, v8, 1
+; CHECK-NEXT: vand.vx v9, v9, a3
+; CHECK-NEXT: vand.vx v8, v8, a3
+; CHECK-NEXT: vremu.vv v8, v8, v9, v0.t
; CHECK-NEXT: vmv.x.s a1, v8
; CHECK-NEXT: vslidedown.vi v9, v8, 1
; CHECK-NEXT: vslidedown.vi v8, v8, 2
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