[llvm] [RISCV] Lower masked_{u, s}{div, rem} and update TTI (PR #192543)

[Pengcheng Wang via llvm-commits]

================
@@ -8796,6 +8810,18 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
     return DAG.getNode(RISCVISD::PSSLAI, DL, VT, Op.getOperand(0),
                        DAG.getTargetConstant(ShAmt, DL, Subtarget.getXLenVT()));
   }
+  case ISD::MASKED_UDIV:
+  case ISD::MASKED_SDIV:
+  case ISD::MASKED_UREM:
+  case ISD::MASKED_SREM: {
+    SDLoc DL(Op);
+    MVT VT = Op.getSimpleValueType();
----------------
wangpc-pp wrote:

> uarchs will use the mask to avoid dispatching uops on disabled lanes

This is easy to implement for in-order cores but is challenging for OoO cores. 

https://github.com/llvm/llvm-project/pull/192543