[llvm] [RISCV] Lower masked_{u, s}{div, rem} and update TTI (PR #192543)

[Luke Lau via llvm-commits]

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@@ -168,6 +168,21 @@ multiclass VPatBinarySDNode_VV_VX_VI<SDPatternOperator vop, string instruction_n
   }
 }
 
+multiclass VPatBinaryMaskedSDNode_VV_VX<SDPatternOperator vop, string instruction_name> {
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lukel97 wrote:

Good idea, I split it into two classes in fdae4f865187dc172a2ca280c513b6c87ede39b2 to match the other patterns, I think usually there's a `_VV_VX` that inherits from `_VV`, since we don't have any .vx only instructions. 

I think the isSEWAware will be dead tablegen code if we add it in this PR, I guess we can add it later though. Although I'm not planning on adding anymore masked SDNodes, so hopefully we never need to extend this :)

https://github.com/llvm/llvm-project/pull/192543