[llvm] [AArch64][SelectionDAG] Improve codegen for insert_into_scalable(zext_fixed_length_vector) (PR #192405)

[Sushant Gokhale via llvm-commits]

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@@ -0,0 +1,223 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=aarch64 -mattr=+sve2 --aarch64-sve-vector-bits-min=256 -o - < %s | FileCheck %s
+
+define <vscale x 16 x i8> @zext_slt_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
+; CHECK-LABEL: zext_slt_nxv16i8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.b
+; CHECK-NEXT:    cmpgt p1.b, p0/z, z1.b, z0.b
+; CHECK-NEXT:    mov z0.b, p1/z, #1 // =0x1
+; CHECK-NEXT:    ret
+  %1 = icmp slt <vscale x 16 x i8> %a, %b
+  %2 = zext <vscale x 16 x i1> %1 to <vscale x 16 x i8>
+  ret <vscale x 16 x i8> %2
+}
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sushgokh wrote:

I will add these tests rather than simplifying the existing one because this pattern can come from other patterns as the previous tests illustrate. Also, the previous cases directly express what code is expected(`zext`).
Thanks.


https://github.com/llvm/llvm-project/pull/192405