[llvm] AMDGPU/GlobalISel: RegBankLegalize rules for BVH intersect ray (PR #192583)

[Petar Avramovic via llvm-commits]

================
@@ -703,6 +722,120 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
       .Any({{DivBRC, BRC, B64, DivS32},
             {{VgprBRC}, {VgprBRC, VgprB64, Vgpr32}, InsVecEltToSel}});
 
+  addRulesForGOpcs({G_AMDGPU_BVH_INTERSECT_RAY})
+      // GFX11+, f32 ray, i64 (3x V3S32)
+      .Any({{UniV4S32, _, S64, S32, V3S32, V3S32, V3S32, V4S32},
+            {{UniInVgprV4S32},
+             {Imm, Vgpr64, Vgpr32, VgprV3S32, VgprV3S32, VgprV3S32,
+              SgprV4S32_WF}}})
+      .Any({{DivV4S32, _, S64, S32, V3S32, V3S32, V3S32, V4S32},
+            {{VgprV4S32},
+             {Imm, Vgpr64, Vgpr32, VgprV3S32, VgprV3S32, VgprV3S32,
+              SgprV4S32_WF}}})
+      // GFX11+, f32 ray, i32 (3x V3S32)
+      .Any({{UniV4S32, _, S32, S32, V3S32, V3S32, V3S32, V4S32},
+            {{UniInVgprV4S32},
+             {Imm, Vgpr32, Vgpr32, VgprV3S32, VgprV3S32, VgprV3S32,
+              SgprV4S32_WF}}})
+      .Any({{DivV4S32, _, S32, S32, V3S32, V3S32, V3S32, V4S32},
+            {{VgprV4S32},
+             {Imm, Vgpr32, Vgpr32, VgprV3S32, VgprV3S32, VgprV3S32,
+              SgprV4S32_WF}}})
+      // GFX11+, f16 ray, i64 (2x V3S32)
+      .Any({{UniV4S32, _, S64, S32, V3S32, V3S32, V4S32},
+            {{UniInVgprV4S32},
+             {Imm, Vgpr64, Vgpr32, VgprV3S32, VgprV3S32, SgprV4S32_WF}}})
+      .Any({{DivV4S32, _, S64, S32, V3S32, V3S32, V4S32},
+            {{VgprV4S32},
+             {Imm, Vgpr64, Vgpr32, VgprV3S32, VgprV3S32, SgprV4S32_WF}}})
+      // GFX11+, f16 ray, i32 (2x V3S32)
+      .Any({{UniV4S32, _, S32, S32, V3S32, V3S32, V4S32},
+            {{UniInVgprV4S32},
+             {Imm, Vgpr32, Vgpr32, VgprV3S32, VgprV3S32, SgprV4S32_WF}}})
+      .Any({{DivV4S32, _, S32, S32, V3S32, V3S32, V4S32},
+            {{VgprV4S32},
+             {Imm, Vgpr32, Vgpr32, VgprV3S32, VgprV3S32, SgprV4S32_WF}}})
+      // GFX10 scalarized, f32 ray, i64 (12 S32)
+      .Any({{UniV4S32, _, S32, S32, S32, S32, S32, S32, S32, S32, S32, S32, S32,
+             S32, V4S32},
+            {{UniInVgprV4S32},
+             {Imm, Vgpr32, Vgpr32, Vgpr32, Vgpr32, Vgpr32, Vgpr32, Vgpr32,
+              Vgpr32, Vgpr32, Vgpr32, Vgpr32, Vgpr32, SgprV4S32_WF}}})
+      .Any({{DivV4S32, _, S32, S32, S32, S32, S32, S32, S32, S32, S32, S32, S32,
+             S32, V4S32},
+            {{VgprV4S32},
+             {Imm, Vgpr32, Vgpr32, Vgpr32, Vgpr32, Vgpr32, Vgpr32, Vgpr32,
+              Vgpr32, Vgpr32, Vgpr32, Vgpr32, Vgpr32, SgprV4S32_WF}}})
+      // GFX10 scalarized, f32 ray, i32 (11 S32)
+      .Any({{UniV4S32, _, S32, S32, S32, S32, S32, S32, S32, S32, S32, S32, S32,
+             V4S32},
+            {{UniInVgprV4S32},
+             {Imm, Vgpr32, Vgpr32, Vgpr32, Vgpr32, Vgpr32, Vgpr32, Vgpr32,
+              Vgpr32, Vgpr32, Vgpr32, Vgpr32, SgprV4S32_WF}}})
+      .Any({{DivV4S32, _, S32, S32, S32, S32, S32, S32, S32, S32, S32, S32, S32,
+             V4S32},
+            {{VgprV4S32},
+             {Imm, Vgpr32, Vgpr32, Vgpr32, Vgpr32, Vgpr32, Vgpr32, Vgpr32,
+              Vgpr32, Vgpr32, Vgpr32, Vgpr32, SgprV4S32_WF}}})
+      // GFX10 scalarized, f16 ray, i64 (9 S32)
+      .Any({{UniV4S32, _, S32, S32, S32, S32, S32, S32, S32, S32, S32, V4S32},
+            {{UniInVgprV4S32},
+             {Imm, Vgpr32, Vgpr32, Vgpr32, Vgpr32, Vgpr32, Vgpr32, Vgpr32,
+              Vgpr32, Vgpr32, SgprV4S32_WF}}})
+      .Any({{DivV4S32, _, S32, S32, S32, S32, S32, S32, S32, S32, S32, V4S32},
+            {{VgprV4S32},
+             {Imm, Vgpr32, Vgpr32, Vgpr32, Vgpr32, Vgpr32, Vgpr32, Vgpr32,
+              Vgpr32, Vgpr32, SgprV4S32_WF}}})
+      // GFX10 scalarized, f16 ray, i32 (8 S32)
+      .Any({{UniV4S32, _, S32, S32, S32, S32, S32, S32, S32, S32, V4S32},
+            {{UniInVgprV4S32},
+             {Imm, Vgpr32, Vgpr32, Vgpr32, Vgpr32, Vgpr32, Vgpr32, Vgpr32,
+              Vgpr32, SgprV4S32_WF}}})
+      .Any({{DivV4S32, _, S32, S32, S32, S32, S32, S32, S32, S32, V4S32},
+            {{VgprV4S32},
+             {Imm, Vgpr32, Vgpr32, Vgpr32, Vgpr32, Vgpr32, Vgpr32, Vgpr32,
+              Vgpr32, SgprV4S32_WF}}})
+      // GFX10 merged, f32 ray, i64 (V12S32)
+      .Any({{UniV4S32, _, V12S32, V4S32},
+            {{UniInVgprV4S32}, {Imm, VgprV12S32, SgprV4S32_WF}}})
+      .Any({{DivV4S32, _, V12S32, V4S32},
+            {{VgprV4S32}, {Imm, VgprV12S32, SgprV4S32_WF}}})
+      // GFX10 merged, f32 ray, i32 (V11S32)
+      .Any({{UniV4S32, _, V11S32, V4S32},
+            {{UniInVgprV4S32}, {Imm, VgprV11S32, SgprV4S32_WF}}})
+      .Any({{DivV4S32, _, V11S32, V4S32},
+            {{VgprV4S32}, {Imm, VgprV11S32, SgprV4S32_WF}}})
+      // GFX10 merged, f16 ray, i64 (V9S32)
+      .Any({{UniV4S32, _, V9S32, V4S32},
+            {{UniInVgprV4S32}, {Imm, VgprV9S32, SgprV4S32_WF}}})
+      .Any({{DivV4S32, _, V9S32, V4S32},
+            {{VgprV4S32}, {Imm, VgprV9S32, SgprV4S32_WF}}})
+      // GFX10 merged, f16 ray, i32 (V8S32)
+      .Any({{UniV4S32, _, V8S32, V4S32},
+            {{UniInVgprV4S32}, {Imm, VgprV8S32, SgprV4S32_WF}}})
+      .Any({{DivV4S32, _, V8S32, V4S32},
+            {{VgprV4S32}, {Imm, VgprV8S32, SgprV4S32_WF}}});
+
+  addRulesForGOpcs({G_AMDGPU_BVH_DUAL_INTERSECT_RAY})
+      .Any({{UniV10S32, V3S32, V3S32},
+            {{UniInVgprV10S32, UniInVgprV3S32, UniInVgprV3S32},
+             {Imm, Vgpr64, VgprV2S32, VgprV3S32, VgprV3S32, VgprV2S32,
+              SgprV4S32_WF}}})
+      .Any({{DivV10S32, V3S32, V3S32},
+            {{VgprV10S32, VgprV3S32, VgprV3S32},
+             {Imm, Vgpr64, VgprV2S32, VgprV3S32, VgprV3S32, VgprV2S32,
+              SgprV4S32_WF}}});
+
+  addRulesForGOpcs({G_AMDGPU_BVH8_INTERSECT_RAY})
----------------
petar-avramovic wrote:

These have too many operands, think it would be better to write something similar to ApplyINTRIN_IMAGE (probably can share some code) and explain in comment what we are doing

https://github.com/llvm/llvm-project/pull/192583