[llvm] [PowerPC] Enable custom lowering for bswap64 builtin on Power8 64 bits with improved parallelism (PR #187259)

[Aditi Medhane via llvm-commits]

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@@ -11622,6 +11623,46 @@ SDValue PPCTargetLowering::LowerBSWAP(SDValue Op, SelectionDAG &DAG) const {
   SDLoc dl(Op);
   if (!Subtarget.isPPC64())
     return Op;
+
+  // Apply the optimization to Power8 and 64-bits which allows parallelism for
+  // rotate instructions which should make the bswap64 builtin faster.
+  if (!Subtarget.hasP9Vector()) {
+    SDValue Input = Op.getOperand(0);
+
+    auto Swap32 = [&](SDValue Val32) -> SDValue {
+      SDValue Rot = DAG.getNode(ISD::ROTL, dl, MVT::i32, Val32,
+                                DAG.getConstant(8, dl, MVT::i32));
+      SDValue Swap =
+          SDValue(DAG.getMachineNode(PPC::RLWIMI, dl, MVT::i32,
+                                     {Rot, Val32,
+                                      DAG.getTargetConstant(24, dl, MVT::i32),
+                                      DAG.getTargetConstant(0, dl, MVT::i32),
+                                      DAG.getTargetConstant(7, dl, MVT::i32)}),
+                  0);
+      return SDValue(DAG.getMachineNode(
+                         PPC::RLWIMI, dl, MVT::i32,
+                         {Swap, Val32, DAG.getTargetConstant(24, dl, MVT::i32),
+                          DAG.getTargetConstant(16, dl, MVT::i32),
+                          DAG.getTargetConstant(23, dl, MVT::i32)}),
+                     0);
+    };
+
+    SDValue Hi32 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
+                               DAG.getNode(ISD::SRL, dl, MVT::i64, Input,
+                                           DAG.getConstant(32, dl, MVT::i64)));
+    SDValue Lo32 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Input);
+
+    SDValue HiSwap = Swap32(Hi32);
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AditiRM wrote:

Replace the definition and minimize the code bloat

https://github.com/llvm/llvm-project/pull/187259