[llvm] [RISCV] Add tests for Zvzip CodeGen (PR #192591)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 16 21:34:55 PDT 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Pengcheng Wang (wangpc-pp)
<details>
<summary>Changes</summary>
Then we can add CodeGen support incrementally.
---
Patch is 207.98 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/192591.diff
7 Files Affected:
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll (+452)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll (+324)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-zipeven-zipodd.ll (+157)
- (modified) llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll (+108)
- (modified) llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll (+367)
- (modified) llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll (+534)
- (modified) llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll (+1950)
``````````diff
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
index 3a14f87c3f18a..5903271cf0d1d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
@@ -8,6 +8,9 @@
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh,+zvl256b,+experimental-xrivosvizip \
; RUN: -lower-interleaved-accesses=false -verify-machineinstrs \
; RUN: | FileCheck %s --check-prefixes=CHECK,ZIP
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh,+zvl256b,+experimental-zvzip \
+; RUN: -lower-interleaved-accesses=false -verify-machineinstrs \
+; RUN: | FileCheck %s --check-prefixes=CHECK,ZVZIP
define void @vnsrl_0_i8(ptr %in, ptr %out) {
; CHECK-LABEL: vnsrl_0_i8:
@@ -68,6 +71,15 @@ define void @vnsrl_0_i16(ptr %in, ptr %out) {
; ZIP-NEXT: vnsrl.wi v8, v8, 0
; ZIP-NEXT: vse16.v v8, (a1)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_0_i16:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
+; ZVZIP-NEXT: vle16.v v8, (a0)
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v8, v8, 0
+; ZVZIP-NEXT: vse16.v v8, (a1)
+; ZVZIP-NEXT: ret
entry:
%0 = load <8 x i16>, ptr %in, align 2
%shuffle.i5 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
@@ -102,6 +114,15 @@ define void @vnsrl_16_i16(ptr %in, ptr %out) {
; ZIP-NEXT: vnsrl.wi v8, v8, 16
; ZIP-NEXT: vse16.v v8, (a1)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_16_i16:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
+; ZVZIP-NEXT: vle16.v v8, (a0)
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v8, v8, 16
+; ZVZIP-NEXT: vse16.v v8, (a1)
+; ZVZIP-NEXT: ret
entry:
%0 = load <8 x i16>, ptr %in, align 2
%shuffle.i5 = shufflevector <8 x i16> %0, <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
@@ -136,6 +157,15 @@ define void @vnsrl_0_half(ptr %in, ptr %out) {
; ZIP-NEXT: vnsrl.wi v8, v8, 0
; ZIP-NEXT: vse16.v v8, (a1)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_0_half:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
+; ZVZIP-NEXT: vle16.v v8, (a0)
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v8, v8, 0
+; ZVZIP-NEXT: vse16.v v8, (a1)
+; ZVZIP-NEXT: ret
entry:
%0 = load <8 x half>, ptr %in, align 2
%shuffle.i5 = shufflevector <8 x half> %0, <8 x half> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
@@ -170,6 +200,15 @@ define void @vnsrl_16_half(ptr %in, ptr %out) {
; ZIP-NEXT: vnsrl.wi v8, v8, 16
; ZIP-NEXT: vse16.v v8, (a1)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_16_half:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 8, e16, mf2, ta, ma
+; ZVZIP-NEXT: vle16.v v8, (a0)
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v8, v8, 16
+; ZVZIP-NEXT: vse16.v v8, (a1)
+; ZVZIP-NEXT: ret
entry:
%0 = load <8 x half>, ptr %in, align 2
%shuffle.i5 = shufflevector <8 x half> %0, <8 x half> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
@@ -205,6 +244,15 @@ define void @vnsrl_0_i32(ptr %in, ptr %out) {
; ZIP-NEXT: vnsrl.wi v8, v8, 0
; ZIP-NEXT: vse32.v v8, (a1)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_0_i32:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 4, e32, mf2, ta, ma
+; ZVZIP-NEXT: vle32.v v8, (a0)
+; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v8, v8, 0
+; ZVZIP-NEXT: vse32.v v8, (a1)
+; ZVZIP-NEXT: ret
entry:
%0 = load <4 x i32>, ptr %in, align 4
%shuffle.i5 = shufflevector <4 x i32> %0, <4 x i32> poison, <2 x i32> <i32 0, i32 2>
@@ -243,6 +291,16 @@ define void @vnsrl_32_i32(ptr %in, ptr %out) {
; ZIP-NEXT: vnsrl.wx v8, v8, a0
; ZIP-NEXT: vse32.v v8, (a1)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_32_i32:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 4, e32, mf2, ta, ma
+; ZVZIP-NEXT: vle32.v v8, (a0)
+; ZVZIP-NEXT: li a0, 32
+; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-NEXT: vnsrl.wx v8, v8, a0
+; ZVZIP-NEXT: vse32.v v8, (a1)
+; ZVZIP-NEXT: ret
entry:
%0 = load <4 x i32>, ptr %in, align 4
%shuffle.i5 = shufflevector <4 x i32> %0, <4 x i32> poison, <2 x i32> <i32 1, i32 3>
@@ -278,6 +336,15 @@ define void @vnsrl_0_float(ptr %in, ptr %out) {
; ZIP-NEXT: vnsrl.wi v8, v8, 0
; ZIP-NEXT: vse32.v v8, (a1)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_0_float:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 4, e32, mf2, ta, ma
+; ZVZIP-NEXT: vle32.v v8, (a0)
+; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v8, v8, 0
+; ZVZIP-NEXT: vse32.v v8, (a1)
+; ZVZIP-NEXT: ret
entry:
%0 = load <4 x float>, ptr %in, align 4
%shuffle.i5 = shufflevector <4 x float> %0, <4 x float> poison, <2 x i32> <i32 0, i32 2>
@@ -316,6 +383,16 @@ define void @vnsrl_32_float(ptr %in, ptr %out) {
; ZIP-NEXT: vnsrl.wx v8, v8, a0
; ZIP-NEXT: vse32.v v8, (a1)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_32_float:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 4, e32, mf2, ta, ma
+; ZVZIP-NEXT: vle32.v v8, (a0)
+; ZVZIP-NEXT: li a0, 32
+; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-NEXT: vnsrl.wx v8, v8, a0
+; ZVZIP-NEXT: vse32.v v8, (a1)
+; ZVZIP-NEXT: ret
entry:
%0 = load <4 x float>, ptr %in, align 4
%shuffle.i5 = shufflevector <4 x float> %0, <4 x float> poison, <2 x i32> <i32 1, i32 3>
@@ -350,6 +427,16 @@ define void @vnsrl_0_i64(ptr %in, ptr %out) {
; ZIP-NEXT: ri.vunzip2a.vv v10, v8, v9
; ZIP-NEXT: vse64.v v10, (a1)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_0_i64:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma
+; ZVZIP-NEXT: vle64.v v8, (a0)
+; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; ZVZIP-NEXT: vslidedown.vi v9, v8, 2
+; ZVZIP-NEXT: vslideup.vi v8, v9, 1
+; ZVZIP-NEXT: vse64.v v8, (a1)
+; ZVZIP-NEXT: ret
entry:
%0 = load <4 x i64>, ptr %in, align 8
%shuffle.i5 = shufflevector <4 x i64> %0, <4 x i64> poison, <2 x i32> <i32 0, i32 2>
@@ -385,6 +472,17 @@ define void @vnsrl_64_i64(ptr %in, ptr %out) {
; ZIP-NEXT: ri.vunzip2b.vv v10, v8, v9
; ZIP-NEXT: vse64.v v10, (a1)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_64_i64:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma
+; ZVZIP-NEXT: vle64.v v8, (a0)
+; ZVZIP-NEXT: vmv.v.i v0, 1
+; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, mu
+; ZVZIP-NEXT: vslidedown.vi v9, v8, 2
+; ZVZIP-NEXT: vslidedown.vi v9, v8, 1, v0.t
+; ZVZIP-NEXT: vse64.v v9, (a1)
+; ZVZIP-NEXT: ret
entry:
%0 = load <4 x i64>, ptr %in, align 8
%shuffle.i5 = shufflevector <4 x i64> %0, <4 x i64> poison, <2 x i32> <i32 1, i32 3>
@@ -419,6 +517,16 @@ define void @vnsrl_0_double(ptr %in, ptr %out) {
; ZIP-NEXT: ri.vunzip2a.vv v10, v8, v9
; ZIP-NEXT: vse64.v v10, (a1)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_0_double:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma
+; ZVZIP-NEXT: vle64.v v8, (a0)
+; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; ZVZIP-NEXT: vslidedown.vi v9, v8, 2
+; ZVZIP-NEXT: vslideup.vi v8, v9, 1
+; ZVZIP-NEXT: vse64.v v8, (a1)
+; ZVZIP-NEXT: ret
entry:
%0 = load <4 x double>, ptr %in, align 8
%shuffle.i5 = shufflevector <4 x double> %0, <4 x double> poison, <2 x i32> <i32 0, i32 2>
@@ -454,6 +562,17 @@ define void @vnsrl_64_double(ptr %in, ptr %out) {
; ZIP-NEXT: ri.vunzip2b.vv v10, v8, v9
; ZIP-NEXT: vse64.v v10, (a1)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_64_double:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma
+; ZVZIP-NEXT: vle64.v v8, (a0)
+; ZVZIP-NEXT: vmv.v.i v0, 1
+; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, mu
+; ZVZIP-NEXT: vslidedown.vi v9, v8, 2
+; ZVZIP-NEXT: vslidedown.vi v9, v8, 1, v0.t
+; ZVZIP-NEXT: vse64.v v9, (a1)
+; ZVZIP-NEXT: ret
entry:
%0 = load <4 x double>, ptr %in, align 8
%shuffle.i5 = shufflevector <4 x double> %0, <4 x double> poison, <2 x i32> <i32 1, i32 3>
@@ -566,6 +685,15 @@ define void @vnsrl_0_i8_single_src(ptr %in, ptr %out) {
; ZIP-NEXT: vnsrl.wi v8, v8, 0
; ZIP-NEXT: vse8.v v8, (a1)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_0_i8_single_src:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
+; ZVZIP-NEXT: vle8.v v8, (a0)
+; ZVZIP-NEXT: vsetivli zero, 4, e8, mf8, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v8, v8, 0
+; ZVZIP-NEXT: vse8.v v8, (a1)
+; ZVZIP-NEXT: ret
entry:
%0 = load <8 x i8>, ptr %in, align 1
%shuffle.i5 = shufflevector <8 x i8> %0, <8 x i8> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
@@ -600,6 +728,15 @@ define void @vnsrl_8_i8_single_src(ptr %in, ptr %out) {
; ZIP-NEXT: vnsrl.wi v8, v8, 8
; ZIP-NEXT: vse8.v v8, (a1)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_8_i8_single_src:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
+; ZVZIP-NEXT: vle8.v v8, (a0)
+; ZVZIP-NEXT: vsetivli zero, 4, e8, mf8, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v8, v8, 8
+; ZVZIP-NEXT: vse8.v v8, (a1)
+; ZVZIP-NEXT: ret
entry:
%0 = load <8 x i8>, ptr %in, align 1
%shuffle.i5 = shufflevector <8 x i8> %0, <8 x i8> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
@@ -637,6 +774,16 @@ define void @vnsrl_0_i8_single_wideuse(ptr %in, ptr %out) {
; ZIP-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
; ZIP-NEXT: vse8.v v8, (a1)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_0_i8_single_wideuse:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
+; ZVZIP-NEXT: vle8.v v8, (a0)
+; ZVZIP-NEXT: vsetivli zero, 4, e8, mf8, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v8, v8, 0
+; ZVZIP-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
+; ZVZIP-NEXT: vse8.v v8, (a1)
+; ZVZIP-NEXT: ret
entry:
%0 = load <8 x i8>, ptr %in, align 1
%shuffle.i5 = shufflevector <8 x i8> %0, <8 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 poison, i32 poison, i32 poison, i32 poison>
@@ -684,6 +831,18 @@ define void @vnsrl_0_i32_single_src_m8(ptr %in, ptr %out) {
; ZIP-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; ZIP-NEXT: vse32.v v16, (a1)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_0_i32_single_src_m8:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: li a2, 64
+; ZVZIP-NEXT: vsetvli zero, a2, e32, m8, ta, ma
+; ZVZIP-NEXT: vle32.v v8, (a0)
+; ZVZIP-NEXT: li a0, 32
+; ZVZIP-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v16, v8, 0
+; ZVZIP-NEXT: vsetvli zero, a2, e32, m8, ta, ma
+; ZVZIP-NEXT: vse32.v v16, (a1)
+; ZVZIP-NEXT: ret
entry:
%0 = load <64 x i32>, ptr %in, align 4
%shuffle.i5 = shufflevector <64 x i32> %0, <64 x i32> poison, <64 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
@@ -729,6 +888,18 @@ define void @vnsrl_0_i32_single_src_m8_2(ptr %in, ptr %out) {
; ZIP-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; ZIP-NEXT: vse32.v v16, (a1)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_0_i32_single_src_m8_2:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: li a2, 64
+; ZVZIP-NEXT: vsetvli zero, a2, e32, m8, ta, ma
+; ZVZIP-NEXT: vle32.v v8, (a0)
+; ZVZIP-NEXT: li a0, 32
+; ZVZIP-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v16, v8, 0
+; ZVZIP-NEXT: vsetvli zero, a2, e32, m8, ta, ma
+; ZVZIP-NEXT: vse32.v v16, (a1)
+; ZVZIP-NEXT: ret
entry:
%0 = load <64 x i32>, ptr %in, align 4
%shuffle.i5 = shufflevector <64 x i32> %0, <64 x i32> poison, <64 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30, i32 32, i32 34, i32 36, i32 38, i32 40, i32 42, i32 44, i32 46, i32 48, i32 50, i32 52, i32 54, i32 56, i32 58, i32 60, i32 62, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
@@ -775,6 +946,19 @@ define void @vnsrl_0_i8_two_source(ptr %in0, ptr %in1, ptr %out) {
; ZIP-NEXT: vslideup.vi v9, v8, 4
; ZIP-NEXT: vse8.v v9, (a2)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_0_i8_two_source:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
+; ZVZIP-NEXT: vle8.v v8, (a1)
+; ZVZIP-NEXT: vle8.v v9, (a0)
+; ZVZIP-NEXT: vsetivli zero, 4, e8, mf8, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v8, v8, 0
+; ZVZIP-NEXT: vnsrl.wi v9, v9, 0
+; ZVZIP-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
+; ZVZIP-NEXT: vslideup.vi v9, v8, 4
+; ZVZIP-NEXT: vse8.v v9, (a2)
+; ZVZIP-NEXT: ret
entry:
%0 = load <8 x i8>, ptr %in0, align 1
%1 = load <8 x i8>, ptr %in1, align 1
@@ -822,6 +1006,19 @@ define void @vnsrl_8_8_two_source(ptr %in0, ptr %in1, ptr %out) {
; ZIP-NEXT: vslideup.vi v9, v8, 4
; ZIP-NEXT: vse8.v v9, (a2)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_8_8_two_source:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
+; ZVZIP-NEXT: vle8.v v8, (a1)
+; ZVZIP-NEXT: vle8.v v9, (a0)
+; ZVZIP-NEXT: vsetivli zero, 4, e8, mf8, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v8, v8, 8
+; ZVZIP-NEXT: vnsrl.wi v9, v9, 8
+; ZVZIP-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
+; ZVZIP-NEXT: vslideup.vi v9, v8, 4
+; ZVZIP-NEXT: vse8.v v9, (a2)
+; ZVZIP-NEXT: ret
entry:
%0 = load <8 x i8>, ptr %in0, align 1
%1 = load <8 x i8>, ptr %in1, align 1
@@ -869,6 +1066,19 @@ define void @vnsrl_0_i16_two_source(ptr %in0, ptr %in1, ptr %out) {
; ZIP-NEXT: vslideup.vi v9, v8, 2
; ZIP-NEXT: vse16.v v9, (a2)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_0_i16_two_source:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZVZIP-NEXT: vle16.v v8, (a1)
+; ZVZIP-NEXT: vle16.v v9, (a0)
+; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v8, v8, 0
+; ZVZIP-NEXT: vnsrl.wi v9, v9, 0
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZVZIP-NEXT: vslideup.vi v9, v8, 2
+; ZVZIP-NEXT: vse16.v v9, (a2)
+; ZVZIP-NEXT: ret
entry:
%0 = load <4 x i16>, ptr %in0, align 2
%1 = load <4 x i16>, ptr %in1, align 2
@@ -916,6 +1126,19 @@ define void @vnsrl_16_i16_two_source(ptr %in0, ptr %in1, ptr %out) {
; ZIP-NEXT: vslideup.vi v9, v8, 2
; ZIP-NEXT: vse16.v v9, (a2)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_16_i16_two_source:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZVZIP-NEXT: vle16.v v8, (a1)
+; ZVZIP-NEXT: vle16.v v9, (a0)
+; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v8, v8, 16
+; ZVZIP-NEXT: vnsrl.wi v9, v9, 16
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZVZIP-NEXT: vslideup.vi v9, v8, 2
+; ZVZIP-NEXT: vse16.v v9, (a2)
+; ZVZIP-NEXT: ret
entry:
%0 = load <4 x i16>, ptr %in0, align 2
%1 = load <4 x i16>, ptr %in1, align 2
@@ -963,6 +1186,19 @@ define void @vnsrl_0_half_two_source(ptr %in0, ptr %in1, ptr %out) {
; ZIP-NEXT: vslideup.vi v9, v8, 2
; ZIP-NEXT: vse16.v v9, (a2)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_0_half_two_source:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZVZIP-NEXT: vle16.v v8, (a1)
+; ZVZIP-NEXT: vle16.v v9, (a0)
+; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v8, v8, 0
+; ZVZIP-NEXT: vnsrl.wi v9, v9, 0
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZVZIP-NEXT: vslideup.vi v9, v8, 2
+; ZVZIP-NEXT: vse16.v v9, (a2)
+; ZVZIP-NEXT: ret
entry:
%0 = load <4 x half>, ptr %in0, align 2
%1 = load <4 x half>, ptr %in1, align 2
@@ -1010,6 +1246,19 @@ define void @vnsrl_16_half_two_source(ptr %in0, ptr %in1, ptr %out) {
; ZIP-NEXT: vslideup.vi v9, v8, 2
; ZIP-NEXT: vse16.v v9, (a2)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_16_half_two_source:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZVZIP-NEXT: vle16.v v8, (a1)
+; ZVZIP-NEXT: vle16.v v9, (a0)
+; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-NEXT: vnsrl.wi v8, v8, 16
+; ZVZIP-NEXT: vnsrl.wi v9, v9, 16
+; ZVZIP-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
+; ZVZIP-NEXT: vslideup.vi v9, v8, 2
+; ZVZIP-NEXT: vse16.v v9, (a2)
+; ZVZIP-NEXT: ret
entry:
%0 = load <4 x half>, ptr %in0, align 2
%1 = load <4 x half>, ptr %in1, align 2
@@ -1045,6 +1294,15 @@ define void @vnsrl_0_i32_two_source(ptr %in0, ptr %in1, ptr %out) {
; ZIP-NEXT: vslideup.vi v8, v9, 1
; ZIP-NEXT: vse32.v v8, (a2)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_0_i32_two_source:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-NEXT: vle32.v v8, (a0)
+; ZVZIP-NEXT: vle32.v v9, (a1)
+; ZVZIP-NEXT: vslideup.vi v8, v9, 1
+; ZVZIP-NEXT: vse32.v v8, (a2)
+; ZVZIP-NEXT: ret
entry:
%0 = load <2 x i32>, ptr %in0, align 4
%1 = load <2 x i32>, ptr %in1, align 4
@@ -1082,6 +1340,16 @@ define void @vnsrl_32_i32_two_source(ptr %in0, ptr %in1, ptr %out) {
; ZIP-NEXT: ri.vzipodd.vv v10, v8, v9
; ZIP-NEXT: vse32.v v10, (a2)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_32_i32_two_source:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
+; ZVZIP-NEXT: vle32.v v8, (a0)
+; ZVZIP-NEXT: vle32.v v9, (a1)
+; ZVZIP-NEXT: vmv.v.i v0, 1
+; ZVZIP-NEXT: vslidedown.vi v9, v8, 1, v0.t
+; ZVZIP-NEXT: vse32.v v9, (a2)
+; ZVZIP-NEXT: ret
entry:
%0 = load <2 x i32>, ptr %in0, align 4
%1 = load <2 x i32>, ptr %in1, align 4
@@ -1117,6 +1385,15 @@ define void @vnsrl_0_float_two_source(ptr %in0, ptr %in1, ptr %out) {
; ZIP-NEXT: vslideup.vi v8, v9, 1
; ZIP-NEXT: vse32.v v8, (a2)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_0_float_two_source:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-NEXT: vle32.v v8, (a0)
+; ZVZIP-NEXT: vle32.v v9, (a1)
+; ZVZIP-NEXT: vslideup.vi v8, v9, 1
+; ZVZIP-NEXT: vse32.v v8, (a2)
+; ZVZIP-NEXT: ret
entry:
%0 = load <2 x float>, ptr %in0, align 4
%1 = load <2 x float>, ptr %in1, align 4
@@ -1154,6 +1431,16 @@ define void @vnsrl_32_float_two_source(ptr %in0, ptr %in1, ptr %out) {
; ZIP-NEXT: ri.vzipodd.vv v10, v8, v9
; ZIP-NEXT: vse32.v v10, (a2)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_32_float_two_source:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
+; ZVZIP-NEXT: vle32.v v8, (a0)
+; ZVZIP-NEXT: vle32.v v9, (a1)
+; ZVZIP-NEXT: vmv.v.i v0, 1
+; ZVZIP-NEXT: vslidedown.vi v9, v8, 1, v0.t
+; ZVZIP-NEXT: vse32.v v9, (a2)
+; ZVZIP-NEXT: ret
entry:
%0 = load <2 x float>, ptr %in0, align 4
%1 = load <2 x float>, ptr %in1, align 4
@@ -1189,6 +1476,15 @@ define void @vnsrl_0_i64_two_source(ptr %in0, ptr %in1, ptr %out) {
; ZIP-NEXT: vslideup.vi v8, v9, 1
; ZIP-NEXT: vse64.v v8, (a2)
; ZIP-NEXT: ret
+;
+; ZVZIP-LABEL: vnsrl_0_i64_two_source:
+; ZVZIP: # %bb.0: # %entry
+; ZVZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; ZVZIP-NEXT: vle64.v v8, (a0)
+; ZVZI...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/192591
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