[llvm] [AMDGPU-MC] update USER_SGPR_COUNT bits for GFX1250 (PR #192579)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 16 18:47:02 PDT 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Zeng Wu (zwu-2025)
<details>
<summary>Changes</summary>
This patch updates bits for USER_SGPR_COUNT from https://llvm.org/docs/AMDGPUUsage.html#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx12-table.
---
Full diff: https://github.com/llvm/llvm-project/pull/192579.diff
5 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp (+6-5)
- (modified) llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp (+1-1)
- (modified) llvm/lib/Target/AMDGPU/SIProgramInfo.cpp (+20-14)
- (modified) llvm/lib/Target/AMDGPU/SIProgramInfo.h (+4-2)
- (added) llvm/test/CodeGen/AMDGPU/gfx125-user-sgpr-encoding.mir (+14)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
index 19ad73f4fb421..77457acfe1462 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -649,7 +649,7 @@ AMDGPUAsmPrinter::getAmdhsaKernelDescriptor(const MachineFunction &MF,
STM.getKernArgSegmentSize(F, MaxKernArgAlign), Ctx);
KernelDescriptor.compute_pgm_rsrc1 = PI.getComputePGMRSrc1(STM, Ctx);
- KernelDescriptor.compute_pgm_rsrc2 = PI.getComputePGMRSrc2(Ctx);
+ KernelDescriptor.compute_pgm_rsrc2 = PI.getComputePGMRSrc2(STM, Ctx);
KernelDescriptor.kernel_code_properties = getAmdhsaKernelCodeProperties(MF);
int64_t PGM_Rsrc3 = 1;
@@ -1371,7 +1371,8 @@ void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
/*Size=*/4);
OutStreamer->emitInt32(R_00B84C_COMPUTE_PGM_RSRC2);
- EmitResolvedOrExpr(CurrentProgramInfo.getComputePGMRSrc2(Ctx), /*Size=*/4);
+ EmitResolvedOrExpr(CurrentProgramInfo.getComputePGMRSrc2(STM, Ctx),
+ /*Size=*/4);
OutStreamer->emitInt32(R_00B860_COMPUTE_TMPRING_SIZE);
@@ -1497,7 +1498,7 @@ void AMDGPUAsmPrinter::EmitPALMetadata(const MachineFunction &MF,
if (MD->getPALMajorVersion() < 3) {
MD->setRsrc1(CC, CurrentProgramInfo.getPGMRSrc1(CC, STM, Ctx), Ctx);
if (AMDGPU::isCompute(CC)) {
- MD->setRsrc2(CC, CurrentProgramInfo.getComputePGMRSrc2(Ctx), Ctx);
+ MD->setRsrc2(CC, CurrentProgramInfo.getComputePGMRSrc2(STM, Ctx), Ctx);
} else {
const MCExpr *HasScratchBlocks =
MCBinaryExpr::createGT(CurrentProgramInfo.ScratchBlocks,
@@ -1579,7 +1580,7 @@ void AMDGPUAsmPrinter::emitPALFunctionMetadata(const MachineFunction &MF) {
CallingConv::AMDGPU_CS,
CurrentProgramInfo.getPGMRSrc1(CallingConv::AMDGPU_CS, ST, Ctx), Ctx);
MD->setRsrc2(CallingConv::AMDGPU_CS,
- CurrentProgramInfo.getComputePGMRSrc2(Ctx), Ctx);
+ CurrentProgramInfo.getComputePGMRSrc2(ST, Ctx), Ctx);
} else {
EmitPALMetadataCommon(
MD, CurrentProgramInfo, CallingConv::AMDGPU_CS, ST,
@@ -1622,7 +1623,7 @@ void AMDGPUAsmPrinter::getAmdKernelCode(AMDGPUMCKernelCodeT &Out,
Out.compute_pgm_resource1_registers =
CurrentProgramInfo.getComputePGMRSrc1(STM, Ctx);
Out.compute_pgm_resource2_registers =
- CurrentProgramInfo.getComputePGMRSrc2(Ctx);
+ CurrentProgramInfo.getComputePGMRSrc2(STM, Ctx);
Out.code_properties |= AMD_CODE_PROPERTY_IS_PTR64;
Out.is_dynamic_callstack = CurrentProgramInfo.DynamicCallStack;
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 3777adc9790e8..ab6612e422541 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -6400,7 +6400,7 @@ bool AMDGPUAsmParser::ParseDirectiveAMDHSAKernel() {
COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT, getContext());
if (ExplicitUserSGPRCount && ImpliedUserSGPRCount > *ExplicitUserSGPRCount)
- return TokError("amdgpu_user_sgpr_count smaller than than implied by "
+ return TokError("amdgpu_user_sgpr_count smaller than implied by "
"enabled user SGPRs");
if (isGFX1250Plus()) {
diff --git a/llvm/lib/Target/AMDGPU/SIProgramInfo.cpp b/llvm/lib/Target/AMDGPU/SIProgramInfo.cpp
index a3f261b87e80b..7a1120de95955 100644
--- a/llvm/lib/Target/AMDGPU/SIProgramInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIProgramInfo.cpp
@@ -136,17 +136,21 @@ static uint64_t getPGMRSrc1Reg(const SIProgramInfo &ProgInfo,
return Reg;
}
-static uint64_t getComputePGMRSrc2Reg(const SIProgramInfo &ProgInfo) {
- uint64_t Reg = S_00B84C_USER_SGPR(ProgInfo.UserSGPR) |
- S_00B84C_TRAP_HANDLER(ProgInfo.TrapHandlerEnable) |
- S_00B84C_TGID_X_EN(ProgInfo.TGIdXEnable) |
- S_00B84C_TGID_Y_EN(ProgInfo.TGIdYEnable) |
- S_00B84C_TGID_Z_EN(ProgInfo.TGIdZEnable) |
- S_00B84C_TG_SIZE_EN(ProgInfo.TGSizeEnable) |
- S_00B84C_TIDIG_COMP_CNT(ProgInfo.TIdIGCompCount) |
- S_00B84C_EXCP_EN_MSB(ProgInfo.EXCPEnMSB) |
- S_00B84C_LDS_SIZE(ProgInfo.LdsSize) |
- S_00B84C_EXCP_EN(ProgInfo.EXCPEnable);
+static uint64_t getComputePGMRSrc2Reg(const GCNSubtarget &ST,
+ const SIProgramInfo &ProgInfo) {
+ uint64_t Reg = ST.hasGFX1250Insts()
+ ? ((ProgInfo.UserSGPR & 0x3F) << 0x1)
+ : (S_00B84C_USER_SGPR(ProgInfo.UserSGPR) |
+ S_00B84C_TRAP_HANDLER(ProgInfo.TrapHandlerEnable));
+
+ Reg |= S_00B84C_TGID_X_EN(ProgInfo.TGIdXEnable) |
+ S_00B84C_TGID_Y_EN(ProgInfo.TGIdYEnable) |
+ S_00B84C_TGID_Z_EN(ProgInfo.TGIdZEnable) |
+ S_00B84C_TG_SIZE_EN(ProgInfo.TGSizeEnable) |
+ S_00B84C_TIDIG_COMP_CNT(ProgInfo.TIdIGCompCount) |
+ S_00B84C_EXCP_EN_MSB(ProgInfo.EXCPEnMSB) |
+ S_00B84C_LDS_SIZE(ProgInfo.LdsSize) |
+ S_00B84C_EXCP_EN(ProgInfo.EXCPEnable);
return Reg;
}
@@ -189,16 +193,18 @@ const MCExpr *SIProgramInfo::getPGMRSrc1(CallingConv::ID CC,
return MCBinaryExpr::createOr(RegExpr, Res, Ctx);
}
-const MCExpr *SIProgramInfo::getComputePGMRSrc2(MCContext &Ctx) const {
- uint64_t Reg = getComputePGMRSrc2Reg(*this);
+const MCExpr *SIProgramInfo::getComputePGMRSrc2(const GCNSubtarget &ST,
+ MCContext &Ctx) const {
+ uint64_t Reg = getComputePGMRSrc2Reg(ST, *this);
const MCExpr *RegExpr = MCConstantExpr::create(Reg, Ctx);
return MCBinaryExpr::createOr(ScratchEnable, RegExpr, Ctx);
}
const MCExpr *SIProgramInfo::getPGMRSrc2(CallingConv::ID CC,
+ const GCNSubtarget &ST,
MCContext &Ctx) const {
if (AMDGPU::isCompute(CC))
- return getComputePGMRSrc2(Ctx);
+ return getComputePGMRSrc2(ST, Ctx);
return MCConstantExpr::create(0, Ctx);
}
diff --git a/llvm/lib/Target/AMDGPU/SIProgramInfo.h b/llvm/lib/Target/AMDGPU/SIProgramInfo.h
index 171c4a313a53b..947b473142a1f 100644
--- a/llvm/lib/Target/AMDGPU/SIProgramInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIProgramInfo.h
@@ -117,8 +117,10 @@ struct LLVM_EXTERNAL_VISIBILITY SIProgramInfo {
MCContext &Ctx) const;
/// Compute the value of the ComputePGMRsrc2 register.
- const MCExpr *getComputePGMRSrc2(MCContext &Ctx) const;
- const MCExpr *getPGMRSrc2(CallingConv::ID CC, MCContext &Ctx) const;
+ const MCExpr *getComputePGMRSrc2(const GCNSubtarget &ST,
+ MCContext &Ctx) const;
+ const MCExpr *getPGMRSrc2(CallingConv::ID CC, const GCNSubtarget &ST,
+ MCContext &Ctx) const;
};
} // namespace llvm
diff --git a/llvm/test/CodeGen/AMDGPU/gfx125-user-sgpr-encoding.mir b/llvm/test/CodeGen/AMDGPU/gfx125-user-sgpr-encoding.mir
new file mode 100644
index 0000000000000..b509491313a56
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/gfx125-user-sgpr-encoding.mir
@@ -0,0 +1,14 @@
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 < %s -o - | llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx1250 -filetype=null
+
+define amdgpu_kernel void @many_inreg_i32(
+ i32 inreg %a0, i32 inreg %a1, i32 inreg %a2, i32 inreg %a3,
+ i32 inreg %a4, i32 inreg %a5, i32 inreg %a6, i32 inreg %a7,
+ i32 inreg %a8, i32 inreg %a9, i32 inreg %a10, i32 inreg %a11,
+ i32 inreg %a12, i32 inreg %a13, i32 inreg %a14, i32 inreg %a15,
+ i32 inreg %a16, i32 inreg %a17, i32 inreg %a18, i32 inreg %a19,
+ i32 inreg %a20, i32 inreg %a21, i32 inreg %a22, i32 inreg %a23,
+ i32 inreg %a24, i32 inreg %a25, i32 inreg %a26, i32 inreg %a27,
+ i32 inreg %a28, i32 inreg %a29, i32 inreg %a30, i32 inreg %a31,
+ i32 inreg %a28, i32 inreg %a29, i32 inreg %a30, i32 inreg %a32) {
+ ret void
+}
``````````
</details>
https://github.com/llvm/llvm-project/pull/192579
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