[llvm] [PowerPC] Add bctar instruction (ISA 2.07) (PR #187322)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 16 18:05:40 PDT 2026
https://github.com/Scottcjn updated https://github.com/llvm/llvm-project/pull/187322
>From 54f07727a58f13361df4ace948346a725b09ace5 Mon Sep 17 00:00:00 2001
From: Scott Boudreaux <121303252+Scottcjn at users.noreply.github.com>
Date: Wed, 18 Mar 2026 11:27:44 -0500
Subject: [PATCH 1/3] [PowerPC] Add bctar instruction support (ISA 2.07 /
POWER8)
Add assembly/disassembly support for the bctar (Branch Conditional to
Target Address Register) instruction family, introduced in Power ISA
2.07 (POWER8). The TAR register provides an additional branch target
alongside LR and CTR.
Instruction definitions added:
- gBCTAR/gBCTARL: Generic bctar/bctarl with BO, BI, BH operands
- BCCTAR/BCCTARL: Predicated forms for extended mnemonics
Mnemonics added:
- bctar/bctarl: Base conditional branch to TAR (3-operand and 2-operand)
- bttar/bftar/bttarl/bftarl: Simple true/false mnemonics with +/- hints
- blttar/bgttar/beqtar/...: Extended condition mnemonics with +/- hints
and link variants (blttarl, bgttarl+, etc.)
- bdnztar/bdztar: Decrement CTR and branch to TAR, with +/- hints and
link variants
All new definitions are gated on the IsISA2_07 predicate.
Encoding: XL-form with opcode=19, XO=560 (cf. bcctr XO=528, bclr XO=16).
Fixes #176864
Co-Authored-By: Claude Opus 4.6 (1M context) <noreply at anthropic.com>
---
llvm/lib/Target/PowerPC/PPCInstrInfo.td | 81 ++++++++++++--
llvm/test/MC/PowerPC/ppc64-encoding-bctar.s | 111 ++++++++++++++++++++
2 files changed, 186 insertions(+), 6 deletions(-)
create mode 100644 llvm/test/MC/PowerPC/ppc64-encoding-bctar.s
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index 3271e4d279f56..0e8209bcb548c 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -1590,6 +1590,24 @@ let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, hasSideEffects = 0 in {
"bcctr 4, $BI, 0", IIC_BrB, []>;
}
}
+
+ // bctar - Branch Conditional to TAR (ISA 2.07 / POWER8)
+ let Predicates = [IsISA2_07] in {
+ let isBranch = 1, isIndirectBranch = 1 in {
+ let isCodeGenOnly = 1 in {
+ def BCCTAR : XLForm_2_br<19, 560, 0, (outs), (ins (pred $BIBO, $CR):$cond),
+ "b${cond:cc}tar${cond:pm} ${cond:reg}", IIC_BrB,
+ []>;
+ }
+ }
+ let isCall = 1, Defs = [LR] in {
+ let isCodeGenOnly = 1 in {
+ def BCCTARL : XLForm_2_br<19, 560, 1, (outs), (ins (pred $BIBO, $CR):$cond),
+ "b${cond:cc}tarl${cond:pm} ${cond:reg}", IIC_BrB,
+ []>;
+ }
+ }
+ }
}
// Set the float rounding mode.
@@ -5223,6 +5241,18 @@ let PPC970_Unit = 7, isBranch = 1, hasSideEffects = 0 in {
def gBCCTRL : XLForm_2<19, 528, 1, (outs),
(ins u5imm:$BO, crbitrc:$BI, i32imm:$BH),
"bcctrl $BO, $BI, $BH", IIC_BrB, []>;
+
+ // bctar/bctarl - Branch Conditional to TAR (ISA 2.07 / POWER8)
+ let Predicates = [IsISA2_07] in {
+ let Uses = [RM] in
+ def gBCTAR : XLForm_2<19, 560, 0, (outs),
+ (ins u5imm:$BO, crbitrc:$BI, i32imm:$BH),
+ "bctar $BO, $BI, $BH", IIC_BrB, []>;
+ let Defs = [LR], Uses = [RM] in
+ def gBCTARL : XLForm_2<19, 560, 1, (outs),
+ (ins u5imm:$BO, crbitrc:$BI, i32imm:$BH),
+ "bctarl $BO, $BI, $BH", IIC_BrB, []>;
+ }
}
multiclass BranchSimpleMnemonicAT<string pm, int at> {
@@ -5242,6 +5272,10 @@ def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>;
def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>;
def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>;
def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>;
+let Predicates = [IsISA2_07] in {
+def : InstAlias<"bctar $bo, $bi", (gBCTAR u5imm:$bo, crbitrc:$bi, 0)>;
+def : InstAlias<"bctarl $bo, $bi", (gBCTARL u5imm:$bo, crbitrc:$bi, 0)>;
+}
multiclass BranchSimpleMnemonic1<string name, string pm, int bo> {
def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>;
@@ -5256,17 +5290,40 @@ multiclass BranchSimpleMnemonic2<string name, string pm, int bo>
def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>;
def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>;
}
-defm : BranchSimpleMnemonic2<"t", "", 12>;
-defm : BranchSimpleMnemonic2<"f", "", 4>;
-defm : BranchSimpleMnemonic2<"t", "-", 14>;
-defm : BranchSimpleMnemonic2<"f", "-", 6>;
-defm : BranchSimpleMnemonic2<"t", "+", 15>;
-defm : BranchSimpleMnemonic2<"f", "+", 7>;
+multiclass BranchSimpleMnemonic3<string name, string pm, int bo>
+ : BranchSimpleMnemonic2<name, pm, bo> {
+ let Predicates = [IsISA2_07] in {
+ def : InstAlias<"b"#name#"tar"#pm#" $bi", (gBCTAR bo, crbitrc:$bi, 0)>;
+ def : InstAlias<"b"#name#"tarl"#pm#" $bi", (gBCTARL bo, crbitrc:$bi, 0)>;
+ }
+}
+defm : BranchSimpleMnemonic3<"t", "", 12>;
+defm : BranchSimpleMnemonic3<"f", "", 4>;
+defm : BranchSimpleMnemonic3<"t", "-", 14>;
+defm : BranchSimpleMnemonic3<"f", "-", 6>;
+defm : BranchSimpleMnemonic3<"t", "+", 15>;
+defm : BranchSimpleMnemonic3<"f", "+", 7>;
defm : BranchSimpleMnemonic1<"dnzt", "", 8>;
defm : BranchSimpleMnemonic1<"dnzf", "", 0>;
defm : BranchSimpleMnemonic1<"dzt", "", 10>;
defm : BranchSimpleMnemonic1<"dzf", "", 2>;
+// bdnztar/bdztar - Branch Decrement CTR to TAR (ISA 2.07)
+let Predicates = [IsISA2_07] in {
+def : InstAlias<"bdnztar", (gBCTAR 16, CR0LT, 0)>;
+def : InstAlias<"bdnztar+", (gBCTAR 25, CR0LT, 0)>;
+def : InstAlias<"bdnztar-", (gBCTAR 24, CR0LT, 0)>;
+def : InstAlias<"bdnztarl", (gBCTARL 16, CR0LT, 0)>;
+def : InstAlias<"bdnztarl+", (gBCTARL 25, CR0LT, 0)>;
+def : InstAlias<"bdnztarl-", (gBCTARL 24, CR0LT, 0)>;
+def : InstAlias<"bdztar", (gBCTAR 18, CR0LT, 0)>;
+def : InstAlias<"bdztar+", (gBCTAR 27, CR0LT, 0)>;
+def : InstAlias<"bdztar-", (gBCTAR 26, CR0LT, 0)>;
+def : InstAlias<"bdztarl", (gBCTARL 18, CR0LT, 0)>;
+def : InstAlias<"bdztarl+", (gBCTARL 27, CR0LT, 0)>;
+def : InstAlias<"bdztarl-", (gBCTARL 26, CR0LT, 0)>;
+}
+
multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> {
def : InstAlias<"b"#name#pm#" $cc, $dst",
(BCC (pred bibo, crrc:$cc), condbrtarget:$dst)>;
@@ -5307,6 +5364,18 @@ multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> {
(BCCCTRL (pred bibo, crrc:$cc))>;
def : InstAlias<"b"#name#"ctrl"#pm,
(BCCCTRL (pred bibo, CR0))>;
+
+ let Predicates = [IsISA2_07] in {
+ def : InstAlias<"b"#name#"tar"#pm#" $cc",
+ (BCCTAR (pred bibo, crrc:$cc))>;
+ def : InstAlias<"b"#name#"tar"#pm,
+ (BCCTAR (pred bibo, CR0))>;
+
+ def : InstAlias<"b"#name#"tarl"#pm#" $cc",
+ (BCCTARL (pred bibo, crrc:$cc))>;
+ def : InstAlias<"b"#name#"tarl"#pm,
+ (BCCTARL (pred bibo, CR0))>;
+ }
}
multiclass BranchExtendedMnemonic<string name, int bibo> {
defm : BranchExtendedMnemonicPM<name, "", bibo>;
diff --git a/llvm/test/MC/PowerPC/ppc64-encoding-bctar.s b/llvm/test/MC/PowerPC/ppc64-encoding-bctar.s
new file mode 100644
index 0000000000000..02cf81866a967
--- /dev/null
+++ b/llvm/test/MC/PowerPC/ppc64-encoding-bctar.s
@@ -0,0 +1,111 @@
+# RUN: llvm-mc -triple powerpc64-unknown-linux-gnu -mcpu=pwr8 -show-encoding %s | \
+# RUN: FileCheck -check-prefix=CHECK-BE %s
+# RUN: llvm-mc -triple powerpc64le-unknown-linux-gnu -mcpu=pwr8 -show-encoding %s | \
+# RUN: FileCheck -check-prefix=CHECK-LE %s
+
+# ISA 2.07 (POWER8) Branch Conditional to Target Address Register
+
+# bctar (generic form, 3-operand)
+# CHECK-BE: bctar 4, 10, 3 # encoding: [0x4c,0x8a,0x1c,0x60]
+# CHECK-LE: bctar 4, 10, 3 # encoding: [0x60,0x1c,0x8a,0x4c]
+ bctar 4, 10, 3
+# CHECK-BE: bctar 4, 10 # encoding: [0x4c,0x8a,0x04,0x60]
+# CHECK-LE: bctar 4, 10 # encoding: [0x60,0x04,0x8a,0x4c]
+ bctar 4, 10
+# CHECK-BE: bctarl 4, 10, 3 # encoding: [0x4c,0x8a,0x1c,0x61]
+# CHECK-LE: bctarl 4, 10, 3 # encoding: [0x61,0x1c,0x8a,0x4c]
+ bctarl 4, 10, 3
+# CHECK-BE: bctarl 4, 10 # encoding: [0x4c,0x8a,0x04,0x61]
+# CHECK-LE: bctarl 4, 10 # encoding: [0x61,0x04,0x8a,0x4c]
+ bctarl 4, 10
+
+# bttar/bftar (simple mnemonics print as generic bctar)
+# CHECK-BE: bctar 12, 2 # encoding: [0x4d,0x82,0x04,0x60]
+# CHECK-LE: bctar 12, 2 # encoding: [0x60,0x04,0x82,0x4d]
+ bttar 2
+# CHECK-BE: bctar 4, 2 # encoding: [0x4c,0x82,0x04,0x60]
+# CHECK-LE: bctar 4, 2 # encoding: [0x60,0x04,0x82,0x4c]
+ bftar 2
+# CHECK-BE: bctarl 12, 2 # encoding: [0x4d,0x82,0x04,0x61]
+# CHECK-LE: bctarl 12, 2 # encoding: [0x61,0x04,0x82,0x4d]
+ bttarl 2
+# CHECK-BE: bctarl 4, 2 # encoding: [0x4c,0x82,0x04,0x61]
+# CHECK-LE: bctarl 4, 2 # encoding: [0x61,0x04,0x82,0x4c]
+ bftarl 2
+
+# bttar/bftar with prediction hints
+# CHECK-BE: bctar 15, 2 # encoding: [0x4d,0xe2,0x04,0x60]
+# CHECK-LE: bctar 15, 2 # encoding: [0x60,0x04,0xe2,0x4d]
+ bttar+ 2
+# CHECK-BE: bctar 14, 2 # encoding: [0x4d,0xc2,0x04,0x60]
+# CHECK-LE: bctar 14, 2 # encoding: [0x60,0x04,0xc2,0x4d]
+ bttar- 2
+# CHECK-BE: bctar 7, 2 # encoding: [0x4c,0xe2,0x04,0x60]
+# CHECK-LE: bctar 7, 2 # encoding: [0x60,0x04,0xe2,0x4c]
+ bftar+ 2
+# CHECK-BE: bctar 6, 2 # encoding: [0x4c,0xc2,0x04,0x60]
+# CHECK-LE: bctar 6, 2 # encoding: [0x60,0x04,0xc2,0x4c]
+ bftar- 2
+
+# Extended mnemonics (blttar, bgttar, etc.)
+# CHECK-BE: blttar 0 # encoding: [0x4d,0x80,0x04,0x60]
+# CHECK-LE: blttar 0 # encoding: [0x60,0x04,0x80,0x4d]
+ blttar
+# CHECK-BE: blttar 2 # encoding: [0x4d,0x88,0x04,0x60]
+# CHECK-LE: blttar 2 # encoding: [0x60,0x04,0x88,0x4d]
+ blttar 2
+# CHECK-BE: blttarl 0 # encoding: [0x4d,0x80,0x04,0x61]
+# CHECK-LE: blttarl 0 # encoding: [0x61,0x04,0x80,0x4d]
+ blttarl
+# CHECK-BE: blttarl 2 # encoding: [0x4d,0x88,0x04,0x61]
+# CHECK-LE: blttarl 2 # encoding: [0x61,0x04,0x88,0x4d]
+ blttarl 2
+
+# CHECK-BE: bgttar 2 # encoding: [0x4d,0x89,0x04,0x60]
+# CHECK-LE: bgttar 2 # encoding: [0x60,0x04,0x89,0x4d]
+ bgttar 2
+# CHECK-BE: beqtar 2 # encoding: [0x4d,0x8a,0x04,0x60]
+# CHECK-LE: beqtar 2 # encoding: [0x60,0x04,0x8a,0x4d]
+ beqtar 2
+
+# Extended mnemonics with prediction hints
+# CHECK-BE: blttar+ 0 # encoding: [0x4d,0xe0,0x04,0x60]
+# CHECK-LE: blttar+ 0 # encoding: [0x60,0x04,0xe0,0x4d]
+ blttar+
+# CHECK-BE: blttar- 0 # encoding: [0x4d,0xc0,0x04,0x60]
+# CHECK-LE: blttar- 0 # encoding: [0x60,0x04,0xc0,0x4d]
+ blttar-
+# CHECK-BE: blttarl+ 0 # encoding: [0x4d,0xe0,0x04,0x61]
+# CHECK-LE: blttarl+ 0 # encoding: [0x61,0x04,0xe0,0x4d]
+ blttarl+
+# CHECK-BE: blttarl- 0 # encoding: [0x4d,0xc0,0x04,0x61]
+# CHECK-LE: blttarl- 0 # encoding: [0x61,0x04,0xc0,0x4d]
+ blttarl-
+
+# bdnztar/bdztar
+# CHECK-BE: bctar 16, 0, 0 # encoding: [0x4e,0x00,0x04,0x60]
+# CHECK-LE: bctar 16, 0, 0 # encoding: [0x60,0x04,0x00,0x4e]
+ bdnztar
+# CHECK-BE: bctar 18, 0, 0 # encoding: [0x4e,0x40,0x04,0x60]
+# CHECK-LE: bctar 18, 0, 0 # encoding: [0x60,0x04,0x40,0x4e]
+ bdztar
+# CHECK-BE: bctarl 16, 0, 0 # encoding: [0x4e,0x00,0x04,0x61]
+# CHECK-LE: bctarl 16, 0, 0 # encoding: [0x61,0x04,0x00,0x4e]
+ bdnztarl
+# CHECK-BE: bctarl 18, 0, 0 # encoding: [0x4e,0x40,0x04,0x61]
+# CHECK-LE: bctarl 18, 0, 0 # encoding: [0x61,0x04,0x40,0x4e]
+ bdztarl
+
+# bdnztar/bdztar with prediction hints
+# CHECK-BE: bctar 25, 0, 0 # encoding: [0x4f,0x20,0x04,0x60]
+# CHECK-LE: bctar 25, 0, 0 # encoding: [0x60,0x04,0x20,0x4f]
+ bdnztar+
+# CHECK-BE: bctar 24, 0, 0 # encoding: [0x4f,0x00,0x04,0x60]
+# CHECK-LE: bctar 24, 0, 0 # encoding: [0x60,0x04,0x00,0x4f]
+ bdnztar-
+# CHECK-BE: bctar 27, 0, 0 # encoding: [0x4f,0x60,0x04,0x60]
+# CHECK-LE: bctar 27, 0, 0 # encoding: [0x60,0x04,0x60,0x4f]
+ bdztar+
+# CHECK-BE: bctar 26, 0, 0 # encoding: [0x4f,0x40,0x04,0x60]
+# CHECK-LE: bctar 26, 0, 0 # encoding: [0x60,0x04,0x40,0x4f]
+ bdztar-
>From 3dd27bde46a9e76111405e0eadf3169752b5c53d Mon Sep 17 00:00:00 2001
From: AutoJanitor <121303252+Scottcjn at users.noreply.github.com>
Date: Thu, 16 Apr 2026 20:05:15 -0500
Subject: [PATCH 2/3] [PowerPC] Add 64-bit BCCTAR8/BCCTARL8 variants for bctar
(addresses review)
Mirrors the BCCTR/BCCTR8 and BCCTRL/BCCCTRL8 split: 64-bit code paths
need variants that Def LR8 rather than LR, matching BLR/BLR8.
- BCCTAR8 (non-linking, IsPPC64) in isTerminator/isBarrier scope
- BCCTARL8 (linking, IsPPC64) in Defs=[LR8] scope with Uses=[RM]
Addresses @lei137 review on llvm/llvm-project#187322.
---
llvm/lib/Target/PowerPC/PPCInstr64Bit.td | 28 ++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
index 2b62654b08986..7a3a96c946ba6 100644
--- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -154,6 +154,34 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR8], hasSideEffects = 0 in {
}
}
+// bctar8 - Branch Conditional to Target Address Register (ISA 2.07 / POWER8)
+// 64-bit variant, mirrors BCCTR/BCCTR8 split.
+let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, hasSideEffects = 0 in {
+ let Predicates = [IsISA2_07] in {
+ let isBranch = 1, isIndirectBranch = 1 in {
+ let isCodeGenOnly = 1 in {
+ def BCCTAR8 : XLForm_2_br<19, 560, 0, (outs), (ins (pred $BIBO, $CR):$cond),
+ "b${cond:cc}tar${cond:pm} ${cond:reg}", IIC_BrB,
+ []>, Requires<[IsPPC64]>;
+ }
+ }
+ }
+}
+
+// bctarl8 - Branch Conditional Link to Target Address Register (ISA 2.07 / POWER8)
+// 64-bit variant with LR8 def, mirrors BCCTRL/BCCCTRL8 split.
+let isCall = 1, PPC970_Unit = 7, Defs = [LR8], hasSideEffects = 0 in {
+ let Predicates = [IsISA2_07] in {
+ let Uses = [RM] in {
+ let isCodeGenOnly = 1 in {
+ def BCCTARL8 : XLForm_2_br<19, 560, 1, (outs), (ins (pred $BIBO, $CR):$cond),
+ "b${cond:cc}tarl${cond:pm} ${cond:reg}", IIC_BrB,
+ []>, Requires<[IsPPC64]>;
+ }
+ }
+ }
+}
+
let isCall = 1, PPC970_Unit = 7, Defs = [LR8, RM], hasSideEffects = 0,
isCodeGenOnly = 1, Uses = [RM] in {
// Convenient aliases for call instructions
>From 157ed0dc4c6509470640233cdcdbaac34f891c27 Mon Sep 17 00:00:00 2001
From: AutoJanitor <121303252+Scottcjn at users.noreply.github.com>
Date: Thu, 16 Apr 2026 20:05:24 -0500
Subject: [PATCH 3/3] [PowerPC][test] Add disassembly tests for bctar
(addresses review)
New ppc64-encoding-bctar.txt exercises the MC disassembler on both BE
and LE powerpc64 for generic bctar/bctarl, simple mnemonics (bttar/bftar),
prediction hints, extended mnemonics (blttar/bgttar/beqtar), and the
bdnztar/bdztar forms that decode as generic bctar with BO values.
Addresses @lei137 review on llvm/llvm-project#187322.
---
.../PowerPC/ppc64-encoding-bctar.txt | 59 +++++++++++++++++++
1 file changed, 59 insertions(+)
create mode 100644 llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-bctar.txt
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-bctar.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-bctar.txt
new file mode 100644
index 0000000000000..43c27f1bfd31d
--- /dev/null
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-bctar.txt
@@ -0,0 +1,59 @@
+# RUN: llvm-mc --disassemble %s -triple powerpc64-unknown-unknown -mcpu=pwr8 | FileCheck %s
+# RUN: llvm-mc --disassemble %s -triple powerpc64le-unknown-unknown -mcpu=pwr8 | FileCheck %s
+
+# ISA 2.07 (POWER8) Branch Conditional to Target Address Register
+# Paired with llvm/test/MC/PowerPC/ppc64-encoding-bctar.s
+
+# Generic bctar / bctarl (3-operand and 2-operand forms)
+# CHECK: bctar 4, 10, 3
+0x4c 0x8a 0x1c 0x60
+# CHECK: bctar 4, 10
+0x4c 0x8a 0x04 0x60
+# CHECK: bctarl 4, 10, 3
+0x4c 0x8a 0x1c 0x61
+# CHECK: bctarl 4, 10
+0x4c 0x8a 0x04 0x61
+
+# Simple mnemonics (bttar/bftar) decode to generic bctar with BO value
+# CHECK: bctar 12, 2
+0x4d 0x82 0x04 0x60
+# CHECK: bctar 4, 2
+0x4c 0x82 0x04 0x60
+# CHECK: bctarl 12, 2
+0x4d 0x82 0x04 0x61
+# CHECK: bctarl 4, 2
+0x4c 0x82 0x04 0x61
+
+# Prediction hints (+/-)
+# CHECK: bctar 15, 2
+0x4d 0xe2 0x04 0x60
+# CHECK: bctar 14, 2
+0x4d 0xc2 0x04 0x60
+# CHECK: bctar 7, 2
+0x4c 0xe2 0x04 0x60
+# CHECK: bctar 6, 2
+0x4c 0xc2 0x04 0x60
+
+# Extended mnemonics that round-trip (blttar / bgttar / beqtar)
+# CHECK: blttar 0
+0x4d 0x80 0x04 0x60
+# CHECK: blttar 2
+0x4d 0x88 0x04 0x60
+# CHECK: blttarl 0
+0x4d 0x80 0x04 0x61
+# CHECK: blttarl 2
+0x4d 0x88 0x04 0x61
+# CHECK: bgttar 2
+0x4d 0x89 0x04 0x60
+# CHECK: beqtar 2
+0x4d 0x8a 0x04 0x60
+
+# bdnztar / bdztar decode as generic bctar BO={16,18,24,25,26,27}, BI=0
+# CHECK: bctar 16, 0, 0
+0x4e 0x00 0x04 0x60
+# CHECK: bctar 18, 0, 0
+0x4e 0x40 0x04 0x60
+# CHECK: bctarl 16, 0, 0
+0x4e 0x00 0x04 0x61
+# CHECK: bctarl 18, 0, 0
+0x4e 0x40 0x04 0x61
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