[llvm] [VPlan] Scalarize to first-lane-only directly on VPlan (PR #184267)

[Andrei Elovikov via llvm-commits]

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@@ -485,6 +485,12 @@ struct VPlanTransforms {
                                          VPRecipeBuilder &RecipeBuilder,
                                          VPCostContext &CostCtx,
                                          LoopVectorizationLegality &Legal);
+
+  /// Make VPlan-based scalarization decision prior to delegating to the ones
+  /// made by the legacy CM. Only transforms "usesFirstLaneOnly` def-use chains
+  /// enabled by prior widening of consecutive memory operations for now.
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eas wrote:

> if we simply narrow the load/store without creating an interleave group?

what do you mean by that?

Current flow: 
1) Legacy CM makes decisions about memory operations (both unit-strided **and** interleave groups)
2) Legacy CM uses all decisions from 1) to scalarize address computations used in those memory operations
3) We go to VPlan and lower memory decision in https://github.com/llvm/llvm-project/blob/9f74e0f7df988977a643f847b83ce77b93780442/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp#L7842-L7843 However, only strided memory ops produce something where information about pointer being used from first lane only is reflected in VPlan at that point. Interleave groups are indistinguishable from gathers/scatters at that point (to the best of my understanding).
4) We use **CM's** decision to scalarize address chain computation in VPlan immediately after that in the loop at https://github.com/llvm/llvm-project/blob/9f74e0f7df988977a643f847b83ce77b93780442/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp#L7845-L7849 that has the following TODO: https://github.com/llvm/llvm-project/blob/9f74e0f7df988977a643f847b83ce77b93780442/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp#L7861-L7863

I'm inserting this pass between 3) and 4), but the VPlan itself has no information about interleave groups at that point, so this pass has no way to figure out that this particular address computation is only used at first lane for operations belonging to an interleave group.


https://github.com/llvm/llvm-project/pull/184267