[llvm] [AMDGPU][GlobalIsel] Add RegBankLegalize rules and lowering for G_AMDGPU_S_BUFFER_LOAD (PR #192480)

[Petar Avramovic via llvm-commits]

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@@ -300,6 +300,73 @@ bool RegBankLegalizeHelper::executeInWaterfallLoop(MachineIRBuilder &B,
   return true;
 }
 
+// Analyze a combined offset from an llvm.amdgcn.s.buffer intrinsic and store
+// the three offsets (voffset, soffset and instoffset)
+unsigned RegBankLegalizeHelper::setBufferOffsets(
+    MachineIRBuilder &B, Register CombinedOffset, Register &VOffsetReg,
+    Register &SOffsetReg, int64_t &InstOffsetVal, Align Alignment) {
+  const GCNSubtarget &ST = B.getMF().getSubtarget<GCNSubtarget>();
+  const SIInstrInfo &TII = *ST.getInstrInfo();
+  if (std::optional<int64_t> Imm =
+          getIConstantVRegSExtVal(CombinedOffset, MRI)) {
+    uint32_t SOffset, ImmOffset;
+    if (TII.splitMUBUFOffset(*Imm, SOffset, ImmOffset, Alignment)) {
+      VOffsetReg = B.buildConstant({VgprRB, S32}, 0).getReg(0);
+      SOffsetReg = B.buildConstant({SgprRB, S32}, SOffset).getReg(0);
+      InstOffsetVal = ImmOffset;
+      return SOffset + ImmOffset;
+    }
+  }
+  Register Base;
+  unsigned Offset;
+  std::tie(Base, Offset) =
+      AMDGPU::getBaseWithConstantOffset(MRI, CombinedOffset);
+  uint32_t SOffset, ImmOffset;
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petar-avramovic wrote:

I am a little unsure if it is correct to ask if bank is equal to something here.
Overall all the pattern matching with register banks feels like a regbankcombiner material, would it be possible to generate conservatively correct offset registers (I assume use VOffsetReg) and do this folding later

https://github.com/llvm/llvm-project/pull/192480