[llvm] AMDGPU/GlobalISel: RegBankLegalize rules for wave_reduce intrinsics (PR #192377)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 16 09:57:28 PDT 2026
https://github.com/vangthao95 updated https://github.com/llvm/llvm-project/pull/192377
>From 8868356708e51b87955423d4fae1124691d11080 Mon Sep 17 00:00:00 2001
From: Vang Thao <Vang.Thao at amd.com>
Date: Wed, 15 Apr 2026 21:59:37 -0400
Subject: [PATCH 1/2] AMDGPU/GlobalISel: RegBankLegalize rules for wave_reduce
intrinsics
---
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 8 +-
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll | 277 ++++----
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll | 220 ++++---
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll | 215 +++---
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll | 621 ++++++++++--------
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll | 621 ++++++++++--------
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll | 215 +++---
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll | 220 ++++---
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll | 220 ++++---
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll | 220 ++++---
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll | 297 +++++----
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll | 65 +-
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll | 65 +-
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll | 239 ++++---
14 files changed, 1973 insertions(+), 1530 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 315f006dada50..8b17bd67e0e8c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -1630,7 +1630,13 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Uni(S32, {{UniInVgprS32}, {IntrId, Vgpr32, Vgpr32, Vgpr32}})
.Div(S32, {{Vgpr32}, {IntrId, Vgpr32, Vgpr32, Vgpr32}});
- addRulesForIOpcs({amdgcn_wave_reduce_umax, amdgcn_wave_reduce_umin}, Standard)
+ addRulesForIOpcs(
+ {amdgcn_wave_reduce_add, amdgcn_wave_reduce_and, amdgcn_wave_reduce_fadd,
+ amdgcn_wave_reduce_fmax, amdgcn_wave_reduce_fmin,
+ amdgcn_wave_reduce_fsub, amdgcn_wave_reduce_max, amdgcn_wave_reduce_min,
+ amdgcn_wave_reduce_or, amdgcn_wave_reduce_sub, amdgcn_wave_reduce_umax,
+ amdgcn_wave_reduce_umin, amdgcn_wave_reduce_xor},
+ Standard)
.Uni(S32, {{Sgpr32}, {IntrId, Sgpr32}})
.Div(S32, {{Sgpr32ToVgprDst}, {IntrId, VgprB32}})
.Uni(S64, {{Sgpr64}, {IntrId, Sgpr64}})
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
index b78b580d3ed59..0d0554266fdea 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
@@ -1,16 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=0 < %s | FileCheck -check-prefixes=GFX8DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=1 < %s | FileCheck -check-prefixes=GFX8GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX8GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=0 < %s | FileCheck -check-prefixes=GFX9DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=1 < %s | FileCheck -check-prefixes=GFX9GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX9GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1064DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1064GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1064GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1032DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1032GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1032GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1164DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1164GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1164GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1132DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1132GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1132GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -global-isel=0 < %s | FileCheck -check-prefixes=GFX12DAGISEL %s
define amdgpu_kernel void @uniform_value(ptr addrspace(1) %out, i32 %in) {
@@ -2349,7 +2349,7 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX8GISEL-LABEL: divergent_cfg:
; GFX8GISEL: ; %bb.0: ; %entry
; GFX8GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v0
-; GFX8GISEL-NEXT: ; implicit-def: $sgpr6
+; GFX8GISEL-NEXT: ; implicit-def: $sgpr2
; GFX8GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX8GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
; GFX8GISEL-NEXT: s_cbranch_execz .LBB6_2
@@ -2359,10 +2359,12 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX8GISEL-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
; GFX8GISEL-NEXT: ; implicit-def: $vgpr0
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8GISEL-NEXT: s_mul_i32 s6, s6, s2
+; GFX8GISEL-NEXT: s_mul_i32 s2, s6, s2
; GFX8GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX8GISEL-NEXT: s_andn2_saveexec_b64 s[0:1], s[0:1]
-; GFX8GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX8GISEL-NEXT: s_or_saveexec_b64 s[0:1], s[0:1]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s2
+; GFX8GISEL-NEXT: s_xor_b64 exec, exec, s[0:1]
+; GFX8GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX8GISEL-NEXT: ; %bb.3: ; %if
; GFX8GISEL-NEXT: s_mov_b64 s[2:3], exec
; GFX8GISEL-NEXT: s_mov_b32 s6, 0
@@ -2373,14 +2375,15 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX8GISEL-NEXT: s_add_i32 s6, s6, s8
; GFX8GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX8GISEL-NEXT: .LBB6_5: ; %endif
+; GFX8GISEL-NEXT: ; %bb.5:
+; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s6
+; GFX8GISEL-NEXT: .LBB6_6: ; %endif
; GFX8GISEL-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX8GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s6
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s1
-; GFX8GISEL-NEXT: flat_store_dword v[0:1], v2
+; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
+; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
+; GFX8GISEL-NEXT: flat_store_dword v[2:3], v1
; GFX8GISEL-NEXT: s_endpgm
;
; GFX9DAGISEL-LABEL: divergent_cfg:
@@ -2425,7 +2428,7 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX9GISEL-LABEL: divergent_cfg:
; GFX9GISEL: ; %bb.0: ; %entry
; GFX9GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v0
-; GFX9GISEL-NEXT: ; implicit-def: $sgpr6
+; GFX9GISEL-NEXT: ; implicit-def: $sgpr2
; GFX9GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX9GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
; GFX9GISEL-NEXT: s_cbranch_execz .LBB6_2
@@ -2435,10 +2438,12 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX9GISEL-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
; GFX9GISEL-NEXT: ; implicit-def: $vgpr0
; GFX9GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9GISEL-NEXT: s_mul_i32 s6, s6, s2
+; GFX9GISEL-NEXT: s_mul_i32 s2, s6, s2
; GFX9GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX9GISEL-NEXT: s_andn2_saveexec_b64 s[0:1], s[0:1]
-; GFX9GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX9GISEL-NEXT: s_or_saveexec_b64 s[0:1], s[0:1]
+; GFX9GISEL-NEXT: v_mov_b32_e32 v1, s2
+; GFX9GISEL-NEXT: s_xor_b64 exec, exec, s[0:1]
+; GFX9GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX9GISEL-NEXT: ; %bb.3: ; %if
; GFX9GISEL-NEXT: s_mov_b64 s[2:3], exec
; GFX9GISEL-NEXT: s_mov_b32 s6, 0
@@ -2449,13 +2454,14 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX9GISEL-NEXT: s_add_i32 s6, s6, s8
; GFX9GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX9GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX9GISEL-NEXT: .LBB6_5: ; %endif
+; GFX9GISEL-NEXT: ; %bb.5:
+; GFX9GISEL-NEXT: v_mov_b32_e32 v1, s6
+; GFX9GISEL-NEXT: .LBB6_6: ; %endif
; GFX9GISEL-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX9GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX9GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX9GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX9GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9GISEL-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX9GISEL-NEXT: global_store_dword v0, v1, s[0:1]
; GFX9GISEL-NEXT: s_endpgm
;
; GFX1064DAGISEL-LABEL: divergent_cfg:
@@ -2500,7 +2506,7 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1064GISEL-LABEL: divergent_cfg:
; GFX1064GISEL: ; %bb.0: ; %entry
; GFX1064GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v0
-; GFX1064GISEL-NEXT: ; implicit-def: $sgpr6
+; GFX1064GISEL-NEXT: ; implicit-def: $sgpr2
; GFX1064GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1064GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
; GFX1064GISEL-NEXT: s_cbranch_execz .LBB6_2
@@ -2510,10 +2516,12 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1064GISEL-NEXT: ; implicit-def: $vgpr0
; GFX1064GISEL-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064GISEL-NEXT: s_mul_i32 s6, s6, s2
+; GFX1064GISEL-NEXT: s_mul_i32 s2, s6, s2
; GFX1064GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX1064GISEL-NEXT: s_andn2_saveexec_b64 s[0:1], s[0:1]
-; GFX1064GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX1064GISEL-NEXT: s_or_saveexec_b64 s[0:1], s[0:1]
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s2
+; GFX1064GISEL-NEXT: s_xor_b64 exec, exec, s[0:1]
+; GFX1064GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX1064GISEL-NEXT: ; %bb.3: ; %if
; GFX1064GISEL-NEXT: s_mov_b64 s[2:3], exec
; GFX1064GISEL-NEXT: s_mov_b32 s6, 0
@@ -2524,13 +2532,14 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1064GISEL-NEXT: s_add_i32 s6, s6, s8
; GFX1064GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX1064GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX1064GISEL-NEXT: .LBB6_5: ; %endif
+; GFX1064GISEL-NEXT: ; %bb.5:
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s6
+; GFX1064GISEL-NEXT: .LBB6_6: ; %endif
; GFX1064GISEL-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064GISEL-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX1064GISEL-NEXT: global_store_dword v0, v1, s[0:1]
; GFX1064GISEL-NEXT: s_endpgm
;
; GFX1032DAGISEL-LABEL: divergent_cfg:
@@ -2575,37 +2584,40 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1032GISEL-LABEL: divergent_cfg:
; GFX1032GISEL: ; %bb.0: ; %entry
; GFX1032GISEL-NEXT: v_cmp_le_u32_e32 vcc_lo, 16, v0
-; GFX1032GISEL-NEXT: ; implicit-def: $sgpr0
-; GFX1032GISEL-NEXT: s_and_saveexec_b32 s1, vcc_lo
-; GFX1032GISEL-NEXT: s_xor_b32 s1, exec_lo, s1
+; GFX1032GISEL-NEXT: ; implicit-def: $sgpr1
+; GFX1032GISEL-NEXT: s_and_saveexec_b32 s0, vcc_lo
+; GFX1032GISEL-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX1032GISEL-NEXT: s_cbranch_execz .LBB6_2
; GFX1032GISEL-NEXT: ; %bb.1: ; %else
-; GFX1032GISEL-NEXT: s_load_dword s0, s[4:5], 0x2c
+; GFX1032GISEL-NEXT: s_load_dword s1, s[4:5], 0x2c
; GFX1032GISEL-NEXT: s_mov_b32 s2, exec_lo
; GFX1032GISEL-NEXT: ; implicit-def: $vgpr0
; GFX1032GISEL-NEXT: s_bcnt1_i32_b32 s2, s2
; GFX1032GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1032GISEL-NEXT: s_mul_i32 s0, s0, s2
+; GFX1032GISEL-NEXT: s_mul_i32 s1, s1, s2
; GFX1032GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX1032GISEL-NEXT: s_andn2_saveexec_b32 s1, s1
-; GFX1032GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX1032GISEL-NEXT: s_or_saveexec_b32 s0, s0
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX1032GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s0
+; GFX1032GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX1032GISEL-NEXT: ; %bb.3: ; %if
; GFX1032GISEL-NEXT: s_mov_b32 s2, exec_lo
-; GFX1032GISEL-NEXT: s_mov_b32 s0, 0
+; GFX1032GISEL-NEXT: s_mov_b32 s1, 0
; GFX1032GISEL-NEXT: .LBB6_4: ; =>This Inner Loop Header: Depth=1
; GFX1032GISEL-NEXT: s_ff1_i32_b32 s3, s2
; GFX1032GISEL-NEXT: v_readlane_b32 s6, v0, s3
; GFX1032GISEL-NEXT: s_bitset0_b32 s2, s3
-; GFX1032GISEL-NEXT: s_add_i32 s0, s0, s6
+; GFX1032GISEL-NEXT: s_add_i32 s1, s1, s6
; GFX1032GISEL-NEXT: s_cmp_lg_u32 s2, 0
; GFX1032GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX1032GISEL-NEXT: .LBB6_5: ; %endif
-; GFX1032GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s1
-; GFX1032GISEL-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
-; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1032GISEL-NEXT: ; %bb.5:
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX1032GISEL-NEXT: .LBB6_6: ; %endif
+; GFX1032GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX1032GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX1032GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1032GISEL-NEXT: global_store_dword v1, v0, s[2:3]
+; GFX1032GISEL-NEXT: global_store_dword v0, v1, s[0:1]
; GFX1032GISEL-NEXT: s_endpgm
;
; GFX1164DAGISEL-LABEL: divergent_cfg:
@@ -2655,7 +2667,7 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1164GISEL: ; %bb.0: ; %entry
; GFX1164GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX1164GISEL-NEXT: s_mov_b64 s[0:1], exec
-; GFX1164GISEL-NEXT: ; implicit-def: $sgpr6
+; GFX1164GISEL-NEXT: ; implicit-def: $sgpr2
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164GISEL-NEXT: v_cmpx_le_u32_e32 16, v0
; GFX1164GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
@@ -2667,10 +2679,12 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1164GISEL-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-NEXT: s_mul_i32 s6, s6, s2
+; GFX1164GISEL-NEXT: s_mul_i32 s2, s6, s2
; GFX1164GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX1164GISEL-NEXT: s_and_not1_saveexec_b64 s[0:1], s[0:1]
-; GFX1164GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX1164GISEL-NEXT: s_or_saveexec_b64 s[0:1], s[0:1]
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s2
+; GFX1164GISEL-NEXT: s_xor_b64 exec, exec, s[0:1]
+; GFX1164GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX1164GISEL-NEXT: ; %bb.3: ; %if
; GFX1164GISEL-NEXT: s_mov_b64 s[2:3], exec
; GFX1164GISEL-NEXT: s_mov_b32 s6, 0
@@ -2682,13 +2696,14 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1164GISEL-NEXT: s_add_i32 s6, s6, s8
; GFX1164GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX1164GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX1164GISEL-NEXT: .LBB6_5: ; %endif
+; GFX1164GISEL-NEXT: ; %bb.5:
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s6
+; GFX1164GISEL-NEXT: .LBB6_6: ; %endif
; GFX1164GISEL-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1164GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX1164GISEL-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX1164GISEL-NEXT: s_endpgm
;
; GFX1132DAGISEL-LABEL: divergent_cfg:
@@ -2737,40 +2752,44 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1132GISEL-LABEL: divergent_cfg:
; GFX1132GISEL: ; %bb.0: ; %entry
; GFX1132GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX1132GISEL-NEXT: s_mov_b32 s1, exec_lo
-; GFX1132GISEL-NEXT: ; implicit-def: $sgpr0
+; GFX1132GISEL-NEXT: s_mov_b32 s0, exec_lo
+; GFX1132GISEL-NEXT: ; implicit-def: $sgpr1
; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1132GISEL-NEXT: v_cmpx_le_u32_e32 16, v0
-; GFX1132GISEL-NEXT: s_xor_b32 s1, exec_lo, s1
+; GFX1132GISEL-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX1132GISEL-NEXT: s_cbranch_execz .LBB6_2
; GFX1132GISEL-NEXT: ; %bb.1: ; %else
-; GFX1132GISEL-NEXT: s_load_b32 s0, s[4:5], 0x2c
+; GFX1132GISEL-NEXT: s_load_b32 s1, s[4:5], 0x2c
; GFX1132GISEL-NEXT: s_mov_b32 s2, exec_lo
; GFX1132GISEL-NEXT: ; implicit-def: $vgpr0
; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1132GISEL-NEXT: s_bcnt1_i32_b32 s2, s2
; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-NEXT: s_mul_i32 s0, s0, s2
+; GFX1132GISEL-NEXT: s_mul_i32 s1, s1, s2
; GFX1132GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX1132GISEL-NEXT: s_and_not1_saveexec_b32 s1, s1
-; GFX1132GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX1132GISEL-NEXT: s_or_saveexec_b32 s0, s0
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX1132GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s0
+; GFX1132GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX1132GISEL-NEXT: ; %bb.3: ; %if
; GFX1132GISEL-NEXT: s_mov_b32 s2, exec_lo
-; GFX1132GISEL-NEXT: s_mov_b32 s0, 0
+; GFX1132GISEL-NEXT: s_mov_b32 s1, 0
; GFX1132GISEL-NEXT: .LBB6_4: ; =>This Inner Loop Header: Depth=1
; GFX1132GISEL-NEXT: s_ctz_i32_b32 s3, s2
; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1132GISEL-NEXT: v_readlane_b32 s6, v0, s3
; GFX1132GISEL-NEXT: s_bitset0_b32 s2, s3
-; GFX1132GISEL-NEXT: s_add_i32 s0, s0, s6
+; GFX1132GISEL-NEXT: s_add_i32 s1, s1, s6
; GFX1132GISEL-NEXT: s_cmp_lg_u32 s2, 0
; GFX1132GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX1132GISEL-NEXT: .LBB6_5: ; %endif
-; GFX1132GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s1
-; GFX1132GISEL-NEXT: s_load_b64 s[2:3], s[4:5], 0x24
-; GFX1132GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, 0
+; GFX1132GISEL-NEXT: ; %bb.5:
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX1132GISEL-NEXT: .LBB6_6: ; %endif
+; GFX1132GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX1132GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-NEXT: global_store_b32 v1, v0, s[2:3]
+; GFX1132GISEL-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX1132GISEL-NEXT: s_endpgm
;
; GFX12DAGISEL-LABEL: divergent_cfg:
@@ -3387,7 +3406,10 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX8GISEL-NEXT: s_add_u32 s7, s2, s3
; GFX8GISEL-NEXT: .LBB9_2: ; %Flow
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8GISEL-NEXT: s_andn2_saveexec_b64 s[2:3], s[8:9]
+; GFX8GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[8:9]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s7
+; GFX8GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX8GISEL-NEXT: s_cbranch_execz .LBB9_4
; GFX8GISEL-NEXT: ; %bb.3: ; %if
; GFX8GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
@@ -3398,11 +3420,11 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX8GISEL-NEXT: s_mul_hi_u32 s4, s4, s7
; GFX8GISEL-NEXT: s_mul_i32 s5, s5, s7
; GFX8GISEL-NEXT: s_add_u32 s7, s4, s5
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX8GISEL-NEXT: .LBB9_4: ; %endif
; GFX8GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s6
; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
-; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX8GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX8GISEL-NEXT: s_endpgm
@@ -3463,21 +3485,24 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX9GISEL-NEXT: s_add_u32 s7, s2, s3
; GFX9GISEL-NEXT: .LBB9_2: ; %Flow
; GFX9GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9GISEL-NEXT: s_andn2_saveexec_b64 s[2:3], s[8:9]
+; GFX9GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[8:9]
+; GFX9GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX9GISEL-NEXT: v_mov_b32_e32 v1, s7
+; GFX9GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX9GISEL-NEXT: s_cbranch_execz .LBB9_4
; GFX9GISEL-NEXT: ; %bb.3: ; %if
-; GFX9GISEL-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x34
+; GFX9GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX9GISEL-NEXT: s_mov_b64 s[4:5], exec
-; GFX9GISEL-NEXT: s_bcnt1_i32_b64 s4, s[4:5]
+; GFX9GISEL-NEXT: s_bcnt1_i32_b64 s5, s[4:5]
; GFX9GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9GISEL-NEXT: s_mul_i32 s6, s8, s4
-; GFX9GISEL-NEXT: s_mul_hi_u32 s5, s8, s4
-; GFX9GISEL-NEXT: s_mul_i32 s4, s9, s4
-; GFX9GISEL-NEXT: s_add_u32 s7, s5, s4
+; GFX9GISEL-NEXT: s_mul_i32 s4, s6, s5
+; GFX9GISEL-NEXT: s_mul_hi_u32 s6, s6, s5
+; GFX9GISEL-NEXT: s_mul_i32 s5, s7, s5
+; GFX9GISEL-NEXT: s_add_u32 s5, s6, s5
+; GFX9GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX9GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX9GISEL-NEXT: .LBB9_4: ; %endif
; GFX9GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX9GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX9GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX9GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX9GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX9GISEL-NEXT: s_endpgm
@@ -3525,21 +3550,24 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX1064GISEL: ; %bb.0: ; %entry
; GFX1064GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX1064GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v0
-; GFX1064GISEL-NEXT: ; implicit-def: $sgpr6_sgpr7
-; GFX1064GISEL-NEXT: s_and_saveexec_b64 s[8:9], vcc
-; GFX1064GISEL-NEXT: s_xor_b64 s[8:9], exec, s[8:9]
+; GFX1064GISEL-NEXT: ; implicit-def: $sgpr8_sgpr9
+; GFX1064GISEL-NEXT: s_and_saveexec_b64 s[6:7], vcc
+; GFX1064GISEL-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
; GFX1064GISEL-NEXT: s_cbranch_execz .LBB9_2
; GFX1064GISEL-NEXT: ; %bb.1: ; %else
-; GFX1064GISEL-NEXT: s_mov_b64 s[6:7], exec
-; GFX1064GISEL-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
+; GFX1064GISEL-NEXT: s_mov_b64 s[8:9], exec
+; GFX1064GISEL-NEXT: s_bcnt1_i32_b64 s8, s[8:9]
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064GISEL-NEXT: s_mul_hi_u32 s7, s2, s6
-; GFX1064GISEL-NEXT: s_mul_i32 s3, s3, s6
-; GFX1064GISEL-NEXT: s_mul_i32 s6, s2, s6
-; GFX1064GISEL-NEXT: s_add_u32 s7, s7, s3
+; GFX1064GISEL-NEXT: s_mul_hi_u32 s9, s2, s8
+; GFX1064GISEL-NEXT: s_mul_i32 s3, s3, s8
+; GFX1064GISEL-NEXT: s_mul_i32 s8, s2, s8
+; GFX1064GISEL-NEXT: s_add_u32 s9, s9, s3
; GFX1064GISEL-NEXT: .LBB9_2: ; %Flow
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064GISEL-NEXT: s_andn2_saveexec_b64 s[2:3], s[8:9]
+; GFX1064GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[6:7]
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s8
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s9
+; GFX1064GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX1064GISEL-NEXT: s_cbranch_execz .LBB9_4
; GFX1064GISEL-NEXT: ; %bb.3: ; %if
; GFX1064GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
@@ -3548,12 +3576,12 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064GISEL-NEXT: s_mul_hi_u32 s5, s6, s4
; GFX1064GISEL-NEXT: s_mul_i32 s7, s7, s4
-; GFX1064GISEL-NEXT: s_mul_i32 s6, s6, s4
-; GFX1064GISEL-NEXT: s_add_u32 s7, s5, s7
+; GFX1064GISEL-NEXT: s_mul_i32 s4, s6, s4
+; GFX1064GISEL-NEXT: s_add_u32 s5, s5, s7
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX1064GISEL-NEXT: .LBB9_4: ; %endif
; GFX1064GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX1064GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1064GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX1064GISEL-NEXT: s_endpgm
@@ -3615,21 +3643,24 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX1032GISEL-NEXT: s_add_u32 s7, s7, s3
; GFX1032GISEL-NEXT: .LBB9_2: ; %Flow
; GFX1032GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1032GISEL-NEXT: s_andn2_saveexec_b32 s2, s8
+; GFX1032GISEL-NEXT: s_or_saveexec_b32 s2, s8
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, s7
+; GFX1032GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s2
; GFX1032GISEL-NEXT: s_cbranch_execz .LBB9_4
; GFX1032GISEL-NEXT: ; %bb.3: ; %if
; GFX1032GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX1032GISEL-NEXT: s_mov_b32 s3, exec_lo
; GFX1032GISEL-NEXT: s_bcnt1_i32_b32 s3, s3
; GFX1032GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1032GISEL-NEXT: s_mul_hi_u32 s4, s6, s3
-; GFX1032GISEL-NEXT: s_mul_i32 s5, s7, s3
-; GFX1032GISEL-NEXT: s_mul_i32 s6, s6, s3
-; GFX1032GISEL-NEXT: s_add_u32 s7, s4, s5
+; GFX1032GISEL-NEXT: s_mul_hi_u32 s5, s6, s3
+; GFX1032GISEL-NEXT: s_mul_i32 s7, s7, s3
+; GFX1032GISEL-NEXT: s_mul_i32 s4, s6, s3
+; GFX1032GISEL-NEXT: s_add_u32 s5, s5, s7
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX1032GISEL-NEXT: .LBB9_4: ; %endif
; GFX1032GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s2
-; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX1032GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1032GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX1032GISEL-NEXT: s_endpgm
@@ -3682,24 +3713,27 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX1164GISEL: ; %bb.0: ; %entry
; GFX1164GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1164GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX1164GISEL-NEXT: s_mov_b64 s[8:9], exec
-; GFX1164GISEL-NEXT: ; implicit-def: $sgpr6_sgpr7
+; GFX1164GISEL-NEXT: s_mov_b64 s[6:7], exec
+; GFX1164GISEL-NEXT: ; implicit-def: $sgpr8_sgpr9
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164GISEL-NEXT: v_cmpx_le_u32_e32 16, v0
-; GFX1164GISEL-NEXT: s_xor_b64 s[8:9], exec, s[8:9]
+; GFX1164GISEL-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
; GFX1164GISEL-NEXT: s_cbranch_execz .LBB9_2
; GFX1164GISEL-NEXT: ; %bb.1: ; %else
-; GFX1164GISEL-NEXT: s_mov_b64 s[6:7], exec
+; GFX1164GISEL-NEXT: s_mov_b64 s[8:9], exec
; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1164GISEL-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
+; GFX1164GISEL-NEXT: s_bcnt1_i32_b64 s8, s[8:9]
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-NEXT: s_mul_hi_u32 s7, s2, s6
-; GFX1164GISEL-NEXT: s_mul_i32 s3, s3, s6
-; GFX1164GISEL-NEXT: s_mul_i32 s6, s2, s6
-; GFX1164GISEL-NEXT: s_add_u32 s7, s7, s3
+; GFX1164GISEL-NEXT: s_mul_hi_u32 s9, s2, s8
+; GFX1164GISEL-NEXT: s_mul_i32 s3, s3, s8
+; GFX1164GISEL-NEXT: s_mul_i32 s8, s2, s8
+; GFX1164GISEL-NEXT: s_add_u32 s9, s9, s3
; GFX1164GISEL-NEXT: .LBB9_2: ; %Flow
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-NEXT: s_and_not1_saveexec_b64 s[2:3], s[8:9]
+; GFX1164GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[6:7]
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s8
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s9
+; GFX1164GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX1164GISEL-NEXT: s_cbranch_execz .LBB9_4
; GFX1164GISEL-NEXT: ; %bb.3: ; %if
; GFX1164GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
@@ -3709,12 +3743,12 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164GISEL-NEXT: s_mul_hi_u32 s7, s4, s6
; GFX1164GISEL-NEXT: s_mul_i32 s5, s5, s6
-; GFX1164GISEL-NEXT: s_mul_i32 s6, s4, s6
-; GFX1164GISEL-NEXT: s_add_u32 s7, s7, s5
+; GFX1164GISEL-NEXT: s_mul_i32 s4, s4, s6
+; GFX1164GISEL-NEXT: s_add_u32 s5, s7, s5
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX1164GISEL-NEXT: .LBB9_4: ; %endif
; GFX1164GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX1164GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1164GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX1164GISEL-NEXT: s_endpgm
@@ -3782,7 +3816,9 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX1132GISEL-NEXT: s_add_u32 s7, s7, s3
; GFX1132GISEL-NEXT: .LBB9_2: ; %Flow
; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-NEXT: s_and_not1_saveexec_b32 s2, s8
+; GFX1132GISEL-NEXT: s_or_saveexec_b32 s2, s8
+; GFX1132GISEL-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
+; GFX1132GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s2
; GFX1132GISEL-NEXT: s_cbranch_execz .LBB9_4
; GFX1132GISEL-NEXT: ; %bb.3: ; %if
; GFX1132GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
@@ -3790,13 +3826,14 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1132GISEL-NEXT: s_bcnt1_i32_b32 s3, s3
; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-NEXT: s_mul_hi_u32 s7, s4, s3
+; GFX1132GISEL-NEXT: s_mul_hi_u32 s6, s4, s3
; GFX1132GISEL-NEXT: s_mul_i32 s5, s5, s3
-; GFX1132GISEL-NEXT: s_mul_i32 s6, s4, s3
-; GFX1132GISEL-NEXT: s_add_u32 s7, s7, s5
+; GFX1132GISEL-NEXT: s_mul_i32 s4, s4, s3
+; GFX1132GISEL-NEXT: s_add_u32 s5, s6, s5
+; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1132GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
; GFX1132GISEL-NEXT: .LBB9_4: ; %endif
; GFX1132GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s2
-; GFX1132GISEL-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
; GFX1132GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1132GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX1132GISEL-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
index ca82764a788f9..10c5a7f2b42c2 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
@@ -1,16 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=0 < %s | FileCheck -check-prefixes=GFX8DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=1 < %s | FileCheck -check-prefixes=GFX8GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX8GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=0 < %s | FileCheck -check-prefixes=GFX9DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=1 < %s | FileCheck -check-prefixes=GFX9GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX9GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1064DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1064GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1064GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1032DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1032GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1032GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1164DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1164GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1164GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1132DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1132GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1132GISEL %s
define amdgpu_kernel void @uniform_value(ptr addrspace(1) %out, i32 %in) {
; GFX8DAGISEL-LABEL: uniform_value:
@@ -2037,7 +2037,7 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX8GISEL-LABEL: divergent_cfg:
; GFX8GISEL: ; %bb.0: ; %entry
; GFX8GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v0
-; GFX8GISEL-NEXT: ; implicit-def: $sgpr6
+; GFX8GISEL-NEXT: ; implicit-def: $sgpr2
; GFX8GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX8GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
; GFX8GISEL-NEXT: s_cbranch_execz .LBB6_2
@@ -2045,10 +2045,12 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX8GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
; GFX8GISEL-NEXT: ; implicit-def: $vgpr0
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8GISEL-NEXT: s_mov_b32 s6, s2
+; GFX8GISEL-NEXT: s_mov_b32 s2, s2
; GFX8GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX8GISEL-NEXT: s_andn2_saveexec_b64 s[0:1], s[0:1]
-; GFX8GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX8GISEL-NEXT: s_or_saveexec_b64 s[0:1], s[0:1]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s2
+; GFX8GISEL-NEXT: s_xor_b64 exec, exec, s[0:1]
+; GFX8GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX8GISEL-NEXT: ; %bb.3: ; %if
; GFX8GISEL-NEXT: s_mov_b64 s[2:3], exec
; GFX8GISEL-NEXT: s_mov_b32 s6, -1
@@ -2059,14 +2061,15 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX8GISEL-NEXT: s_and_b32 s6, s6, s8
; GFX8GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX8GISEL-NEXT: .LBB6_5: ; %endif
+; GFX8GISEL-NEXT: ; %bb.5:
+; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s6
+; GFX8GISEL-NEXT: .LBB6_6: ; %endif
; GFX8GISEL-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX8GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s6
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s1
-; GFX8GISEL-NEXT: flat_store_dword v[0:1], v2
+; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
+; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
+; GFX8GISEL-NEXT: flat_store_dword v[2:3], v1
; GFX8GISEL-NEXT: s_endpgm
;
; GFX9DAGISEL-LABEL: divergent_cfg:
@@ -2107,7 +2110,7 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX9GISEL-LABEL: divergent_cfg:
; GFX9GISEL: ; %bb.0: ; %entry
; GFX9GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v0
-; GFX9GISEL-NEXT: ; implicit-def: $sgpr6
+; GFX9GISEL-NEXT: ; implicit-def: $sgpr2
; GFX9GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX9GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
; GFX9GISEL-NEXT: s_cbranch_execz .LBB6_2
@@ -2115,10 +2118,12 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX9GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
; GFX9GISEL-NEXT: ; implicit-def: $vgpr0
; GFX9GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9GISEL-NEXT: s_mov_b32 s6, s2
+; GFX9GISEL-NEXT: s_mov_b32 s2, s2
; GFX9GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX9GISEL-NEXT: s_andn2_saveexec_b64 s[0:1], s[0:1]
-; GFX9GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX9GISEL-NEXT: s_or_saveexec_b64 s[0:1], s[0:1]
+; GFX9GISEL-NEXT: v_mov_b32_e32 v1, s2
+; GFX9GISEL-NEXT: s_xor_b64 exec, exec, s[0:1]
+; GFX9GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX9GISEL-NEXT: ; %bb.3: ; %if
; GFX9GISEL-NEXT: s_mov_b64 s[2:3], exec
; GFX9GISEL-NEXT: s_mov_b32 s6, -1
@@ -2129,13 +2134,14 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX9GISEL-NEXT: s_and_b32 s6, s6, s8
; GFX9GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX9GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX9GISEL-NEXT: .LBB6_5: ; %endif
+; GFX9GISEL-NEXT: ; %bb.5:
+; GFX9GISEL-NEXT: v_mov_b32_e32 v1, s6
+; GFX9GISEL-NEXT: .LBB6_6: ; %endif
; GFX9GISEL-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX9GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX9GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX9GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX9GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9GISEL-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX9GISEL-NEXT: global_store_dword v0, v1, s[0:1]
; GFX9GISEL-NEXT: s_endpgm
;
; GFX1064DAGISEL-LABEL: divergent_cfg:
@@ -2176,7 +2182,7 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1064GISEL-LABEL: divergent_cfg:
; GFX1064GISEL: ; %bb.0: ; %entry
; GFX1064GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v0
-; GFX1064GISEL-NEXT: ; implicit-def: $sgpr6
+; GFX1064GISEL-NEXT: ; implicit-def: $sgpr2
; GFX1064GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1064GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
; GFX1064GISEL-NEXT: s_cbranch_execz .LBB6_2
@@ -2184,10 +2190,12 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1064GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
; GFX1064GISEL-NEXT: ; implicit-def: $vgpr0
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064GISEL-NEXT: s_mov_b32 s6, s2
+; GFX1064GISEL-NEXT: s_mov_b32 s2, s2
; GFX1064GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX1064GISEL-NEXT: s_andn2_saveexec_b64 s[0:1], s[0:1]
-; GFX1064GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX1064GISEL-NEXT: s_or_saveexec_b64 s[0:1], s[0:1]
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s2
+; GFX1064GISEL-NEXT: s_xor_b64 exec, exec, s[0:1]
+; GFX1064GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX1064GISEL-NEXT: ; %bb.3: ; %if
; GFX1064GISEL-NEXT: s_mov_b64 s[2:3], exec
; GFX1064GISEL-NEXT: s_mov_b32 s6, -1
@@ -2198,13 +2206,14 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1064GISEL-NEXT: s_and_b32 s6, s6, s8
; GFX1064GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX1064GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX1064GISEL-NEXT: .LBB6_5: ; %endif
+; GFX1064GISEL-NEXT: ; %bb.5:
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s6
+; GFX1064GISEL-NEXT: .LBB6_6: ; %endif
; GFX1064GISEL-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064GISEL-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX1064GISEL-NEXT: global_store_dword v0, v1, s[0:1]
; GFX1064GISEL-NEXT: s_endpgm
;
; GFX1032DAGISEL-LABEL: divergent_cfg:
@@ -2245,35 +2254,38 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1032GISEL-LABEL: divergent_cfg:
; GFX1032GISEL: ; %bb.0: ; %entry
; GFX1032GISEL-NEXT: v_cmp_le_u32_e32 vcc_lo, 16, v0
-; GFX1032GISEL-NEXT: ; implicit-def: $sgpr0
-; GFX1032GISEL-NEXT: s_and_saveexec_b32 s1, vcc_lo
-; GFX1032GISEL-NEXT: s_xor_b32 s1, exec_lo, s1
+; GFX1032GISEL-NEXT: ; implicit-def: $sgpr1
+; GFX1032GISEL-NEXT: s_and_saveexec_b32 s0, vcc_lo
+; GFX1032GISEL-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX1032GISEL-NEXT: s_cbranch_execz .LBB6_2
; GFX1032GISEL-NEXT: ; %bb.1: ; %else
-; GFX1032GISEL-NEXT: s_load_dword s0, s[4:5], 0x2c
+; GFX1032GISEL-NEXT: s_load_dword s1, s[4:5], 0x2c
; GFX1032GISEL-NEXT: ; implicit-def: $vgpr0
; GFX1032GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1032GISEL-NEXT: s_mov_b32 s0, s0
+; GFX1032GISEL-NEXT: s_mov_b32 s1, s1
; GFX1032GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX1032GISEL-NEXT: s_andn2_saveexec_b32 s1, s1
-; GFX1032GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX1032GISEL-NEXT: s_or_saveexec_b32 s0, s0
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX1032GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s0
+; GFX1032GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX1032GISEL-NEXT: ; %bb.3: ; %if
; GFX1032GISEL-NEXT: s_mov_b32 s2, exec_lo
-; GFX1032GISEL-NEXT: s_mov_b32 s0, -1
+; GFX1032GISEL-NEXT: s_mov_b32 s1, -1
; GFX1032GISEL-NEXT: .LBB6_4: ; =>This Inner Loop Header: Depth=1
; GFX1032GISEL-NEXT: s_ff1_i32_b32 s3, s2
; GFX1032GISEL-NEXT: v_readlane_b32 s6, v0, s3
; GFX1032GISEL-NEXT: s_bitset0_b32 s2, s3
-; GFX1032GISEL-NEXT: s_and_b32 s0, s0, s6
+; GFX1032GISEL-NEXT: s_and_b32 s1, s1, s6
; GFX1032GISEL-NEXT: s_cmp_lg_u32 s2, 0
; GFX1032GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX1032GISEL-NEXT: .LBB6_5: ; %endif
-; GFX1032GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s1
-; GFX1032GISEL-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
-; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1032GISEL-NEXT: ; %bb.5:
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX1032GISEL-NEXT: .LBB6_6: ; %endif
+; GFX1032GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX1032GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX1032GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1032GISEL-NEXT: global_store_dword v1, v0, s[2:3]
+; GFX1032GISEL-NEXT: global_store_dword v0, v1, s[0:1]
; GFX1032GISEL-NEXT: s_endpgm
;
; GFX1164DAGISEL-LABEL: divergent_cfg:
@@ -2318,7 +2330,7 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1164GISEL: ; %bb.0: ; %entry
; GFX1164GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX1164GISEL-NEXT: s_mov_b64 s[0:1], exec
-; GFX1164GISEL-NEXT: ; implicit-def: $sgpr6
+; GFX1164GISEL-NEXT: ; implicit-def: $sgpr2
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164GISEL-NEXT: v_cmpx_le_u32_e32 16, v0
; GFX1164GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
@@ -2327,10 +2339,12 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1164GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
; GFX1164GISEL-NEXT: ; implicit-def: $vgpr0
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-NEXT: s_mov_b32 s6, s2
+; GFX1164GISEL-NEXT: s_mov_b32 s2, s2
; GFX1164GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX1164GISEL-NEXT: s_and_not1_saveexec_b64 s[0:1], s[0:1]
-; GFX1164GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX1164GISEL-NEXT: s_or_saveexec_b64 s[0:1], s[0:1]
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s2
+; GFX1164GISEL-NEXT: s_xor_b64 exec, exec, s[0:1]
+; GFX1164GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX1164GISEL-NEXT: ; %bb.3: ; %if
; GFX1164GISEL-NEXT: s_mov_b64 s[2:3], exec
; GFX1164GISEL-NEXT: s_mov_b32 s6, -1
@@ -2342,13 +2356,14 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1164GISEL-NEXT: s_and_b32 s6, s6, s8
; GFX1164GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX1164GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX1164GISEL-NEXT: .LBB6_5: ; %endif
+; GFX1164GISEL-NEXT: ; %bb.5:
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s6
+; GFX1164GISEL-NEXT: .LBB6_6: ; %endif
; GFX1164GISEL-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1164GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX1164GISEL-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX1164GISEL-NEXT: s_endpgm
;
; GFX1132DAGISEL-LABEL: divergent_cfg:
@@ -2392,37 +2407,41 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1132GISEL-LABEL: divergent_cfg:
; GFX1132GISEL: ; %bb.0: ; %entry
; GFX1132GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX1132GISEL-NEXT: s_mov_b32 s1, exec_lo
-; GFX1132GISEL-NEXT: ; implicit-def: $sgpr0
+; GFX1132GISEL-NEXT: s_mov_b32 s0, exec_lo
+; GFX1132GISEL-NEXT: ; implicit-def: $sgpr1
; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1132GISEL-NEXT: v_cmpx_le_u32_e32 16, v0
-; GFX1132GISEL-NEXT: s_xor_b32 s1, exec_lo, s1
+; GFX1132GISEL-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX1132GISEL-NEXT: s_cbranch_execz .LBB6_2
; GFX1132GISEL-NEXT: ; %bb.1: ; %else
-; GFX1132GISEL-NEXT: s_load_b32 s0, s[4:5], 0x2c
+; GFX1132GISEL-NEXT: s_load_b32 s1, s[4:5], 0x2c
; GFX1132GISEL-NEXT: ; implicit-def: $vgpr0
; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-NEXT: s_mov_b32 s0, s0
+; GFX1132GISEL-NEXT: s_mov_b32 s1, s1
; GFX1132GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX1132GISEL-NEXT: s_and_not1_saveexec_b32 s1, s1
-; GFX1132GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX1132GISEL-NEXT: s_or_saveexec_b32 s0, s0
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX1132GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s0
+; GFX1132GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX1132GISEL-NEXT: ; %bb.3: ; %if
; GFX1132GISEL-NEXT: s_mov_b32 s2, exec_lo
-; GFX1132GISEL-NEXT: s_mov_b32 s0, -1
+; GFX1132GISEL-NEXT: s_mov_b32 s1, -1
; GFX1132GISEL-NEXT: .LBB6_4: ; =>This Inner Loop Header: Depth=1
; GFX1132GISEL-NEXT: s_ctz_i32_b32 s3, s2
; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1132GISEL-NEXT: v_readlane_b32 s6, v0, s3
; GFX1132GISEL-NEXT: s_bitset0_b32 s2, s3
-; GFX1132GISEL-NEXT: s_and_b32 s0, s0, s6
+; GFX1132GISEL-NEXT: s_and_b32 s1, s1, s6
; GFX1132GISEL-NEXT: s_cmp_lg_u32 s2, 0
; GFX1132GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX1132GISEL-NEXT: .LBB6_5: ; %endif
-; GFX1132GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s1
-; GFX1132GISEL-NEXT: s_load_b64 s[2:3], s[4:5], 0x24
-; GFX1132GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, 0
+; GFX1132GISEL-NEXT: ; %bb.5:
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX1132GISEL-NEXT: .LBB6_6: ; %endif
+; GFX1132GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX1132GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-NEXT: global_store_b32 v1, v0, s[2:3]
+; GFX1132GISEL-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX1132GISEL-NEXT: s_endpgm
entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x()
@@ -2825,17 +2844,20 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX8GISEL-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX8GISEL-NEXT: .LBB9_2: ; %Flow
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8GISEL-NEXT: s_andn2_saveexec_b64 s[2:3], s[8:9]
+; GFX8GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[8:9]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s7
+; GFX8GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX8GISEL-NEXT: s_cbranch_execz .LBB9_4
; GFX8GISEL-NEXT: ; %bb.3: ; %if
; GFX8GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8GISEL-NEXT: s_mov_b64 s[6:7], s[4:5]
+; GFX8GISEL-NEXT: s_mov_b64 s[4:5], s[4:5]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX8GISEL-NEXT: .LBB9_4: ; %endif
; GFX8GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s6
; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
-; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX8GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX8GISEL-NEXT: s_endpgm
@@ -2874,16 +2896,19 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX9GISEL-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9GISEL-NEXT: .LBB9_2: ; %Flow
; GFX9GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9GISEL-NEXT: s_andn2_saveexec_b64 s[2:3], s[8:9]
+; GFX9GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[8:9]
+; GFX9GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX9GISEL-NEXT: v_mov_b32_e32 v1, s7
+; GFX9GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX9GISEL-NEXT: s_cbranch_execz .LBB9_4
; GFX9GISEL-NEXT: ; %bb.3: ; %if
; GFX9GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX9GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9GISEL-NEXT: s_mov_b64 s[6:7], s[6:7]
+; GFX9GISEL-NEXT: s_mov_b64 s[4:5], s[6:7]
+; GFX9GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX9GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX9GISEL-NEXT: .LBB9_4: ; %endif
; GFX9GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX9GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX9GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX9GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX9GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX9GISEL-NEXT: s_endpgm
@@ -2923,16 +2948,19 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX1064GISEL-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX1064GISEL-NEXT: .LBB9_2: ; %Flow
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064GISEL-NEXT: s_andn2_saveexec_b64 s[2:3], s[8:9]
+; GFX1064GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[8:9]
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s7
+; GFX1064GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX1064GISEL-NEXT: s_cbranch_execz .LBB9_4
; GFX1064GISEL-NEXT: ; %bb.3: ; %if
; GFX1064GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064GISEL-NEXT: s_mov_b64 s[6:7], s[6:7]
+; GFX1064GISEL-NEXT: s_mov_b64 s[4:5], s[6:7]
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX1064GISEL-NEXT: .LBB9_4: ; %endif
; GFX1064GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX1064GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1064GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX1064GISEL-NEXT: s_endpgm
@@ -2972,16 +3000,19 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX1032GISEL-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX1032GISEL-NEXT: .LBB9_2: ; %Flow
; GFX1032GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1032GISEL-NEXT: s_andn2_saveexec_b32 s2, s8
+; GFX1032GISEL-NEXT: s_or_saveexec_b32 s2, s8
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, s7
+; GFX1032GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s2
; GFX1032GISEL-NEXT: s_cbranch_execz .LBB9_4
; GFX1032GISEL-NEXT: ; %bb.3: ; %if
; GFX1032GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX1032GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1032GISEL-NEXT: s_mov_b64 s[6:7], s[6:7]
+; GFX1032GISEL-NEXT: s_mov_b64 s[4:5], s[6:7]
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX1032GISEL-NEXT: .LBB9_4: ; %endif
; GFX1032GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s2
-; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX1032GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1032GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX1032GISEL-NEXT: s_endpgm
@@ -3025,16 +3056,20 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX1164GISEL-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX1164GISEL-NEXT: .LBB9_2: ; %Flow
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-NEXT: s_and_not1_saveexec_b64 s[2:3], s[8:9]
+; GFX1164GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[8:9]
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s7
+; GFX1164GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX1164GISEL-NEXT: s_cbranch_execz .LBB9_4
; GFX1164GISEL-NEXT: ; %bb.3: ; %if
; GFX1164GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-NEXT: s_mov_b64 s[6:7], s[4:5]
+; GFX1164GISEL-NEXT: s_mov_b64 s[4:5], s[4:5]
+; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX1164GISEL-NEXT: .LBB9_4: ; %endif
; GFX1164GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX1164GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1164GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX1164GISEL-NEXT: s_endpgm
@@ -3076,15 +3111,18 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX1132GISEL-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX1132GISEL-NEXT: .LBB9_2: ; %Flow
; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-NEXT: s_and_not1_saveexec_b32 s2, s8
+; GFX1132GISEL-NEXT: s_or_saveexec_b32 s2, s8
+; GFX1132GISEL-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
+; GFX1132GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s2
; GFX1132GISEL-NEXT: s_cbranch_execz .LBB9_4
; GFX1132GISEL-NEXT: ; %bb.3: ; %if
; GFX1132GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-NEXT: s_mov_b64 s[6:7], s[4:5]
+; GFX1132GISEL-NEXT: s_mov_b64 s[4:5], s[4:5]
+; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1132GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
; GFX1132GISEL-NEXT: .LBB9_4: ; %endif
; GFX1132GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s2
-; GFX1132GISEL-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
; GFX1132GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1132GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX1132GISEL-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
index 1906687709c1e..1cca1d87c0826 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
@@ -1,16 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=0 < %s | FileCheck -check-prefixes=GFX8DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=1 < %s | FileCheck -check-prefixes=GFX8GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX8GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=0 < %s | FileCheck -check-prefixes=GFX9DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=1 < %s | FileCheck -check-prefixes=GFX9GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX9GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1064DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1064GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1064GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1032DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1032GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1032GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1164DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1164GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1164GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1132DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1132GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1132GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -global-isel=0 < %s | FileCheck -check-prefixes=GFX12DAGISEL %s
@@ -1883,7 +1883,9 @@ define amdgpu_kernel void @divergent_cfg_float(ptr addrspace(1) %out, float %in,
; GFX8GISEL-NEXT: v_mul_f32_e32 v0, s0, v0
; GFX8GISEL-NEXT: v_readfirstlane_b32 s6, v0
; GFX8GISEL-NEXT: .LBB4_2: ; %Flow
-; GFX8GISEL-NEXT: s_andn2_saveexec_b64 s[2:3], s[2:3]
+; GFX8GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[2:3]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX8GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX8GISEL-NEXT: s_cbranch_execz .LBB4_4
; GFX8GISEL-NEXT: ; %bb.3: ; %if
; GFX8GISEL-NEXT: s_mov_b64 s[6:7], exec
@@ -1891,16 +1893,16 @@ define amdgpu_kernel void @divergent_cfg_float(ptr addrspace(1) %out, float %in,
; GFX8GISEL-NEXT: s_bcnt1_i32_b64 s0, s[6:7]
; GFX8GISEL-NEXT: v_cvt_f32_i32_e32 v0, s0
; GFX8GISEL-NEXT: v_mul_f32_e32 v0, s1, v0
-; GFX8GISEL-NEXT: v_readfirstlane_b32 s6, v0
+; GFX8GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8GISEL-NEXT: .LBB4_4: ; %endif
; GFX8GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s6
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s1
-; GFX8GISEL-NEXT: flat_store_dword v[0:1], v2
+; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s1
+; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s0
+; GFX8GISEL-NEXT: flat_store_dword v[1:2], v0
; GFX8GISEL-NEXT: s_endpgm
;
; GFX9DAGISEL-LABEL: divergent_cfg_float:
@@ -1956,7 +1958,9 @@ define amdgpu_kernel void @divergent_cfg_float(ptr addrspace(1) %out, float %in,
; GFX9GISEL-NEXT: v_mul_f32_e32 v0, s0, v0
; GFX9GISEL-NEXT: v_readfirstlane_b32 s6, v0
; GFX9GISEL-NEXT: .LBB4_2: ; %Flow
-; GFX9GISEL-NEXT: s_andn2_saveexec_b64 s[2:3], s[2:3]
+; GFX9GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[2:3]
+; GFX9GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX9GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX9GISEL-NEXT: s_cbranch_execz .LBB4_4
; GFX9GISEL-NEXT: ; %bb.3: ; %if
; GFX9GISEL-NEXT: s_mov_b64 s[6:7], exec
@@ -1964,12 +1968,12 @@ define amdgpu_kernel void @divergent_cfg_float(ptr addrspace(1) %out, float %in,
; GFX9GISEL-NEXT: s_bcnt1_i32_b64 s0, s[6:7]
; GFX9GISEL-NEXT: v_cvt_f32_i32_e32 v0, s0
; GFX9GISEL-NEXT: v_mul_f32_e32 v0, s1, v0
-; GFX9GISEL-NEXT: v_readfirstlane_b32 s6, v0
+; GFX9GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX9GISEL-NEXT: .LBB4_4: ; %endif
; GFX9GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX9GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9GISEL-NEXT: v_mov_b32_e32 v0, s6
; GFX9GISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX9GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9GISEL-NEXT: global_store_dword v1, v0, s[0:1]
@@ -2028,7 +2032,9 @@ define amdgpu_kernel void @divergent_cfg_float(ptr addrspace(1) %out, float %in,
; GFX1064GISEL-NEXT: v_mul_f32_e32 v0, s0, v0
; GFX1064GISEL-NEXT: v_readfirstlane_b32 s6, v0
; GFX1064GISEL-NEXT: .LBB4_2: ; %Flow
-; GFX1064GISEL-NEXT: s_andn2_saveexec_b64 s[2:3], s[2:3]
+; GFX1064GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[2:3]
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX1064GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX1064GISEL-NEXT: s_cbranch_execz .LBB4_4
; GFX1064GISEL-NEXT: ; %bb.3: ; %if
; GFX1064GISEL-NEXT: s_mov_b64 s[6:7], exec
@@ -2036,12 +2042,12 @@ define amdgpu_kernel void @divergent_cfg_float(ptr addrspace(1) %out, float %in,
; GFX1064GISEL-NEXT: s_bcnt1_i32_b64 s0, s[6:7]
; GFX1064GISEL-NEXT: v_cvt_f32_i32_e32 v0, s0
; GFX1064GISEL-NEXT: v_mul_f32_e32 v0, s1, v0
-; GFX1064GISEL-NEXT: v_readfirstlane_b32 s6, v0
+; GFX1064GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX1064GISEL-NEXT: .LBB4_4: ; %endif
; GFX1064GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s6
; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064GISEL-NEXT: global_store_dword v1, v0, s[0:1]
@@ -2087,31 +2093,33 @@ define amdgpu_kernel void @divergent_cfg_float(ptr addrspace(1) %out, float %in,
; GFX1032GISEL: ; %bb.0: ; %entry
; GFX1032GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2c
; GFX1032GISEL-NEXT: v_cmp_le_u32_e32 vcc_lo, 16, v0
-; GFX1032GISEL-NEXT: ; implicit-def: $sgpr2
-; GFX1032GISEL-NEXT: s_and_saveexec_b32 s3, vcc_lo
-; GFX1032GISEL-NEXT: s_xor_b32 s3, exec_lo, s3
+; GFX1032GISEL-NEXT: ; implicit-def: $sgpr3
+; GFX1032GISEL-NEXT: s_and_saveexec_b32 s2, vcc_lo
+; GFX1032GISEL-NEXT: s_xor_b32 s2, exec_lo, s2
; GFX1032GISEL-NEXT: s_cbranch_execz .LBB4_2
; GFX1032GISEL-NEXT: ; %bb.1: ; %else
-; GFX1032GISEL-NEXT: s_mov_b32 s2, exec_lo
-; GFX1032GISEL-NEXT: s_bcnt1_i32_b32 s2, s2
-; GFX1032GISEL-NEXT: v_cvt_f32_i32_e32 v0, s2
+; GFX1032GISEL-NEXT: s_mov_b32 s3, exec_lo
+; GFX1032GISEL-NEXT: s_bcnt1_i32_b32 s3, s3
+; GFX1032GISEL-NEXT: v_cvt_f32_i32_e32 v0, s3
; GFX1032GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032GISEL-NEXT: v_mul_f32_e32 v0, s0, v0
-; GFX1032GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1032GISEL-NEXT: v_readfirstlane_b32 s3, v0
; GFX1032GISEL-NEXT: .LBB4_2: ; %Flow
; GFX1032GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1032GISEL-NEXT: s_andn2_saveexec_b32 s0, s3
+; GFX1032GISEL-NEXT: s_or_saveexec_b32 s0, s2
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, s3
+; GFX1032GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX1032GISEL-NEXT: s_cbranch_execz .LBB4_4
; GFX1032GISEL-NEXT: ; %bb.3: ; %if
; GFX1032GISEL-NEXT: s_mov_b32 s2, exec_lo
; GFX1032GISEL-NEXT: s_bcnt1_i32_b32 s2, s2
; GFX1032GISEL-NEXT: v_cvt_f32_i32_e32 v0, s2
; GFX1032GISEL-NEXT: v_mul_f32_e32 v0, s1, v0
-; GFX1032GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1032GISEL-NEXT: v_readfirstlane_b32 s1, v0
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, s1
; GFX1032GISEL-NEXT: .LBB4_4: ; %endif
; GFX1032GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1032GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX1032GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032GISEL-NEXT: global_store_dword v1, v0, s[0:1]
@@ -2181,7 +2189,10 @@ define amdgpu_kernel void @divergent_cfg_float(ptr addrspace(1) %out, float %in,
; GFX1164GISEL-NEXT: v_mul_f32_e32 v0, s0, v0
; GFX1164GISEL-NEXT: v_readfirstlane_b32 s6, v0
; GFX1164GISEL-NEXT: .LBB4_2: ; %Flow
-; GFX1164GISEL-NEXT: s_and_not1_saveexec_b64 s[2:3], s[2:3]
+; GFX1164GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[2:3]
+; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX1164GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX1164GISEL-NEXT: s_cbranch_execz .LBB4_4
; GFX1164GISEL-NEXT: ; %bb.3: ; %if
; GFX1164GISEL-NEXT: s_mov_b64 s[6:7], exec
@@ -2190,14 +2201,13 @@ define amdgpu_kernel void @divergent_cfg_float(ptr addrspace(1) %out, float %in,
; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164GISEL-NEXT: v_cvt_f32_i32_e32 v0, s0
; GFX1164GISEL-NEXT: v_mul_f32_e32 v0, s1, v0
-; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1164GISEL-NEXT: v_readfirstlane_b32 s6, v0
+; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1164GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX1164GISEL-NEXT: .LBB4_4: ; %endif
; GFX1164GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s6
; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
@@ -2251,24 +2261,27 @@ define amdgpu_kernel void @divergent_cfg_float(ptr addrspace(1) %out, float %in,
; GFX1132GISEL: ; %bb.0: ; %entry
; GFX1132GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x2c
; GFX1132GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX1132GISEL-NEXT: s_mov_b32 s3, exec_lo
-; GFX1132GISEL-NEXT: ; implicit-def: $sgpr2
+; GFX1132GISEL-NEXT: s_mov_b32 s2, exec_lo
+; GFX1132GISEL-NEXT: ; implicit-def: $sgpr3
; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1132GISEL-NEXT: v_cmpx_le_u32_e32 16, v0
-; GFX1132GISEL-NEXT: s_xor_b32 s3, exec_lo, s3
+; GFX1132GISEL-NEXT: s_xor_b32 s2, exec_lo, s2
; GFX1132GISEL-NEXT: s_cbranch_execz .LBB4_2
; GFX1132GISEL-NEXT: ; %bb.1: ; %else
-; GFX1132GISEL-NEXT: s_mov_b32 s2, exec_lo
+; GFX1132GISEL-NEXT: s_mov_b32 s3, exec_lo
; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1132GISEL-NEXT: s_bcnt1_i32_b32 s2, s2
-; GFX1132GISEL-NEXT: v_cvt_f32_i32_e32 v0, s2
+; GFX1132GISEL-NEXT: s_bcnt1_i32_b32 s3, s3
+; GFX1132GISEL-NEXT: v_cvt_f32_i32_e32 v0, s3
; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1132GISEL-NEXT: v_mul_f32_e32 v0, s0, v0
-; GFX1132GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1132GISEL-NEXT: v_readfirstlane_b32 s3, v0
; GFX1132GISEL-NEXT: .LBB4_2: ; %Flow
; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-NEXT: s_and_not1_saveexec_b32 s0, s3
+; GFX1132GISEL-NEXT: s_or_saveexec_b32 s0, s2
+; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v0, s3
+; GFX1132GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX1132GISEL-NEXT: s_cbranch_execz .LBB4_4
; GFX1132GISEL-NEXT: ; %bb.3: ; %if
; GFX1132GISEL-NEXT: s_mov_b32 s2, exec_lo
@@ -2277,12 +2290,13 @@ define amdgpu_kernel void @divergent_cfg_float(ptr addrspace(1) %out, float %in,
; GFX1132GISEL-NEXT: v_cvt_f32_i32_e32 v0, s2
; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1132GISEL-NEXT: v_mul_f32_e32 v0, s1, v0
-; GFX1132GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1132GISEL-NEXT: v_readfirstlane_b32 s1, v0
+; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v0, s1
; GFX1132GISEL-NEXT: .LBB4_4: ; %endif
; GFX1132GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1132GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1132GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX1132GISEL-NEXT: s_endpgm
@@ -2962,7 +2976,10 @@ define amdgpu_kernel void @divergent_cfg_double(ptr addrspace(1) %out, double %i
; GFX8GISEL-NEXT: v_readfirstlane_b32 s7, v1
; GFX8GISEL-NEXT: .LBB7_2: ; %Flow
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8GISEL-NEXT: s_andn2_saveexec_b64 s[2:3], s[8:9]
+; GFX8GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[8:9]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s7
+; GFX8GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX8GISEL-NEXT: s_cbranch_execz .LBB7_4
; GFX8GISEL-NEXT: ; %bb.3: ; %if
; GFX8GISEL-NEXT: s_mov_b64 s[6:7], exec
@@ -2971,13 +2988,13 @@ define amdgpu_kernel void @divergent_cfg_double(ptr addrspace(1) %out, double %i
; GFX8GISEL-NEXT: v_cvt_f64_i32_e32 v[0:1], s6
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: v_mul_f64 v[0:1], s[4:5], v[0:1]
-; GFX8GISEL-NEXT: v_readfirstlane_b32 s6, v0
-; GFX8GISEL-NEXT: v_readfirstlane_b32 s7, v1
+; GFX8GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX8GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX8GISEL-NEXT: .LBB7_4: ; %endif
; GFX8GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s6
; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
-; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX8GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX8GISEL-NEXT: s_endpgm
@@ -3039,7 +3056,10 @@ define amdgpu_kernel void @divergent_cfg_double(ptr addrspace(1) %out, double %i
; GFX9GISEL-NEXT: v_readfirstlane_b32 s7, v1
; GFX9GISEL-NEXT: .LBB7_2: ; %Flow
; GFX9GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9GISEL-NEXT: s_andn2_saveexec_b64 s[2:3], s[8:9]
+; GFX9GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[8:9]
+; GFX9GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX9GISEL-NEXT: v_mov_b32_e32 v1, s7
+; GFX9GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX9GISEL-NEXT: s_cbranch_execz .LBB7_4
; GFX9GISEL-NEXT: ; %bb.3: ; %if
; GFX9GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
@@ -3048,12 +3068,12 @@ define amdgpu_kernel void @divergent_cfg_double(ptr addrspace(1) %out, double %i
; GFX9GISEL-NEXT: v_cvt_f64_i32_e32 v[0:1], s4
; GFX9GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9GISEL-NEXT: v_mul_f64 v[0:1], s[6:7], v[0:1]
-; GFX9GISEL-NEXT: v_readfirstlane_b32 s6, v0
-; GFX9GISEL-NEXT: v_readfirstlane_b32 s7, v1
+; GFX9GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX9GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; GFX9GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX9GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX9GISEL-NEXT: .LBB7_4: ; %endif
; GFX9GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX9GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX9GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX9GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX9GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX9GISEL-NEXT: s_endpgm
@@ -3102,21 +3122,24 @@ define amdgpu_kernel void @divergent_cfg_double(ptr addrspace(1) %out, double %i
; GFX1064GISEL: ; %bb.0: ; %entry
; GFX1064GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX1064GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v0
-; GFX1064GISEL-NEXT: ; implicit-def: $sgpr6_sgpr7
-; GFX1064GISEL-NEXT: s_and_saveexec_b64 s[8:9], vcc
-; GFX1064GISEL-NEXT: s_xor_b64 s[8:9], exec, s[8:9]
+; GFX1064GISEL-NEXT: ; implicit-def: $sgpr8_sgpr9
+; GFX1064GISEL-NEXT: s_and_saveexec_b64 s[6:7], vcc
+; GFX1064GISEL-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
; GFX1064GISEL-NEXT: s_cbranch_execz .LBB7_2
; GFX1064GISEL-NEXT: ; %bb.1: ; %else
-; GFX1064GISEL-NEXT: s_mov_b64 s[6:7], exec
-; GFX1064GISEL-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
-; GFX1064GISEL-NEXT: v_cvt_f64_i32_e32 v[0:1], s6
+; GFX1064GISEL-NEXT: s_mov_b64 s[8:9], exec
+; GFX1064GISEL-NEXT: s_bcnt1_i32_b64 s8, s[8:9]
+; GFX1064GISEL-NEXT: v_cvt_f64_i32_e32 v[0:1], s8
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064GISEL-NEXT: v_mul_f64 v[0:1], s[2:3], v[0:1]
-; GFX1064GISEL-NEXT: v_readfirstlane_b32 s6, v0
-; GFX1064GISEL-NEXT: v_readfirstlane_b32 s7, v1
+; GFX1064GISEL-NEXT: v_readfirstlane_b32 s8, v0
+; GFX1064GISEL-NEXT: v_readfirstlane_b32 s9, v1
; GFX1064GISEL-NEXT: .LBB7_2: ; %Flow
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064GISEL-NEXT: s_andn2_saveexec_b64 s[2:3], s[8:9]
+; GFX1064GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[6:7]
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s8
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s9
+; GFX1064GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX1064GISEL-NEXT: s_cbranch_execz .LBB7_4
; GFX1064GISEL-NEXT: ; %bb.3: ; %if
; GFX1064GISEL-NEXT: s_mov_b64 s[6:7], exec
@@ -3125,12 +3148,12 @@ define amdgpu_kernel void @divergent_cfg_double(ptr addrspace(1) %out, double %i
; GFX1064GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064GISEL-NEXT: v_mul_f64 v[0:1], s[6:7], v[0:1]
-; GFX1064GISEL-NEXT: v_readfirstlane_b32 s6, v0
-; GFX1064GISEL-NEXT: v_readfirstlane_b32 s7, v1
+; GFX1064GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX1064GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX1064GISEL-NEXT: .LBB7_4: ; %endif
; GFX1064GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX1064GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1064GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX1064GISEL-NEXT: s_endpgm
@@ -3193,7 +3216,10 @@ define amdgpu_kernel void @divergent_cfg_double(ptr addrspace(1) %out, double %i
; GFX1032GISEL-NEXT: v_readfirstlane_b32 s7, v1
; GFX1032GISEL-NEXT: .LBB7_2: ; %Flow
; GFX1032GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1032GISEL-NEXT: s_andn2_saveexec_b32 s2, s8
+; GFX1032GISEL-NEXT: s_or_saveexec_b32 s2, s8
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, s7
+; GFX1032GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s2
; GFX1032GISEL-NEXT: s_cbranch_execz .LBB7_4
; GFX1032GISEL-NEXT: ; %bb.3: ; %if
; GFX1032GISEL-NEXT: s_mov_b32 s3, exec_lo
@@ -3202,12 +3228,12 @@ define amdgpu_kernel void @divergent_cfg_double(ptr addrspace(1) %out, double %i
; GFX1032GISEL-NEXT: v_cvt_f64_i32_e32 v[0:1], s3
; GFX1032GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032GISEL-NEXT: v_mul_f64 v[0:1], s[6:7], v[0:1]
-; GFX1032GISEL-NEXT: v_readfirstlane_b32 s6, v0
-; GFX1032GISEL-NEXT: v_readfirstlane_b32 s7, v1
+; GFX1032GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX1032GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX1032GISEL-NEXT: .LBB7_4: ; %endif
; GFX1032GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s2
-; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX1032GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1032GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX1032GISEL-NEXT: s_endpgm
@@ -3266,26 +3292,30 @@ define amdgpu_kernel void @divergent_cfg_double(ptr addrspace(1) %out, double %i
; GFX1164GISEL: ; %bb.0: ; %entry
; GFX1164GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1164GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX1164GISEL-NEXT: s_mov_b64 s[8:9], exec
-; GFX1164GISEL-NEXT: ; implicit-def: $sgpr6_sgpr7
+; GFX1164GISEL-NEXT: s_mov_b64 s[6:7], exec
+; GFX1164GISEL-NEXT: ; implicit-def: $sgpr8_sgpr9
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164GISEL-NEXT: v_cmpx_le_u32_e32 16, v0
-; GFX1164GISEL-NEXT: s_xor_b64 s[8:9], exec, s[8:9]
+; GFX1164GISEL-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
; GFX1164GISEL-NEXT: s_cbranch_execz .LBB7_2
; GFX1164GISEL-NEXT: ; %bb.1: ; %else
-; GFX1164GISEL-NEXT: s_mov_b64 s[6:7], exec
+; GFX1164GISEL-NEXT: s_mov_b64 s[8:9], exec
; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1164GISEL-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
-; GFX1164GISEL-NEXT: v_cvt_f64_i32_e32 v[0:1], s6
+; GFX1164GISEL-NEXT: s_bcnt1_i32_b64 s8, s[8:9]
+; GFX1164GISEL-NEXT: v_cvt_f64_i32_e32 v[0:1], s8
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164GISEL-NEXT: v_mul_f64 v[0:1], s[2:3], v[0:1]
-; GFX1164GISEL-NEXT: v_readfirstlane_b32 s6, v0
+; GFX1164GISEL-NEXT: v_readfirstlane_b32 s8, v0
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1164GISEL-NEXT: v_readfirstlane_b32 s7, v1
+; GFX1164GISEL-NEXT: v_readfirstlane_b32 s9, v1
; GFX1164GISEL-NEXT: .LBB7_2: ; %Flow
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-NEXT: s_and_not1_saveexec_b64 s[2:3], s[8:9]
+; GFX1164GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[6:7]
+; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s8
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s9
+; GFX1164GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX1164GISEL-NEXT: s_cbranch_execz .LBB7_4
; GFX1164GISEL-NEXT: ; %bb.3: ; %if
; GFX1164GISEL-NEXT: s_mov_b64 s[6:7], exec
@@ -3296,13 +3326,13 @@ define amdgpu_kernel void @divergent_cfg_double(ptr addrspace(1) %out, double %i
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164GISEL-NEXT: v_mul_f64 v[0:1], s[4:5], v[0:1]
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1164GISEL-NEXT: v_readfirstlane_b32 s6, v0
-; GFX1164GISEL-NEXT: v_readfirstlane_b32 s7, v1
+; GFX1164GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX1164GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX1164GISEL-NEXT: .LBB7_4: ; %endif
; GFX1164GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX1164GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1164GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX1164GISEL-NEXT: s_endpgm
@@ -3377,7 +3407,10 @@ define amdgpu_kernel void @divergent_cfg_double(ptr addrspace(1) %out, double %i
; GFX1132GISEL-NEXT: v_readfirstlane_b32 s7, v1
; GFX1132GISEL-NEXT: .LBB7_2: ; %Flow
; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-NEXT: s_and_not1_saveexec_b32 s2, s8
+; GFX1132GISEL-NEXT: s_or_saveexec_b32 s2, s8
+; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1132GISEL-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
+; GFX1132GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s2
; GFX1132GISEL-NEXT: s_cbranch_execz .LBB7_4
; GFX1132GISEL-NEXT: ; %bb.3: ; %if
; GFX1132GISEL-NEXT: s_mov_b32 s3, exec_lo
@@ -3388,12 +3421,12 @@ define amdgpu_kernel void @divergent_cfg_double(ptr addrspace(1) %out, double %i
; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132GISEL-NEXT: v_mul_f64 v[0:1], s[4:5], v[0:1]
; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1132GISEL-NEXT: v_readfirstlane_b32 s6, v0
-; GFX1132GISEL-NEXT: v_readfirstlane_b32 s7, v1
+; GFX1132GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX1132GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1132GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
; GFX1132GISEL-NEXT: .LBB7_4: ; %endif
; GFX1132GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s2
-; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1132GISEL-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
; GFX1132GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1132GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX1132GISEL-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
index 1e151ccf20c36..400611e205c8a 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
@@ -1,16 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=0 < %s | FileCheck -check-prefixes=GFX8DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=1 < %s | FileCheck -check-prefixes=GFX8GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX8GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=0 < %s | FileCheck -check-prefixes=GFX9DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=1 < %s | FileCheck -check-prefixes=GFX9GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX9GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1064DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1064GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1064GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1032DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1032GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1032GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1164DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1164GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1164GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1132DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1132GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1132GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -global-isel=0 < %s | FileCheck -check-prefixes=GFX12DAGISEL %s
@@ -1789,30 +1789,32 @@ define void @divergent_cfg_float(ptr addrspace(1) %out, float %in, float %in2) {
; GFX8GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8GISEL-NEXT: v_and_b32_e32 v4, 0x3ff, v31
; GFX8GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v4
-; GFX8GISEL-NEXT: ; implicit-def: $sgpr8
+; GFX8GISEL-NEXT: ; implicit-def: $vgpr4
; GFX8GISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX8GISEL-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
-; GFX8GISEL-NEXT: s_cbranch_execz .LBB4_3
+; GFX8GISEL-NEXT: s_cbranch_execz .LBB4_4
; GFX8GISEL-NEXT: ; %bb.1: ; %else
; GFX8GISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX8GISEL-NEXT: s_mov_b32 s8, 0x7fc00000
-; GFX8GISEL-NEXT: ; implicit-def: $vgpr3
; GFX8GISEL-NEXT: .LBB4_2: ; =>This Inner Loop Header: Depth=1
; GFX8GISEL-NEXT: s_ff1_i32_b64 s9, s[6:7]
; GFX8GISEL-NEXT: v_readlane_b32 s10, v2, s9
-; GFX8GISEL-NEXT: v_mov_b32_e32 v4, s10
+; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s10
; GFX8GISEL-NEXT: s_bitset0_b64 s[6:7], s9
-; GFX8GISEL-NEXT: v_max_f32_e32 v4, s8, v4
+; GFX8GISEL-NEXT: v_max_f32_e32 v3, s8, v3
; GFX8GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
-; GFX8GISEL-NEXT: v_readfirstlane_b32 s8, v4
+; GFX8GISEL-NEXT: v_readfirstlane_b32 s8, v3
; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB4_2
-; GFX8GISEL-NEXT: .LBB4_3: ; %Flow
+; GFX8GISEL-NEXT: ; %bb.3:
+; GFX8GISEL-NEXT: v_mov_b32_e32 v4, s8
+; GFX8GISEL-NEXT: ; implicit-def: $vgpr3
+; GFX8GISEL-NEXT: .LBB4_4: ; %Flow
; GFX8GISEL-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX8GISEL-NEXT: s_cbranch_execz .LBB4_6
-; GFX8GISEL-NEXT: ; %bb.4: ; %if
+; GFX8GISEL-NEXT: s_cbranch_execz .LBB4_8
+; GFX8GISEL-NEXT: ; %bb.5: ; %if
; GFX8GISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX8GISEL-NEXT: s_mov_b32 s8, 0x7fc00000
-; GFX8GISEL-NEXT: .LBB4_5: ; =>This Inner Loop Header: Depth=1
+; GFX8GISEL-NEXT: .LBB4_6: ; =>This Inner Loop Header: Depth=1
; GFX8GISEL-NEXT: s_ff1_i32_b64 s9, s[6:7]
; GFX8GISEL-NEXT: v_readlane_b32 s10, v3, s9
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s10
@@ -1820,11 +1822,12 @@ define void @divergent_cfg_float(ptr addrspace(1) %out, float %in, float %in2) {
; GFX8GISEL-NEXT: v_max_f32_e32 v2, s8, v2
; GFX8GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
; GFX8GISEL-NEXT: v_readfirstlane_b32 s8, v2
-; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB4_5
-; GFX8GISEL-NEXT: .LBB4_6: ; %endif
+; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB4_6
+; GFX8GISEL-NEXT: ; %bb.7:
+; GFX8GISEL-NEXT: v_mov_b32_e32 v4, s8
+; GFX8GISEL-NEXT: .LBB4_8: ; %endif
; GFX8GISEL-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s8
-; GFX8GISEL-NEXT: flat_store_dword v[0:1], v2
+; GFX8GISEL-NEXT: flat_store_dword v[0:1], v4
; GFX8GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX8GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -1880,30 +1883,32 @@ define void @divergent_cfg_float(ptr addrspace(1) %out, float %in, float %in2) {
; GFX9GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9GISEL-NEXT: v_and_b32_e32 v4, 0x3ff, v31
; GFX9GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v4
-; GFX9GISEL-NEXT: ; implicit-def: $sgpr8
+; GFX9GISEL-NEXT: ; implicit-def: $vgpr4
; GFX9GISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9GISEL-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
-; GFX9GISEL-NEXT: s_cbranch_execz .LBB4_3
+; GFX9GISEL-NEXT: s_cbranch_execz .LBB4_4
; GFX9GISEL-NEXT: ; %bb.1: ; %else
; GFX9GISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX9GISEL-NEXT: s_mov_b32 s8, 0x7fc00000
-; GFX9GISEL-NEXT: ; implicit-def: $vgpr3
; GFX9GISEL-NEXT: .LBB4_2: ; =>This Inner Loop Header: Depth=1
; GFX9GISEL-NEXT: s_ff1_i32_b64 s9, s[6:7]
; GFX9GISEL-NEXT: v_readlane_b32 s10, v2, s9
-; GFX9GISEL-NEXT: v_mov_b32_e32 v4, s10
+; GFX9GISEL-NEXT: v_mov_b32_e32 v3, s10
; GFX9GISEL-NEXT: s_bitset0_b64 s[6:7], s9
-; GFX9GISEL-NEXT: v_max_f32_e32 v4, s8, v4
+; GFX9GISEL-NEXT: v_max_f32_e32 v3, s8, v3
; GFX9GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
-; GFX9GISEL-NEXT: v_readfirstlane_b32 s8, v4
+; GFX9GISEL-NEXT: v_readfirstlane_b32 s8, v3
; GFX9GISEL-NEXT: s_cbranch_scc1 .LBB4_2
-; GFX9GISEL-NEXT: .LBB4_3: ; %Flow
+; GFX9GISEL-NEXT: ; %bb.3:
+; GFX9GISEL-NEXT: v_mov_b32_e32 v4, s8
+; GFX9GISEL-NEXT: ; implicit-def: $vgpr3
+; GFX9GISEL-NEXT: .LBB4_4: ; %Flow
; GFX9GISEL-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9GISEL-NEXT: s_cbranch_execz .LBB4_6
-; GFX9GISEL-NEXT: ; %bb.4: ; %if
+; GFX9GISEL-NEXT: s_cbranch_execz .LBB4_8
+; GFX9GISEL-NEXT: ; %bb.5: ; %if
; GFX9GISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX9GISEL-NEXT: s_mov_b32 s8, 0x7fc00000
-; GFX9GISEL-NEXT: .LBB4_5: ; =>This Inner Loop Header: Depth=1
+; GFX9GISEL-NEXT: .LBB4_6: ; =>This Inner Loop Header: Depth=1
; GFX9GISEL-NEXT: s_ff1_i32_b64 s9, s[6:7]
; GFX9GISEL-NEXT: v_readlane_b32 s10, v3, s9
; GFX9GISEL-NEXT: v_mov_b32_e32 v2, s10
@@ -1911,11 +1916,12 @@ define void @divergent_cfg_float(ptr addrspace(1) %out, float %in, float %in2) {
; GFX9GISEL-NEXT: v_max_f32_e32 v2, s8, v2
; GFX9GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
; GFX9GISEL-NEXT: v_readfirstlane_b32 s8, v2
-; GFX9GISEL-NEXT: s_cbranch_scc1 .LBB4_5
-; GFX9GISEL-NEXT: .LBB4_6: ; %endif
+; GFX9GISEL-NEXT: s_cbranch_scc1 .LBB4_6
+; GFX9GISEL-NEXT: ; %bb.7:
+; GFX9GISEL-NEXT: v_mov_b32_e32 v4, s8
+; GFX9GISEL-NEXT: .LBB4_8: ; %endif
; GFX9GISEL-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX9GISEL-NEXT: v_mov_b32_e32 v2, s8
-; GFX9GISEL-NEXT: global_store_dword v[0:1], v2, off
+; GFX9GISEL-NEXT: global_store_dword v[0:1], v4, off
; GFX9GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX9GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -1967,11 +1973,11 @@ define void @divergent_cfg_float(ptr addrspace(1) %out, float %in, float %in2) {
; GFX1064GISEL: ; %bb.0: ; %entry
; GFX1064GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1064GISEL-NEXT: v_and_b32_e32 v4, 0x3ff, v31
-; GFX1064GISEL-NEXT: ; implicit-def: $sgpr8
; GFX1064GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v4
+; GFX1064GISEL-NEXT: ; implicit-def: $vgpr4
; GFX1064GISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX1064GISEL-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
-; GFX1064GISEL-NEXT: s_cbranch_execz .LBB4_3
+; GFX1064GISEL-NEXT: s_cbranch_execz .LBB4_4
; GFX1064GISEL-NEXT: ; %bb.1: ; %else
; GFX1064GISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX1064GISEL-NEXT: s_mov_b32 s8, 0x7fc00000
@@ -1982,26 +1988,29 @@ define void @divergent_cfg_float(ptr addrspace(1) %out, float %in, float %in2) {
; GFX1064GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
; GFX1064GISEL-NEXT: v_max_f32_e64 v3, s8, s10
; GFX1064GISEL-NEXT: v_readfirstlane_b32 s8, v3
-; GFX1064GISEL-NEXT: ; implicit-def: $vgpr3
; GFX1064GISEL-NEXT: s_cbranch_scc1 .LBB4_2
-; GFX1064GISEL-NEXT: .LBB4_3: ; %Flow
+; GFX1064GISEL-NEXT: ; %bb.3:
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v4, s8
+; GFX1064GISEL-NEXT: ; implicit-def: $vgpr3
+; GFX1064GISEL-NEXT: .LBB4_4: ; %Flow
; GFX1064GISEL-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX1064GISEL-NEXT: s_cbranch_execz .LBB4_6
-; GFX1064GISEL-NEXT: ; %bb.4: ; %if
+; GFX1064GISEL-NEXT: s_cbranch_execz .LBB4_8
+; GFX1064GISEL-NEXT: ; %bb.5: ; %if
; GFX1064GISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX1064GISEL-NEXT: s_mov_b32 s8, 0x7fc00000
-; GFX1064GISEL-NEXT: .LBB4_5: ; =>This Inner Loop Header: Depth=1
+; GFX1064GISEL-NEXT: .LBB4_6: ; =>This Inner Loop Header: Depth=1
; GFX1064GISEL-NEXT: s_ff1_i32_b64 s9, s[6:7]
; GFX1064GISEL-NEXT: v_readlane_b32 s10, v3, s9
; GFX1064GISEL-NEXT: s_bitset0_b64 s[6:7], s9
; GFX1064GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
; GFX1064GISEL-NEXT: v_max_f32_e64 v2, s8, s10
; GFX1064GISEL-NEXT: v_readfirstlane_b32 s8, v2
-; GFX1064GISEL-NEXT: s_cbranch_scc1 .LBB4_5
-; GFX1064GISEL-NEXT: .LBB4_6: ; %endif
+; GFX1064GISEL-NEXT: s_cbranch_scc1 .LBB4_6
+; GFX1064GISEL-NEXT: ; %bb.7:
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v4, s8
+; GFX1064GISEL-NEXT: .LBB4_8: ; %endif
; GFX1064GISEL-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v2, s8
-; GFX1064GISEL-NEXT: global_store_dword v[0:1], v2, off
+; GFX1064GISEL-NEXT: global_store_dword v[0:1], v4, off
; GFX1064GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1032DAGISEL-LABEL: divergent_cfg_float:
@@ -2052,41 +2061,44 @@ define void @divergent_cfg_float(ptr addrspace(1) %out, float %in, float %in2) {
; GFX1032GISEL: ; %bb.0: ; %entry
; GFX1032GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1032GISEL-NEXT: v_and_b32_e32 v4, 0x3ff, v31
-; GFX1032GISEL-NEXT: ; implicit-def: $sgpr4
; GFX1032GISEL-NEXT: v_cmp_le_u32_e32 vcc_lo, 16, v4
-; GFX1032GISEL-NEXT: s_and_saveexec_b32 s5, vcc_lo
-; GFX1032GISEL-NEXT: s_xor_b32 s5, exec_lo, s5
-; GFX1032GISEL-NEXT: s_cbranch_execz .LBB4_3
+; GFX1032GISEL-NEXT: ; implicit-def: $vgpr4
+; GFX1032GISEL-NEXT: s_and_saveexec_b32 s4, vcc_lo
+; GFX1032GISEL-NEXT: s_xor_b32 s4, exec_lo, s4
+; GFX1032GISEL-NEXT: s_cbranch_execz .LBB4_4
; GFX1032GISEL-NEXT: ; %bb.1: ; %else
-; GFX1032GISEL-NEXT: s_mov_b32 s6, exec_lo
-; GFX1032GISEL-NEXT: s_mov_b32 s4, 0x7fc00000
+; GFX1032GISEL-NEXT: s_mov_b32 s5, exec_lo
+; GFX1032GISEL-NEXT: s_mov_b32 s6, 0x7fc00000
; GFX1032GISEL-NEXT: .LBB4_2: ; =>This Inner Loop Header: Depth=1
-; GFX1032GISEL-NEXT: s_ff1_i32_b32 s7, s6
+; GFX1032GISEL-NEXT: s_ff1_i32_b32 s7, s5
; GFX1032GISEL-NEXT: v_readlane_b32 s8, v2, s7
-; GFX1032GISEL-NEXT: s_bitset0_b32 s6, s7
-; GFX1032GISEL-NEXT: s_cmp_lg_u32 s6, 0
-; GFX1032GISEL-NEXT: v_max_f32_e64 v3, s4, s8
-; GFX1032GISEL-NEXT: v_readfirstlane_b32 s4, v3
-; GFX1032GISEL-NEXT: ; implicit-def: $vgpr3
+; GFX1032GISEL-NEXT: s_bitset0_b32 s5, s7
+; GFX1032GISEL-NEXT: s_cmp_lg_u32 s5, 0
+; GFX1032GISEL-NEXT: v_max_f32_e64 v3, s6, s8
+; GFX1032GISEL-NEXT: v_readfirstlane_b32 s6, v3
; GFX1032GISEL-NEXT: s_cbranch_scc1 .LBB4_2
-; GFX1032GISEL-NEXT: .LBB4_3: ; %Flow
-; GFX1032GISEL-NEXT: s_andn2_saveexec_b32 s5, s5
-; GFX1032GISEL-NEXT: s_cbranch_execz .LBB4_6
-; GFX1032GISEL-NEXT: ; %bb.4: ; %if
-; GFX1032GISEL-NEXT: s_mov_b32 s6, exec_lo
-; GFX1032GISEL-NEXT: s_mov_b32 s4, 0x7fc00000
-; GFX1032GISEL-NEXT: .LBB4_5: ; =>This Inner Loop Header: Depth=1
-; GFX1032GISEL-NEXT: s_ff1_i32_b32 s7, s6
+; GFX1032GISEL-NEXT: ; %bb.3:
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v4, s6
+; GFX1032GISEL-NEXT: ; implicit-def: $vgpr3
+; GFX1032GISEL-NEXT: .LBB4_4: ; %Flow
+; GFX1032GISEL-NEXT: s_andn2_saveexec_b32 s4, s4
+; GFX1032GISEL-NEXT: s_cbranch_execz .LBB4_8
+; GFX1032GISEL-NEXT: ; %bb.5: ; %if
+; GFX1032GISEL-NEXT: s_mov_b32 s5, exec_lo
+; GFX1032GISEL-NEXT: s_mov_b32 s6, 0x7fc00000
+; GFX1032GISEL-NEXT: .LBB4_6: ; =>This Inner Loop Header: Depth=1
+; GFX1032GISEL-NEXT: s_ff1_i32_b32 s7, s5
; GFX1032GISEL-NEXT: v_readlane_b32 s8, v3, s7
-; GFX1032GISEL-NEXT: s_bitset0_b32 s6, s7
-; GFX1032GISEL-NEXT: s_cmp_lg_u32 s6, 0
-; GFX1032GISEL-NEXT: v_max_f32_e64 v2, s4, s8
-; GFX1032GISEL-NEXT: v_readfirstlane_b32 s4, v2
-; GFX1032GISEL-NEXT: s_cbranch_scc1 .LBB4_5
-; GFX1032GISEL-NEXT: .LBB4_6: ; %endif
-; GFX1032GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s5
-; GFX1032GISEL-NEXT: v_mov_b32_e32 v2, s4
-; GFX1032GISEL-NEXT: global_store_dword v[0:1], v2, off
+; GFX1032GISEL-NEXT: s_bitset0_b32 s5, s7
+; GFX1032GISEL-NEXT: s_cmp_lg_u32 s5, 0
+; GFX1032GISEL-NEXT: v_max_f32_e64 v2, s6, s8
+; GFX1032GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; GFX1032GISEL-NEXT: s_cbranch_scc1 .LBB4_6
+; GFX1032GISEL-NEXT: ; %bb.7:
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v4, s6
+; GFX1032GISEL-NEXT: .LBB4_8: ; %endif
+; GFX1032GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s4
+; GFX1032GISEL-NEXT: global_store_dword v[0:1], v4, off
; GFX1032GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1164DAGISEL-LABEL: divergent_cfg_float:
@@ -2142,12 +2154,12 @@ define void @divergent_cfg_float(ptr addrspace(1) %out, float %in, float %in2) {
; GFX1164GISEL: ; %bb.0: ; %entry
; GFX1164GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1164GISEL-NEXT: v_and_b32_e32 v4, 0x3ff, v31
-; GFX1164GISEL-NEXT: s_mov_b64 s[0:1], exec
-; GFX1164GISEL-NEXT: ; implicit-def: $sgpr4
-; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1164GISEL-NEXT: v_cmpx_le_u32_e32 16, v4
+; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1164GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v4
+; GFX1164GISEL-NEXT: ; implicit-def: $vgpr4
+; GFX1164GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1164GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
-; GFX1164GISEL-NEXT: s_cbranch_execz .LBB4_3
+; GFX1164GISEL-NEXT: s_cbranch_execz .LBB4_4
; GFX1164GISEL-NEXT: ; %bb.1: ; %else
; GFX1164GISEL-NEXT: s_mov_b64 s[2:3], exec
; GFX1164GISEL-NEXT: s_mov_b32 s4, 0x7fc00000
@@ -2160,15 +2172,17 @@ define void @divergent_cfg_float(ptr addrspace(1) %out, float %in, float %in2) {
; GFX1164GISEL-NEXT: v_max_f32_e64 v3, s4, s6
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164GISEL-NEXT: v_readfirstlane_b32 s4, v3
-; GFX1164GISEL-NEXT: ; implicit-def: $vgpr3
; GFX1164GISEL-NEXT: s_cbranch_scc1 .LBB4_2
-; GFX1164GISEL-NEXT: .LBB4_3: ; %Flow
+; GFX1164GISEL-NEXT: ; %bb.3:
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v4, s4
+; GFX1164GISEL-NEXT: ; implicit-def: $vgpr3
+; GFX1164GISEL-NEXT: .LBB4_4: ; %Flow
; GFX1164GISEL-NEXT: s_and_not1_saveexec_b64 s[0:1], s[0:1]
-; GFX1164GISEL-NEXT: s_cbranch_execz .LBB4_6
-; GFX1164GISEL-NEXT: ; %bb.4: ; %if
+; GFX1164GISEL-NEXT: s_cbranch_execz .LBB4_8
+; GFX1164GISEL-NEXT: ; %bb.5: ; %if
; GFX1164GISEL-NEXT: s_mov_b64 s[2:3], exec
; GFX1164GISEL-NEXT: s_mov_b32 s4, 0x7fc00000
-; GFX1164GISEL-NEXT: .LBB4_5: ; =>This Inner Loop Header: Depth=1
+; GFX1164GISEL-NEXT: .LBB4_6: ; =>This Inner Loop Header: Depth=1
; GFX1164GISEL-NEXT: s_ctz_i32_b64 s5, s[2:3]
; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1164GISEL-NEXT: v_readlane_b32 s6, v3, s5
@@ -2177,11 +2191,12 @@ define void @divergent_cfg_float(ptr addrspace(1) %out, float %in, float %in2) {
; GFX1164GISEL-NEXT: v_max_f32_e64 v2, s4, s6
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164GISEL-NEXT: v_readfirstlane_b32 s4, v2
-; GFX1164GISEL-NEXT: s_cbranch_scc1 .LBB4_5
-; GFX1164GISEL-NEXT: .LBB4_6: ; %endif
+; GFX1164GISEL-NEXT: s_cbranch_scc1 .LBB4_6
+; GFX1164GISEL-NEXT: ; %bb.7:
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v4, s4
+; GFX1164GISEL-NEXT: .LBB4_8: ; %endif
; GFX1164GISEL-NEXT: s_or_b64 exec, exec, s[0:1]
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v2, s4
-; GFX1164GISEL-NEXT: global_store_b32 v[0:1], v2, off
+; GFX1164GISEL-NEXT: global_store_b32 v[0:1], v4, off
; GFX1164GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1132DAGISEL-LABEL: divergent_cfg_float:
@@ -2237,46 +2252,49 @@ define void @divergent_cfg_float(ptr addrspace(1) %out, float %in, float %in2) {
; GFX1132GISEL: ; %bb.0: ; %entry
; GFX1132GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1132GISEL-NEXT: v_and_b32_e32 v4, 0x3ff, v31
-; GFX1132GISEL-NEXT: s_mov_b32 s1, exec_lo
-; GFX1132GISEL-NEXT: ; implicit-def: $sgpr0
-; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1132GISEL-NEXT: v_cmpx_le_u32_e32 16, v4
-; GFX1132GISEL-NEXT: s_xor_b32 s1, exec_lo, s1
-; GFX1132GISEL-NEXT: s_cbranch_execz .LBB4_3
+; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1132GISEL-NEXT: v_cmp_le_u32_e32 vcc_lo, 16, v4
+; GFX1132GISEL-NEXT: ; implicit-def: $vgpr4
+; GFX1132GISEL-NEXT: s_and_saveexec_b32 s0, vcc_lo
+; GFX1132GISEL-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX1132GISEL-NEXT: s_cbranch_execz .LBB4_4
; GFX1132GISEL-NEXT: ; %bb.1: ; %else
-; GFX1132GISEL-NEXT: s_mov_b32 s2, exec_lo
-; GFX1132GISEL-NEXT: s_mov_b32 s0, 0x7fc00000
+; GFX1132GISEL-NEXT: s_mov_b32 s1, exec_lo
+; GFX1132GISEL-NEXT: s_mov_b32 s2, 0x7fc00000
; GFX1132GISEL-NEXT: .LBB4_2: ; =>This Inner Loop Header: Depth=1
-; GFX1132GISEL-NEXT: s_ctz_i32_b32 s3, s2
+; GFX1132GISEL-NEXT: s_ctz_i32_b32 s3, s1
; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1132GISEL-NEXT: v_readlane_b32 s4, v2, s3
-; GFX1132GISEL-NEXT: s_bitset0_b32 s2, s3
-; GFX1132GISEL-NEXT: s_cmp_lg_u32 s2, 0
-; GFX1132GISEL-NEXT: v_max_f32_e64 v3, s0, s4
+; GFX1132GISEL-NEXT: s_bitset0_b32 s1, s3
+; GFX1132GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1132GISEL-NEXT: v_max_f32_e64 v3, s2, s4
; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1132GISEL-NEXT: v_readfirstlane_b32 s0, v3
-; GFX1132GISEL-NEXT: ; implicit-def: $vgpr3
+; GFX1132GISEL-NEXT: v_readfirstlane_b32 s2, v3
; GFX1132GISEL-NEXT: s_cbranch_scc1 .LBB4_2
-; GFX1132GISEL-NEXT: .LBB4_3: ; %Flow
-; GFX1132GISEL-NEXT: s_and_not1_saveexec_b32 s1, s1
-; GFX1132GISEL-NEXT: s_cbranch_execz .LBB4_6
-; GFX1132GISEL-NEXT: ; %bb.4: ; %if
-; GFX1132GISEL-NEXT: s_mov_b32 s2, exec_lo
-; GFX1132GISEL-NEXT: s_mov_b32 s0, 0x7fc00000
-; GFX1132GISEL-NEXT: .LBB4_5: ; =>This Inner Loop Header: Depth=1
-; GFX1132GISEL-NEXT: s_ctz_i32_b32 s3, s2
+; GFX1132GISEL-NEXT: ; %bb.3:
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v4, s2
+; GFX1132GISEL-NEXT: ; implicit-def: $vgpr3
+; GFX1132GISEL-NEXT: .LBB4_4: ; %Flow
+; GFX1132GISEL-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX1132GISEL-NEXT: s_cbranch_execz .LBB4_8
+; GFX1132GISEL-NEXT: ; %bb.5: ; %if
+; GFX1132GISEL-NEXT: s_mov_b32 s1, exec_lo
+; GFX1132GISEL-NEXT: s_mov_b32 s2, 0x7fc00000
+; GFX1132GISEL-NEXT: .LBB4_6: ; =>This Inner Loop Header: Depth=1
+; GFX1132GISEL-NEXT: s_ctz_i32_b32 s3, s1
; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1132GISEL-NEXT: v_readlane_b32 s4, v3, s3
-; GFX1132GISEL-NEXT: s_bitset0_b32 s2, s3
-; GFX1132GISEL-NEXT: s_cmp_lg_u32 s2, 0
-; GFX1132GISEL-NEXT: v_max_f32_e64 v2, s0, s4
+; GFX1132GISEL-NEXT: s_bitset0_b32 s1, s3
+; GFX1132GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1132GISEL-NEXT: v_max_f32_e64 v2, s2, s4
; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1132GISEL-NEXT: v_readfirstlane_b32 s0, v2
-; GFX1132GISEL-NEXT: s_cbranch_scc1 .LBB4_5
-; GFX1132GISEL-NEXT: .LBB4_6: ; %endif
-; GFX1132GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s1
-; GFX1132GISEL-NEXT: v_mov_b32_e32 v2, s0
-; GFX1132GISEL-NEXT: global_store_b32 v[0:1], v2, off
+; GFX1132GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; GFX1132GISEL-NEXT: s_cbranch_scc1 .LBB4_6
+; GFX1132GISEL-NEXT: ; %bb.7:
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v4, s2
+; GFX1132GISEL-NEXT: .LBB4_8: ; %endif
+; GFX1132GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX1132GISEL-NEXT: global_store_b32 v[0:1], v4, off
; GFX1132GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12DAGISEL-LABEL: divergent_cfg_float:
@@ -2860,52 +2878,56 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX8GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8GISEL-NEXT: v_and_b32_e32 v6, 0x3ff, v31
; GFX8GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v6
-; GFX8GISEL-NEXT: ; implicit-def: $sgpr4_sgpr5
-; GFX8GISEL-NEXT: s_and_saveexec_b64 s[6:7], vcc
-; GFX8GISEL-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
-; GFX8GISEL-NEXT: s_cbranch_execz .LBB7_3
+; GFX8GISEL-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX8GISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc
+; GFX8GISEL-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX8GISEL-NEXT: s_cbranch_execz .LBB7_4
; GFX8GISEL-NEXT: ; %bb.1: ; %else
-; GFX8GISEL-NEXT: s_mov_b32 s4, 0
-; GFX8GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
-; GFX8GISEL-NEXT: s_mov_b64 s[8:9], exec
+; GFX8GISEL-NEXT: s_mov_b32 s8, 0
+; GFX8GISEL-NEXT: s_mov_b32 s9, 0x7ff80000
+; GFX8GISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX8GISEL-NEXT: .LBB7_2: ; =>This Inner Loop Header: Depth=1
-; GFX8GISEL-NEXT: s_ff1_i32_b64 s12, s[8:9]
-; GFX8GISEL-NEXT: v_mov_b32_e32 v4, s4
+; GFX8GISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v4, s8
; GFX8GISEL-NEXT: v_readlane_b32 s10, v2, s12
; GFX8GISEL-NEXT: v_readlane_b32 s11, v3, s12
-; GFX8GISEL-NEXT: v_mov_b32_e32 v5, s5
+; GFX8GISEL-NEXT: v_mov_b32_e32 v5, s9
; GFX8GISEL-NEXT: v_max_f64 v[4:5], s[10:11], v[4:5]
-; GFX8GISEL-NEXT: s_bitset0_b64 s[8:9], s12
-; GFX8GISEL-NEXT: s_cmp_lg_u64 s[8:9], 0
-; GFX8GISEL-NEXT: v_readfirstlane_b32 s4, v4
-; GFX8GISEL-NEXT: v_readfirstlane_b32 s5, v5
+; GFX8GISEL-NEXT: s_bitset0_b64 s[6:7], s12
+; GFX8GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; GFX8GISEL-NEXT: v_readfirstlane_b32 s8, v4
+; GFX8GISEL-NEXT: v_readfirstlane_b32 s9, v5
+; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB7_2
+; GFX8GISEL-NEXT: ; %bb.3:
+; GFX8GISEL-NEXT: v_mov_b32_e32 v6, s8
+; GFX8GISEL-NEXT: v_mov_b32_e32 v7, s9
; GFX8GISEL-NEXT: ; implicit-def: $vgpr4
; GFX8GISEL-NEXT: ; implicit-def: $vgpr5
-; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB7_2
-; GFX8GISEL-NEXT: .LBB7_3: ; %Flow
-; GFX8GISEL-NEXT: s_andn2_saveexec_b64 s[6:7], s[6:7]
-; GFX8GISEL-NEXT: s_cbranch_execz .LBB7_6
-; GFX8GISEL-NEXT: ; %bb.4: ; %if
-; GFX8GISEL-NEXT: s_mov_b32 s4, 0
-; GFX8GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
-; GFX8GISEL-NEXT: s_mov_b64 s[8:9], exec
-; GFX8GISEL-NEXT: .LBB7_5: ; =>This Inner Loop Header: Depth=1
-; GFX8GISEL-NEXT: s_ff1_i32_b64 s12, s[8:9]
-; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s4
+; GFX8GISEL-NEXT: .LBB7_4: ; %Flow
+; GFX8GISEL-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX8GISEL-NEXT: s_cbranch_execz .LBB7_8
+; GFX8GISEL-NEXT: ; %bb.5: ; %if
+; GFX8GISEL-NEXT: s_mov_b32 s8, 0
+; GFX8GISEL-NEXT: s_mov_b32 s9, 0x7ff80000
+; GFX8GISEL-NEXT: s_mov_b64 s[6:7], exec
+; GFX8GISEL-NEXT: .LBB7_6: ; =>This Inner Loop Header: Depth=1
+; GFX8GISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s8
; GFX8GISEL-NEXT: v_readlane_b32 s10, v4, s12
; GFX8GISEL-NEXT: v_readlane_b32 s11, v5, s12
-; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s5
+; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s9
; GFX8GISEL-NEXT: v_max_f64 v[2:3], s[10:11], v[2:3]
-; GFX8GISEL-NEXT: s_bitset0_b64 s[8:9], s12
-; GFX8GISEL-NEXT: s_cmp_lg_u64 s[8:9], 0
-; GFX8GISEL-NEXT: v_readfirstlane_b32 s4, v2
-; GFX8GISEL-NEXT: v_readfirstlane_b32 s5, v3
-; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB7_5
-; GFX8GISEL-NEXT: .LBB7_6: ; %endif
-; GFX8GISEL-NEXT: s_or_b64 exec, exec, s[6:7]
-; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s4
-; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s5
-; GFX8GISEL-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; GFX8GISEL-NEXT: s_bitset0_b64 s[6:7], s12
+; GFX8GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; GFX8GISEL-NEXT: v_readfirstlane_b32 s8, v2
+; GFX8GISEL-NEXT: v_readfirstlane_b32 s9, v3
+; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB7_6
+; GFX8GISEL-NEXT: ; %bb.7:
+; GFX8GISEL-NEXT: v_mov_b32_e32 v6, s8
+; GFX8GISEL-NEXT: v_mov_b32_e32 v7, s9
+; GFX8GISEL-NEXT: .LBB7_8: ; %endif
+; GFX8GISEL-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX8GISEL-NEXT: flat_store_dwordx2 v[0:1], v[6:7]
; GFX8GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX8GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2972,52 +2994,56 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX9GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9GISEL-NEXT: v_and_b32_e32 v6, 0x3ff, v31
; GFX9GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v6
-; GFX9GISEL-NEXT: ; implicit-def: $sgpr4_sgpr5
-; GFX9GISEL-NEXT: s_and_saveexec_b64 s[6:7], vcc
-; GFX9GISEL-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
-; GFX9GISEL-NEXT: s_cbranch_execz .LBB7_3
+; GFX9GISEL-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX9GISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc
+; GFX9GISEL-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9GISEL-NEXT: s_cbranch_execz .LBB7_4
; GFX9GISEL-NEXT: ; %bb.1: ; %else
-; GFX9GISEL-NEXT: s_mov_b32 s4, 0
-; GFX9GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
-; GFX9GISEL-NEXT: s_mov_b64 s[8:9], exec
+; GFX9GISEL-NEXT: s_mov_b32 s8, 0
+; GFX9GISEL-NEXT: s_mov_b32 s9, 0x7ff80000
+; GFX9GISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX9GISEL-NEXT: .LBB7_2: ; =>This Inner Loop Header: Depth=1
-; GFX9GISEL-NEXT: s_ff1_i32_b64 s12, s[8:9]
-; GFX9GISEL-NEXT: v_mov_b32_e32 v4, s4
+; GFX9GISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
+; GFX9GISEL-NEXT: v_mov_b32_e32 v4, s8
; GFX9GISEL-NEXT: v_readlane_b32 s10, v2, s12
; GFX9GISEL-NEXT: v_readlane_b32 s11, v3, s12
-; GFX9GISEL-NEXT: v_mov_b32_e32 v5, s5
+; GFX9GISEL-NEXT: v_mov_b32_e32 v5, s9
; GFX9GISEL-NEXT: v_max_f64 v[4:5], s[10:11], v[4:5]
-; GFX9GISEL-NEXT: s_bitset0_b64 s[8:9], s12
-; GFX9GISEL-NEXT: s_cmp_lg_u64 s[8:9], 0
-; GFX9GISEL-NEXT: v_readfirstlane_b32 s4, v4
-; GFX9GISEL-NEXT: v_readfirstlane_b32 s5, v5
+; GFX9GISEL-NEXT: s_bitset0_b64 s[6:7], s12
+; GFX9GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; GFX9GISEL-NEXT: v_readfirstlane_b32 s8, v4
+; GFX9GISEL-NEXT: v_readfirstlane_b32 s9, v5
+; GFX9GISEL-NEXT: s_cbranch_scc1 .LBB7_2
+; GFX9GISEL-NEXT: ; %bb.3:
+; GFX9GISEL-NEXT: v_mov_b32_e32 v6, s8
+; GFX9GISEL-NEXT: v_mov_b32_e32 v7, s9
; GFX9GISEL-NEXT: ; implicit-def: $vgpr4
; GFX9GISEL-NEXT: ; implicit-def: $vgpr5
-; GFX9GISEL-NEXT: s_cbranch_scc1 .LBB7_2
-; GFX9GISEL-NEXT: .LBB7_3: ; %Flow
-; GFX9GISEL-NEXT: s_andn2_saveexec_b64 s[6:7], s[6:7]
-; GFX9GISEL-NEXT: s_cbranch_execz .LBB7_6
-; GFX9GISEL-NEXT: ; %bb.4: ; %if
-; GFX9GISEL-NEXT: s_mov_b32 s4, 0
-; GFX9GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
-; GFX9GISEL-NEXT: s_mov_b64 s[8:9], exec
-; GFX9GISEL-NEXT: .LBB7_5: ; =>This Inner Loop Header: Depth=1
-; GFX9GISEL-NEXT: s_ff1_i32_b64 s12, s[8:9]
-; GFX9GISEL-NEXT: v_mov_b32_e32 v2, s4
+; GFX9GISEL-NEXT: .LBB7_4: ; %Flow
+; GFX9GISEL-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9GISEL-NEXT: s_cbranch_execz .LBB7_8
+; GFX9GISEL-NEXT: ; %bb.5: ; %if
+; GFX9GISEL-NEXT: s_mov_b32 s8, 0
+; GFX9GISEL-NEXT: s_mov_b32 s9, 0x7ff80000
+; GFX9GISEL-NEXT: s_mov_b64 s[6:7], exec
+; GFX9GISEL-NEXT: .LBB7_6: ; =>This Inner Loop Header: Depth=1
+; GFX9GISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
+; GFX9GISEL-NEXT: v_mov_b32_e32 v2, s8
; GFX9GISEL-NEXT: v_readlane_b32 s10, v4, s12
; GFX9GISEL-NEXT: v_readlane_b32 s11, v5, s12
-; GFX9GISEL-NEXT: v_mov_b32_e32 v3, s5
+; GFX9GISEL-NEXT: v_mov_b32_e32 v3, s9
; GFX9GISEL-NEXT: v_max_f64 v[2:3], s[10:11], v[2:3]
-; GFX9GISEL-NEXT: s_bitset0_b64 s[8:9], s12
-; GFX9GISEL-NEXT: s_cmp_lg_u64 s[8:9], 0
-; GFX9GISEL-NEXT: v_readfirstlane_b32 s4, v2
-; GFX9GISEL-NEXT: v_readfirstlane_b32 s5, v3
-; GFX9GISEL-NEXT: s_cbranch_scc1 .LBB7_5
-; GFX9GISEL-NEXT: .LBB7_6: ; %endif
-; GFX9GISEL-NEXT: s_or_b64 exec, exec, s[6:7]
-; GFX9GISEL-NEXT: v_mov_b32_e32 v2, s4
-; GFX9GISEL-NEXT: v_mov_b32_e32 v3, s5
-; GFX9GISEL-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
+; GFX9GISEL-NEXT: s_bitset0_b64 s[6:7], s12
+; GFX9GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; GFX9GISEL-NEXT: v_readfirstlane_b32 s8, v2
+; GFX9GISEL-NEXT: v_readfirstlane_b32 s9, v3
+; GFX9GISEL-NEXT: s_cbranch_scc1 .LBB7_6
+; GFX9GISEL-NEXT: ; %bb.7:
+; GFX9GISEL-NEXT: v_mov_b32_e32 v6, s8
+; GFX9GISEL-NEXT: v_mov_b32_e32 v7, s9
+; GFX9GISEL-NEXT: .LBB7_8: ; %endif
+; GFX9GISEL-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9GISEL-NEXT: global_store_dwordx2 v[0:1], v[6:7], off
; GFX9GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX9GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -3078,49 +3104,53 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1064GISEL: ; %bb.0: ; %entry
; GFX1064GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1064GISEL-NEXT: v_and_b32_e32 v6, 0x3ff, v31
-; GFX1064GISEL-NEXT: ; implicit-def: $sgpr4_sgpr5
; GFX1064GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v6
-; GFX1064GISEL-NEXT: s_and_saveexec_b64 s[6:7], vcc
-; GFX1064GISEL-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
-; GFX1064GISEL-NEXT: s_cbranch_execz .LBB7_3
+; GFX1064GISEL-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX1064GISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc
+; GFX1064GISEL-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX1064GISEL-NEXT: s_cbranch_execz .LBB7_4
; GFX1064GISEL-NEXT: ; %bb.1: ; %else
-; GFX1064GISEL-NEXT: s_mov_b32 s4, 0
-; GFX1064GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
-; GFX1064GISEL-NEXT: s_mov_b64 s[8:9], exec
+; GFX1064GISEL-NEXT: s_mov_b32 s8, 0
+; GFX1064GISEL-NEXT: s_mov_b32 s9, 0x7ff80000
+; GFX1064GISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX1064GISEL-NEXT: .LBB7_2: ; =>This Inner Loop Header: Depth=1
-; GFX1064GISEL-NEXT: s_ff1_i32_b64 s12, s[8:9]
+; GFX1064GISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
; GFX1064GISEL-NEXT: v_readlane_b32 s10, v2, s12
; GFX1064GISEL-NEXT: v_readlane_b32 s11, v3, s12
-; GFX1064GISEL-NEXT: s_bitset0_b64 s[8:9], s12
-; GFX1064GISEL-NEXT: s_cmp_lg_u64 s[8:9], 0
-; GFX1064GISEL-NEXT: v_max_f64 v[4:5], s[10:11], s[4:5]
-; GFX1064GISEL-NEXT: v_readfirstlane_b32 s4, v4
-; GFX1064GISEL-NEXT: v_readfirstlane_b32 s5, v5
+; GFX1064GISEL-NEXT: s_bitset0_b64 s[6:7], s12
+; GFX1064GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; GFX1064GISEL-NEXT: v_max_f64 v[4:5], s[10:11], s[8:9]
+; GFX1064GISEL-NEXT: v_readfirstlane_b32 s8, v4
+; GFX1064GISEL-NEXT: v_readfirstlane_b32 s9, v5
+; GFX1064GISEL-NEXT: s_cbranch_scc1 .LBB7_2
+; GFX1064GISEL-NEXT: ; %bb.3:
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v6, s8
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v7, s9
; GFX1064GISEL-NEXT: ; implicit-def: $vgpr4
; GFX1064GISEL-NEXT: ; implicit-def: $vgpr5
-; GFX1064GISEL-NEXT: s_cbranch_scc1 .LBB7_2
-; GFX1064GISEL-NEXT: .LBB7_3: ; %Flow
-; GFX1064GISEL-NEXT: s_andn2_saveexec_b64 s[6:7], s[6:7]
-; GFX1064GISEL-NEXT: s_cbranch_execz .LBB7_6
-; GFX1064GISEL-NEXT: ; %bb.4: ; %if
-; GFX1064GISEL-NEXT: s_mov_b32 s4, 0
-; GFX1064GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
-; GFX1064GISEL-NEXT: s_mov_b64 s[8:9], exec
-; GFX1064GISEL-NEXT: .LBB7_5: ; =>This Inner Loop Header: Depth=1
-; GFX1064GISEL-NEXT: s_ff1_i32_b64 s12, s[8:9]
+; GFX1064GISEL-NEXT: .LBB7_4: ; %Flow
+; GFX1064GISEL-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX1064GISEL-NEXT: s_cbranch_execz .LBB7_8
+; GFX1064GISEL-NEXT: ; %bb.5: ; %if
+; GFX1064GISEL-NEXT: s_mov_b32 s8, 0
+; GFX1064GISEL-NEXT: s_mov_b32 s9, 0x7ff80000
+; GFX1064GISEL-NEXT: s_mov_b64 s[6:7], exec
+; GFX1064GISEL-NEXT: .LBB7_6: ; =>This Inner Loop Header: Depth=1
+; GFX1064GISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
; GFX1064GISEL-NEXT: v_readlane_b32 s10, v4, s12
; GFX1064GISEL-NEXT: v_readlane_b32 s11, v5, s12
-; GFX1064GISEL-NEXT: s_bitset0_b64 s[8:9], s12
-; GFX1064GISEL-NEXT: s_cmp_lg_u64 s[8:9], 0
-; GFX1064GISEL-NEXT: v_max_f64 v[2:3], s[10:11], s[4:5]
-; GFX1064GISEL-NEXT: v_readfirstlane_b32 s4, v2
-; GFX1064GISEL-NEXT: v_readfirstlane_b32 s5, v3
-; GFX1064GISEL-NEXT: s_cbranch_scc1 .LBB7_5
-; GFX1064GISEL-NEXT: .LBB7_6: ; %endif
-; GFX1064GISEL-NEXT: s_or_b64 exec, exec, s[6:7]
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v2, s4
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v3, s5
-; GFX1064GISEL-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
+; GFX1064GISEL-NEXT: s_bitset0_b64 s[6:7], s12
+; GFX1064GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; GFX1064GISEL-NEXT: v_max_f64 v[2:3], s[10:11], s[8:9]
+; GFX1064GISEL-NEXT: v_readfirstlane_b32 s8, v2
+; GFX1064GISEL-NEXT: v_readfirstlane_b32 s9, v3
+; GFX1064GISEL-NEXT: s_cbranch_scc1 .LBB7_6
+; GFX1064GISEL-NEXT: ; %bb.7:
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v6, s8
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v7, s9
+; GFX1064GISEL-NEXT: .LBB7_8: ; %endif
+; GFX1064GISEL-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX1064GISEL-NEXT: global_store_dwordx2 v[0:1], v[6:7], off
; GFX1064GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1032DAGISEL-LABEL: divergent_cfg_double:
@@ -3180,11 +3210,11 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1032GISEL: ; %bb.0: ; %entry
; GFX1032GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1032GISEL-NEXT: v_and_b32_e32 v6, 0x3ff, v31
-; GFX1032GISEL-NEXT: ; implicit-def: $sgpr4_sgpr5
; GFX1032GISEL-NEXT: v_cmp_le_u32_e32 vcc_lo, 16, v6
-; GFX1032GISEL-NEXT: s_and_saveexec_b32 s6, vcc_lo
-; GFX1032GISEL-NEXT: s_xor_b32 s6, exec_lo, s6
-; GFX1032GISEL-NEXT: s_cbranch_execz .LBB7_3
+; GFX1032GISEL-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX1032GISEL-NEXT: s_and_saveexec_b32 s4, vcc_lo
+; GFX1032GISEL-NEXT: s_xor_b32 s6, exec_lo, s4
+; GFX1032GISEL-NEXT: s_cbranch_execz .LBB7_4
; GFX1032GISEL-NEXT: ; %bb.1: ; %else
; GFX1032GISEL-NEXT: s_mov_b32 s4, 0
; GFX1032GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
@@ -3198,17 +3228,20 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1032GISEL-NEXT: v_max_f64 v[4:5], s[8:9], s[4:5]
; GFX1032GISEL-NEXT: v_readfirstlane_b32 s4, v4
; GFX1032GISEL-NEXT: v_readfirstlane_b32 s5, v5
+; GFX1032GISEL-NEXT: s_cbranch_scc1 .LBB7_2
+; GFX1032GISEL-NEXT: ; %bb.3:
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v7, s5
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v6, s4
; GFX1032GISEL-NEXT: ; implicit-def: $vgpr4
; GFX1032GISEL-NEXT: ; implicit-def: $vgpr5
-; GFX1032GISEL-NEXT: s_cbranch_scc1 .LBB7_2
-; GFX1032GISEL-NEXT: .LBB7_3: ; %Flow
+; GFX1032GISEL-NEXT: .LBB7_4: ; %Flow
; GFX1032GISEL-NEXT: s_andn2_saveexec_b32 s6, s6
-; GFX1032GISEL-NEXT: s_cbranch_execz .LBB7_6
-; GFX1032GISEL-NEXT: ; %bb.4: ; %if
+; GFX1032GISEL-NEXT: s_cbranch_execz .LBB7_8
+; GFX1032GISEL-NEXT: ; %bb.5: ; %if
; GFX1032GISEL-NEXT: s_mov_b32 s4, 0
; GFX1032GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
; GFX1032GISEL-NEXT: s_mov_b32 s7, exec_lo
-; GFX1032GISEL-NEXT: .LBB7_5: ; =>This Inner Loop Header: Depth=1
+; GFX1032GISEL-NEXT: .LBB7_6: ; =>This Inner Loop Header: Depth=1
; GFX1032GISEL-NEXT: s_ff1_i32_b32 s10, s7
; GFX1032GISEL-NEXT: v_readlane_b32 s8, v4, s10
; GFX1032GISEL-NEXT: v_readlane_b32 s9, v5, s10
@@ -3217,12 +3250,13 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1032GISEL-NEXT: v_max_f64 v[2:3], s[8:9], s[4:5]
; GFX1032GISEL-NEXT: v_readfirstlane_b32 s4, v2
; GFX1032GISEL-NEXT: v_readfirstlane_b32 s5, v3
-; GFX1032GISEL-NEXT: s_cbranch_scc1 .LBB7_5
-; GFX1032GISEL-NEXT: .LBB7_6: ; %endif
+; GFX1032GISEL-NEXT: s_cbranch_scc1 .LBB7_6
+; GFX1032GISEL-NEXT: ; %bb.7:
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v7, s5
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v6, s4
+; GFX1032GISEL-NEXT: .LBB7_8: ; %endif
; GFX1032GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s6
-; GFX1032GISEL-NEXT: v_mov_b32_e32 v2, s4
-; GFX1032GISEL-NEXT: v_mov_b32_e32 v3, s5
-; GFX1032GISEL-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
+; GFX1032GISEL-NEXT: global_store_dwordx2 v[0:1], v[6:7], off
; GFX1032GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1164DAGISEL-LABEL: divergent_cfg_double:
@@ -3289,56 +3323,60 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1164GISEL: ; %bb.0: ; %entry
; GFX1164GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1164GISEL-NEXT: v_and_b32_e32 v6, 0x3ff, v31
-; GFX1164GISEL-NEXT: s_mov_b64 s[2:3], exec
-; GFX1164GISEL-NEXT: ; implicit-def: $sgpr0_sgpr1
-; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1164GISEL-NEXT: v_cmpx_le_u32_e32 16, v6
-; GFX1164GISEL-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
-; GFX1164GISEL-NEXT: s_cbranch_execz .LBB7_3
+; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1164GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v6
+; GFX1164GISEL-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX1164GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc
+; GFX1164GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
+; GFX1164GISEL-NEXT: s_cbranch_execz .LBB7_4
; GFX1164GISEL-NEXT: ; %bb.1: ; %else
-; GFX1164GISEL-NEXT: s_mov_b32 s0, 0
-; GFX1164GISEL-NEXT: s_mov_b32 s1, 0x7ff80000
-; GFX1164GISEL-NEXT: s_mov_b64 s[4:5], exec
+; GFX1164GISEL-NEXT: s_mov_b32 s4, 0
+; GFX1164GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
+; GFX1164GISEL-NEXT: s_mov_b64 s[2:3], exec
; GFX1164GISEL-NEXT: .LBB7_2: ; =>This Inner Loop Header: Depth=1
; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1164GISEL-NEXT: s_ctz_i32_b64 s8, s[4:5]
+; GFX1164GISEL-NEXT: s_ctz_i32_b64 s8, s[2:3]
; GFX1164GISEL-NEXT: v_readlane_b32 s6, v2, s8
; GFX1164GISEL-NEXT: v_readlane_b32 s7, v3, s8
-; GFX1164GISEL-NEXT: s_bitset0_b64 s[4:5], s8
+; GFX1164GISEL-NEXT: s_bitset0_b64 s[2:3], s8
; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1164GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
-; GFX1164GISEL-NEXT: v_max_f64 v[4:5], s[6:7], s[0:1]
-; GFX1164GISEL-NEXT: v_readfirstlane_b32 s0, v4
+; GFX1164GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; GFX1164GISEL-NEXT: v_max_f64 v[4:5], s[6:7], s[4:5]
+; GFX1164GISEL-NEXT: v_readfirstlane_b32 s4, v4
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1164GISEL-NEXT: v_readfirstlane_b32 s1, v5
+; GFX1164GISEL-NEXT: v_readfirstlane_b32 s5, v5
+; GFX1164GISEL-NEXT: s_cbranch_scc1 .LBB7_2
+; GFX1164GISEL-NEXT: ; %bb.3:
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v7, s5
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v6, s4
; GFX1164GISEL-NEXT: ; implicit-def: $vgpr4
; GFX1164GISEL-NEXT: ; implicit-def: $vgpr5
-; GFX1164GISEL-NEXT: s_cbranch_scc1 .LBB7_2
-; GFX1164GISEL-NEXT: .LBB7_3: ; %Flow
-; GFX1164GISEL-NEXT: s_and_not1_saveexec_b64 s[2:3], s[2:3]
-; GFX1164GISEL-NEXT: s_cbranch_execz .LBB7_6
-; GFX1164GISEL-NEXT: ; %bb.4: ; %if
-; GFX1164GISEL-NEXT: s_mov_b32 s0, 0
-; GFX1164GISEL-NEXT: s_mov_b32 s1, 0x7ff80000
-; GFX1164GISEL-NEXT: s_mov_b64 s[4:5], exec
-; GFX1164GISEL-NEXT: .LBB7_5: ; =>This Inner Loop Header: Depth=1
+; GFX1164GISEL-NEXT: .LBB7_4: ; %Flow
+; GFX1164GISEL-NEXT: s_and_not1_saveexec_b64 s[0:1], s[0:1]
+; GFX1164GISEL-NEXT: s_cbranch_execz .LBB7_8
+; GFX1164GISEL-NEXT: ; %bb.5: ; %if
+; GFX1164GISEL-NEXT: s_mov_b32 s4, 0
+; GFX1164GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
+; GFX1164GISEL-NEXT: s_mov_b64 s[2:3], exec
+; GFX1164GISEL-NEXT: .LBB7_6: ; =>This Inner Loop Header: Depth=1
; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1164GISEL-NEXT: s_ctz_i32_b64 s8, s[4:5]
+; GFX1164GISEL-NEXT: s_ctz_i32_b64 s8, s[2:3]
; GFX1164GISEL-NEXT: v_readlane_b32 s6, v4, s8
; GFX1164GISEL-NEXT: v_readlane_b32 s7, v5, s8
-; GFX1164GISEL-NEXT: s_bitset0_b64 s[4:5], s8
+; GFX1164GISEL-NEXT: s_bitset0_b64 s[2:3], s8
; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1164GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
-; GFX1164GISEL-NEXT: v_max_f64 v[2:3], s[6:7], s[0:1]
-; GFX1164GISEL-NEXT: v_readfirstlane_b32 s0, v2
+; GFX1164GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; GFX1164GISEL-NEXT: v_max_f64 v[2:3], s[6:7], s[4:5]
+; GFX1164GISEL-NEXT: v_readfirstlane_b32 s4, v2
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1164GISEL-NEXT: v_readfirstlane_b32 s1, v3
-; GFX1164GISEL-NEXT: s_cbranch_scc1 .LBB7_5
-; GFX1164GISEL-NEXT: .LBB7_6: ; %endif
-; GFX1164GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v3, s1
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v2, s0
-; GFX1164GISEL-NEXT: global_store_b64 v[0:1], v[2:3], off
+; GFX1164GISEL-NEXT: v_readfirstlane_b32 s5, v3
+; GFX1164GISEL-NEXT: s_cbranch_scc1 .LBB7_6
+; GFX1164GISEL-NEXT: ; %bb.7:
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v7, s5
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v6, s4
+; GFX1164GISEL-NEXT: .LBB7_8: ; %endif
+; GFX1164GISEL-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX1164GISEL-NEXT: global_store_b64 v[0:1], v[6:7], off
; GFX1164GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1132DAGISEL-LABEL: divergent_cfg_double:
@@ -3403,12 +3441,12 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1132GISEL: ; %bb.0: ; %entry
; GFX1132GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1132GISEL-NEXT: v_and_b32_e32 v6, 0x3ff, v31
-; GFX1132GISEL-NEXT: s_mov_b32 s2, exec_lo
-; GFX1132GISEL-NEXT: ; implicit-def: $sgpr0_sgpr1
-; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1132GISEL-NEXT: v_cmpx_le_u32_e32 16, v6
-; GFX1132GISEL-NEXT: s_xor_b32 s2, exec_lo, s2
-; GFX1132GISEL-NEXT: s_cbranch_execz .LBB7_3
+; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1132GISEL-NEXT: v_cmp_le_u32_e32 vcc_lo, 16, v6
+; GFX1132GISEL-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX1132GISEL-NEXT: s_and_saveexec_b32 s0, vcc_lo
+; GFX1132GISEL-NEXT: s_xor_b32 s2, exec_lo, s0
+; GFX1132GISEL-NEXT: s_cbranch_execz .LBB7_4
; GFX1132GISEL-NEXT: ; %bb.1: ; %else
; GFX1132GISEL-NEXT: s_mov_b32 s0, 0
; GFX1132GISEL-NEXT: s_mov_b32 s1, 0x7ff80000
@@ -3425,17 +3463,19 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1132GISEL-NEXT: v_readfirstlane_b32 s0, v4
; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1132GISEL-NEXT: v_readfirstlane_b32 s1, v5
+; GFX1132GISEL-NEXT: s_cbranch_scc1 .LBB7_2
+; GFX1132GISEL-NEXT: ; %bb.3:
+; GFX1132GISEL-NEXT: v_dual_mov_b32 v7, s1 :: v_dual_mov_b32 v6, s0
; GFX1132GISEL-NEXT: ; implicit-def: $vgpr4
; GFX1132GISEL-NEXT: ; implicit-def: $vgpr5
-; GFX1132GISEL-NEXT: s_cbranch_scc1 .LBB7_2
-; GFX1132GISEL-NEXT: .LBB7_3: ; %Flow
+; GFX1132GISEL-NEXT: .LBB7_4: ; %Flow
; GFX1132GISEL-NEXT: s_and_not1_saveexec_b32 s2, s2
-; GFX1132GISEL-NEXT: s_cbranch_execz .LBB7_6
-; GFX1132GISEL-NEXT: ; %bb.4: ; %if
+; GFX1132GISEL-NEXT: s_cbranch_execz .LBB7_8
+; GFX1132GISEL-NEXT: ; %bb.5: ; %if
; GFX1132GISEL-NEXT: s_mov_b32 s0, 0
; GFX1132GISEL-NEXT: s_mov_b32 s1, 0x7ff80000
; GFX1132GISEL-NEXT: s_mov_b32 s3, exec_lo
-; GFX1132GISEL-NEXT: .LBB7_5: ; =>This Inner Loop Header: Depth=1
+; GFX1132GISEL-NEXT: .LBB7_6: ; =>This Inner Loop Header: Depth=1
; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1132GISEL-NEXT: s_ctz_i32_b32 s6, s3
; GFX1132GISEL-NEXT: v_readlane_b32 s4, v4, s6
@@ -3447,11 +3487,12 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1132GISEL-NEXT: v_readfirstlane_b32 s0, v2
; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1132GISEL-NEXT: v_readfirstlane_b32 s1, v3
-; GFX1132GISEL-NEXT: s_cbranch_scc1 .LBB7_5
-; GFX1132GISEL-NEXT: .LBB7_6: ; %endif
+; GFX1132GISEL-NEXT: s_cbranch_scc1 .LBB7_6
+; GFX1132GISEL-NEXT: ; %bb.7:
+; GFX1132GISEL-NEXT: v_dual_mov_b32 v7, s1 :: v_dual_mov_b32 v6, s0
+; GFX1132GISEL-NEXT: .LBB7_8: ; %endif
; GFX1132GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s2
-; GFX1132GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
-; GFX1132GISEL-NEXT: global_store_b64 v[0:1], v[2:3], off
+; GFX1132GISEL-NEXT: global_store_b64 v[0:1], v[6:7], off
; GFX1132GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12DAGISEL-LABEL: divergent_cfg_double:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
index 86e9dad936ed8..a02736ec43174 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
@@ -1,16 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=0 < %s | FileCheck -check-prefixes=GFX8DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=1 < %s | FileCheck -check-prefixes=GFX8GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX8GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=0 < %s | FileCheck -check-prefixes=GFX9DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=1 < %s | FileCheck -check-prefixes=GFX9GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX9GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1064DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1064GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1064GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1032DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1032GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1032GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1164DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1164GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1164GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1132DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1132GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1132GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -global-isel=0 < %s | FileCheck -check-prefixes=GFX12DAGISEL %s
@@ -1789,30 +1789,32 @@ define void @divergent_cfg_float(ptr addrspace(1) %out, float %in, float %in2) {
; GFX8GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8GISEL-NEXT: v_and_b32_e32 v4, 0x3ff, v31
; GFX8GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v4
-; GFX8GISEL-NEXT: ; implicit-def: $sgpr8
+; GFX8GISEL-NEXT: ; implicit-def: $vgpr4
; GFX8GISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX8GISEL-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
-; GFX8GISEL-NEXT: s_cbranch_execz .LBB4_3
+; GFX8GISEL-NEXT: s_cbranch_execz .LBB4_4
; GFX8GISEL-NEXT: ; %bb.1: ; %else
; GFX8GISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX8GISEL-NEXT: s_mov_b32 s8, 0x7fc00000
-; GFX8GISEL-NEXT: ; implicit-def: $vgpr3
; GFX8GISEL-NEXT: .LBB4_2: ; =>This Inner Loop Header: Depth=1
; GFX8GISEL-NEXT: s_ff1_i32_b64 s9, s[6:7]
; GFX8GISEL-NEXT: v_readlane_b32 s10, v2, s9
-; GFX8GISEL-NEXT: v_mov_b32_e32 v4, s10
+; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s10
; GFX8GISEL-NEXT: s_bitset0_b64 s[6:7], s9
-; GFX8GISEL-NEXT: v_min_f32_e32 v4, s8, v4
+; GFX8GISEL-NEXT: v_min_f32_e32 v3, s8, v3
; GFX8GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
-; GFX8GISEL-NEXT: v_readfirstlane_b32 s8, v4
+; GFX8GISEL-NEXT: v_readfirstlane_b32 s8, v3
; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB4_2
-; GFX8GISEL-NEXT: .LBB4_3: ; %Flow
+; GFX8GISEL-NEXT: ; %bb.3:
+; GFX8GISEL-NEXT: v_mov_b32_e32 v4, s8
+; GFX8GISEL-NEXT: ; implicit-def: $vgpr3
+; GFX8GISEL-NEXT: .LBB4_4: ; %Flow
; GFX8GISEL-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX8GISEL-NEXT: s_cbranch_execz .LBB4_6
-; GFX8GISEL-NEXT: ; %bb.4: ; %if
+; GFX8GISEL-NEXT: s_cbranch_execz .LBB4_8
+; GFX8GISEL-NEXT: ; %bb.5: ; %if
; GFX8GISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX8GISEL-NEXT: s_mov_b32 s8, 0x7fc00000
-; GFX8GISEL-NEXT: .LBB4_5: ; =>This Inner Loop Header: Depth=1
+; GFX8GISEL-NEXT: .LBB4_6: ; =>This Inner Loop Header: Depth=1
; GFX8GISEL-NEXT: s_ff1_i32_b64 s9, s[6:7]
; GFX8GISEL-NEXT: v_readlane_b32 s10, v3, s9
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s10
@@ -1820,11 +1822,12 @@ define void @divergent_cfg_float(ptr addrspace(1) %out, float %in, float %in2) {
; GFX8GISEL-NEXT: v_min_f32_e32 v2, s8, v2
; GFX8GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
; GFX8GISEL-NEXT: v_readfirstlane_b32 s8, v2
-; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB4_5
-; GFX8GISEL-NEXT: .LBB4_6: ; %endif
+; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB4_6
+; GFX8GISEL-NEXT: ; %bb.7:
+; GFX8GISEL-NEXT: v_mov_b32_e32 v4, s8
+; GFX8GISEL-NEXT: .LBB4_8: ; %endif
; GFX8GISEL-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s8
-; GFX8GISEL-NEXT: flat_store_dword v[0:1], v2
+; GFX8GISEL-NEXT: flat_store_dword v[0:1], v4
; GFX8GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX8GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -1880,30 +1883,32 @@ define void @divergent_cfg_float(ptr addrspace(1) %out, float %in, float %in2) {
; GFX9GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9GISEL-NEXT: v_and_b32_e32 v4, 0x3ff, v31
; GFX9GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v4
-; GFX9GISEL-NEXT: ; implicit-def: $sgpr8
+; GFX9GISEL-NEXT: ; implicit-def: $vgpr4
; GFX9GISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX9GISEL-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
-; GFX9GISEL-NEXT: s_cbranch_execz .LBB4_3
+; GFX9GISEL-NEXT: s_cbranch_execz .LBB4_4
; GFX9GISEL-NEXT: ; %bb.1: ; %else
; GFX9GISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX9GISEL-NEXT: s_mov_b32 s8, 0x7fc00000
-; GFX9GISEL-NEXT: ; implicit-def: $vgpr3
; GFX9GISEL-NEXT: .LBB4_2: ; =>This Inner Loop Header: Depth=1
; GFX9GISEL-NEXT: s_ff1_i32_b64 s9, s[6:7]
; GFX9GISEL-NEXT: v_readlane_b32 s10, v2, s9
-; GFX9GISEL-NEXT: v_mov_b32_e32 v4, s10
+; GFX9GISEL-NEXT: v_mov_b32_e32 v3, s10
; GFX9GISEL-NEXT: s_bitset0_b64 s[6:7], s9
-; GFX9GISEL-NEXT: v_min_f32_e32 v4, s8, v4
+; GFX9GISEL-NEXT: v_min_f32_e32 v3, s8, v3
; GFX9GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
-; GFX9GISEL-NEXT: v_readfirstlane_b32 s8, v4
+; GFX9GISEL-NEXT: v_readfirstlane_b32 s8, v3
; GFX9GISEL-NEXT: s_cbranch_scc1 .LBB4_2
-; GFX9GISEL-NEXT: .LBB4_3: ; %Flow
+; GFX9GISEL-NEXT: ; %bb.3:
+; GFX9GISEL-NEXT: v_mov_b32_e32 v4, s8
+; GFX9GISEL-NEXT: ; implicit-def: $vgpr3
+; GFX9GISEL-NEXT: .LBB4_4: ; %Flow
; GFX9GISEL-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX9GISEL-NEXT: s_cbranch_execz .LBB4_6
-; GFX9GISEL-NEXT: ; %bb.4: ; %if
+; GFX9GISEL-NEXT: s_cbranch_execz .LBB4_8
+; GFX9GISEL-NEXT: ; %bb.5: ; %if
; GFX9GISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX9GISEL-NEXT: s_mov_b32 s8, 0x7fc00000
-; GFX9GISEL-NEXT: .LBB4_5: ; =>This Inner Loop Header: Depth=1
+; GFX9GISEL-NEXT: .LBB4_6: ; =>This Inner Loop Header: Depth=1
; GFX9GISEL-NEXT: s_ff1_i32_b64 s9, s[6:7]
; GFX9GISEL-NEXT: v_readlane_b32 s10, v3, s9
; GFX9GISEL-NEXT: v_mov_b32_e32 v2, s10
@@ -1911,11 +1916,12 @@ define void @divergent_cfg_float(ptr addrspace(1) %out, float %in, float %in2) {
; GFX9GISEL-NEXT: v_min_f32_e32 v2, s8, v2
; GFX9GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
; GFX9GISEL-NEXT: v_readfirstlane_b32 s8, v2
-; GFX9GISEL-NEXT: s_cbranch_scc1 .LBB4_5
-; GFX9GISEL-NEXT: .LBB4_6: ; %endif
+; GFX9GISEL-NEXT: s_cbranch_scc1 .LBB4_6
+; GFX9GISEL-NEXT: ; %bb.7:
+; GFX9GISEL-NEXT: v_mov_b32_e32 v4, s8
+; GFX9GISEL-NEXT: .LBB4_8: ; %endif
; GFX9GISEL-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX9GISEL-NEXT: v_mov_b32_e32 v2, s8
-; GFX9GISEL-NEXT: global_store_dword v[0:1], v2, off
+; GFX9GISEL-NEXT: global_store_dword v[0:1], v4, off
; GFX9GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX9GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -1967,11 +1973,11 @@ define void @divergent_cfg_float(ptr addrspace(1) %out, float %in, float %in2) {
; GFX1064GISEL: ; %bb.0: ; %entry
; GFX1064GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1064GISEL-NEXT: v_and_b32_e32 v4, 0x3ff, v31
-; GFX1064GISEL-NEXT: ; implicit-def: $sgpr8
; GFX1064GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v4
+; GFX1064GISEL-NEXT: ; implicit-def: $vgpr4
; GFX1064GISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX1064GISEL-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
-; GFX1064GISEL-NEXT: s_cbranch_execz .LBB4_3
+; GFX1064GISEL-NEXT: s_cbranch_execz .LBB4_4
; GFX1064GISEL-NEXT: ; %bb.1: ; %else
; GFX1064GISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX1064GISEL-NEXT: s_mov_b32 s8, 0x7fc00000
@@ -1982,26 +1988,29 @@ define void @divergent_cfg_float(ptr addrspace(1) %out, float %in, float %in2) {
; GFX1064GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
; GFX1064GISEL-NEXT: v_min_f32_e64 v3, s8, s10
; GFX1064GISEL-NEXT: v_readfirstlane_b32 s8, v3
-; GFX1064GISEL-NEXT: ; implicit-def: $vgpr3
; GFX1064GISEL-NEXT: s_cbranch_scc1 .LBB4_2
-; GFX1064GISEL-NEXT: .LBB4_3: ; %Flow
+; GFX1064GISEL-NEXT: ; %bb.3:
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v4, s8
+; GFX1064GISEL-NEXT: ; implicit-def: $vgpr3
+; GFX1064GISEL-NEXT: .LBB4_4: ; %Flow
; GFX1064GISEL-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
-; GFX1064GISEL-NEXT: s_cbranch_execz .LBB4_6
-; GFX1064GISEL-NEXT: ; %bb.4: ; %if
+; GFX1064GISEL-NEXT: s_cbranch_execz .LBB4_8
+; GFX1064GISEL-NEXT: ; %bb.5: ; %if
; GFX1064GISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX1064GISEL-NEXT: s_mov_b32 s8, 0x7fc00000
-; GFX1064GISEL-NEXT: .LBB4_5: ; =>This Inner Loop Header: Depth=1
+; GFX1064GISEL-NEXT: .LBB4_6: ; =>This Inner Loop Header: Depth=1
; GFX1064GISEL-NEXT: s_ff1_i32_b64 s9, s[6:7]
; GFX1064GISEL-NEXT: v_readlane_b32 s10, v3, s9
; GFX1064GISEL-NEXT: s_bitset0_b64 s[6:7], s9
; GFX1064GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
; GFX1064GISEL-NEXT: v_min_f32_e64 v2, s8, s10
; GFX1064GISEL-NEXT: v_readfirstlane_b32 s8, v2
-; GFX1064GISEL-NEXT: s_cbranch_scc1 .LBB4_5
-; GFX1064GISEL-NEXT: .LBB4_6: ; %endif
+; GFX1064GISEL-NEXT: s_cbranch_scc1 .LBB4_6
+; GFX1064GISEL-NEXT: ; %bb.7:
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v4, s8
+; GFX1064GISEL-NEXT: .LBB4_8: ; %endif
; GFX1064GISEL-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v2, s8
-; GFX1064GISEL-NEXT: global_store_dword v[0:1], v2, off
+; GFX1064GISEL-NEXT: global_store_dword v[0:1], v4, off
; GFX1064GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1032DAGISEL-LABEL: divergent_cfg_float:
@@ -2052,41 +2061,44 @@ define void @divergent_cfg_float(ptr addrspace(1) %out, float %in, float %in2) {
; GFX1032GISEL: ; %bb.0: ; %entry
; GFX1032GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1032GISEL-NEXT: v_and_b32_e32 v4, 0x3ff, v31
-; GFX1032GISEL-NEXT: ; implicit-def: $sgpr4
; GFX1032GISEL-NEXT: v_cmp_le_u32_e32 vcc_lo, 16, v4
-; GFX1032GISEL-NEXT: s_and_saveexec_b32 s5, vcc_lo
-; GFX1032GISEL-NEXT: s_xor_b32 s5, exec_lo, s5
-; GFX1032GISEL-NEXT: s_cbranch_execz .LBB4_3
+; GFX1032GISEL-NEXT: ; implicit-def: $vgpr4
+; GFX1032GISEL-NEXT: s_and_saveexec_b32 s4, vcc_lo
+; GFX1032GISEL-NEXT: s_xor_b32 s4, exec_lo, s4
+; GFX1032GISEL-NEXT: s_cbranch_execz .LBB4_4
; GFX1032GISEL-NEXT: ; %bb.1: ; %else
-; GFX1032GISEL-NEXT: s_mov_b32 s6, exec_lo
-; GFX1032GISEL-NEXT: s_mov_b32 s4, 0x7fc00000
+; GFX1032GISEL-NEXT: s_mov_b32 s5, exec_lo
+; GFX1032GISEL-NEXT: s_mov_b32 s6, 0x7fc00000
; GFX1032GISEL-NEXT: .LBB4_2: ; =>This Inner Loop Header: Depth=1
-; GFX1032GISEL-NEXT: s_ff1_i32_b32 s7, s6
+; GFX1032GISEL-NEXT: s_ff1_i32_b32 s7, s5
; GFX1032GISEL-NEXT: v_readlane_b32 s8, v2, s7
-; GFX1032GISEL-NEXT: s_bitset0_b32 s6, s7
-; GFX1032GISEL-NEXT: s_cmp_lg_u32 s6, 0
-; GFX1032GISEL-NEXT: v_min_f32_e64 v3, s4, s8
-; GFX1032GISEL-NEXT: v_readfirstlane_b32 s4, v3
-; GFX1032GISEL-NEXT: ; implicit-def: $vgpr3
+; GFX1032GISEL-NEXT: s_bitset0_b32 s5, s7
+; GFX1032GISEL-NEXT: s_cmp_lg_u32 s5, 0
+; GFX1032GISEL-NEXT: v_min_f32_e64 v3, s6, s8
+; GFX1032GISEL-NEXT: v_readfirstlane_b32 s6, v3
; GFX1032GISEL-NEXT: s_cbranch_scc1 .LBB4_2
-; GFX1032GISEL-NEXT: .LBB4_3: ; %Flow
-; GFX1032GISEL-NEXT: s_andn2_saveexec_b32 s5, s5
-; GFX1032GISEL-NEXT: s_cbranch_execz .LBB4_6
-; GFX1032GISEL-NEXT: ; %bb.4: ; %if
-; GFX1032GISEL-NEXT: s_mov_b32 s6, exec_lo
-; GFX1032GISEL-NEXT: s_mov_b32 s4, 0x7fc00000
-; GFX1032GISEL-NEXT: .LBB4_5: ; =>This Inner Loop Header: Depth=1
-; GFX1032GISEL-NEXT: s_ff1_i32_b32 s7, s6
+; GFX1032GISEL-NEXT: ; %bb.3:
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v4, s6
+; GFX1032GISEL-NEXT: ; implicit-def: $vgpr3
+; GFX1032GISEL-NEXT: .LBB4_4: ; %Flow
+; GFX1032GISEL-NEXT: s_andn2_saveexec_b32 s4, s4
+; GFX1032GISEL-NEXT: s_cbranch_execz .LBB4_8
+; GFX1032GISEL-NEXT: ; %bb.5: ; %if
+; GFX1032GISEL-NEXT: s_mov_b32 s5, exec_lo
+; GFX1032GISEL-NEXT: s_mov_b32 s6, 0x7fc00000
+; GFX1032GISEL-NEXT: .LBB4_6: ; =>This Inner Loop Header: Depth=1
+; GFX1032GISEL-NEXT: s_ff1_i32_b32 s7, s5
; GFX1032GISEL-NEXT: v_readlane_b32 s8, v3, s7
-; GFX1032GISEL-NEXT: s_bitset0_b32 s6, s7
-; GFX1032GISEL-NEXT: s_cmp_lg_u32 s6, 0
-; GFX1032GISEL-NEXT: v_min_f32_e64 v2, s4, s8
-; GFX1032GISEL-NEXT: v_readfirstlane_b32 s4, v2
-; GFX1032GISEL-NEXT: s_cbranch_scc1 .LBB4_5
-; GFX1032GISEL-NEXT: .LBB4_6: ; %endif
-; GFX1032GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s5
-; GFX1032GISEL-NEXT: v_mov_b32_e32 v2, s4
-; GFX1032GISEL-NEXT: global_store_dword v[0:1], v2, off
+; GFX1032GISEL-NEXT: s_bitset0_b32 s5, s7
+; GFX1032GISEL-NEXT: s_cmp_lg_u32 s5, 0
+; GFX1032GISEL-NEXT: v_min_f32_e64 v2, s6, s8
+; GFX1032GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; GFX1032GISEL-NEXT: s_cbranch_scc1 .LBB4_6
+; GFX1032GISEL-NEXT: ; %bb.7:
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v4, s6
+; GFX1032GISEL-NEXT: .LBB4_8: ; %endif
+; GFX1032GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s4
+; GFX1032GISEL-NEXT: global_store_dword v[0:1], v4, off
; GFX1032GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1164DAGISEL-LABEL: divergent_cfg_float:
@@ -2142,12 +2154,12 @@ define void @divergent_cfg_float(ptr addrspace(1) %out, float %in, float %in2) {
; GFX1164GISEL: ; %bb.0: ; %entry
; GFX1164GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1164GISEL-NEXT: v_and_b32_e32 v4, 0x3ff, v31
-; GFX1164GISEL-NEXT: s_mov_b64 s[0:1], exec
-; GFX1164GISEL-NEXT: ; implicit-def: $sgpr4
-; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1164GISEL-NEXT: v_cmpx_le_u32_e32 16, v4
+; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1164GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v4
+; GFX1164GISEL-NEXT: ; implicit-def: $vgpr4
+; GFX1164GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1164GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
-; GFX1164GISEL-NEXT: s_cbranch_execz .LBB4_3
+; GFX1164GISEL-NEXT: s_cbranch_execz .LBB4_4
; GFX1164GISEL-NEXT: ; %bb.1: ; %else
; GFX1164GISEL-NEXT: s_mov_b64 s[2:3], exec
; GFX1164GISEL-NEXT: s_mov_b32 s4, 0x7fc00000
@@ -2160,15 +2172,17 @@ define void @divergent_cfg_float(ptr addrspace(1) %out, float %in, float %in2) {
; GFX1164GISEL-NEXT: v_min_f32_e64 v3, s4, s6
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164GISEL-NEXT: v_readfirstlane_b32 s4, v3
-; GFX1164GISEL-NEXT: ; implicit-def: $vgpr3
; GFX1164GISEL-NEXT: s_cbranch_scc1 .LBB4_2
-; GFX1164GISEL-NEXT: .LBB4_3: ; %Flow
+; GFX1164GISEL-NEXT: ; %bb.3:
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v4, s4
+; GFX1164GISEL-NEXT: ; implicit-def: $vgpr3
+; GFX1164GISEL-NEXT: .LBB4_4: ; %Flow
; GFX1164GISEL-NEXT: s_and_not1_saveexec_b64 s[0:1], s[0:1]
-; GFX1164GISEL-NEXT: s_cbranch_execz .LBB4_6
-; GFX1164GISEL-NEXT: ; %bb.4: ; %if
+; GFX1164GISEL-NEXT: s_cbranch_execz .LBB4_8
+; GFX1164GISEL-NEXT: ; %bb.5: ; %if
; GFX1164GISEL-NEXT: s_mov_b64 s[2:3], exec
; GFX1164GISEL-NEXT: s_mov_b32 s4, 0x7fc00000
-; GFX1164GISEL-NEXT: .LBB4_5: ; =>This Inner Loop Header: Depth=1
+; GFX1164GISEL-NEXT: .LBB4_6: ; =>This Inner Loop Header: Depth=1
; GFX1164GISEL-NEXT: s_ctz_i32_b64 s5, s[2:3]
; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1164GISEL-NEXT: v_readlane_b32 s6, v3, s5
@@ -2177,11 +2191,12 @@ define void @divergent_cfg_float(ptr addrspace(1) %out, float %in, float %in2) {
; GFX1164GISEL-NEXT: v_min_f32_e64 v2, s4, s6
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164GISEL-NEXT: v_readfirstlane_b32 s4, v2
-; GFX1164GISEL-NEXT: s_cbranch_scc1 .LBB4_5
-; GFX1164GISEL-NEXT: .LBB4_6: ; %endif
+; GFX1164GISEL-NEXT: s_cbranch_scc1 .LBB4_6
+; GFX1164GISEL-NEXT: ; %bb.7:
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v4, s4
+; GFX1164GISEL-NEXT: .LBB4_8: ; %endif
; GFX1164GISEL-NEXT: s_or_b64 exec, exec, s[0:1]
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v2, s4
-; GFX1164GISEL-NEXT: global_store_b32 v[0:1], v2, off
+; GFX1164GISEL-NEXT: global_store_b32 v[0:1], v4, off
; GFX1164GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1132DAGISEL-LABEL: divergent_cfg_float:
@@ -2237,46 +2252,49 @@ define void @divergent_cfg_float(ptr addrspace(1) %out, float %in, float %in2) {
; GFX1132GISEL: ; %bb.0: ; %entry
; GFX1132GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1132GISEL-NEXT: v_and_b32_e32 v4, 0x3ff, v31
-; GFX1132GISEL-NEXT: s_mov_b32 s1, exec_lo
-; GFX1132GISEL-NEXT: ; implicit-def: $sgpr0
-; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1132GISEL-NEXT: v_cmpx_le_u32_e32 16, v4
-; GFX1132GISEL-NEXT: s_xor_b32 s1, exec_lo, s1
-; GFX1132GISEL-NEXT: s_cbranch_execz .LBB4_3
+; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1132GISEL-NEXT: v_cmp_le_u32_e32 vcc_lo, 16, v4
+; GFX1132GISEL-NEXT: ; implicit-def: $vgpr4
+; GFX1132GISEL-NEXT: s_and_saveexec_b32 s0, vcc_lo
+; GFX1132GISEL-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX1132GISEL-NEXT: s_cbranch_execz .LBB4_4
; GFX1132GISEL-NEXT: ; %bb.1: ; %else
-; GFX1132GISEL-NEXT: s_mov_b32 s2, exec_lo
-; GFX1132GISEL-NEXT: s_mov_b32 s0, 0x7fc00000
+; GFX1132GISEL-NEXT: s_mov_b32 s1, exec_lo
+; GFX1132GISEL-NEXT: s_mov_b32 s2, 0x7fc00000
; GFX1132GISEL-NEXT: .LBB4_2: ; =>This Inner Loop Header: Depth=1
-; GFX1132GISEL-NEXT: s_ctz_i32_b32 s3, s2
+; GFX1132GISEL-NEXT: s_ctz_i32_b32 s3, s1
; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1132GISEL-NEXT: v_readlane_b32 s4, v2, s3
-; GFX1132GISEL-NEXT: s_bitset0_b32 s2, s3
-; GFX1132GISEL-NEXT: s_cmp_lg_u32 s2, 0
-; GFX1132GISEL-NEXT: v_min_f32_e64 v3, s0, s4
+; GFX1132GISEL-NEXT: s_bitset0_b32 s1, s3
+; GFX1132GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1132GISEL-NEXT: v_min_f32_e64 v3, s2, s4
; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1132GISEL-NEXT: v_readfirstlane_b32 s0, v3
-; GFX1132GISEL-NEXT: ; implicit-def: $vgpr3
+; GFX1132GISEL-NEXT: v_readfirstlane_b32 s2, v3
; GFX1132GISEL-NEXT: s_cbranch_scc1 .LBB4_2
-; GFX1132GISEL-NEXT: .LBB4_3: ; %Flow
-; GFX1132GISEL-NEXT: s_and_not1_saveexec_b32 s1, s1
-; GFX1132GISEL-NEXT: s_cbranch_execz .LBB4_6
-; GFX1132GISEL-NEXT: ; %bb.4: ; %if
-; GFX1132GISEL-NEXT: s_mov_b32 s2, exec_lo
-; GFX1132GISEL-NEXT: s_mov_b32 s0, 0x7fc00000
-; GFX1132GISEL-NEXT: .LBB4_5: ; =>This Inner Loop Header: Depth=1
-; GFX1132GISEL-NEXT: s_ctz_i32_b32 s3, s2
+; GFX1132GISEL-NEXT: ; %bb.3:
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v4, s2
+; GFX1132GISEL-NEXT: ; implicit-def: $vgpr3
+; GFX1132GISEL-NEXT: .LBB4_4: ; %Flow
+; GFX1132GISEL-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX1132GISEL-NEXT: s_cbranch_execz .LBB4_8
+; GFX1132GISEL-NEXT: ; %bb.5: ; %if
+; GFX1132GISEL-NEXT: s_mov_b32 s1, exec_lo
+; GFX1132GISEL-NEXT: s_mov_b32 s2, 0x7fc00000
+; GFX1132GISEL-NEXT: .LBB4_6: ; =>This Inner Loop Header: Depth=1
+; GFX1132GISEL-NEXT: s_ctz_i32_b32 s3, s1
; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1132GISEL-NEXT: v_readlane_b32 s4, v3, s3
-; GFX1132GISEL-NEXT: s_bitset0_b32 s2, s3
-; GFX1132GISEL-NEXT: s_cmp_lg_u32 s2, 0
-; GFX1132GISEL-NEXT: v_min_f32_e64 v2, s0, s4
+; GFX1132GISEL-NEXT: s_bitset0_b32 s1, s3
+; GFX1132GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1132GISEL-NEXT: v_min_f32_e64 v2, s2, s4
; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1132GISEL-NEXT: v_readfirstlane_b32 s0, v2
-; GFX1132GISEL-NEXT: s_cbranch_scc1 .LBB4_5
-; GFX1132GISEL-NEXT: .LBB4_6: ; %endif
-; GFX1132GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s1
-; GFX1132GISEL-NEXT: v_mov_b32_e32 v2, s0
-; GFX1132GISEL-NEXT: global_store_b32 v[0:1], v2, off
+; GFX1132GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; GFX1132GISEL-NEXT: s_cbranch_scc1 .LBB4_6
+; GFX1132GISEL-NEXT: ; %bb.7:
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v4, s2
+; GFX1132GISEL-NEXT: .LBB4_8: ; %endif
+; GFX1132GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX1132GISEL-NEXT: global_store_b32 v[0:1], v4, off
; GFX1132GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12DAGISEL-LABEL: divergent_cfg_float:
@@ -2860,52 +2878,56 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX8GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8GISEL-NEXT: v_and_b32_e32 v6, 0x3ff, v31
; GFX8GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v6
-; GFX8GISEL-NEXT: ; implicit-def: $sgpr4_sgpr5
-; GFX8GISEL-NEXT: s_and_saveexec_b64 s[6:7], vcc
-; GFX8GISEL-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
-; GFX8GISEL-NEXT: s_cbranch_execz .LBB7_3
+; GFX8GISEL-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX8GISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc
+; GFX8GISEL-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX8GISEL-NEXT: s_cbranch_execz .LBB7_4
; GFX8GISEL-NEXT: ; %bb.1: ; %else
-; GFX8GISEL-NEXT: s_mov_b32 s4, 0
-; GFX8GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
-; GFX8GISEL-NEXT: s_mov_b64 s[8:9], exec
+; GFX8GISEL-NEXT: s_mov_b32 s8, 0
+; GFX8GISEL-NEXT: s_mov_b32 s9, 0x7ff80000
+; GFX8GISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX8GISEL-NEXT: .LBB7_2: ; =>This Inner Loop Header: Depth=1
-; GFX8GISEL-NEXT: s_ff1_i32_b64 s12, s[8:9]
-; GFX8GISEL-NEXT: v_mov_b32_e32 v4, s4
+; GFX8GISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v4, s8
; GFX8GISEL-NEXT: v_readlane_b32 s10, v2, s12
; GFX8GISEL-NEXT: v_readlane_b32 s11, v3, s12
-; GFX8GISEL-NEXT: v_mov_b32_e32 v5, s5
+; GFX8GISEL-NEXT: v_mov_b32_e32 v5, s9
; GFX8GISEL-NEXT: v_min_f64 v[4:5], s[10:11], v[4:5]
-; GFX8GISEL-NEXT: s_bitset0_b64 s[8:9], s12
-; GFX8GISEL-NEXT: s_cmp_lg_u64 s[8:9], 0
-; GFX8GISEL-NEXT: v_readfirstlane_b32 s4, v4
-; GFX8GISEL-NEXT: v_readfirstlane_b32 s5, v5
+; GFX8GISEL-NEXT: s_bitset0_b64 s[6:7], s12
+; GFX8GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; GFX8GISEL-NEXT: v_readfirstlane_b32 s8, v4
+; GFX8GISEL-NEXT: v_readfirstlane_b32 s9, v5
+; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB7_2
+; GFX8GISEL-NEXT: ; %bb.3:
+; GFX8GISEL-NEXT: v_mov_b32_e32 v6, s8
+; GFX8GISEL-NEXT: v_mov_b32_e32 v7, s9
; GFX8GISEL-NEXT: ; implicit-def: $vgpr4
; GFX8GISEL-NEXT: ; implicit-def: $vgpr5
-; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB7_2
-; GFX8GISEL-NEXT: .LBB7_3: ; %Flow
-; GFX8GISEL-NEXT: s_andn2_saveexec_b64 s[6:7], s[6:7]
-; GFX8GISEL-NEXT: s_cbranch_execz .LBB7_6
-; GFX8GISEL-NEXT: ; %bb.4: ; %if
-; GFX8GISEL-NEXT: s_mov_b32 s4, 0
-; GFX8GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
-; GFX8GISEL-NEXT: s_mov_b64 s[8:9], exec
-; GFX8GISEL-NEXT: .LBB7_5: ; =>This Inner Loop Header: Depth=1
-; GFX8GISEL-NEXT: s_ff1_i32_b64 s12, s[8:9]
-; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s4
+; GFX8GISEL-NEXT: .LBB7_4: ; %Flow
+; GFX8GISEL-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX8GISEL-NEXT: s_cbranch_execz .LBB7_8
+; GFX8GISEL-NEXT: ; %bb.5: ; %if
+; GFX8GISEL-NEXT: s_mov_b32 s8, 0
+; GFX8GISEL-NEXT: s_mov_b32 s9, 0x7ff80000
+; GFX8GISEL-NEXT: s_mov_b64 s[6:7], exec
+; GFX8GISEL-NEXT: .LBB7_6: ; =>This Inner Loop Header: Depth=1
+; GFX8GISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s8
; GFX8GISEL-NEXT: v_readlane_b32 s10, v4, s12
; GFX8GISEL-NEXT: v_readlane_b32 s11, v5, s12
-; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s5
+; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s9
; GFX8GISEL-NEXT: v_min_f64 v[2:3], s[10:11], v[2:3]
-; GFX8GISEL-NEXT: s_bitset0_b64 s[8:9], s12
-; GFX8GISEL-NEXT: s_cmp_lg_u64 s[8:9], 0
-; GFX8GISEL-NEXT: v_readfirstlane_b32 s4, v2
-; GFX8GISEL-NEXT: v_readfirstlane_b32 s5, v3
-; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB7_5
-; GFX8GISEL-NEXT: .LBB7_6: ; %endif
-; GFX8GISEL-NEXT: s_or_b64 exec, exec, s[6:7]
-; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s4
-; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s5
-; GFX8GISEL-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; GFX8GISEL-NEXT: s_bitset0_b64 s[6:7], s12
+; GFX8GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; GFX8GISEL-NEXT: v_readfirstlane_b32 s8, v2
+; GFX8GISEL-NEXT: v_readfirstlane_b32 s9, v3
+; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB7_6
+; GFX8GISEL-NEXT: ; %bb.7:
+; GFX8GISEL-NEXT: v_mov_b32_e32 v6, s8
+; GFX8GISEL-NEXT: v_mov_b32_e32 v7, s9
+; GFX8GISEL-NEXT: .LBB7_8: ; %endif
+; GFX8GISEL-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX8GISEL-NEXT: flat_store_dwordx2 v[0:1], v[6:7]
; GFX8GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX8GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -2972,52 +2994,56 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX9GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9GISEL-NEXT: v_and_b32_e32 v6, 0x3ff, v31
; GFX9GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v6
-; GFX9GISEL-NEXT: ; implicit-def: $sgpr4_sgpr5
-; GFX9GISEL-NEXT: s_and_saveexec_b64 s[6:7], vcc
-; GFX9GISEL-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
-; GFX9GISEL-NEXT: s_cbranch_execz .LBB7_3
+; GFX9GISEL-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX9GISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc
+; GFX9GISEL-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9GISEL-NEXT: s_cbranch_execz .LBB7_4
; GFX9GISEL-NEXT: ; %bb.1: ; %else
-; GFX9GISEL-NEXT: s_mov_b32 s4, 0
-; GFX9GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
-; GFX9GISEL-NEXT: s_mov_b64 s[8:9], exec
+; GFX9GISEL-NEXT: s_mov_b32 s8, 0
+; GFX9GISEL-NEXT: s_mov_b32 s9, 0x7ff80000
+; GFX9GISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX9GISEL-NEXT: .LBB7_2: ; =>This Inner Loop Header: Depth=1
-; GFX9GISEL-NEXT: s_ff1_i32_b64 s12, s[8:9]
-; GFX9GISEL-NEXT: v_mov_b32_e32 v4, s4
+; GFX9GISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
+; GFX9GISEL-NEXT: v_mov_b32_e32 v4, s8
; GFX9GISEL-NEXT: v_readlane_b32 s10, v2, s12
; GFX9GISEL-NEXT: v_readlane_b32 s11, v3, s12
-; GFX9GISEL-NEXT: v_mov_b32_e32 v5, s5
+; GFX9GISEL-NEXT: v_mov_b32_e32 v5, s9
; GFX9GISEL-NEXT: v_min_f64 v[4:5], s[10:11], v[4:5]
-; GFX9GISEL-NEXT: s_bitset0_b64 s[8:9], s12
-; GFX9GISEL-NEXT: s_cmp_lg_u64 s[8:9], 0
-; GFX9GISEL-NEXT: v_readfirstlane_b32 s4, v4
-; GFX9GISEL-NEXT: v_readfirstlane_b32 s5, v5
+; GFX9GISEL-NEXT: s_bitset0_b64 s[6:7], s12
+; GFX9GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; GFX9GISEL-NEXT: v_readfirstlane_b32 s8, v4
+; GFX9GISEL-NEXT: v_readfirstlane_b32 s9, v5
+; GFX9GISEL-NEXT: s_cbranch_scc1 .LBB7_2
+; GFX9GISEL-NEXT: ; %bb.3:
+; GFX9GISEL-NEXT: v_mov_b32_e32 v6, s8
+; GFX9GISEL-NEXT: v_mov_b32_e32 v7, s9
; GFX9GISEL-NEXT: ; implicit-def: $vgpr4
; GFX9GISEL-NEXT: ; implicit-def: $vgpr5
-; GFX9GISEL-NEXT: s_cbranch_scc1 .LBB7_2
-; GFX9GISEL-NEXT: .LBB7_3: ; %Flow
-; GFX9GISEL-NEXT: s_andn2_saveexec_b64 s[6:7], s[6:7]
-; GFX9GISEL-NEXT: s_cbranch_execz .LBB7_6
-; GFX9GISEL-NEXT: ; %bb.4: ; %if
-; GFX9GISEL-NEXT: s_mov_b32 s4, 0
-; GFX9GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
-; GFX9GISEL-NEXT: s_mov_b64 s[8:9], exec
-; GFX9GISEL-NEXT: .LBB7_5: ; =>This Inner Loop Header: Depth=1
-; GFX9GISEL-NEXT: s_ff1_i32_b64 s12, s[8:9]
-; GFX9GISEL-NEXT: v_mov_b32_e32 v2, s4
+; GFX9GISEL-NEXT: .LBB7_4: ; %Flow
+; GFX9GISEL-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9GISEL-NEXT: s_cbranch_execz .LBB7_8
+; GFX9GISEL-NEXT: ; %bb.5: ; %if
+; GFX9GISEL-NEXT: s_mov_b32 s8, 0
+; GFX9GISEL-NEXT: s_mov_b32 s9, 0x7ff80000
+; GFX9GISEL-NEXT: s_mov_b64 s[6:7], exec
+; GFX9GISEL-NEXT: .LBB7_6: ; =>This Inner Loop Header: Depth=1
+; GFX9GISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
+; GFX9GISEL-NEXT: v_mov_b32_e32 v2, s8
; GFX9GISEL-NEXT: v_readlane_b32 s10, v4, s12
; GFX9GISEL-NEXT: v_readlane_b32 s11, v5, s12
-; GFX9GISEL-NEXT: v_mov_b32_e32 v3, s5
+; GFX9GISEL-NEXT: v_mov_b32_e32 v3, s9
; GFX9GISEL-NEXT: v_min_f64 v[2:3], s[10:11], v[2:3]
-; GFX9GISEL-NEXT: s_bitset0_b64 s[8:9], s12
-; GFX9GISEL-NEXT: s_cmp_lg_u64 s[8:9], 0
-; GFX9GISEL-NEXT: v_readfirstlane_b32 s4, v2
-; GFX9GISEL-NEXT: v_readfirstlane_b32 s5, v3
-; GFX9GISEL-NEXT: s_cbranch_scc1 .LBB7_5
-; GFX9GISEL-NEXT: .LBB7_6: ; %endif
-; GFX9GISEL-NEXT: s_or_b64 exec, exec, s[6:7]
-; GFX9GISEL-NEXT: v_mov_b32_e32 v2, s4
-; GFX9GISEL-NEXT: v_mov_b32_e32 v3, s5
-; GFX9GISEL-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
+; GFX9GISEL-NEXT: s_bitset0_b64 s[6:7], s12
+; GFX9GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; GFX9GISEL-NEXT: v_readfirstlane_b32 s8, v2
+; GFX9GISEL-NEXT: v_readfirstlane_b32 s9, v3
+; GFX9GISEL-NEXT: s_cbranch_scc1 .LBB7_6
+; GFX9GISEL-NEXT: ; %bb.7:
+; GFX9GISEL-NEXT: v_mov_b32_e32 v6, s8
+; GFX9GISEL-NEXT: v_mov_b32_e32 v7, s9
+; GFX9GISEL-NEXT: .LBB7_8: ; %endif
+; GFX9GISEL-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9GISEL-NEXT: global_store_dwordx2 v[0:1], v[6:7], off
; GFX9GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX9GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -3078,49 +3104,53 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1064GISEL: ; %bb.0: ; %entry
; GFX1064GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1064GISEL-NEXT: v_and_b32_e32 v6, 0x3ff, v31
-; GFX1064GISEL-NEXT: ; implicit-def: $sgpr4_sgpr5
; GFX1064GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v6
-; GFX1064GISEL-NEXT: s_and_saveexec_b64 s[6:7], vcc
-; GFX1064GISEL-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
-; GFX1064GISEL-NEXT: s_cbranch_execz .LBB7_3
+; GFX1064GISEL-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX1064GISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc
+; GFX1064GISEL-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX1064GISEL-NEXT: s_cbranch_execz .LBB7_4
; GFX1064GISEL-NEXT: ; %bb.1: ; %else
-; GFX1064GISEL-NEXT: s_mov_b32 s4, 0
-; GFX1064GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
-; GFX1064GISEL-NEXT: s_mov_b64 s[8:9], exec
+; GFX1064GISEL-NEXT: s_mov_b32 s8, 0
+; GFX1064GISEL-NEXT: s_mov_b32 s9, 0x7ff80000
+; GFX1064GISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX1064GISEL-NEXT: .LBB7_2: ; =>This Inner Loop Header: Depth=1
-; GFX1064GISEL-NEXT: s_ff1_i32_b64 s12, s[8:9]
+; GFX1064GISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
; GFX1064GISEL-NEXT: v_readlane_b32 s10, v2, s12
; GFX1064GISEL-NEXT: v_readlane_b32 s11, v3, s12
-; GFX1064GISEL-NEXT: s_bitset0_b64 s[8:9], s12
-; GFX1064GISEL-NEXT: s_cmp_lg_u64 s[8:9], 0
-; GFX1064GISEL-NEXT: v_min_f64 v[4:5], s[10:11], s[4:5]
-; GFX1064GISEL-NEXT: v_readfirstlane_b32 s4, v4
-; GFX1064GISEL-NEXT: v_readfirstlane_b32 s5, v5
+; GFX1064GISEL-NEXT: s_bitset0_b64 s[6:7], s12
+; GFX1064GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; GFX1064GISEL-NEXT: v_min_f64 v[4:5], s[10:11], s[8:9]
+; GFX1064GISEL-NEXT: v_readfirstlane_b32 s8, v4
+; GFX1064GISEL-NEXT: v_readfirstlane_b32 s9, v5
+; GFX1064GISEL-NEXT: s_cbranch_scc1 .LBB7_2
+; GFX1064GISEL-NEXT: ; %bb.3:
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v6, s8
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v7, s9
; GFX1064GISEL-NEXT: ; implicit-def: $vgpr4
; GFX1064GISEL-NEXT: ; implicit-def: $vgpr5
-; GFX1064GISEL-NEXT: s_cbranch_scc1 .LBB7_2
-; GFX1064GISEL-NEXT: .LBB7_3: ; %Flow
-; GFX1064GISEL-NEXT: s_andn2_saveexec_b64 s[6:7], s[6:7]
-; GFX1064GISEL-NEXT: s_cbranch_execz .LBB7_6
-; GFX1064GISEL-NEXT: ; %bb.4: ; %if
-; GFX1064GISEL-NEXT: s_mov_b32 s4, 0
-; GFX1064GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
-; GFX1064GISEL-NEXT: s_mov_b64 s[8:9], exec
-; GFX1064GISEL-NEXT: .LBB7_5: ; =>This Inner Loop Header: Depth=1
-; GFX1064GISEL-NEXT: s_ff1_i32_b64 s12, s[8:9]
+; GFX1064GISEL-NEXT: .LBB7_4: ; %Flow
+; GFX1064GISEL-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX1064GISEL-NEXT: s_cbranch_execz .LBB7_8
+; GFX1064GISEL-NEXT: ; %bb.5: ; %if
+; GFX1064GISEL-NEXT: s_mov_b32 s8, 0
+; GFX1064GISEL-NEXT: s_mov_b32 s9, 0x7ff80000
+; GFX1064GISEL-NEXT: s_mov_b64 s[6:7], exec
+; GFX1064GISEL-NEXT: .LBB7_6: ; =>This Inner Loop Header: Depth=1
+; GFX1064GISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
; GFX1064GISEL-NEXT: v_readlane_b32 s10, v4, s12
; GFX1064GISEL-NEXT: v_readlane_b32 s11, v5, s12
-; GFX1064GISEL-NEXT: s_bitset0_b64 s[8:9], s12
-; GFX1064GISEL-NEXT: s_cmp_lg_u64 s[8:9], 0
-; GFX1064GISEL-NEXT: v_min_f64 v[2:3], s[10:11], s[4:5]
-; GFX1064GISEL-NEXT: v_readfirstlane_b32 s4, v2
-; GFX1064GISEL-NEXT: v_readfirstlane_b32 s5, v3
-; GFX1064GISEL-NEXT: s_cbranch_scc1 .LBB7_5
-; GFX1064GISEL-NEXT: .LBB7_6: ; %endif
-; GFX1064GISEL-NEXT: s_or_b64 exec, exec, s[6:7]
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v2, s4
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v3, s5
-; GFX1064GISEL-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
+; GFX1064GISEL-NEXT: s_bitset0_b64 s[6:7], s12
+; GFX1064GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; GFX1064GISEL-NEXT: v_min_f64 v[2:3], s[10:11], s[8:9]
+; GFX1064GISEL-NEXT: v_readfirstlane_b32 s8, v2
+; GFX1064GISEL-NEXT: v_readfirstlane_b32 s9, v3
+; GFX1064GISEL-NEXT: s_cbranch_scc1 .LBB7_6
+; GFX1064GISEL-NEXT: ; %bb.7:
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v6, s8
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v7, s9
+; GFX1064GISEL-NEXT: .LBB7_8: ; %endif
+; GFX1064GISEL-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX1064GISEL-NEXT: global_store_dwordx2 v[0:1], v[6:7], off
; GFX1064GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1032DAGISEL-LABEL: divergent_cfg_double:
@@ -3180,11 +3210,11 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1032GISEL: ; %bb.0: ; %entry
; GFX1032GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1032GISEL-NEXT: v_and_b32_e32 v6, 0x3ff, v31
-; GFX1032GISEL-NEXT: ; implicit-def: $sgpr4_sgpr5
; GFX1032GISEL-NEXT: v_cmp_le_u32_e32 vcc_lo, 16, v6
-; GFX1032GISEL-NEXT: s_and_saveexec_b32 s6, vcc_lo
-; GFX1032GISEL-NEXT: s_xor_b32 s6, exec_lo, s6
-; GFX1032GISEL-NEXT: s_cbranch_execz .LBB7_3
+; GFX1032GISEL-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX1032GISEL-NEXT: s_and_saveexec_b32 s4, vcc_lo
+; GFX1032GISEL-NEXT: s_xor_b32 s6, exec_lo, s4
+; GFX1032GISEL-NEXT: s_cbranch_execz .LBB7_4
; GFX1032GISEL-NEXT: ; %bb.1: ; %else
; GFX1032GISEL-NEXT: s_mov_b32 s4, 0
; GFX1032GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
@@ -3198,17 +3228,20 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1032GISEL-NEXT: v_min_f64 v[4:5], s[8:9], s[4:5]
; GFX1032GISEL-NEXT: v_readfirstlane_b32 s4, v4
; GFX1032GISEL-NEXT: v_readfirstlane_b32 s5, v5
+; GFX1032GISEL-NEXT: s_cbranch_scc1 .LBB7_2
+; GFX1032GISEL-NEXT: ; %bb.3:
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v7, s5
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v6, s4
; GFX1032GISEL-NEXT: ; implicit-def: $vgpr4
; GFX1032GISEL-NEXT: ; implicit-def: $vgpr5
-; GFX1032GISEL-NEXT: s_cbranch_scc1 .LBB7_2
-; GFX1032GISEL-NEXT: .LBB7_3: ; %Flow
+; GFX1032GISEL-NEXT: .LBB7_4: ; %Flow
; GFX1032GISEL-NEXT: s_andn2_saveexec_b32 s6, s6
-; GFX1032GISEL-NEXT: s_cbranch_execz .LBB7_6
-; GFX1032GISEL-NEXT: ; %bb.4: ; %if
+; GFX1032GISEL-NEXT: s_cbranch_execz .LBB7_8
+; GFX1032GISEL-NEXT: ; %bb.5: ; %if
; GFX1032GISEL-NEXT: s_mov_b32 s4, 0
; GFX1032GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
; GFX1032GISEL-NEXT: s_mov_b32 s7, exec_lo
-; GFX1032GISEL-NEXT: .LBB7_5: ; =>This Inner Loop Header: Depth=1
+; GFX1032GISEL-NEXT: .LBB7_6: ; =>This Inner Loop Header: Depth=1
; GFX1032GISEL-NEXT: s_ff1_i32_b32 s10, s7
; GFX1032GISEL-NEXT: v_readlane_b32 s8, v4, s10
; GFX1032GISEL-NEXT: v_readlane_b32 s9, v5, s10
@@ -3217,12 +3250,13 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1032GISEL-NEXT: v_min_f64 v[2:3], s[8:9], s[4:5]
; GFX1032GISEL-NEXT: v_readfirstlane_b32 s4, v2
; GFX1032GISEL-NEXT: v_readfirstlane_b32 s5, v3
-; GFX1032GISEL-NEXT: s_cbranch_scc1 .LBB7_5
-; GFX1032GISEL-NEXT: .LBB7_6: ; %endif
+; GFX1032GISEL-NEXT: s_cbranch_scc1 .LBB7_6
+; GFX1032GISEL-NEXT: ; %bb.7:
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v7, s5
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v6, s4
+; GFX1032GISEL-NEXT: .LBB7_8: ; %endif
; GFX1032GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s6
-; GFX1032GISEL-NEXT: v_mov_b32_e32 v2, s4
-; GFX1032GISEL-NEXT: v_mov_b32_e32 v3, s5
-; GFX1032GISEL-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
+; GFX1032GISEL-NEXT: global_store_dwordx2 v[0:1], v[6:7], off
; GFX1032GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1164DAGISEL-LABEL: divergent_cfg_double:
@@ -3289,56 +3323,60 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1164GISEL: ; %bb.0: ; %entry
; GFX1164GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1164GISEL-NEXT: v_and_b32_e32 v6, 0x3ff, v31
-; GFX1164GISEL-NEXT: s_mov_b64 s[2:3], exec
-; GFX1164GISEL-NEXT: ; implicit-def: $sgpr0_sgpr1
-; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1164GISEL-NEXT: v_cmpx_le_u32_e32 16, v6
-; GFX1164GISEL-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
-; GFX1164GISEL-NEXT: s_cbranch_execz .LBB7_3
+; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1164GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v6
+; GFX1164GISEL-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX1164GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc
+; GFX1164GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
+; GFX1164GISEL-NEXT: s_cbranch_execz .LBB7_4
; GFX1164GISEL-NEXT: ; %bb.1: ; %else
-; GFX1164GISEL-NEXT: s_mov_b32 s0, 0
-; GFX1164GISEL-NEXT: s_mov_b32 s1, 0x7ff80000
-; GFX1164GISEL-NEXT: s_mov_b64 s[4:5], exec
+; GFX1164GISEL-NEXT: s_mov_b32 s4, 0
+; GFX1164GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
+; GFX1164GISEL-NEXT: s_mov_b64 s[2:3], exec
; GFX1164GISEL-NEXT: .LBB7_2: ; =>This Inner Loop Header: Depth=1
; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1164GISEL-NEXT: s_ctz_i32_b64 s8, s[4:5]
+; GFX1164GISEL-NEXT: s_ctz_i32_b64 s8, s[2:3]
; GFX1164GISEL-NEXT: v_readlane_b32 s6, v2, s8
; GFX1164GISEL-NEXT: v_readlane_b32 s7, v3, s8
-; GFX1164GISEL-NEXT: s_bitset0_b64 s[4:5], s8
+; GFX1164GISEL-NEXT: s_bitset0_b64 s[2:3], s8
; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1164GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
-; GFX1164GISEL-NEXT: v_min_f64 v[4:5], s[6:7], s[0:1]
-; GFX1164GISEL-NEXT: v_readfirstlane_b32 s0, v4
+; GFX1164GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; GFX1164GISEL-NEXT: v_min_f64 v[4:5], s[6:7], s[4:5]
+; GFX1164GISEL-NEXT: v_readfirstlane_b32 s4, v4
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1164GISEL-NEXT: v_readfirstlane_b32 s1, v5
+; GFX1164GISEL-NEXT: v_readfirstlane_b32 s5, v5
+; GFX1164GISEL-NEXT: s_cbranch_scc1 .LBB7_2
+; GFX1164GISEL-NEXT: ; %bb.3:
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v7, s5
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v6, s4
; GFX1164GISEL-NEXT: ; implicit-def: $vgpr4
; GFX1164GISEL-NEXT: ; implicit-def: $vgpr5
-; GFX1164GISEL-NEXT: s_cbranch_scc1 .LBB7_2
-; GFX1164GISEL-NEXT: .LBB7_3: ; %Flow
-; GFX1164GISEL-NEXT: s_and_not1_saveexec_b64 s[2:3], s[2:3]
-; GFX1164GISEL-NEXT: s_cbranch_execz .LBB7_6
-; GFX1164GISEL-NEXT: ; %bb.4: ; %if
-; GFX1164GISEL-NEXT: s_mov_b32 s0, 0
-; GFX1164GISEL-NEXT: s_mov_b32 s1, 0x7ff80000
-; GFX1164GISEL-NEXT: s_mov_b64 s[4:5], exec
-; GFX1164GISEL-NEXT: .LBB7_5: ; =>This Inner Loop Header: Depth=1
+; GFX1164GISEL-NEXT: .LBB7_4: ; %Flow
+; GFX1164GISEL-NEXT: s_and_not1_saveexec_b64 s[0:1], s[0:1]
+; GFX1164GISEL-NEXT: s_cbranch_execz .LBB7_8
+; GFX1164GISEL-NEXT: ; %bb.5: ; %if
+; GFX1164GISEL-NEXT: s_mov_b32 s4, 0
+; GFX1164GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
+; GFX1164GISEL-NEXT: s_mov_b64 s[2:3], exec
+; GFX1164GISEL-NEXT: .LBB7_6: ; =>This Inner Loop Header: Depth=1
; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1164GISEL-NEXT: s_ctz_i32_b64 s8, s[4:5]
+; GFX1164GISEL-NEXT: s_ctz_i32_b64 s8, s[2:3]
; GFX1164GISEL-NEXT: v_readlane_b32 s6, v4, s8
; GFX1164GISEL-NEXT: v_readlane_b32 s7, v5, s8
-; GFX1164GISEL-NEXT: s_bitset0_b64 s[4:5], s8
+; GFX1164GISEL-NEXT: s_bitset0_b64 s[2:3], s8
; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1164GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
-; GFX1164GISEL-NEXT: v_min_f64 v[2:3], s[6:7], s[0:1]
-; GFX1164GISEL-NEXT: v_readfirstlane_b32 s0, v2
+; GFX1164GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; GFX1164GISEL-NEXT: v_min_f64 v[2:3], s[6:7], s[4:5]
+; GFX1164GISEL-NEXT: v_readfirstlane_b32 s4, v2
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1164GISEL-NEXT: v_readfirstlane_b32 s1, v3
-; GFX1164GISEL-NEXT: s_cbranch_scc1 .LBB7_5
-; GFX1164GISEL-NEXT: .LBB7_6: ; %endif
-; GFX1164GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v3, s1
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v2, s0
-; GFX1164GISEL-NEXT: global_store_b64 v[0:1], v[2:3], off
+; GFX1164GISEL-NEXT: v_readfirstlane_b32 s5, v3
+; GFX1164GISEL-NEXT: s_cbranch_scc1 .LBB7_6
+; GFX1164GISEL-NEXT: ; %bb.7:
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v7, s5
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v6, s4
+; GFX1164GISEL-NEXT: .LBB7_8: ; %endif
+; GFX1164GISEL-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX1164GISEL-NEXT: global_store_b64 v[0:1], v[6:7], off
; GFX1164GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1132DAGISEL-LABEL: divergent_cfg_double:
@@ -3403,12 +3441,12 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1132GISEL: ; %bb.0: ; %entry
; GFX1132GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1132GISEL-NEXT: v_and_b32_e32 v6, 0x3ff, v31
-; GFX1132GISEL-NEXT: s_mov_b32 s2, exec_lo
-; GFX1132GISEL-NEXT: ; implicit-def: $sgpr0_sgpr1
-; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1132GISEL-NEXT: v_cmpx_le_u32_e32 16, v6
-; GFX1132GISEL-NEXT: s_xor_b32 s2, exec_lo, s2
-; GFX1132GISEL-NEXT: s_cbranch_execz .LBB7_3
+; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1132GISEL-NEXT: v_cmp_le_u32_e32 vcc_lo, 16, v6
+; GFX1132GISEL-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX1132GISEL-NEXT: s_and_saveexec_b32 s0, vcc_lo
+; GFX1132GISEL-NEXT: s_xor_b32 s2, exec_lo, s0
+; GFX1132GISEL-NEXT: s_cbranch_execz .LBB7_4
; GFX1132GISEL-NEXT: ; %bb.1: ; %else
; GFX1132GISEL-NEXT: s_mov_b32 s0, 0
; GFX1132GISEL-NEXT: s_mov_b32 s1, 0x7ff80000
@@ -3425,17 +3463,19 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1132GISEL-NEXT: v_readfirstlane_b32 s0, v4
; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1132GISEL-NEXT: v_readfirstlane_b32 s1, v5
+; GFX1132GISEL-NEXT: s_cbranch_scc1 .LBB7_2
+; GFX1132GISEL-NEXT: ; %bb.3:
+; GFX1132GISEL-NEXT: v_dual_mov_b32 v7, s1 :: v_dual_mov_b32 v6, s0
; GFX1132GISEL-NEXT: ; implicit-def: $vgpr4
; GFX1132GISEL-NEXT: ; implicit-def: $vgpr5
-; GFX1132GISEL-NEXT: s_cbranch_scc1 .LBB7_2
-; GFX1132GISEL-NEXT: .LBB7_3: ; %Flow
+; GFX1132GISEL-NEXT: .LBB7_4: ; %Flow
; GFX1132GISEL-NEXT: s_and_not1_saveexec_b32 s2, s2
-; GFX1132GISEL-NEXT: s_cbranch_execz .LBB7_6
-; GFX1132GISEL-NEXT: ; %bb.4: ; %if
+; GFX1132GISEL-NEXT: s_cbranch_execz .LBB7_8
+; GFX1132GISEL-NEXT: ; %bb.5: ; %if
; GFX1132GISEL-NEXT: s_mov_b32 s0, 0
; GFX1132GISEL-NEXT: s_mov_b32 s1, 0x7ff80000
; GFX1132GISEL-NEXT: s_mov_b32 s3, exec_lo
-; GFX1132GISEL-NEXT: .LBB7_5: ; =>This Inner Loop Header: Depth=1
+; GFX1132GISEL-NEXT: .LBB7_6: ; =>This Inner Loop Header: Depth=1
; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1132GISEL-NEXT: s_ctz_i32_b32 s6, s3
; GFX1132GISEL-NEXT: v_readlane_b32 s4, v4, s6
@@ -3447,11 +3487,12 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1132GISEL-NEXT: v_readfirstlane_b32 s0, v2
; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1132GISEL-NEXT: v_readfirstlane_b32 s1, v3
-; GFX1132GISEL-NEXT: s_cbranch_scc1 .LBB7_5
-; GFX1132GISEL-NEXT: .LBB7_6: ; %endif
+; GFX1132GISEL-NEXT: s_cbranch_scc1 .LBB7_6
+; GFX1132GISEL-NEXT: ; %bb.7:
+; GFX1132GISEL-NEXT: v_dual_mov_b32 v7, s1 :: v_dual_mov_b32 v6, s0
+; GFX1132GISEL-NEXT: .LBB7_8: ; %endif
; GFX1132GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s2
-; GFX1132GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
-; GFX1132GISEL-NEXT: global_store_b64 v[0:1], v[2:3], off
+; GFX1132GISEL-NEXT: global_store_b64 v[0:1], v[6:7], off
; GFX1132GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12DAGISEL-LABEL: divergent_cfg_double:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
index 67e470cf2ea64..636ba88c5ff18 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
@@ -1,16 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=0 < %s | FileCheck -check-prefixes=GFX8DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=1 < %s | FileCheck -check-prefixes=GFX8GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX8GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=0 < %s | FileCheck -check-prefixes=GFX9DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=1 < %s | FileCheck -check-prefixes=GFX9GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX9GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1064DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1064GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1064GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1032DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1032GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1032GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1164DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1164GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1164GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1132DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1132GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1132GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -global-isel=0 < %s | FileCheck -check-prefixes=GFX12DAGISEL %s
@@ -1916,7 +1916,9 @@ define amdgpu_kernel void @divergent_cfg_float(ptr addrspace(1) %out, float %in,
; GFX8GISEL-NEXT: v_mul_f32_e64 v0, -s0, v0
; GFX8GISEL-NEXT: v_readfirstlane_b32 s6, v0
; GFX8GISEL-NEXT: .LBB4_2: ; %Flow
-; GFX8GISEL-NEXT: s_andn2_saveexec_b64 s[2:3], s[2:3]
+; GFX8GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[2:3]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX8GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX8GISEL-NEXT: s_cbranch_execz .LBB4_4
; GFX8GISEL-NEXT: ; %bb.3: ; %if
; GFX8GISEL-NEXT: s_mov_b64 s[6:7], exec
@@ -1924,16 +1926,16 @@ define amdgpu_kernel void @divergent_cfg_float(ptr addrspace(1) %out, float %in,
; GFX8GISEL-NEXT: s_bcnt1_i32_b64 s0, s[6:7]
; GFX8GISEL-NEXT: v_cvt_f32_i32_e32 v0, s0
; GFX8GISEL-NEXT: v_mul_f32_e64 v0, -s1, v0
-; GFX8GISEL-NEXT: v_readfirstlane_b32 s6, v0
+; GFX8GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX8GISEL-NEXT: .LBB4_4: ; %endif
; GFX8GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s6
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s1
-; GFX8GISEL-NEXT: flat_store_dword v[0:1], v2
+; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s1
+; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s0
+; GFX8GISEL-NEXT: flat_store_dword v[1:2], v0
; GFX8GISEL-NEXT: s_endpgm
;
; GFX9DAGISEL-LABEL: divergent_cfg_float:
@@ -1989,7 +1991,9 @@ define amdgpu_kernel void @divergent_cfg_float(ptr addrspace(1) %out, float %in,
; GFX9GISEL-NEXT: v_mul_f32_e64 v0, -s0, v0
; GFX9GISEL-NEXT: v_readfirstlane_b32 s6, v0
; GFX9GISEL-NEXT: .LBB4_2: ; %Flow
-; GFX9GISEL-NEXT: s_andn2_saveexec_b64 s[2:3], s[2:3]
+; GFX9GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[2:3]
+; GFX9GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX9GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX9GISEL-NEXT: s_cbranch_execz .LBB4_4
; GFX9GISEL-NEXT: ; %bb.3: ; %if
; GFX9GISEL-NEXT: s_mov_b64 s[6:7], exec
@@ -1997,12 +2001,12 @@ define amdgpu_kernel void @divergent_cfg_float(ptr addrspace(1) %out, float %in,
; GFX9GISEL-NEXT: s_bcnt1_i32_b64 s0, s[6:7]
; GFX9GISEL-NEXT: v_cvt_f32_i32_e32 v0, s0
; GFX9GISEL-NEXT: v_mul_f32_e64 v0, -s1, v0
-; GFX9GISEL-NEXT: v_readfirstlane_b32 s6, v0
+; GFX9GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX9GISEL-NEXT: .LBB4_4: ; %endif
; GFX9GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX9GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9GISEL-NEXT: v_mov_b32_e32 v0, s6
; GFX9GISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX9GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9GISEL-NEXT: global_store_dword v1, v0, s[0:1]
@@ -2061,7 +2065,9 @@ define amdgpu_kernel void @divergent_cfg_float(ptr addrspace(1) %out, float %in,
; GFX1064GISEL-NEXT: v_mul_f32_e64 v0, -s0, v0
; GFX1064GISEL-NEXT: v_readfirstlane_b32 s6, v0
; GFX1064GISEL-NEXT: .LBB4_2: ; %Flow
-; GFX1064GISEL-NEXT: s_andn2_saveexec_b64 s[2:3], s[2:3]
+; GFX1064GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[2:3]
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX1064GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX1064GISEL-NEXT: s_cbranch_execz .LBB4_4
; GFX1064GISEL-NEXT: ; %bb.3: ; %if
; GFX1064GISEL-NEXT: s_mov_b64 s[6:7], exec
@@ -2069,12 +2075,12 @@ define amdgpu_kernel void @divergent_cfg_float(ptr addrspace(1) %out, float %in,
; GFX1064GISEL-NEXT: s_bcnt1_i32_b64 s0, s[6:7]
; GFX1064GISEL-NEXT: v_cvt_f32_i32_e32 v0, s0
; GFX1064GISEL-NEXT: v_mul_f32_e64 v0, -s1, v0
-; GFX1064GISEL-NEXT: v_readfirstlane_b32 s6, v0
+; GFX1064GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX1064GISEL-NEXT: .LBB4_4: ; %endif
; GFX1064GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s6
; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064GISEL-NEXT: global_store_dword v1, v0, s[0:1]
@@ -2120,31 +2126,33 @@ define amdgpu_kernel void @divergent_cfg_float(ptr addrspace(1) %out, float %in,
; GFX1032GISEL: ; %bb.0: ; %entry
; GFX1032GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2c
; GFX1032GISEL-NEXT: v_cmp_le_u32_e32 vcc_lo, 16, v0
-; GFX1032GISEL-NEXT: ; implicit-def: $sgpr2
-; GFX1032GISEL-NEXT: s_and_saveexec_b32 s3, vcc_lo
-; GFX1032GISEL-NEXT: s_xor_b32 s3, exec_lo, s3
+; GFX1032GISEL-NEXT: ; implicit-def: $sgpr3
+; GFX1032GISEL-NEXT: s_and_saveexec_b32 s2, vcc_lo
+; GFX1032GISEL-NEXT: s_xor_b32 s2, exec_lo, s2
; GFX1032GISEL-NEXT: s_cbranch_execz .LBB4_2
; GFX1032GISEL-NEXT: ; %bb.1: ; %else
-; GFX1032GISEL-NEXT: s_mov_b32 s2, exec_lo
-; GFX1032GISEL-NEXT: s_bcnt1_i32_b32 s2, s2
-; GFX1032GISEL-NEXT: v_cvt_f32_i32_e32 v0, s2
+; GFX1032GISEL-NEXT: s_mov_b32 s3, exec_lo
+; GFX1032GISEL-NEXT: s_bcnt1_i32_b32 s3, s3
+; GFX1032GISEL-NEXT: v_cvt_f32_i32_e32 v0, s3
; GFX1032GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032GISEL-NEXT: v_mul_f32_e64 v0, -s0, v0
-; GFX1032GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1032GISEL-NEXT: v_readfirstlane_b32 s3, v0
; GFX1032GISEL-NEXT: .LBB4_2: ; %Flow
; GFX1032GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1032GISEL-NEXT: s_andn2_saveexec_b32 s0, s3
+; GFX1032GISEL-NEXT: s_or_saveexec_b32 s0, s2
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, s3
+; GFX1032GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX1032GISEL-NEXT: s_cbranch_execz .LBB4_4
; GFX1032GISEL-NEXT: ; %bb.3: ; %if
; GFX1032GISEL-NEXT: s_mov_b32 s2, exec_lo
; GFX1032GISEL-NEXT: s_bcnt1_i32_b32 s2, s2
; GFX1032GISEL-NEXT: v_cvt_f32_i32_e32 v0, s2
; GFX1032GISEL-NEXT: v_mul_f32_e64 v0, -s1, v0
-; GFX1032GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1032GISEL-NEXT: v_readfirstlane_b32 s1, v0
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, s1
; GFX1032GISEL-NEXT: .LBB4_4: ; %endif
; GFX1032GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1032GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX1032GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032GISEL-NEXT: global_store_dword v1, v0, s[0:1]
@@ -2214,7 +2222,10 @@ define amdgpu_kernel void @divergent_cfg_float(ptr addrspace(1) %out, float %in,
; GFX1164GISEL-NEXT: v_mul_f32_e64 v0, -s0, v0
; GFX1164GISEL-NEXT: v_readfirstlane_b32 s6, v0
; GFX1164GISEL-NEXT: .LBB4_2: ; %Flow
-; GFX1164GISEL-NEXT: s_and_not1_saveexec_b64 s[2:3], s[2:3]
+; GFX1164GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[2:3]
+; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX1164GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX1164GISEL-NEXT: s_cbranch_execz .LBB4_4
; GFX1164GISEL-NEXT: ; %bb.3: ; %if
; GFX1164GISEL-NEXT: s_mov_b64 s[6:7], exec
@@ -2223,14 +2234,13 @@ define amdgpu_kernel void @divergent_cfg_float(ptr addrspace(1) %out, float %in,
; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164GISEL-NEXT: v_cvt_f32_i32_e32 v0, s0
; GFX1164GISEL-NEXT: v_mul_f32_e64 v0, -s1, v0
-; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1164GISEL-NEXT: v_readfirstlane_b32 s6, v0
+; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1164GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX1164GISEL-NEXT: .LBB4_4: ; %endif
; GFX1164GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s6
; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
@@ -2284,24 +2294,27 @@ define amdgpu_kernel void @divergent_cfg_float(ptr addrspace(1) %out, float %in,
; GFX1132GISEL: ; %bb.0: ; %entry
; GFX1132GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x2c
; GFX1132GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX1132GISEL-NEXT: s_mov_b32 s3, exec_lo
-; GFX1132GISEL-NEXT: ; implicit-def: $sgpr2
+; GFX1132GISEL-NEXT: s_mov_b32 s2, exec_lo
+; GFX1132GISEL-NEXT: ; implicit-def: $sgpr3
; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1132GISEL-NEXT: v_cmpx_le_u32_e32 16, v0
-; GFX1132GISEL-NEXT: s_xor_b32 s3, exec_lo, s3
+; GFX1132GISEL-NEXT: s_xor_b32 s2, exec_lo, s2
; GFX1132GISEL-NEXT: s_cbranch_execz .LBB4_2
; GFX1132GISEL-NEXT: ; %bb.1: ; %else
-; GFX1132GISEL-NEXT: s_mov_b32 s2, exec_lo
+; GFX1132GISEL-NEXT: s_mov_b32 s3, exec_lo
; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1132GISEL-NEXT: s_bcnt1_i32_b32 s2, s2
-; GFX1132GISEL-NEXT: v_cvt_f32_i32_e32 v0, s2
+; GFX1132GISEL-NEXT: s_bcnt1_i32_b32 s3, s3
+; GFX1132GISEL-NEXT: v_cvt_f32_i32_e32 v0, s3
; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1132GISEL-NEXT: v_mul_f32_e64 v0, -s0, v0
-; GFX1132GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1132GISEL-NEXT: v_readfirstlane_b32 s3, v0
; GFX1132GISEL-NEXT: .LBB4_2: ; %Flow
; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-NEXT: s_and_not1_saveexec_b32 s0, s3
+; GFX1132GISEL-NEXT: s_or_saveexec_b32 s0, s2
+; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v0, s3
+; GFX1132GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s0
; GFX1132GISEL-NEXT: s_cbranch_execz .LBB4_4
; GFX1132GISEL-NEXT: ; %bb.3: ; %if
; GFX1132GISEL-NEXT: s_mov_b32 s2, exec_lo
@@ -2310,12 +2323,13 @@ define amdgpu_kernel void @divergent_cfg_float(ptr addrspace(1) %out, float %in,
; GFX1132GISEL-NEXT: v_cvt_f32_i32_e32 v0, s2
; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1132GISEL-NEXT: v_mul_f32_e64 v0, -s1, v0
-; GFX1132GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1132GISEL-NEXT: v_readfirstlane_b32 s1, v0
+; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v0, s1
; GFX1132GISEL-NEXT: .LBB4_4: ; %endif
; GFX1132GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX1132GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1132GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX1132GISEL-NEXT: s_endpgm
@@ -2982,7 +2996,10 @@ define amdgpu_kernel void @divergent_cfg_double(ptr addrspace(1) %out, double %i
; GFX8GISEL-NEXT: v_readfirstlane_b32 s7, v1
; GFX8GISEL-NEXT: .LBB7_2: ; %Flow
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8GISEL-NEXT: s_andn2_saveexec_b64 s[2:3], s[8:9]
+; GFX8GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[8:9]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s7
+; GFX8GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX8GISEL-NEXT: s_cbranch_execz .LBB7_4
; GFX8GISEL-NEXT: ; %bb.3: ; %if
; GFX8GISEL-NEXT: s_mov_b64 s[6:7], exec
@@ -2991,13 +3008,13 @@ define amdgpu_kernel void @divergent_cfg_double(ptr addrspace(1) %out, double %i
; GFX8GISEL-NEXT: v_cvt_f64_i32_e32 v[0:1], s6
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: v_mul_f64 v[0:1], -s[4:5], v[0:1]
-; GFX8GISEL-NEXT: v_readfirstlane_b32 s6, v0
-; GFX8GISEL-NEXT: v_readfirstlane_b32 s7, v1
+; GFX8GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX8GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX8GISEL-NEXT: .LBB7_4: ; %endif
; GFX8GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s6
; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
-; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX8GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX8GISEL-NEXT: s_endpgm
@@ -3059,7 +3076,10 @@ define amdgpu_kernel void @divergent_cfg_double(ptr addrspace(1) %out, double %i
; GFX9GISEL-NEXT: v_readfirstlane_b32 s7, v1
; GFX9GISEL-NEXT: .LBB7_2: ; %Flow
; GFX9GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9GISEL-NEXT: s_andn2_saveexec_b64 s[2:3], s[8:9]
+; GFX9GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[8:9]
+; GFX9GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX9GISEL-NEXT: v_mov_b32_e32 v1, s7
+; GFX9GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX9GISEL-NEXT: s_cbranch_execz .LBB7_4
; GFX9GISEL-NEXT: ; %bb.3: ; %if
; GFX9GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
@@ -3068,12 +3088,12 @@ define amdgpu_kernel void @divergent_cfg_double(ptr addrspace(1) %out, double %i
; GFX9GISEL-NEXT: v_cvt_f64_i32_e32 v[0:1], s4
; GFX9GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9GISEL-NEXT: v_mul_f64 v[0:1], -s[6:7], v[0:1]
-; GFX9GISEL-NEXT: v_readfirstlane_b32 s6, v0
-; GFX9GISEL-NEXT: v_readfirstlane_b32 s7, v1
+; GFX9GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX9GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; GFX9GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX9GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX9GISEL-NEXT: .LBB7_4: ; %endif
; GFX9GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX9GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX9GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX9GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX9GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX9GISEL-NEXT: s_endpgm
@@ -3122,21 +3142,24 @@ define amdgpu_kernel void @divergent_cfg_double(ptr addrspace(1) %out, double %i
; GFX1064GISEL: ; %bb.0: ; %entry
; GFX1064GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX1064GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v0
-; GFX1064GISEL-NEXT: ; implicit-def: $sgpr6_sgpr7
-; GFX1064GISEL-NEXT: s_and_saveexec_b64 s[8:9], vcc
-; GFX1064GISEL-NEXT: s_xor_b64 s[8:9], exec, s[8:9]
+; GFX1064GISEL-NEXT: ; implicit-def: $sgpr8_sgpr9
+; GFX1064GISEL-NEXT: s_and_saveexec_b64 s[6:7], vcc
+; GFX1064GISEL-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
; GFX1064GISEL-NEXT: s_cbranch_execz .LBB7_2
; GFX1064GISEL-NEXT: ; %bb.1: ; %else
-; GFX1064GISEL-NEXT: s_mov_b64 s[6:7], exec
-; GFX1064GISEL-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
-; GFX1064GISEL-NEXT: v_cvt_f64_i32_e32 v[0:1], s6
+; GFX1064GISEL-NEXT: s_mov_b64 s[8:9], exec
+; GFX1064GISEL-NEXT: s_bcnt1_i32_b64 s8, s[8:9]
+; GFX1064GISEL-NEXT: v_cvt_f64_i32_e32 v[0:1], s8
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064GISEL-NEXT: v_mul_f64 v[0:1], -s[2:3], v[0:1]
-; GFX1064GISEL-NEXT: v_readfirstlane_b32 s6, v0
-; GFX1064GISEL-NEXT: v_readfirstlane_b32 s7, v1
+; GFX1064GISEL-NEXT: v_readfirstlane_b32 s8, v0
+; GFX1064GISEL-NEXT: v_readfirstlane_b32 s9, v1
; GFX1064GISEL-NEXT: .LBB7_2: ; %Flow
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064GISEL-NEXT: s_andn2_saveexec_b64 s[2:3], s[8:9]
+; GFX1064GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[6:7]
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s8
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s9
+; GFX1064GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX1064GISEL-NEXT: s_cbranch_execz .LBB7_4
; GFX1064GISEL-NEXT: ; %bb.3: ; %if
; GFX1064GISEL-NEXT: s_mov_b64 s[6:7], exec
@@ -3145,12 +3168,12 @@ define amdgpu_kernel void @divergent_cfg_double(ptr addrspace(1) %out, double %i
; GFX1064GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064GISEL-NEXT: v_mul_f64 v[0:1], -s[6:7], v[0:1]
-; GFX1064GISEL-NEXT: v_readfirstlane_b32 s6, v0
-; GFX1064GISEL-NEXT: v_readfirstlane_b32 s7, v1
+; GFX1064GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX1064GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX1064GISEL-NEXT: .LBB7_4: ; %endif
; GFX1064GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX1064GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1064GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX1064GISEL-NEXT: s_endpgm
@@ -3213,7 +3236,10 @@ define amdgpu_kernel void @divergent_cfg_double(ptr addrspace(1) %out, double %i
; GFX1032GISEL-NEXT: v_readfirstlane_b32 s7, v1
; GFX1032GISEL-NEXT: .LBB7_2: ; %Flow
; GFX1032GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1032GISEL-NEXT: s_andn2_saveexec_b32 s2, s8
+; GFX1032GISEL-NEXT: s_or_saveexec_b32 s2, s8
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, s7
+; GFX1032GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s2
; GFX1032GISEL-NEXT: s_cbranch_execz .LBB7_4
; GFX1032GISEL-NEXT: ; %bb.3: ; %if
; GFX1032GISEL-NEXT: s_mov_b32 s3, exec_lo
@@ -3222,12 +3248,12 @@ define amdgpu_kernel void @divergent_cfg_double(ptr addrspace(1) %out, double %i
; GFX1032GISEL-NEXT: v_cvt_f64_i32_e32 v[0:1], s3
; GFX1032GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032GISEL-NEXT: v_mul_f64 v[0:1], -s[6:7], v[0:1]
-; GFX1032GISEL-NEXT: v_readfirstlane_b32 s6, v0
-; GFX1032GISEL-NEXT: v_readfirstlane_b32 s7, v1
+; GFX1032GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX1032GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX1032GISEL-NEXT: .LBB7_4: ; %endif
; GFX1032GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s2
-; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX1032GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1032GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX1032GISEL-NEXT: s_endpgm
@@ -3286,26 +3312,30 @@ define amdgpu_kernel void @divergent_cfg_double(ptr addrspace(1) %out, double %i
; GFX1164GISEL: ; %bb.0: ; %entry
; GFX1164GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1164GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX1164GISEL-NEXT: s_mov_b64 s[8:9], exec
-; GFX1164GISEL-NEXT: ; implicit-def: $sgpr6_sgpr7
+; GFX1164GISEL-NEXT: s_mov_b64 s[6:7], exec
+; GFX1164GISEL-NEXT: ; implicit-def: $sgpr8_sgpr9
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164GISEL-NEXT: v_cmpx_le_u32_e32 16, v0
-; GFX1164GISEL-NEXT: s_xor_b64 s[8:9], exec, s[8:9]
+; GFX1164GISEL-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
; GFX1164GISEL-NEXT: s_cbranch_execz .LBB7_2
; GFX1164GISEL-NEXT: ; %bb.1: ; %else
-; GFX1164GISEL-NEXT: s_mov_b64 s[6:7], exec
+; GFX1164GISEL-NEXT: s_mov_b64 s[8:9], exec
; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1164GISEL-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
-; GFX1164GISEL-NEXT: v_cvt_f64_i32_e32 v[0:1], s6
+; GFX1164GISEL-NEXT: s_bcnt1_i32_b64 s8, s[8:9]
+; GFX1164GISEL-NEXT: v_cvt_f64_i32_e32 v[0:1], s8
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1164GISEL-NEXT: v_mul_f64 v[0:1], -s[2:3], v[0:1]
-; GFX1164GISEL-NEXT: v_readfirstlane_b32 s6, v0
+; GFX1164GISEL-NEXT: v_readfirstlane_b32 s8, v0
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1164GISEL-NEXT: v_readfirstlane_b32 s7, v1
+; GFX1164GISEL-NEXT: v_readfirstlane_b32 s9, v1
; GFX1164GISEL-NEXT: .LBB7_2: ; %Flow
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-NEXT: s_and_not1_saveexec_b64 s[2:3], s[8:9]
+; GFX1164GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[6:7]
+; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s8
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s9
+; GFX1164GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX1164GISEL-NEXT: s_cbranch_execz .LBB7_4
; GFX1164GISEL-NEXT: ; %bb.3: ; %if
; GFX1164GISEL-NEXT: s_mov_b64 s[6:7], exec
@@ -3316,13 +3346,13 @@ define amdgpu_kernel void @divergent_cfg_double(ptr addrspace(1) %out, double %i
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164GISEL-NEXT: v_mul_f64 v[0:1], -s[4:5], v[0:1]
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1164GISEL-NEXT: v_readfirstlane_b32 s6, v0
-; GFX1164GISEL-NEXT: v_readfirstlane_b32 s7, v1
+; GFX1164GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX1164GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX1164GISEL-NEXT: .LBB7_4: ; %endif
; GFX1164GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX1164GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1164GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX1164GISEL-NEXT: s_endpgm
@@ -3397,7 +3427,10 @@ define amdgpu_kernel void @divergent_cfg_double(ptr addrspace(1) %out, double %i
; GFX1132GISEL-NEXT: v_readfirstlane_b32 s7, v1
; GFX1132GISEL-NEXT: .LBB7_2: ; %Flow
; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-NEXT: s_and_not1_saveexec_b32 s2, s8
+; GFX1132GISEL-NEXT: s_or_saveexec_b32 s2, s8
+; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1132GISEL-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
+; GFX1132GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s2
; GFX1132GISEL-NEXT: s_cbranch_execz .LBB7_4
; GFX1132GISEL-NEXT: ; %bb.3: ; %if
; GFX1132GISEL-NEXT: s_mov_b32 s3, exec_lo
@@ -3408,12 +3441,12 @@ define amdgpu_kernel void @divergent_cfg_double(ptr addrspace(1) %out, double %i
; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132GISEL-NEXT: v_mul_f64 v[0:1], -s[4:5], v[0:1]
; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1132GISEL-NEXT: v_readfirstlane_b32 s6, v0
-; GFX1132GISEL-NEXT: v_readfirstlane_b32 s7, v1
+; GFX1132GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX1132GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1132GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
; GFX1132GISEL-NEXT: .LBB7_4: ; %endif
; GFX1132GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s2
-; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1132GISEL-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
; GFX1132GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1132GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX1132GISEL-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
index 8f49864792794..b02c6f60d4332 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
@@ -1,16 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=0 < %s | FileCheck -check-prefixes=GFX8DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=1 < %s | FileCheck -check-prefixes=GFX8GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX8GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=0 < %s | FileCheck -check-prefixes=GFX9DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=1 < %s | FileCheck -check-prefixes=GFX9GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX9GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1064DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1064GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1064GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1032DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1032GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1032GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1164DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1164GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1164GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1132DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1132GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1132GISEL %s
define amdgpu_kernel void @uniform_value(ptr addrspace(1) %out, i32 %in) {
; GFX8DAGISEL-LABEL: uniform_value:
@@ -2169,7 +2169,7 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX8GISEL-LABEL: divergent_cfg:
; GFX8GISEL: ; %bb.0: ; %entry
; GFX8GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v0
-; GFX8GISEL-NEXT: ; implicit-def: $sgpr6
+; GFX8GISEL-NEXT: ; implicit-def: $sgpr2
; GFX8GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX8GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
; GFX8GISEL-NEXT: s_cbranch_execz .LBB6_2
@@ -2177,10 +2177,12 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX8GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
; GFX8GISEL-NEXT: ; implicit-def: $vgpr0
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8GISEL-NEXT: s_mov_b32 s6, s2
+; GFX8GISEL-NEXT: s_mov_b32 s2, s2
; GFX8GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX8GISEL-NEXT: s_andn2_saveexec_b64 s[0:1], s[0:1]
-; GFX8GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX8GISEL-NEXT: s_or_saveexec_b64 s[0:1], s[0:1]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s2
+; GFX8GISEL-NEXT: s_xor_b64 exec, exec, s[0:1]
+; GFX8GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX8GISEL-NEXT: ; %bb.3: ; %if
; GFX8GISEL-NEXT: s_mov_b64 s[2:3], exec
; GFX8GISEL-NEXT: s_brev_b32 s6, 1
@@ -2191,14 +2193,15 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX8GISEL-NEXT: s_max_i32 s6, s6, s8
; GFX8GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX8GISEL-NEXT: .LBB6_5: ; %endif
+; GFX8GISEL-NEXT: ; %bb.5:
+; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s6
+; GFX8GISEL-NEXT: .LBB6_6: ; %endif
; GFX8GISEL-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX8GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s6
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s1
-; GFX8GISEL-NEXT: flat_store_dword v[0:1], v2
+; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
+; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
+; GFX8GISEL-NEXT: flat_store_dword v[2:3], v1
; GFX8GISEL-NEXT: s_endpgm
;
; GFX9DAGISEL-LABEL: divergent_cfg:
@@ -2239,7 +2242,7 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX9GISEL-LABEL: divergent_cfg:
; GFX9GISEL: ; %bb.0: ; %entry
; GFX9GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v0
-; GFX9GISEL-NEXT: ; implicit-def: $sgpr6
+; GFX9GISEL-NEXT: ; implicit-def: $sgpr2
; GFX9GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX9GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
; GFX9GISEL-NEXT: s_cbranch_execz .LBB6_2
@@ -2247,10 +2250,12 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX9GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
; GFX9GISEL-NEXT: ; implicit-def: $vgpr0
; GFX9GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9GISEL-NEXT: s_mov_b32 s6, s2
+; GFX9GISEL-NEXT: s_mov_b32 s2, s2
; GFX9GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX9GISEL-NEXT: s_andn2_saveexec_b64 s[0:1], s[0:1]
-; GFX9GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX9GISEL-NEXT: s_or_saveexec_b64 s[0:1], s[0:1]
+; GFX9GISEL-NEXT: v_mov_b32_e32 v1, s2
+; GFX9GISEL-NEXT: s_xor_b64 exec, exec, s[0:1]
+; GFX9GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX9GISEL-NEXT: ; %bb.3: ; %if
; GFX9GISEL-NEXT: s_mov_b64 s[2:3], exec
; GFX9GISEL-NEXT: s_brev_b32 s6, 1
@@ -2261,13 +2266,14 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX9GISEL-NEXT: s_max_i32 s6, s6, s8
; GFX9GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX9GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX9GISEL-NEXT: .LBB6_5: ; %endif
+; GFX9GISEL-NEXT: ; %bb.5:
+; GFX9GISEL-NEXT: v_mov_b32_e32 v1, s6
+; GFX9GISEL-NEXT: .LBB6_6: ; %endif
; GFX9GISEL-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX9GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX9GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX9GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX9GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9GISEL-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX9GISEL-NEXT: global_store_dword v0, v1, s[0:1]
; GFX9GISEL-NEXT: s_endpgm
;
; GFX1064DAGISEL-LABEL: divergent_cfg:
@@ -2308,7 +2314,7 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1064GISEL-LABEL: divergent_cfg:
; GFX1064GISEL: ; %bb.0: ; %entry
; GFX1064GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v0
-; GFX1064GISEL-NEXT: ; implicit-def: $sgpr6
+; GFX1064GISEL-NEXT: ; implicit-def: $sgpr2
; GFX1064GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1064GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
; GFX1064GISEL-NEXT: s_cbranch_execz .LBB6_2
@@ -2316,10 +2322,12 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1064GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
; GFX1064GISEL-NEXT: ; implicit-def: $vgpr0
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064GISEL-NEXT: s_mov_b32 s6, s2
+; GFX1064GISEL-NEXT: s_mov_b32 s2, s2
; GFX1064GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX1064GISEL-NEXT: s_andn2_saveexec_b64 s[0:1], s[0:1]
-; GFX1064GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX1064GISEL-NEXT: s_or_saveexec_b64 s[0:1], s[0:1]
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s2
+; GFX1064GISEL-NEXT: s_xor_b64 exec, exec, s[0:1]
+; GFX1064GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX1064GISEL-NEXT: ; %bb.3: ; %if
; GFX1064GISEL-NEXT: s_mov_b64 s[2:3], exec
; GFX1064GISEL-NEXT: s_brev_b32 s6, 1
@@ -2330,13 +2338,14 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1064GISEL-NEXT: s_max_i32 s6, s6, s8
; GFX1064GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX1064GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX1064GISEL-NEXT: .LBB6_5: ; %endif
+; GFX1064GISEL-NEXT: ; %bb.5:
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s6
+; GFX1064GISEL-NEXT: .LBB6_6: ; %endif
; GFX1064GISEL-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064GISEL-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX1064GISEL-NEXT: global_store_dword v0, v1, s[0:1]
; GFX1064GISEL-NEXT: s_endpgm
;
; GFX1032DAGISEL-LABEL: divergent_cfg:
@@ -2377,35 +2386,38 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1032GISEL-LABEL: divergent_cfg:
; GFX1032GISEL: ; %bb.0: ; %entry
; GFX1032GISEL-NEXT: v_cmp_le_u32_e32 vcc_lo, 16, v0
-; GFX1032GISEL-NEXT: ; implicit-def: $sgpr0
-; GFX1032GISEL-NEXT: s_and_saveexec_b32 s1, vcc_lo
-; GFX1032GISEL-NEXT: s_xor_b32 s1, exec_lo, s1
+; GFX1032GISEL-NEXT: ; implicit-def: $sgpr1
+; GFX1032GISEL-NEXT: s_and_saveexec_b32 s0, vcc_lo
+; GFX1032GISEL-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX1032GISEL-NEXT: s_cbranch_execz .LBB6_2
; GFX1032GISEL-NEXT: ; %bb.1: ; %else
-; GFX1032GISEL-NEXT: s_load_dword s0, s[4:5], 0x2c
+; GFX1032GISEL-NEXT: s_load_dword s1, s[4:5], 0x2c
; GFX1032GISEL-NEXT: ; implicit-def: $vgpr0
; GFX1032GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1032GISEL-NEXT: s_mov_b32 s0, s0
+; GFX1032GISEL-NEXT: s_mov_b32 s1, s1
; GFX1032GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX1032GISEL-NEXT: s_andn2_saveexec_b32 s1, s1
-; GFX1032GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX1032GISEL-NEXT: s_or_saveexec_b32 s0, s0
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX1032GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s0
+; GFX1032GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX1032GISEL-NEXT: ; %bb.3: ; %if
; GFX1032GISEL-NEXT: s_mov_b32 s2, exec_lo
-; GFX1032GISEL-NEXT: s_brev_b32 s0, 1
+; GFX1032GISEL-NEXT: s_brev_b32 s1, 1
; GFX1032GISEL-NEXT: .LBB6_4: ; =>This Inner Loop Header: Depth=1
; GFX1032GISEL-NEXT: s_ff1_i32_b32 s3, s2
; GFX1032GISEL-NEXT: v_readlane_b32 s6, v0, s3
; GFX1032GISEL-NEXT: s_bitset0_b32 s2, s3
-; GFX1032GISEL-NEXT: s_max_i32 s0, s0, s6
+; GFX1032GISEL-NEXT: s_max_i32 s1, s1, s6
; GFX1032GISEL-NEXT: s_cmp_lg_u32 s2, 0
; GFX1032GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX1032GISEL-NEXT: .LBB6_5: ; %endif
-; GFX1032GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s1
-; GFX1032GISEL-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
-; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1032GISEL-NEXT: ; %bb.5:
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX1032GISEL-NEXT: .LBB6_6: ; %endif
+; GFX1032GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX1032GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX1032GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1032GISEL-NEXT: global_store_dword v1, v0, s[2:3]
+; GFX1032GISEL-NEXT: global_store_dword v0, v1, s[0:1]
; GFX1032GISEL-NEXT: s_endpgm
;
; GFX1164DAGISEL-LABEL: divergent_cfg:
@@ -2450,7 +2462,7 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1164GISEL: ; %bb.0: ; %entry
; GFX1164GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX1164GISEL-NEXT: s_mov_b64 s[0:1], exec
-; GFX1164GISEL-NEXT: ; implicit-def: $sgpr6
+; GFX1164GISEL-NEXT: ; implicit-def: $sgpr2
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164GISEL-NEXT: v_cmpx_le_u32_e32 16, v0
; GFX1164GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
@@ -2459,10 +2471,12 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1164GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
; GFX1164GISEL-NEXT: ; implicit-def: $vgpr0
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-NEXT: s_mov_b32 s6, s2
+; GFX1164GISEL-NEXT: s_mov_b32 s2, s2
; GFX1164GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX1164GISEL-NEXT: s_and_not1_saveexec_b64 s[0:1], s[0:1]
-; GFX1164GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX1164GISEL-NEXT: s_or_saveexec_b64 s[0:1], s[0:1]
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s2
+; GFX1164GISEL-NEXT: s_xor_b64 exec, exec, s[0:1]
+; GFX1164GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX1164GISEL-NEXT: ; %bb.3: ; %if
; GFX1164GISEL-NEXT: s_mov_b64 s[2:3], exec
; GFX1164GISEL-NEXT: s_brev_b32 s6, 1
@@ -2474,13 +2488,14 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1164GISEL-NEXT: s_max_i32 s6, s6, s8
; GFX1164GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX1164GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX1164GISEL-NEXT: .LBB6_5: ; %endif
+; GFX1164GISEL-NEXT: ; %bb.5:
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s6
+; GFX1164GISEL-NEXT: .LBB6_6: ; %endif
; GFX1164GISEL-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1164GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX1164GISEL-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX1164GISEL-NEXT: s_endpgm
;
; GFX1132DAGISEL-LABEL: divergent_cfg:
@@ -2524,37 +2539,41 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1132GISEL-LABEL: divergent_cfg:
; GFX1132GISEL: ; %bb.0: ; %entry
; GFX1132GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX1132GISEL-NEXT: s_mov_b32 s1, exec_lo
-; GFX1132GISEL-NEXT: ; implicit-def: $sgpr0
+; GFX1132GISEL-NEXT: s_mov_b32 s0, exec_lo
+; GFX1132GISEL-NEXT: ; implicit-def: $sgpr1
; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1132GISEL-NEXT: v_cmpx_le_u32_e32 16, v0
-; GFX1132GISEL-NEXT: s_xor_b32 s1, exec_lo, s1
+; GFX1132GISEL-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX1132GISEL-NEXT: s_cbranch_execz .LBB6_2
; GFX1132GISEL-NEXT: ; %bb.1: ; %else
-; GFX1132GISEL-NEXT: s_load_b32 s0, s[4:5], 0x2c
+; GFX1132GISEL-NEXT: s_load_b32 s1, s[4:5], 0x2c
; GFX1132GISEL-NEXT: ; implicit-def: $vgpr0
; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-NEXT: s_mov_b32 s0, s0
+; GFX1132GISEL-NEXT: s_mov_b32 s1, s1
; GFX1132GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX1132GISEL-NEXT: s_and_not1_saveexec_b32 s1, s1
-; GFX1132GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX1132GISEL-NEXT: s_or_saveexec_b32 s0, s0
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX1132GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s0
+; GFX1132GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX1132GISEL-NEXT: ; %bb.3: ; %if
; GFX1132GISEL-NEXT: s_mov_b32 s2, exec_lo
-; GFX1132GISEL-NEXT: s_brev_b32 s0, 1
+; GFX1132GISEL-NEXT: s_brev_b32 s1, 1
; GFX1132GISEL-NEXT: .LBB6_4: ; =>This Inner Loop Header: Depth=1
; GFX1132GISEL-NEXT: s_ctz_i32_b32 s3, s2
; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1132GISEL-NEXT: v_readlane_b32 s6, v0, s3
; GFX1132GISEL-NEXT: s_bitset0_b32 s2, s3
-; GFX1132GISEL-NEXT: s_max_i32 s0, s0, s6
+; GFX1132GISEL-NEXT: s_max_i32 s1, s1, s6
; GFX1132GISEL-NEXT: s_cmp_lg_u32 s2, 0
; GFX1132GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX1132GISEL-NEXT: .LBB6_5: ; %endif
-; GFX1132GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s1
-; GFX1132GISEL-NEXT: s_load_b64 s[2:3], s[4:5], 0x24
-; GFX1132GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, 0
+; GFX1132GISEL-NEXT: ; %bb.5:
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX1132GISEL-NEXT: .LBB6_6: ; %endif
+; GFX1132GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX1132GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-NEXT: global_store_b32 v1, v0, s[2:3]
+; GFX1132GISEL-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX1132GISEL-NEXT: s_endpgm
entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x()
@@ -3015,17 +3034,20 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX8GISEL-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX8GISEL-NEXT: .LBB9_2: ; %Flow
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8GISEL-NEXT: s_andn2_saveexec_b64 s[2:3], s[8:9]
+; GFX8GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[8:9]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s7
+; GFX8GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX8GISEL-NEXT: s_cbranch_execz .LBB9_4
; GFX8GISEL-NEXT: ; %bb.3: ; %if
; GFX8GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8GISEL-NEXT: s_mov_b64 s[6:7], s[4:5]
+; GFX8GISEL-NEXT: s_mov_b64 s[4:5], s[4:5]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX8GISEL-NEXT: .LBB9_4: ; %endif
; GFX8GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s6
; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
-; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX8GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX8GISEL-NEXT: s_endpgm
@@ -3064,16 +3086,19 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX9GISEL-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9GISEL-NEXT: .LBB9_2: ; %Flow
; GFX9GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9GISEL-NEXT: s_andn2_saveexec_b64 s[2:3], s[8:9]
+; GFX9GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[8:9]
+; GFX9GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX9GISEL-NEXT: v_mov_b32_e32 v1, s7
+; GFX9GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX9GISEL-NEXT: s_cbranch_execz .LBB9_4
; GFX9GISEL-NEXT: ; %bb.3: ; %if
; GFX9GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX9GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9GISEL-NEXT: s_mov_b64 s[6:7], s[6:7]
+; GFX9GISEL-NEXT: s_mov_b64 s[4:5], s[6:7]
+; GFX9GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX9GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX9GISEL-NEXT: .LBB9_4: ; %endif
; GFX9GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX9GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX9GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX9GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX9GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX9GISEL-NEXT: s_endpgm
@@ -3113,16 +3138,19 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX1064GISEL-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX1064GISEL-NEXT: .LBB9_2: ; %Flow
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064GISEL-NEXT: s_andn2_saveexec_b64 s[2:3], s[8:9]
+; GFX1064GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[8:9]
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s7
+; GFX1064GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX1064GISEL-NEXT: s_cbranch_execz .LBB9_4
; GFX1064GISEL-NEXT: ; %bb.3: ; %if
; GFX1064GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064GISEL-NEXT: s_mov_b64 s[6:7], s[6:7]
+; GFX1064GISEL-NEXT: s_mov_b64 s[4:5], s[6:7]
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX1064GISEL-NEXT: .LBB9_4: ; %endif
; GFX1064GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX1064GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1064GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX1064GISEL-NEXT: s_endpgm
@@ -3162,16 +3190,19 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX1032GISEL-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX1032GISEL-NEXT: .LBB9_2: ; %Flow
; GFX1032GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1032GISEL-NEXT: s_andn2_saveexec_b32 s2, s8
+; GFX1032GISEL-NEXT: s_or_saveexec_b32 s2, s8
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, s7
+; GFX1032GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s2
; GFX1032GISEL-NEXT: s_cbranch_execz .LBB9_4
; GFX1032GISEL-NEXT: ; %bb.3: ; %if
; GFX1032GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX1032GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1032GISEL-NEXT: s_mov_b64 s[6:7], s[6:7]
+; GFX1032GISEL-NEXT: s_mov_b64 s[4:5], s[6:7]
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX1032GISEL-NEXT: .LBB9_4: ; %endif
; GFX1032GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s2
-; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX1032GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1032GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX1032GISEL-NEXT: s_endpgm
@@ -3215,16 +3246,20 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX1164GISEL-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX1164GISEL-NEXT: .LBB9_2: ; %Flow
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-NEXT: s_and_not1_saveexec_b64 s[2:3], s[8:9]
+; GFX1164GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[8:9]
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s7
+; GFX1164GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX1164GISEL-NEXT: s_cbranch_execz .LBB9_4
; GFX1164GISEL-NEXT: ; %bb.3: ; %if
; GFX1164GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-NEXT: s_mov_b64 s[6:7], s[4:5]
+; GFX1164GISEL-NEXT: s_mov_b64 s[4:5], s[4:5]
+; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX1164GISEL-NEXT: .LBB9_4: ; %endif
; GFX1164GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX1164GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1164GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX1164GISEL-NEXT: s_endpgm
@@ -3266,15 +3301,18 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX1132GISEL-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX1132GISEL-NEXT: .LBB9_2: ; %Flow
; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-NEXT: s_and_not1_saveexec_b32 s2, s8
+; GFX1132GISEL-NEXT: s_or_saveexec_b32 s2, s8
+; GFX1132GISEL-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
+; GFX1132GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s2
; GFX1132GISEL-NEXT: s_cbranch_execz .LBB9_4
; GFX1132GISEL-NEXT: ; %bb.3: ; %if
; GFX1132GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-NEXT: s_mov_b64 s[6:7], s[4:5]
+; GFX1132GISEL-NEXT: s_mov_b64 s[4:5], s[4:5]
+; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1132GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
; GFX1132GISEL-NEXT: .LBB9_4: ; %endif
; GFX1132GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s2
-; GFX1132GISEL-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
; GFX1132GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1132GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX1132GISEL-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
index 23d10af9371b0..85b74fc1320fb 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
@@ -1,16 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=0 < %s | FileCheck -check-prefixes=GFX8DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=1 < %s | FileCheck -check-prefixes=GFX8GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX8GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=0 < %s | FileCheck -check-prefixes=GFX9DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=1 < %s | FileCheck -check-prefixes=GFX9GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX9GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1064DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1064GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1064GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1032DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1032GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1032GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1164DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1164GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1164GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1132DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1132GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1132GISEL %s
define amdgpu_kernel void @uniform_value(ptr addrspace(1) %out, i32 %in) {
; GFX8DAGISEL-LABEL: uniform_value:
@@ -2169,7 +2169,7 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX8GISEL-LABEL: divergent_cfg:
; GFX8GISEL: ; %bb.0: ; %entry
; GFX8GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v0
-; GFX8GISEL-NEXT: ; implicit-def: $sgpr6
+; GFX8GISEL-NEXT: ; implicit-def: $sgpr2
; GFX8GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX8GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
; GFX8GISEL-NEXT: s_cbranch_execz .LBB6_2
@@ -2177,10 +2177,12 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX8GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
; GFX8GISEL-NEXT: ; implicit-def: $vgpr0
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8GISEL-NEXT: s_mov_b32 s6, s2
+; GFX8GISEL-NEXT: s_mov_b32 s2, s2
; GFX8GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX8GISEL-NEXT: s_andn2_saveexec_b64 s[0:1], s[0:1]
-; GFX8GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX8GISEL-NEXT: s_or_saveexec_b64 s[0:1], s[0:1]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s2
+; GFX8GISEL-NEXT: s_xor_b64 exec, exec, s[0:1]
+; GFX8GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX8GISEL-NEXT: ; %bb.3: ; %if
; GFX8GISEL-NEXT: s_mov_b64 s[2:3], exec
; GFX8GISEL-NEXT: s_brev_b32 s6, -2
@@ -2191,14 +2193,15 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX8GISEL-NEXT: s_min_i32 s6, s6, s8
; GFX8GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX8GISEL-NEXT: .LBB6_5: ; %endif
+; GFX8GISEL-NEXT: ; %bb.5:
+; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s6
+; GFX8GISEL-NEXT: .LBB6_6: ; %endif
; GFX8GISEL-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX8GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s6
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s1
-; GFX8GISEL-NEXT: flat_store_dword v[0:1], v2
+; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
+; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
+; GFX8GISEL-NEXT: flat_store_dword v[2:3], v1
; GFX8GISEL-NEXT: s_endpgm
;
; GFX9DAGISEL-LABEL: divergent_cfg:
@@ -2239,7 +2242,7 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX9GISEL-LABEL: divergent_cfg:
; GFX9GISEL: ; %bb.0: ; %entry
; GFX9GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v0
-; GFX9GISEL-NEXT: ; implicit-def: $sgpr6
+; GFX9GISEL-NEXT: ; implicit-def: $sgpr2
; GFX9GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX9GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
; GFX9GISEL-NEXT: s_cbranch_execz .LBB6_2
@@ -2247,10 +2250,12 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX9GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
; GFX9GISEL-NEXT: ; implicit-def: $vgpr0
; GFX9GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9GISEL-NEXT: s_mov_b32 s6, s2
+; GFX9GISEL-NEXT: s_mov_b32 s2, s2
; GFX9GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX9GISEL-NEXT: s_andn2_saveexec_b64 s[0:1], s[0:1]
-; GFX9GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX9GISEL-NEXT: s_or_saveexec_b64 s[0:1], s[0:1]
+; GFX9GISEL-NEXT: v_mov_b32_e32 v1, s2
+; GFX9GISEL-NEXT: s_xor_b64 exec, exec, s[0:1]
+; GFX9GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX9GISEL-NEXT: ; %bb.3: ; %if
; GFX9GISEL-NEXT: s_mov_b64 s[2:3], exec
; GFX9GISEL-NEXT: s_brev_b32 s6, -2
@@ -2261,13 +2266,14 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX9GISEL-NEXT: s_min_i32 s6, s6, s8
; GFX9GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX9GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX9GISEL-NEXT: .LBB6_5: ; %endif
+; GFX9GISEL-NEXT: ; %bb.5:
+; GFX9GISEL-NEXT: v_mov_b32_e32 v1, s6
+; GFX9GISEL-NEXT: .LBB6_6: ; %endif
; GFX9GISEL-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX9GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX9GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX9GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX9GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9GISEL-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX9GISEL-NEXT: global_store_dword v0, v1, s[0:1]
; GFX9GISEL-NEXT: s_endpgm
;
; GFX1064DAGISEL-LABEL: divergent_cfg:
@@ -2308,7 +2314,7 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1064GISEL-LABEL: divergent_cfg:
; GFX1064GISEL: ; %bb.0: ; %entry
; GFX1064GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v0
-; GFX1064GISEL-NEXT: ; implicit-def: $sgpr6
+; GFX1064GISEL-NEXT: ; implicit-def: $sgpr2
; GFX1064GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1064GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
; GFX1064GISEL-NEXT: s_cbranch_execz .LBB6_2
@@ -2316,10 +2322,12 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1064GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
; GFX1064GISEL-NEXT: ; implicit-def: $vgpr0
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064GISEL-NEXT: s_mov_b32 s6, s2
+; GFX1064GISEL-NEXT: s_mov_b32 s2, s2
; GFX1064GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX1064GISEL-NEXT: s_andn2_saveexec_b64 s[0:1], s[0:1]
-; GFX1064GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX1064GISEL-NEXT: s_or_saveexec_b64 s[0:1], s[0:1]
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s2
+; GFX1064GISEL-NEXT: s_xor_b64 exec, exec, s[0:1]
+; GFX1064GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX1064GISEL-NEXT: ; %bb.3: ; %if
; GFX1064GISEL-NEXT: s_mov_b64 s[2:3], exec
; GFX1064GISEL-NEXT: s_brev_b32 s6, -2
@@ -2330,13 +2338,14 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1064GISEL-NEXT: s_min_i32 s6, s6, s8
; GFX1064GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX1064GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX1064GISEL-NEXT: .LBB6_5: ; %endif
+; GFX1064GISEL-NEXT: ; %bb.5:
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s6
+; GFX1064GISEL-NEXT: .LBB6_6: ; %endif
; GFX1064GISEL-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064GISEL-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX1064GISEL-NEXT: global_store_dword v0, v1, s[0:1]
; GFX1064GISEL-NEXT: s_endpgm
;
; GFX1032DAGISEL-LABEL: divergent_cfg:
@@ -2377,35 +2386,38 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1032GISEL-LABEL: divergent_cfg:
; GFX1032GISEL: ; %bb.0: ; %entry
; GFX1032GISEL-NEXT: v_cmp_le_u32_e32 vcc_lo, 16, v0
-; GFX1032GISEL-NEXT: ; implicit-def: $sgpr0
-; GFX1032GISEL-NEXT: s_and_saveexec_b32 s1, vcc_lo
-; GFX1032GISEL-NEXT: s_xor_b32 s1, exec_lo, s1
+; GFX1032GISEL-NEXT: ; implicit-def: $sgpr1
+; GFX1032GISEL-NEXT: s_and_saveexec_b32 s0, vcc_lo
+; GFX1032GISEL-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX1032GISEL-NEXT: s_cbranch_execz .LBB6_2
; GFX1032GISEL-NEXT: ; %bb.1: ; %else
-; GFX1032GISEL-NEXT: s_load_dword s0, s[4:5], 0x2c
+; GFX1032GISEL-NEXT: s_load_dword s1, s[4:5], 0x2c
; GFX1032GISEL-NEXT: ; implicit-def: $vgpr0
; GFX1032GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1032GISEL-NEXT: s_mov_b32 s0, s0
+; GFX1032GISEL-NEXT: s_mov_b32 s1, s1
; GFX1032GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX1032GISEL-NEXT: s_andn2_saveexec_b32 s1, s1
-; GFX1032GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX1032GISEL-NEXT: s_or_saveexec_b32 s0, s0
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX1032GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s0
+; GFX1032GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX1032GISEL-NEXT: ; %bb.3: ; %if
; GFX1032GISEL-NEXT: s_mov_b32 s2, exec_lo
-; GFX1032GISEL-NEXT: s_brev_b32 s0, -2
+; GFX1032GISEL-NEXT: s_brev_b32 s1, -2
; GFX1032GISEL-NEXT: .LBB6_4: ; =>This Inner Loop Header: Depth=1
; GFX1032GISEL-NEXT: s_ff1_i32_b32 s3, s2
; GFX1032GISEL-NEXT: v_readlane_b32 s6, v0, s3
; GFX1032GISEL-NEXT: s_bitset0_b32 s2, s3
-; GFX1032GISEL-NEXT: s_min_i32 s0, s0, s6
+; GFX1032GISEL-NEXT: s_min_i32 s1, s1, s6
; GFX1032GISEL-NEXT: s_cmp_lg_u32 s2, 0
; GFX1032GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX1032GISEL-NEXT: .LBB6_5: ; %endif
-; GFX1032GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s1
-; GFX1032GISEL-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
-; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1032GISEL-NEXT: ; %bb.5:
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX1032GISEL-NEXT: .LBB6_6: ; %endif
+; GFX1032GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX1032GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX1032GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1032GISEL-NEXT: global_store_dword v1, v0, s[2:3]
+; GFX1032GISEL-NEXT: global_store_dword v0, v1, s[0:1]
; GFX1032GISEL-NEXT: s_endpgm
;
; GFX1164DAGISEL-LABEL: divergent_cfg:
@@ -2450,7 +2462,7 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1164GISEL: ; %bb.0: ; %entry
; GFX1164GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX1164GISEL-NEXT: s_mov_b64 s[0:1], exec
-; GFX1164GISEL-NEXT: ; implicit-def: $sgpr6
+; GFX1164GISEL-NEXT: ; implicit-def: $sgpr2
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164GISEL-NEXT: v_cmpx_le_u32_e32 16, v0
; GFX1164GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
@@ -2459,10 +2471,12 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1164GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
; GFX1164GISEL-NEXT: ; implicit-def: $vgpr0
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-NEXT: s_mov_b32 s6, s2
+; GFX1164GISEL-NEXT: s_mov_b32 s2, s2
; GFX1164GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX1164GISEL-NEXT: s_and_not1_saveexec_b64 s[0:1], s[0:1]
-; GFX1164GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX1164GISEL-NEXT: s_or_saveexec_b64 s[0:1], s[0:1]
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s2
+; GFX1164GISEL-NEXT: s_xor_b64 exec, exec, s[0:1]
+; GFX1164GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX1164GISEL-NEXT: ; %bb.3: ; %if
; GFX1164GISEL-NEXT: s_mov_b64 s[2:3], exec
; GFX1164GISEL-NEXT: s_brev_b32 s6, -2
@@ -2474,13 +2488,14 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1164GISEL-NEXT: s_min_i32 s6, s6, s8
; GFX1164GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX1164GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX1164GISEL-NEXT: .LBB6_5: ; %endif
+; GFX1164GISEL-NEXT: ; %bb.5:
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s6
+; GFX1164GISEL-NEXT: .LBB6_6: ; %endif
; GFX1164GISEL-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1164GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX1164GISEL-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX1164GISEL-NEXT: s_endpgm
;
; GFX1132DAGISEL-LABEL: divergent_cfg:
@@ -2524,37 +2539,41 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1132GISEL-LABEL: divergent_cfg:
; GFX1132GISEL: ; %bb.0: ; %entry
; GFX1132GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX1132GISEL-NEXT: s_mov_b32 s1, exec_lo
-; GFX1132GISEL-NEXT: ; implicit-def: $sgpr0
+; GFX1132GISEL-NEXT: s_mov_b32 s0, exec_lo
+; GFX1132GISEL-NEXT: ; implicit-def: $sgpr1
; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1132GISEL-NEXT: v_cmpx_le_u32_e32 16, v0
-; GFX1132GISEL-NEXT: s_xor_b32 s1, exec_lo, s1
+; GFX1132GISEL-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX1132GISEL-NEXT: s_cbranch_execz .LBB6_2
; GFX1132GISEL-NEXT: ; %bb.1: ; %else
-; GFX1132GISEL-NEXT: s_load_b32 s0, s[4:5], 0x2c
+; GFX1132GISEL-NEXT: s_load_b32 s1, s[4:5], 0x2c
; GFX1132GISEL-NEXT: ; implicit-def: $vgpr0
; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-NEXT: s_mov_b32 s0, s0
+; GFX1132GISEL-NEXT: s_mov_b32 s1, s1
; GFX1132GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX1132GISEL-NEXT: s_and_not1_saveexec_b32 s1, s1
-; GFX1132GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX1132GISEL-NEXT: s_or_saveexec_b32 s0, s0
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX1132GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s0
+; GFX1132GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX1132GISEL-NEXT: ; %bb.3: ; %if
; GFX1132GISEL-NEXT: s_mov_b32 s2, exec_lo
-; GFX1132GISEL-NEXT: s_brev_b32 s0, -2
+; GFX1132GISEL-NEXT: s_brev_b32 s1, -2
; GFX1132GISEL-NEXT: .LBB6_4: ; =>This Inner Loop Header: Depth=1
; GFX1132GISEL-NEXT: s_ctz_i32_b32 s3, s2
; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1132GISEL-NEXT: v_readlane_b32 s6, v0, s3
; GFX1132GISEL-NEXT: s_bitset0_b32 s2, s3
-; GFX1132GISEL-NEXT: s_min_i32 s0, s0, s6
+; GFX1132GISEL-NEXT: s_min_i32 s1, s1, s6
; GFX1132GISEL-NEXT: s_cmp_lg_u32 s2, 0
; GFX1132GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX1132GISEL-NEXT: .LBB6_5: ; %endif
-; GFX1132GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s1
-; GFX1132GISEL-NEXT: s_load_b64 s[2:3], s[4:5], 0x24
-; GFX1132GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, 0
+; GFX1132GISEL-NEXT: ; %bb.5:
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX1132GISEL-NEXT: .LBB6_6: ; %endif
+; GFX1132GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX1132GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-NEXT: global_store_b32 v1, v0, s[2:3]
+; GFX1132GISEL-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX1132GISEL-NEXT: s_endpgm
entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x()
@@ -3015,17 +3034,20 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX8GISEL-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX8GISEL-NEXT: .LBB9_2: ; %Flow
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8GISEL-NEXT: s_andn2_saveexec_b64 s[2:3], s[8:9]
+; GFX8GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[8:9]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s7
+; GFX8GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX8GISEL-NEXT: s_cbranch_execz .LBB9_4
; GFX8GISEL-NEXT: ; %bb.3: ; %if
; GFX8GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8GISEL-NEXT: s_mov_b64 s[6:7], s[4:5]
+; GFX8GISEL-NEXT: s_mov_b64 s[4:5], s[4:5]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX8GISEL-NEXT: .LBB9_4: ; %endif
; GFX8GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s6
; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
-; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX8GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX8GISEL-NEXT: s_endpgm
@@ -3064,16 +3086,19 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX9GISEL-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9GISEL-NEXT: .LBB9_2: ; %Flow
; GFX9GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9GISEL-NEXT: s_andn2_saveexec_b64 s[2:3], s[8:9]
+; GFX9GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[8:9]
+; GFX9GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX9GISEL-NEXT: v_mov_b32_e32 v1, s7
+; GFX9GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX9GISEL-NEXT: s_cbranch_execz .LBB9_4
; GFX9GISEL-NEXT: ; %bb.3: ; %if
; GFX9GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX9GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9GISEL-NEXT: s_mov_b64 s[6:7], s[6:7]
+; GFX9GISEL-NEXT: s_mov_b64 s[4:5], s[6:7]
+; GFX9GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX9GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX9GISEL-NEXT: .LBB9_4: ; %endif
; GFX9GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX9GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX9GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX9GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX9GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX9GISEL-NEXT: s_endpgm
@@ -3113,16 +3138,19 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX1064GISEL-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX1064GISEL-NEXT: .LBB9_2: ; %Flow
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064GISEL-NEXT: s_andn2_saveexec_b64 s[2:3], s[8:9]
+; GFX1064GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[8:9]
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s7
+; GFX1064GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX1064GISEL-NEXT: s_cbranch_execz .LBB9_4
; GFX1064GISEL-NEXT: ; %bb.3: ; %if
; GFX1064GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064GISEL-NEXT: s_mov_b64 s[6:7], s[6:7]
+; GFX1064GISEL-NEXT: s_mov_b64 s[4:5], s[6:7]
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX1064GISEL-NEXT: .LBB9_4: ; %endif
; GFX1064GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX1064GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1064GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX1064GISEL-NEXT: s_endpgm
@@ -3162,16 +3190,19 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX1032GISEL-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX1032GISEL-NEXT: .LBB9_2: ; %Flow
; GFX1032GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1032GISEL-NEXT: s_andn2_saveexec_b32 s2, s8
+; GFX1032GISEL-NEXT: s_or_saveexec_b32 s2, s8
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, s7
+; GFX1032GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s2
; GFX1032GISEL-NEXT: s_cbranch_execz .LBB9_4
; GFX1032GISEL-NEXT: ; %bb.3: ; %if
; GFX1032GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX1032GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1032GISEL-NEXT: s_mov_b64 s[6:7], s[6:7]
+; GFX1032GISEL-NEXT: s_mov_b64 s[4:5], s[6:7]
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX1032GISEL-NEXT: .LBB9_4: ; %endif
; GFX1032GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s2
-; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX1032GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1032GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX1032GISEL-NEXT: s_endpgm
@@ -3215,16 +3246,20 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX1164GISEL-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX1164GISEL-NEXT: .LBB9_2: ; %Flow
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-NEXT: s_and_not1_saveexec_b64 s[2:3], s[8:9]
+; GFX1164GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[8:9]
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s7
+; GFX1164GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX1164GISEL-NEXT: s_cbranch_execz .LBB9_4
; GFX1164GISEL-NEXT: ; %bb.3: ; %if
; GFX1164GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-NEXT: s_mov_b64 s[6:7], s[4:5]
+; GFX1164GISEL-NEXT: s_mov_b64 s[4:5], s[4:5]
+; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX1164GISEL-NEXT: .LBB9_4: ; %endif
; GFX1164GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX1164GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1164GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX1164GISEL-NEXT: s_endpgm
@@ -3266,15 +3301,18 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX1132GISEL-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX1132GISEL-NEXT: .LBB9_2: ; %Flow
; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-NEXT: s_and_not1_saveexec_b32 s2, s8
+; GFX1132GISEL-NEXT: s_or_saveexec_b32 s2, s8
+; GFX1132GISEL-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
+; GFX1132GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s2
; GFX1132GISEL-NEXT: s_cbranch_execz .LBB9_4
; GFX1132GISEL-NEXT: ; %bb.3: ; %if
; GFX1132GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-NEXT: s_mov_b64 s[6:7], s[4:5]
+; GFX1132GISEL-NEXT: s_mov_b64 s[4:5], s[4:5]
+; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1132GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
; GFX1132GISEL-NEXT: .LBB9_4: ; %endif
; GFX1132GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s2
-; GFX1132GISEL-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
; GFX1132GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1132GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX1132GISEL-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
index f3b28281c4633..eee9c3785176b 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
@@ -1,16 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=0 < %s | FileCheck -check-prefixes=GFX8DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=1 < %s | FileCheck -check-prefixes=GFX8GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX8GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=0 < %s | FileCheck -check-prefixes=GFX9DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=1 < %s | FileCheck -check-prefixes=GFX9GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX9GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1064DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1064GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1064GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1032DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1032GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1032GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1164DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1164GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1164GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1132DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1132GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1132GISEL %s
define amdgpu_kernel void @uniform_value(ptr addrspace(1) %out, i32 %in) {
; GFX8DAGISEL-LABEL: uniform_value:
@@ -2037,7 +2037,7 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX8GISEL-LABEL: divergent_cfg:
; GFX8GISEL: ; %bb.0: ; %entry
; GFX8GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v0
-; GFX8GISEL-NEXT: ; implicit-def: $sgpr6
+; GFX8GISEL-NEXT: ; implicit-def: $sgpr2
; GFX8GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX8GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
; GFX8GISEL-NEXT: s_cbranch_execz .LBB6_2
@@ -2045,10 +2045,12 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX8GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
; GFX8GISEL-NEXT: ; implicit-def: $vgpr0
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8GISEL-NEXT: s_mov_b32 s6, s2
+; GFX8GISEL-NEXT: s_mov_b32 s2, s2
; GFX8GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX8GISEL-NEXT: s_andn2_saveexec_b64 s[0:1], s[0:1]
-; GFX8GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX8GISEL-NEXT: s_or_saveexec_b64 s[0:1], s[0:1]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s2
+; GFX8GISEL-NEXT: s_xor_b64 exec, exec, s[0:1]
+; GFX8GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX8GISEL-NEXT: ; %bb.3: ; %if
; GFX8GISEL-NEXT: s_mov_b64 s[2:3], exec
; GFX8GISEL-NEXT: s_mov_b32 s6, 0
@@ -2059,14 +2061,15 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX8GISEL-NEXT: s_or_b32 s6, s6, s8
; GFX8GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX8GISEL-NEXT: .LBB6_5: ; %endif
+; GFX8GISEL-NEXT: ; %bb.5:
+; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s6
+; GFX8GISEL-NEXT: .LBB6_6: ; %endif
; GFX8GISEL-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX8GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s6
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s1
-; GFX8GISEL-NEXT: flat_store_dword v[0:1], v2
+; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
+; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
+; GFX8GISEL-NEXT: flat_store_dword v[2:3], v1
; GFX8GISEL-NEXT: s_endpgm
;
; GFX9DAGISEL-LABEL: divergent_cfg:
@@ -2107,7 +2110,7 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX9GISEL-LABEL: divergent_cfg:
; GFX9GISEL: ; %bb.0: ; %entry
; GFX9GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v0
-; GFX9GISEL-NEXT: ; implicit-def: $sgpr6
+; GFX9GISEL-NEXT: ; implicit-def: $sgpr2
; GFX9GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX9GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
; GFX9GISEL-NEXT: s_cbranch_execz .LBB6_2
@@ -2115,10 +2118,12 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX9GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
; GFX9GISEL-NEXT: ; implicit-def: $vgpr0
; GFX9GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9GISEL-NEXT: s_mov_b32 s6, s2
+; GFX9GISEL-NEXT: s_mov_b32 s2, s2
; GFX9GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX9GISEL-NEXT: s_andn2_saveexec_b64 s[0:1], s[0:1]
-; GFX9GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX9GISEL-NEXT: s_or_saveexec_b64 s[0:1], s[0:1]
+; GFX9GISEL-NEXT: v_mov_b32_e32 v1, s2
+; GFX9GISEL-NEXT: s_xor_b64 exec, exec, s[0:1]
+; GFX9GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX9GISEL-NEXT: ; %bb.3: ; %if
; GFX9GISEL-NEXT: s_mov_b64 s[2:3], exec
; GFX9GISEL-NEXT: s_mov_b32 s6, 0
@@ -2129,13 +2134,14 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX9GISEL-NEXT: s_or_b32 s6, s6, s8
; GFX9GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX9GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX9GISEL-NEXT: .LBB6_5: ; %endif
+; GFX9GISEL-NEXT: ; %bb.5:
+; GFX9GISEL-NEXT: v_mov_b32_e32 v1, s6
+; GFX9GISEL-NEXT: .LBB6_6: ; %endif
; GFX9GISEL-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX9GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX9GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX9GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX9GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9GISEL-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX9GISEL-NEXT: global_store_dword v0, v1, s[0:1]
; GFX9GISEL-NEXT: s_endpgm
;
; GFX1064DAGISEL-LABEL: divergent_cfg:
@@ -2176,7 +2182,7 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1064GISEL-LABEL: divergent_cfg:
; GFX1064GISEL: ; %bb.0: ; %entry
; GFX1064GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v0
-; GFX1064GISEL-NEXT: ; implicit-def: $sgpr6
+; GFX1064GISEL-NEXT: ; implicit-def: $sgpr2
; GFX1064GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1064GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
; GFX1064GISEL-NEXT: s_cbranch_execz .LBB6_2
@@ -2184,10 +2190,12 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1064GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
; GFX1064GISEL-NEXT: ; implicit-def: $vgpr0
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064GISEL-NEXT: s_mov_b32 s6, s2
+; GFX1064GISEL-NEXT: s_mov_b32 s2, s2
; GFX1064GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX1064GISEL-NEXT: s_andn2_saveexec_b64 s[0:1], s[0:1]
-; GFX1064GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX1064GISEL-NEXT: s_or_saveexec_b64 s[0:1], s[0:1]
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s2
+; GFX1064GISEL-NEXT: s_xor_b64 exec, exec, s[0:1]
+; GFX1064GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX1064GISEL-NEXT: ; %bb.3: ; %if
; GFX1064GISEL-NEXT: s_mov_b64 s[2:3], exec
; GFX1064GISEL-NEXT: s_mov_b32 s6, 0
@@ -2198,13 +2206,14 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1064GISEL-NEXT: s_or_b32 s6, s6, s8
; GFX1064GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX1064GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX1064GISEL-NEXT: .LBB6_5: ; %endif
+; GFX1064GISEL-NEXT: ; %bb.5:
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s6
+; GFX1064GISEL-NEXT: .LBB6_6: ; %endif
; GFX1064GISEL-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064GISEL-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX1064GISEL-NEXT: global_store_dword v0, v1, s[0:1]
; GFX1064GISEL-NEXT: s_endpgm
;
; GFX1032DAGISEL-LABEL: divergent_cfg:
@@ -2245,35 +2254,38 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1032GISEL-LABEL: divergent_cfg:
; GFX1032GISEL: ; %bb.0: ; %entry
; GFX1032GISEL-NEXT: v_cmp_le_u32_e32 vcc_lo, 16, v0
-; GFX1032GISEL-NEXT: ; implicit-def: $sgpr0
-; GFX1032GISEL-NEXT: s_and_saveexec_b32 s1, vcc_lo
-; GFX1032GISEL-NEXT: s_xor_b32 s1, exec_lo, s1
+; GFX1032GISEL-NEXT: ; implicit-def: $sgpr1
+; GFX1032GISEL-NEXT: s_and_saveexec_b32 s0, vcc_lo
+; GFX1032GISEL-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX1032GISEL-NEXT: s_cbranch_execz .LBB6_2
; GFX1032GISEL-NEXT: ; %bb.1: ; %else
-; GFX1032GISEL-NEXT: s_load_dword s0, s[4:5], 0x2c
+; GFX1032GISEL-NEXT: s_load_dword s1, s[4:5], 0x2c
; GFX1032GISEL-NEXT: ; implicit-def: $vgpr0
; GFX1032GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1032GISEL-NEXT: s_mov_b32 s0, s0
+; GFX1032GISEL-NEXT: s_mov_b32 s1, s1
; GFX1032GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX1032GISEL-NEXT: s_andn2_saveexec_b32 s1, s1
-; GFX1032GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX1032GISEL-NEXT: s_or_saveexec_b32 s0, s0
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX1032GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s0
+; GFX1032GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX1032GISEL-NEXT: ; %bb.3: ; %if
; GFX1032GISEL-NEXT: s_mov_b32 s2, exec_lo
-; GFX1032GISEL-NEXT: s_mov_b32 s0, 0
+; GFX1032GISEL-NEXT: s_mov_b32 s1, 0
; GFX1032GISEL-NEXT: .LBB6_4: ; =>This Inner Loop Header: Depth=1
; GFX1032GISEL-NEXT: s_ff1_i32_b32 s3, s2
; GFX1032GISEL-NEXT: v_readlane_b32 s6, v0, s3
; GFX1032GISEL-NEXT: s_bitset0_b32 s2, s3
-; GFX1032GISEL-NEXT: s_or_b32 s0, s0, s6
+; GFX1032GISEL-NEXT: s_or_b32 s1, s1, s6
; GFX1032GISEL-NEXT: s_cmp_lg_u32 s2, 0
; GFX1032GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX1032GISEL-NEXT: .LBB6_5: ; %endif
-; GFX1032GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s1
-; GFX1032GISEL-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
-; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1032GISEL-NEXT: ; %bb.5:
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX1032GISEL-NEXT: .LBB6_6: ; %endif
+; GFX1032GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX1032GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX1032GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1032GISEL-NEXT: global_store_dword v1, v0, s[2:3]
+; GFX1032GISEL-NEXT: global_store_dword v0, v1, s[0:1]
; GFX1032GISEL-NEXT: s_endpgm
;
; GFX1164DAGISEL-LABEL: divergent_cfg:
@@ -2318,7 +2330,7 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1164GISEL: ; %bb.0: ; %entry
; GFX1164GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX1164GISEL-NEXT: s_mov_b64 s[0:1], exec
-; GFX1164GISEL-NEXT: ; implicit-def: $sgpr6
+; GFX1164GISEL-NEXT: ; implicit-def: $sgpr2
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164GISEL-NEXT: v_cmpx_le_u32_e32 16, v0
; GFX1164GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
@@ -2327,10 +2339,12 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1164GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
; GFX1164GISEL-NEXT: ; implicit-def: $vgpr0
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-NEXT: s_mov_b32 s6, s2
+; GFX1164GISEL-NEXT: s_mov_b32 s2, s2
; GFX1164GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX1164GISEL-NEXT: s_and_not1_saveexec_b64 s[0:1], s[0:1]
-; GFX1164GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX1164GISEL-NEXT: s_or_saveexec_b64 s[0:1], s[0:1]
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s2
+; GFX1164GISEL-NEXT: s_xor_b64 exec, exec, s[0:1]
+; GFX1164GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX1164GISEL-NEXT: ; %bb.3: ; %if
; GFX1164GISEL-NEXT: s_mov_b64 s[2:3], exec
; GFX1164GISEL-NEXT: s_mov_b32 s6, 0
@@ -2342,13 +2356,14 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1164GISEL-NEXT: s_or_b32 s6, s6, s8
; GFX1164GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX1164GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX1164GISEL-NEXT: .LBB6_5: ; %endif
+; GFX1164GISEL-NEXT: ; %bb.5:
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s6
+; GFX1164GISEL-NEXT: .LBB6_6: ; %endif
; GFX1164GISEL-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1164GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX1164GISEL-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX1164GISEL-NEXT: s_endpgm
;
; GFX1132DAGISEL-LABEL: divergent_cfg:
@@ -2392,37 +2407,41 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1132GISEL-LABEL: divergent_cfg:
; GFX1132GISEL: ; %bb.0: ; %entry
; GFX1132GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX1132GISEL-NEXT: s_mov_b32 s1, exec_lo
-; GFX1132GISEL-NEXT: ; implicit-def: $sgpr0
+; GFX1132GISEL-NEXT: s_mov_b32 s0, exec_lo
+; GFX1132GISEL-NEXT: ; implicit-def: $sgpr1
; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1132GISEL-NEXT: v_cmpx_le_u32_e32 16, v0
-; GFX1132GISEL-NEXT: s_xor_b32 s1, exec_lo, s1
+; GFX1132GISEL-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX1132GISEL-NEXT: s_cbranch_execz .LBB6_2
; GFX1132GISEL-NEXT: ; %bb.1: ; %else
-; GFX1132GISEL-NEXT: s_load_b32 s0, s[4:5], 0x2c
+; GFX1132GISEL-NEXT: s_load_b32 s1, s[4:5], 0x2c
; GFX1132GISEL-NEXT: ; implicit-def: $vgpr0
; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-NEXT: s_mov_b32 s0, s0
+; GFX1132GISEL-NEXT: s_mov_b32 s1, s1
; GFX1132GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX1132GISEL-NEXT: s_and_not1_saveexec_b32 s1, s1
-; GFX1132GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX1132GISEL-NEXT: s_or_saveexec_b32 s0, s0
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX1132GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s0
+; GFX1132GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX1132GISEL-NEXT: ; %bb.3: ; %if
; GFX1132GISEL-NEXT: s_mov_b32 s2, exec_lo
-; GFX1132GISEL-NEXT: s_mov_b32 s0, 0
+; GFX1132GISEL-NEXT: s_mov_b32 s1, 0
; GFX1132GISEL-NEXT: .LBB6_4: ; =>This Inner Loop Header: Depth=1
; GFX1132GISEL-NEXT: s_ctz_i32_b32 s3, s2
; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1132GISEL-NEXT: v_readlane_b32 s6, v0, s3
; GFX1132GISEL-NEXT: s_bitset0_b32 s2, s3
-; GFX1132GISEL-NEXT: s_or_b32 s0, s0, s6
+; GFX1132GISEL-NEXT: s_or_b32 s1, s1, s6
; GFX1132GISEL-NEXT: s_cmp_lg_u32 s2, 0
; GFX1132GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX1132GISEL-NEXT: .LBB6_5: ; %endif
-; GFX1132GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s1
-; GFX1132GISEL-NEXT: s_load_b64 s[2:3], s[4:5], 0x24
-; GFX1132GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, 0
+; GFX1132GISEL-NEXT: ; %bb.5:
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX1132GISEL-NEXT: .LBB6_6: ; %endif
+; GFX1132GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX1132GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-NEXT: global_store_b32 v1, v0, s[2:3]
+; GFX1132GISEL-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX1132GISEL-NEXT: s_endpgm
entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x()
@@ -2826,17 +2845,20 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX8GISEL-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX8GISEL-NEXT: .LBB9_2: ; %Flow
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8GISEL-NEXT: s_andn2_saveexec_b64 s[2:3], s[8:9]
+; GFX8GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[8:9]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s7
+; GFX8GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX8GISEL-NEXT: s_cbranch_execz .LBB9_4
; GFX8GISEL-NEXT: ; %bb.3: ; %if
; GFX8GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8GISEL-NEXT: s_mov_b64 s[6:7], s[4:5]
+; GFX8GISEL-NEXT: s_mov_b64 s[4:5], s[4:5]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX8GISEL-NEXT: .LBB9_4: ; %endif
; GFX8GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s6
; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
-; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX8GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX8GISEL-NEXT: s_endpgm
@@ -2875,16 +2897,19 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX9GISEL-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX9GISEL-NEXT: .LBB9_2: ; %Flow
; GFX9GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9GISEL-NEXT: s_andn2_saveexec_b64 s[2:3], s[8:9]
+; GFX9GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[8:9]
+; GFX9GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX9GISEL-NEXT: v_mov_b32_e32 v1, s7
+; GFX9GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX9GISEL-NEXT: s_cbranch_execz .LBB9_4
; GFX9GISEL-NEXT: ; %bb.3: ; %if
; GFX9GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX9GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9GISEL-NEXT: s_mov_b64 s[6:7], s[6:7]
+; GFX9GISEL-NEXT: s_mov_b64 s[4:5], s[6:7]
+; GFX9GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX9GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX9GISEL-NEXT: .LBB9_4: ; %endif
; GFX9GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX9GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX9GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX9GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX9GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX9GISEL-NEXT: s_endpgm
@@ -2924,16 +2949,19 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX1064GISEL-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX1064GISEL-NEXT: .LBB9_2: ; %Flow
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064GISEL-NEXT: s_andn2_saveexec_b64 s[2:3], s[8:9]
+; GFX1064GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[8:9]
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s7
+; GFX1064GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX1064GISEL-NEXT: s_cbranch_execz .LBB9_4
; GFX1064GISEL-NEXT: ; %bb.3: ; %if
; GFX1064GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064GISEL-NEXT: s_mov_b64 s[6:7], s[6:7]
+; GFX1064GISEL-NEXT: s_mov_b64 s[4:5], s[6:7]
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX1064GISEL-NEXT: .LBB9_4: ; %endif
; GFX1064GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX1064GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1064GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX1064GISEL-NEXT: s_endpgm
@@ -2973,16 +3001,19 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX1032GISEL-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX1032GISEL-NEXT: .LBB9_2: ; %Flow
; GFX1032GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1032GISEL-NEXT: s_andn2_saveexec_b32 s2, s8
+; GFX1032GISEL-NEXT: s_or_saveexec_b32 s2, s8
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, s7
+; GFX1032GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s2
; GFX1032GISEL-NEXT: s_cbranch_execz .LBB9_4
; GFX1032GISEL-NEXT: ; %bb.3: ; %if
; GFX1032GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX1032GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1032GISEL-NEXT: s_mov_b64 s[6:7], s[6:7]
+; GFX1032GISEL-NEXT: s_mov_b64 s[4:5], s[6:7]
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX1032GISEL-NEXT: .LBB9_4: ; %endif
; GFX1032GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s2
-; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX1032GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1032GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX1032GISEL-NEXT: s_endpgm
@@ -3026,16 +3057,20 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX1164GISEL-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX1164GISEL-NEXT: .LBB9_2: ; %Flow
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-NEXT: s_and_not1_saveexec_b64 s[2:3], s[8:9]
+; GFX1164GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[8:9]
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s7
+; GFX1164GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX1164GISEL-NEXT: s_cbranch_execz .LBB9_4
; GFX1164GISEL-NEXT: ; %bb.3: ; %if
; GFX1164GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-NEXT: s_mov_b64 s[6:7], s[4:5]
+; GFX1164GISEL-NEXT: s_mov_b64 s[4:5], s[4:5]
+; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX1164GISEL-NEXT: .LBB9_4: ; %endif
; GFX1164GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX1164GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1164GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX1164GISEL-NEXT: s_endpgm
@@ -3077,15 +3112,18 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX1132GISEL-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX1132GISEL-NEXT: .LBB9_2: ; %Flow
; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-NEXT: s_and_not1_saveexec_b32 s2, s8
+; GFX1132GISEL-NEXT: s_or_saveexec_b32 s2, s8
+; GFX1132GISEL-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
+; GFX1132GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s2
; GFX1132GISEL-NEXT: s_cbranch_execz .LBB9_4
; GFX1132GISEL-NEXT: ; %bb.3: ; %if
; GFX1132GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-NEXT: s_mov_b64 s[6:7], s[4:5]
+; GFX1132GISEL-NEXT: s_mov_b64 s[4:5], s[4:5]
+; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1132GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
; GFX1132GISEL-NEXT: .LBB9_4: ; %endif
; GFX1132GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s2
-; GFX1132GISEL-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
; GFX1132GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1132GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX1132GISEL-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
index 4d83751d4454d..302d6bc3bfad4 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
@@ -1,16 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=0 < %s | FileCheck -check-prefixes=GFX8DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=1 < %s | FileCheck -check-prefixes=GFX8GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX8GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=0 < %s | FileCheck -check-prefixes=GFX9DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=1 < %s | FileCheck -check-prefixes=GFX9GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX9GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1064DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1064GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1064GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1032DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1032GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1032GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1164DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1164GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1164GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1132DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1132GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1132GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -global-isel=0 < %s | FileCheck -check-prefixes=GFX12DAGISEL %s
define amdgpu_kernel void @uniform_value(ptr addrspace(1) %out, i32 %in) {
@@ -2440,7 +2440,7 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX8GISEL-LABEL: divergent_cfg:
; GFX8GISEL: ; %bb.0: ; %entry
; GFX8GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v0
-; GFX8GISEL-NEXT: ; implicit-def: $sgpr6
+; GFX8GISEL-NEXT: ; implicit-def: $sgpr2
; GFX8GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX8GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
; GFX8GISEL-NEXT: s_cbranch_execz .LBB6_2
@@ -2451,10 +2451,12 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX8GISEL-NEXT: ; implicit-def: $vgpr0
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX8GISEL-NEXT: s_sub_i32 s3, 0, s6
-; GFX8GISEL-NEXT: s_mul_i32 s6, s3, s2
+; GFX8GISEL-NEXT: s_mul_i32 s2, s3, s2
; GFX8GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX8GISEL-NEXT: s_andn2_saveexec_b64 s[0:1], s[0:1]
-; GFX8GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX8GISEL-NEXT: s_or_saveexec_b64 s[0:1], s[0:1]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s2
+; GFX8GISEL-NEXT: s_xor_b64 exec, exec, s[0:1]
+; GFX8GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX8GISEL-NEXT: ; %bb.3: ; %if
; GFX8GISEL-NEXT: s_mov_b64 s[2:3], exec
; GFX8GISEL-NEXT: s_mov_b32 s6, 0
@@ -2465,14 +2467,15 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX8GISEL-NEXT: s_sub_i32 s6, s6, s8
; GFX8GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX8GISEL-NEXT: .LBB6_5: ; %endif
+; GFX8GISEL-NEXT: ; %bb.5:
+; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s6
+; GFX8GISEL-NEXT: .LBB6_6: ; %endif
; GFX8GISEL-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX8GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s6
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s1
-; GFX8GISEL-NEXT: flat_store_dword v[0:1], v2
+; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
+; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
+; GFX8GISEL-NEXT: flat_store_dword v[2:3], v1
; GFX8GISEL-NEXT: s_endpgm
;
; GFX9DAGISEL-LABEL: divergent_cfg:
@@ -2518,7 +2521,7 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX9GISEL-LABEL: divergent_cfg:
; GFX9GISEL: ; %bb.0: ; %entry
; GFX9GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v0
-; GFX9GISEL-NEXT: ; implicit-def: $sgpr6
+; GFX9GISEL-NEXT: ; implicit-def: $sgpr2
; GFX9GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX9GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
; GFX9GISEL-NEXT: s_cbranch_execz .LBB6_2
@@ -2529,10 +2532,12 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX9GISEL-NEXT: ; implicit-def: $vgpr0
; GFX9GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9GISEL-NEXT: s_sub_i32 s3, 0, s6
-; GFX9GISEL-NEXT: s_mul_i32 s6, s3, s2
+; GFX9GISEL-NEXT: s_mul_i32 s2, s3, s2
; GFX9GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX9GISEL-NEXT: s_andn2_saveexec_b64 s[0:1], s[0:1]
-; GFX9GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX9GISEL-NEXT: s_or_saveexec_b64 s[0:1], s[0:1]
+; GFX9GISEL-NEXT: v_mov_b32_e32 v1, s2
+; GFX9GISEL-NEXT: s_xor_b64 exec, exec, s[0:1]
+; GFX9GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX9GISEL-NEXT: ; %bb.3: ; %if
; GFX9GISEL-NEXT: s_mov_b64 s[2:3], exec
; GFX9GISEL-NEXT: s_mov_b32 s6, 0
@@ -2543,13 +2548,14 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX9GISEL-NEXT: s_sub_i32 s6, s6, s8
; GFX9GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX9GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX9GISEL-NEXT: .LBB6_5: ; %endif
+; GFX9GISEL-NEXT: ; %bb.5:
+; GFX9GISEL-NEXT: v_mov_b32_e32 v1, s6
+; GFX9GISEL-NEXT: .LBB6_6: ; %endif
; GFX9GISEL-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX9GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX9GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX9GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX9GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9GISEL-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX9GISEL-NEXT: global_store_dword v0, v1, s[0:1]
; GFX9GISEL-NEXT: s_endpgm
;
; GFX1064DAGISEL-LABEL: divergent_cfg:
@@ -2595,7 +2601,7 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1064GISEL-LABEL: divergent_cfg:
; GFX1064GISEL: ; %bb.0: ; %entry
; GFX1064GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v0
-; GFX1064GISEL-NEXT: ; implicit-def: $sgpr6
+; GFX1064GISEL-NEXT: ; implicit-def: $sgpr2
; GFX1064GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1064GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
; GFX1064GISEL-NEXT: s_cbranch_execz .LBB6_2
@@ -2606,10 +2612,12 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1064GISEL-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1064GISEL-NEXT: s_sub_i32 s3, 0, s6
-; GFX1064GISEL-NEXT: s_mul_i32 s6, s3, s2
+; GFX1064GISEL-NEXT: s_mul_i32 s2, s3, s2
; GFX1064GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX1064GISEL-NEXT: s_andn2_saveexec_b64 s[0:1], s[0:1]
-; GFX1064GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX1064GISEL-NEXT: s_or_saveexec_b64 s[0:1], s[0:1]
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s2
+; GFX1064GISEL-NEXT: s_xor_b64 exec, exec, s[0:1]
+; GFX1064GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX1064GISEL-NEXT: ; %bb.3: ; %if
; GFX1064GISEL-NEXT: s_mov_b64 s[2:3], exec
; GFX1064GISEL-NEXT: s_mov_b32 s6, 0
@@ -2620,13 +2628,14 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1064GISEL-NEXT: s_sub_i32 s6, s6, s8
; GFX1064GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX1064GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX1064GISEL-NEXT: .LBB6_5: ; %endif
+; GFX1064GISEL-NEXT: ; %bb.5:
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s6
+; GFX1064GISEL-NEXT: .LBB6_6: ; %endif
; GFX1064GISEL-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064GISEL-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX1064GISEL-NEXT: global_store_dword v0, v1, s[0:1]
; GFX1064GISEL-NEXT: s_endpgm
;
; GFX1032DAGISEL-LABEL: divergent_cfg:
@@ -2672,38 +2681,41 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1032GISEL-LABEL: divergent_cfg:
; GFX1032GISEL: ; %bb.0: ; %entry
; GFX1032GISEL-NEXT: v_cmp_le_u32_e32 vcc_lo, 16, v0
-; GFX1032GISEL-NEXT: ; implicit-def: $sgpr0
-; GFX1032GISEL-NEXT: s_and_saveexec_b32 s1, vcc_lo
-; GFX1032GISEL-NEXT: s_xor_b32 s1, exec_lo, s1
+; GFX1032GISEL-NEXT: ; implicit-def: $sgpr1
+; GFX1032GISEL-NEXT: s_and_saveexec_b32 s0, vcc_lo
+; GFX1032GISEL-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX1032GISEL-NEXT: s_cbranch_execz .LBB6_2
; GFX1032GISEL-NEXT: ; %bb.1: ; %else
-; GFX1032GISEL-NEXT: s_load_dword s0, s[4:5], 0x2c
+; GFX1032GISEL-NEXT: s_load_dword s1, s[4:5], 0x2c
; GFX1032GISEL-NEXT: s_mov_b32 s2, exec_lo
; GFX1032GISEL-NEXT: ; implicit-def: $vgpr0
; GFX1032GISEL-NEXT: s_bcnt1_i32_b32 s2, s2
; GFX1032GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1032GISEL-NEXT: s_sub_i32 s0, 0, s0
-; GFX1032GISEL-NEXT: s_mul_i32 s0, s0, s2
+; GFX1032GISEL-NEXT: s_sub_i32 s1, 0, s1
+; GFX1032GISEL-NEXT: s_mul_i32 s1, s1, s2
; GFX1032GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX1032GISEL-NEXT: s_andn2_saveexec_b32 s1, s1
-; GFX1032GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX1032GISEL-NEXT: s_or_saveexec_b32 s0, s0
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX1032GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s0
+; GFX1032GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX1032GISEL-NEXT: ; %bb.3: ; %if
; GFX1032GISEL-NEXT: s_mov_b32 s2, exec_lo
-; GFX1032GISEL-NEXT: s_mov_b32 s0, 0
+; GFX1032GISEL-NEXT: s_mov_b32 s1, 0
; GFX1032GISEL-NEXT: .LBB6_4: ; =>This Inner Loop Header: Depth=1
; GFX1032GISEL-NEXT: s_ff1_i32_b32 s3, s2
; GFX1032GISEL-NEXT: v_readlane_b32 s6, v0, s3
; GFX1032GISEL-NEXT: s_bitset0_b32 s2, s3
-; GFX1032GISEL-NEXT: s_sub_i32 s0, s0, s6
+; GFX1032GISEL-NEXT: s_sub_i32 s1, s1, s6
; GFX1032GISEL-NEXT: s_cmp_lg_u32 s2, 0
; GFX1032GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX1032GISEL-NEXT: .LBB6_5: ; %endif
-; GFX1032GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s1
-; GFX1032GISEL-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
-; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1032GISEL-NEXT: ; %bb.5:
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX1032GISEL-NEXT: .LBB6_6: ; %endif
+; GFX1032GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX1032GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX1032GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1032GISEL-NEXT: global_store_dword v1, v0, s[2:3]
+; GFX1032GISEL-NEXT: global_store_dword v0, v1, s[0:1]
; GFX1032GISEL-NEXT: s_endpgm
;
; GFX1164DAGISEL-LABEL: divergent_cfg:
@@ -2754,7 +2766,7 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1164GISEL: ; %bb.0: ; %entry
; GFX1164GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX1164GISEL-NEXT: s_mov_b64 s[0:1], exec
-; GFX1164GISEL-NEXT: ; implicit-def: $sgpr6
+; GFX1164GISEL-NEXT: ; implicit-def: $sgpr2
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164GISEL-NEXT: v_cmpx_le_u32_e32 16, v0
; GFX1164GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
@@ -2767,10 +2779,12 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1164GISEL-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1164GISEL-NEXT: s_sub_i32 s3, 0, s6
-; GFX1164GISEL-NEXT: s_mul_i32 s6, s3, s2
+; GFX1164GISEL-NEXT: s_mul_i32 s2, s3, s2
; GFX1164GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX1164GISEL-NEXT: s_and_not1_saveexec_b64 s[0:1], s[0:1]
-; GFX1164GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX1164GISEL-NEXT: s_or_saveexec_b64 s[0:1], s[0:1]
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s2
+; GFX1164GISEL-NEXT: s_xor_b64 exec, exec, s[0:1]
+; GFX1164GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX1164GISEL-NEXT: ; %bb.3: ; %if
; GFX1164GISEL-NEXT: s_mov_b64 s[2:3], exec
; GFX1164GISEL-NEXT: s_mov_b32 s6, 0
@@ -2782,13 +2796,14 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1164GISEL-NEXT: s_sub_i32 s6, s6, s8
; GFX1164GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX1164GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX1164GISEL-NEXT: .LBB6_5: ; %endif
+; GFX1164GISEL-NEXT: ; %bb.5:
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s6
+; GFX1164GISEL-NEXT: .LBB6_6: ; %endif
; GFX1164GISEL-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1164GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX1164GISEL-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX1164GISEL-NEXT: s_endpgm
;
; GFX1132DAGISEL-LABEL: divergent_cfg:
@@ -2838,41 +2853,45 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1132GISEL-LABEL: divergent_cfg:
; GFX1132GISEL: ; %bb.0: ; %entry
; GFX1132GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX1132GISEL-NEXT: s_mov_b32 s1, exec_lo
-; GFX1132GISEL-NEXT: ; implicit-def: $sgpr0
+; GFX1132GISEL-NEXT: s_mov_b32 s0, exec_lo
+; GFX1132GISEL-NEXT: ; implicit-def: $sgpr1
; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1132GISEL-NEXT: v_cmpx_le_u32_e32 16, v0
-; GFX1132GISEL-NEXT: s_xor_b32 s1, exec_lo, s1
+; GFX1132GISEL-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX1132GISEL-NEXT: s_cbranch_execz .LBB6_2
; GFX1132GISEL-NEXT: ; %bb.1: ; %else
-; GFX1132GISEL-NEXT: s_load_b32 s0, s[4:5], 0x2c
+; GFX1132GISEL-NEXT: s_load_b32 s1, s[4:5], 0x2c
; GFX1132GISEL-NEXT: s_mov_b32 s2, exec_lo
; GFX1132GISEL-NEXT: ; implicit-def: $vgpr0
; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
; GFX1132GISEL-NEXT: s_bcnt1_i32_b32 s2, s2
; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-NEXT: s_sub_i32 s0, 0, s0
-; GFX1132GISEL-NEXT: s_mul_i32 s0, s0, s2
+; GFX1132GISEL-NEXT: s_sub_i32 s1, 0, s1
+; GFX1132GISEL-NEXT: s_mul_i32 s1, s1, s2
; GFX1132GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX1132GISEL-NEXT: s_and_not1_saveexec_b32 s1, s1
-; GFX1132GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX1132GISEL-NEXT: s_or_saveexec_b32 s0, s0
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX1132GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s0
+; GFX1132GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX1132GISEL-NEXT: ; %bb.3: ; %if
; GFX1132GISEL-NEXT: s_mov_b32 s2, exec_lo
-; GFX1132GISEL-NEXT: s_mov_b32 s0, 0
+; GFX1132GISEL-NEXT: s_mov_b32 s1, 0
; GFX1132GISEL-NEXT: .LBB6_4: ; =>This Inner Loop Header: Depth=1
; GFX1132GISEL-NEXT: s_ctz_i32_b32 s3, s2
; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1132GISEL-NEXT: v_readlane_b32 s6, v0, s3
; GFX1132GISEL-NEXT: s_bitset0_b32 s2, s3
-; GFX1132GISEL-NEXT: s_sub_i32 s0, s0, s6
+; GFX1132GISEL-NEXT: s_sub_i32 s1, s1, s6
; GFX1132GISEL-NEXT: s_cmp_lg_u32 s2, 0
; GFX1132GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX1132GISEL-NEXT: .LBB6_5: ; %endif
-; GFX1132GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s1
-; GFX1132GISEL-NEXT: s_load_b64 s[2:3], s[4:5], 0x24
-; GFX1132GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, 0
+; GFX1132GISEL-NEXT: ; %bb.5:
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX1132GISEL-NEXT: .LBB6_6: ; %endif
+; GFX1132GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX1132GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-NEXT: global_store_b32 v1, v0, s[2:3]
+; GFX1132GISEL-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX1132GISEL-NEXT: s_endpgm
;
; GFX12DAGISEL-LABEL: divergent_cfg:
@@ -3560,7 +3579,10 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX8GISEL-NEXT: s_add_u32 s7, s2, s10
; GFX8GISEL-NEXT: .LBB9_2: ; %Flow
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8GISEL-NEXT: s_andn2_saveexec_b64 s[2:3], s[8:9]
+; GFX8GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[8:9]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s7
+; GFX8GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX8GISEL-NEXT: s_cbranch_execz .LBB9_4
; GFX8GISEL-NEXT: ; %bb.3: ; %if
; GFX8GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
@@ -3575,11 +3597,11 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX8GISEL-NEXT: s_mul_i32 s5, s5, s7
; GFX8GISEL-NEXT: s_add_u32 s4, s4, s5
; GFX8GISEL-NEXT: s_add_u32 s7, s4, s8
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX8GISEL-NEXT: .LBB9_4: ; %endif
; GFX8GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s6
; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
-; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX8GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX8GISEL-NEXT: s_endpgm
@@ -3653,25 +3675,28 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX9GISEL-NEXT: s_add_u32 s7, s2, s10
; GFX9GISEL-NEXT: .LBB9_2: ; %Flow
; GFX9GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9GISEL-NEXT: s_andn2_saveexec_b64 s[2:3], s[8:9]
+; GFX9GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[8:9]
+; GFX9GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX9GISEL-NEXT: v_mov_b32_e32 v1, s7
+; GFX9GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX9GISEL-NEXT: s_cbranch_execz .LBB9_4
; GFX9GISEL-NEXT: ; %bb.3: ; %if
-; GFX9GISEL-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x34
+; GFX9GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX9GISEL-NEXT: s_mov_b64 s[4:5], exec
; GFX9GISEL-NEXT: s_bcnt1_i32_b64 s4, s[4:5]
-; GFX9GISEL-NEXT: s_sub_i32 s4, 0, s4
-; GFX9GISEL-NEXT: s_ashr_i32 s5, s4, 31
+; GFX9GISEL-NEXT: s_sub_i32 s5, 0, s4
+; GFX9GISEL-NEXT: s_ashr_i32 s4, s5, 31
; GFX9GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9GISEL-NEXT: s_mul_i32 s6, s8, s4
-; GFX9GISEL-NEXT: s_mul_hi_u32 s7, s8, s4
-; GFX9GISEL-NEXT: s_mul_i32 s4, s9, s4
-; GFX9GISEL-NEXT: s_mul_i32 s5, s8, s5
-; GFX9GISEL-NEXT: s_add_u32 s4, s7, s4
-; GFX9GISEL-NEXT: s_add_u32 s7, s4, s5
+; GFX9GISEL-NEXT: s_mul_i32 s8, s6, s4
+; GFX9GISEL-NEXT: s_mul_i32 s4, s6, s5
+; GFX9GISEL-NEXT: s_mul_hi_u32 s6, s6, s5
+; GFX9GISEL-NEXT: s_mul_i32 s5, s7, s5
+; GFX9GISEL-NEXT: s_add_u32 s5, s6, s5
+; GFX9GISEL-NEXT: s_add_u32 s5, s5, s8
+; GFX9GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX9GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX9GISEL-NEXT: .LBB9_4: ; %endif
; GFX9GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX9GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX9GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX9GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX9GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX9GISEL-NEXT: s_endpgm
@@ -3727,25 +3752,28 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX1064GISEL: ; %bb.0: ; %entry
; GFX1064GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX1064GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v0
-; GFX1064GISEL-NEXT: ; implicit-def: $sgpr6_sgpr7
-; GFX1064GISEL-NEXT: s_and_saveexec_b64 s[8:9], vcc
-; GFX1064GISEL-NEXT: s_xor_b64 s[8:9], exec, s[8:9]
+; GFX1064GISEL-NEXT: ; implicit-def: $sgpr8_sgpr9
+; GFX1064GISEL-NEXT: s_and_saveexec_b64 s[6:7], vcc
+; GFX1064GISEL-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
; GFX1064GISEL-NEXT: s_cbranch_execz .LBB9_2
; GFX1064GISEL-NEXT: ; %bb.1: ; %else
-; GFX1064GISEL-NEXT: s_mov_b64 s[6:7], exec
-; GFX1064GISEL-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
-; GFX1064GISEL-NEXT: s_sub_i32 s6, 0, s6
-; GFX1064GISEL-NEXT: s_ashr_i32 s7, s6, 31
+; GFX1064GISEL-NEXT: s_mov_b64 s[8:9], exec
+; GFX1064GISEL-NEXT: s_bcnt1_i32_b64 s8, s[8:9]
+; GFX1064GISEL-NEXT: s_sub_i32 s8, 0, s8
+; GFX1064GISEL-NEXT: s_ashr_i32 s9, s8, 31
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064GISEL-NEXT: s_mul_hi_u32 s10, s2, s6
-; GFX1064GISEL-NEXT: s_mul_i32 s3, s3, s6
-; GFX1064GISEL-NEXT: s_mul_i32 s7, s2, s7
+; GFX1064GISEL-NEXT: s_mul_hi_u32 s10, s2, s8
+; GFX1064GISEL-NEXT: s_mul_i32 s3, s3, s8
+; GFX1064GISEL-NEXT: s_mul_i32 s9, s2, s9
; GFX1064GISEL-NEXT: s_add_u32 s3, s10, s3
-; GFX1064GISEL-NEXT: s_mul_i32 s6, s2, s6
-; GFX1064GISEL-NEXT: s_add_u32 s7, s3, s7
+; GFX1064GISEL-NEXT: s_mul_i32 s8, s2, s8
+; GFX1064GISEL-NEXT: s_add_u32 s9, s3, s9
; GFX1064GISEL-NEXT: .LBB9_2: ; %Flow
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064GISEL-NEXT: s_andn2_saveexec_b64 s[2:3], s[8:9]
+; GFX1064GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[6:7]
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s8
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s9
+; GFX1064GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX1064GISEL-NEXT: s_cbranch_execz .LBB9_4
; GFX1064GISEL-NEXT: ; %bb.3: ; %if
; GFX1064GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
@@ -3758,12 +3786,12 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX1064GISEL-NEXT: s_mul_i32 s7, s7, s4
; GFX1064GISEL-NEXT: s_mul_i32 s5, s6, s5
; GFX1064GISEL-NEXT: s_add_u32 s7, s8, s7
-; GFX1064GISEL-NEXT: s_mul_i32 s6, s6, s4
-; GFX1064GISEL-NEXT: s_add_u32 s7, s7, s5
+; GFX1064GISEL-NEXT: s_mul_i32 s4, s6, s4
+; GFX1064GISEL-NEXT: s_add_u32 s5, s7, s5
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX1064GISEL-NEXT: .LBB9_4: ; %endif
; GFX1064GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX1064GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1064GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX1064GISEL-NEXT: s_endpgm
@@ -3837,7 +3865,10 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX1032GISEL-NEXT: s_add_u32 s7, s3, s7
; GFX1032GISEL-NEXT: .LBB9_2: ; %Flow
; GFX1032GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1032GISEL-NEXT: s_andn2_saveexec_b32 s2, s8
+; GFX1032GISEL-NEXT: s_or_saveexec_b32 s2, s8
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, s7
+; GFX1032GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s2
; GFX1032GISEL-NEXT: s_cbranch_execz .LBB9_4
; GFX1032GISEL-NEXT: ; %bb.3: ; %if
; GFX1032GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
@@ -3848,14 +3879,14 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX1032GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1032GISEL-NEXT: s_mul_hi_u32 s5, s6, s3
; GFX1032GISEL-NEXT: s_mul_i32 s7, s7, s3
-; GFX1032GISEL-NEXT: s_mul_i32 s4, s6, s4
+; GFX1032GISEL-NEXT: s_mul_i32 s8, s6, s4
; GFX1032GISEL-NEXT: s_add_u32 s5, s5, s7
-; GFX1032GISEL-NEXT: s_mul_i32 s6, s6, s3
-; GFX1032GISEL-NEXT: s_add_u32 s7, s5, s4
+; GFX1032GISEL-NEXT: s_mul_i32 s4, s6, s3
+; GFX1032GISEL-NEXT: s_add_u32 s5, s5, s8
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX1032GISEL-NEXT: .LBB9_4: ; %endif
; GFX1032GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s2
-; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX1032GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1032GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX1032GISEL-NEXT: s_endpgm
@@ -3917,29 +3948,32 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX1164GISEL: ; %bb.0: ; %entry
; GFX1164GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1164GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX1164GISEL-NEXT: s_mov_b64 s[8:9], exec
-; GFX1164GISEL-NEXT: ; implicit-def: $sgpr6_sgpr7
+; GFX1164GISEL-NEXT: s_mov_b64 s[6:7], exec
+; GFX1164GISEL-NEXT: ; implicit-def: $sgpr8_sgpr9
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164GISEL-NEXT: v_cmpx_le_u32_e32 16, v0
-; GFX1164GISEL-NEXT: s_xor_b64 s[8:9], exec, s[8:9]
+; GFX1164GISEL-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
; GFX1164GISEL-NEXT: s_cbranch_execz .LBB9_2
; GFX1164GISEL-NEXT: ; %bb.1: ; %else
-; GFX1164GISEL-NEXT: s_mov_b64 s[6:7], exec
+; GFX1164GISEL-NEXT: s_mov_b64 s[8:9], exec
; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1164GISEL-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
-; GFX1164GISEL-NEXT: s_sub_i32 s6, 0, s6
+; GFX1164GISEL-NEXT: s_bcnt1_i32_b64 s8, s[8:9]
+; GFX1164GISEL-NEXT: s_sub_i32 s8, 0, s8
; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1164GISEL-NEXT: s_ashr_i32 s7, s6, 31
+; GFX1164GISEL-NEXT: s_ashr_i32 s9, s8, 31
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-NEXT: s_mul_hi_u32 s10, s2, s6
-; GFX1164GISEL-NEXT: s_mul_i32 s3, s3, s6
-; GFX1164GISEL-NEXT: s_mul_i32 s7, s2, s7
+; GFX1164GISEL-NEXT: s_mul_hi_u32 s10, s2, s8
+; GFX1164GISEL-NEXT: s_mul_i32 s3, s3, s8
+; GFX1164GISEL-NEXT: s_mul_i32 s9, s2, s9
; GFX1164GISEL-NEXT: s_add_u32 s3, s10, s3
-; GFX1164GISEL-NEXT: s_mul_i32 s6, s2, s6
-; GFX1164GISEL-NEXT: s_add_u32 s7, s3, s7
+; GFX1164GISEL-NEXT: s_mul_i32 s8, s2, s8
+; GFX1164GISEL-NEXT: s_add_u32 s9, s3, s9
; GFX1164GISEL-NEXT: .LBB9_2: ; %Flow
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-NEXT: s_and_not1_saveexec_b64 s[2:3], s[8:9]
+; GFX1164GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[6:7]
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s8
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s9
+; GFX1164GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX1164GISEL-NEXT: s_cbranch_execz .LBB9_4
; GFX1164GISEL-NEXT: ; %bb.3: ; %if
; GFX1164GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
@@ -3954,12 +3988,12 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX1164GISEL-NEXT: s_mul_i32 s5, s5, s6
; GFX1164GISEL-NEXT: s_mul_i32 s7, s4, s7
; GFX1164GISEL-NEXT: s_add_u32 s5, s8, s5
-; GFX1164GISEL-NEXT: s_mul_i32 s6, s4, s6
-; GFX1164GISEL-NEXT: s_add_u32 s7, s5, s7
+; GFX1164GISEL-NEXT: s_mul_i32 s4, s4, s6
+; GFX1164GISEL-NEXT: s_add_u32 s5, s5, s7
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX1164GISEL-NEXT: .LBB9_4: ; %endif
; GFX1164GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX1164GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1164GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX1164GISEL-NEXT: s_endpgm
@@ -4042,7 +4076,9 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX1132GISEL-NEXT: s_add_u32 s7, s3, s7
; GFX1132GISEL-NEXT: .LBB9_2: ; %Flow
; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-NEXT: s_and_not1_saveexec_b32 s2, s8
+; GFX1132GISEL-NEXT: s_or_saveexec_b32 s2, s8
+; GFX1132GISEL-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
+; GFX1132GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s2
; GFX1132GISEL-NEXT: s_cbranch_execz .LBB9_4
; GFX1132GISEL-NEXT: ; %bb.3: ; %if
; GFX1132GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
@@ -4055,13 +4091,14 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132GISEL-NEXT: s_mul_hi_u32 s7, s4, s3
; GFX1132GISEL-NEXT: s_mul_i32 s5, s5, s3
-; GFX1132GISEL-NEXT: s_mul_i32 s8, s4, s6
+; GFX1132GISEL-NEXT: s_mul_i32 s6, s4, s6
; GFX1132GISEL-NEXT: s_add_u32 s5, s7, s5
-; GFX1132GISEL-NEXT: s_mul_i32 s6, s4, s3
-; GFX1132GISEL-NEXT: s_add_u32 s7, s5, s8
+; GFX1132GISEL-NEXT: s_mul_i32 s4, s4, s3
+; GFX1132GISEL-NEXT: s_add_u32 s5, s5, s6
+; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1132GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
; GFX1132GISEL-NEXT: .LBB9_4: ; %endif
; GFX1132GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s2
-; GFX1132GISEL-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
; GFX1132GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1132GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX1132GISEL-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
index 966853f92e24d..81ee4574e5824 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
@@ -4,11 +4,11 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=0 < %s | FileCheck -check-prefixes=GFX9DAGISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX9GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1064DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1064GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1064GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1032DAGISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1032GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1164DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1164GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1164GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1132DAGISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1132GISEL %s
@@ -2267,7 +2267,7 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1064GISEL-LABEL: divergent_cfg:
; GFX1064GISEL: ; %bb.0: ; %entry
; GFX1064GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v0
-; GFX1064GISEL-NEXT: ; implicit-def: $sgpr6
+; GFX1064GISEL-NEXT: ; implicit-def: $sgpr2
; GFX1064GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1064GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
; GFX1064GISEL-NEXT: s_cbranch_execz .LBB6_2
@@ -2275,10 +2275,12 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1064GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
; GFX1064GISEL-NEXT: ; implicit-def: $vgpr0
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064GISEL-NEXT: s_mov_b32 s6, s2
+; GFX1064GISEL-NEXT: s_mov_b32 s2, s2
; GFX1064GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX1064GISEL-NEXT: s_andn2_saveexec_b64 s[0:1], s[0:1]
-; GFX1064GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX1064GISEL-NEXT: s_or_saveexec_b64 s[0:1], s[0:1]
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s2
+; GFX1064GISEL-NEXT: s_xor_b64 exec, exec, s[0:1]
+; GFX1064GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX1064GISEL-NEXT: ; %bb.3: ; %if
; GFX1064GISEL-NEXT: s_mov_b64 s[2:3], exec
; GFX1064GISEL-NEXT: s_mov_b32 s6, 0
@@ -2289,13 +2291,14 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1064GISEL-NEXT: s_max_u32 s6, s6, s8
; GFX1064GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX1064GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX1064GISEL-NEXT: .LBB6_5: ; %endif
+; GFX1064GISEL-NEXT: ; %bb.5:
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s6
+; GFX1064GISEL-NEXT: .LBB6_6: ; %endif
; GFX1064GISEL-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064GISEL-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX1064GISEL-NEXT: global_store_dword v0, v1, s[0:1]
; GFX1064GISEL-NEXT: s_endpgm
;
; GFX1032DAGISEL-LABEL: divergent_cfg:
@@ -2412,7 +2415,7 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1164GISEL: ; %bb.0: ; %entry
; GFX1164GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX1164GISEL-NEXT: s_mov_b64 s[0:1], exec
-; GFX1164GISEL-NEXT: ; implicit-def: $sgpr6
+; GFX1164GISEL-NEXT: ; implicit-def: $sgpr2
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164GISEL-NEXT: v_cmpx_le_u32_e32 16, v0
; GFX1164GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
@@ -2421,10 +2424,12 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1164GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
; GFX1164GISEL-NEXT: ; implicit-def: $vgpr0
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-NEXT: s_mov_b32 s6, s2
+; GFX1164GISEL-NEXT: s_mov_b32 s2, s2
; GFX1164GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX1164GISEL-NEXT: s_and_not1_saveexec_b64 s[0:1], s[0:1]
-; GFX1164GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX1164GISEL-NEXT: s_or_saveexec_b64 s[0:1], s[0:1]
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s2
+; GFX1164GISEL-NEXT: s_xor_b64 exec, exec, s[0:1]
+; GFX1164GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX1164GISEL-NEXT: ; %bb.3: ; %if
; GFX1164GISEL-NEXT: s_mov_b64 s[2:3], exec
; GFX1164GISEL-NEXT: s_mov_b32 s6, 0
@@ -2436,13 +2441,14 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1164GISEL-NEXT: s_max_u32 s6, s6, s8
; GFX1164GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX1164GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX1164GISEL-NEXT: .LBB6_5: ; %endif
+; GFX1164GISEL-NEXT: ; %bb.5:
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s6
+; GFX1164GISEL-NEXT: .LBB6_6: ; %endif
; GFX1164GISEL-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1164GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX1164GISEL-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX1164GISEL-NEXT: s_endpgm
;
; GFX1132DAGISEL-LABEL: divergent_cfg:
@@ -3213,16 +3219,19 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX1064GISEL-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX1064GISEL-NEXT: .LBB11_2: ; %Flow
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064GISEL-NEXT: s_andn2_saveexec_b64 s[2:3], s[8:9]
+; GFX1064GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[8:9]
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s7
+; GFX1064GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX1064GISEL-NEXT: s_cbranch_execz .LBB11_4
; GFX1064GISEL-NEXT: ; %bb.3: ; %if
; GFX1064GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064GISEL-NEXT: s_mov_b64 s[6:7], s[6:7]
+; GFX1064GISEL-NEXT: s_mov_b64 s[4:5], s[6:7]
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX1064GISEL-NEXT: .LBB11_4: ; %endif
; GFX1064GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX1064GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1064GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX1064GISEL-NEXT: s_endpgm
@@ -3318,16 +3327,20 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX1164GISEL-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX1164GISEL-NEXT: .LBB11_2: ; %Flow
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-NEXT: s_and_not1_saveexec_b64 s[2:3], s[8:9]
+; GFX1164GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[8:9]
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s7
+; GFX1164GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX1164GISEL-NEXT: s_cbranch_execz .LBB11_4
; GFX1164GISEL-NEXT: ; %bb.3: ; %if
; GFX1164GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-NEXT: s_mov_b64 s[6:7], s[4:5]
+; GFX1164GISEL-NEXT: s_mov_b64 s[4:5], s[4:5]
+; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX1164GISEL-NEXT: .LBB11_4: ; %endif
; GFX1164GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX1164GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1164GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX1164GISEL-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
index dda651251a269..6787e7a970100 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
@@ -4,11 +4,11 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=0 < %s | FileCheck -check-prefixes=GFX9DAGISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX9GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1064DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1064GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1064GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1032DAGISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1032GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1164DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1164GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1164GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1132DAGISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1132GISEL %s
@@ -2267,7 +2267,7 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1064GISEL-LABEL: divergent_cfg:
; GFX1064GISEL: ; %bb.0: ; %entry
; GFX1064GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v0
-; GFX1064GISEL-NEXT: ; implicit-def: $sgpr6
+; GFX1064GISEL-NEXT: ; implicit-def: $sgpr2
; GFX1064GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1064GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
; GFX1064GISEL-NEXT: s_cbranch_execz .LBB6_2
@@ -2275,10 +2275,12 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1064GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
; GFX1064GISEL-NEXT: ; implicit-def: $vgpr0
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064GISEL-NEXT: s_mov_b32 s6, s2
+; GFX1064GISEL-NEXT: s_mov_b32 s2, s2
; GFX1064GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX1064GISEL-NEXT: s_andn2_saveexec_b64 s[0:1], s[0:1]
-; GFX1064GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX1064GISEL-NEXT: s_or_saveexec_b64 s[0:1], s[0:1]
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s2
+; GFX1064GISEL-NEXT: s_xor_b64 exec, exec, s[0:1]
+; GFX1064GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX1064GISEL-NEXT: ; %bb.3: ; %if
; GFX1064GISEL-NEXT: s_mov_b64 s[2:3], exec
; GFX1064GISEL-NEXT: s_mov_b32 s6, -1
@@ -2289,13 +2291,14 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1064GISEL-NEXT: s_min_u32 s6, s6, s8
; GFX1064GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX1064GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX1064GISEL-NEXT: .LBB6_5: ; %endif
+; GFX1064GISEL-NEXT: ; %bb.5:
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s6
+; GFX1064GISEL-NEXT: .LBB6_6: ; %endif
; GFX1064GISEL-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064GISEL-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX1064GISEL-NEXT: global_store_dword v0, v1, s[0:1]
; GFX1064GISEL-NEXT: s_endpgm
;
; GFX1032DAGISEL-LABEL: divergent_cfg:
@@ -2412,7 +2415,7 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1164GISEL: ; %bb.0: ; %entry
; GFX1164GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX1164GISEL-NEXT: s_mov_b64 s[0:1], exec
-; GFX1164GISEL-NEXT: ; implicit-def: $sgpr6
+; GFX1164GISEL-NEXT: ; implicit-def: $sgpr2
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164GISEL-NEXT: v_cmpx_le_u32_e32 16, v0
; GFX1164GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
@@ -2421,10 +2424,12 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1164GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
; GFX1164GISEL-NEXT: ; implicit-def: $vgpr0
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-NEXT: s_mov_b32 s6, s2
+; GFX1164GISEL-NEXT: s_mov_b32 s2, s2
; GFX1164GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX1164GISEL-NEXT: s_and_not1_saveexec_b64 s[0:1], s[0:1]
-; GFX1164GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX1164GISEL-NEXT: s_or_saveexec_b64 s[0:1], s[0:1]
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s2
+; GFX1164GISEL-NEXT: s_xor_b64 exec, exec, s[0:1]
+; GFX1164GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX1164GISEL-NEXT: ; %bb.3: ; %if
; GFX1164GISEL-NEXT: s_mov_b64 s[2:3], exec
; GFX1164GISEL-NEXT: s_mov_b32 s6, -1
@@ -2436,13 +2441,14 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1164GISEL-NEXT: s_min_u32 s6, s6, s8
; GFX1164GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX1164GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX1164GISEL-NEXT: .LBB6_5: ; %endif
+; GFX1164GISEL-NEXT: ; %bb.5:
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s6
+; GFX1164GISEL-NEXT: .LBB6_6: ; %endif
; GFX1164GISEL-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1164GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX1164GISEL-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX1164GISEL-NEXT: s_endpgm
;
; GFX1132DAGISEL-LABEL: divergent_cfg:
@@ -3073,16 +3079,19 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX1064GISEL-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX1064GISEL-NEXT: .LBB9_2: ; %Flow
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064GISEL-NEXT: s_andn2_saveexec_b64 s[2:3], s[8:9]
+; GFX1064GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[8:9]
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s7
+; GFX1064GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX1064GISEL-NEXT: s_cbranch_execz .LBB9_4
; GFX1064GISEL-NEXT: ; %bb.3: ; %if
; GFX1064GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064GISEL-NEXT: s_mov_b64 s[6:7], s[6:7]
+; GFX1064GISEL-NEXT: s_mov_b64 s[4:5], s[6:7]
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX1064GISEL-NEXT: .LBB9_4: ; %endif
; GFX1064GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX1064GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1064GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX1064GISEL-NEXT: s_endpgm
@@ -3178,16 +3187,20 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX1164GISEL-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX1164GISEL-NEXT: .LBB9_2: ; %Flow
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-NEXT: s_and_not1_saveexec_b64 s[2:3], s[8:9]
+; GFX1164GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[8:9]
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s7
+; GFX1164GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX1164GISEL-NEXT: s_cbranch_execz .LBB9_4
; GFX1164GISEL-NEXT: ; %bb.3: ; %if
; GFX1164GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-NEXT: s_mov_b64 s[6:7], s[4:5]
+; GFX1164GISEL-NEXT: s_mov_b64 s[4:5], s[4:5]
+; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX1164GISEL-NEXT: .LBB9_4: ; %endif
; GFX1164GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX1164GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1164GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX1164GISEL-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
index 1ecfc082b8cbc..9ba154ca4ac3e 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
@@ -1,16 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=0 < %s | FileCheck -check-prefixes=GFX8DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=1 < %s | FileCheck -check-prefixes=GFX8GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX8GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=0 < %s | FileCheck -check-prefixes=GFX9DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=1 < %s | FileCheck -check-prefixes=GFX9GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX9GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1064DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1064GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1064GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1032DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1032GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1032GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1164DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1164GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1164GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1132DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1132GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1132GISEL %s
define amdgpu_kernel void @uniform_value(ptr addrspace(1) %out, i32 %in) {
; GFX8DAGISEL-LABEL: uniform_value:
@@ -2194,7 +2194,7 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX8GISEL-LABEL: divergent_cfg:
; GFX8GISEL: ; %bb.0: ; %entry
; GFX8GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v0
-; GFX8GISEL-NEXT: ; implicit-def: $sgpr6
+; GFX8GISEL-NEXT: ; implicit-def: $sgpr2
; GFX8GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX8GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
; GFX8GISEL-NEXT: s_cbranch_execz .LBB6_2
@@ -2205,10 +2205,12 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX8GISEL-NEXT: s_and_b32 s2, s2, 1
; GFX8GISEL-NEXT: ; implicit-def: $vgpr0
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8GISEL-NEXT: s_mul_i32 s6, s6, s2
+; GFX8GISEL-NEXT: s_mul_i32 s2, s6, s2
; GFX8GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX8GISEL-NEXT: s_andn2_saveexec_b64 s[0:1], s[0:1]
-; GFX8GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX8GISEL-NEXT: s_or_saveexec_b64 s[0:1], s[0:1]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s2
+; GFX8GISEL-NEXT: s_xor_b64 exec, exec, s[0:1]
+; GFX8GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX8GISEL-NEXT: ; %bb.3: ; %if
; GFX8GISEL-NEXT: s_mov_b64 s[2:3], exec
; GFX8GISEL-NEXT: s_mov_b32 s6, 0
@@ -2219,14 +2221,15 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX8GISEL-NEXT: s_xor_b32 s6, s6, s8
; GFX8GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX8GISEL-NEXT: .LBB6_5: ; %endif
+; GFX8GISEL-NEXT: ; %bb.5:
+; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s6
+; GFX8GISEL-NEXT: .LBB6_6: ; %endif
; GFX8GISEL-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX8GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s6
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s1
-; GFX8GISEL-NEXT: flat_store_dword v[0:1], v2
+; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
+; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
+; GFX8GISEL-NEXT: flat_store_dword v[2:3], v1
; GFX8GISEL-NEXT: s_endpgm
;
; GFX9DAGISEL-LABEL: divergent_cfg:
@@ -2272,7 +2275,7 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX9GISEL-LABEL: divergent_cfg:
; GFX9GISEL: ; %bb.0: ; %entry
; GFX9GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v0
-; GFX9GISEL-NEXT: ; implicit-def: $sgpr6
+; GFX9GISEL-NEXT: ; implicit-def: $sgpr2
; GFX9GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX9GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
; GFX9GISEL-NEXT: s_cbranch_execz .LBB6_2
@@ -2283,10 +2286,12 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX9GISEL-NEXT: s_and_b32 s2, s2, 1
; GFX9GISEL-NEXT: ; implicit-def: $vgpr0
; GFX9GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9GISEL-NEXT: s_mul_i32 s6, s6, s2
+; GFX9GISEL-NEXT: s_mul_i32 s2, s6, s2
; GFX9GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX9GISEL-NEXT: s_andn2_saveexec_b64 s[0:1], s[0:1]
-; GFX9GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX9GISEL-NEXT: s_or_saveexec_b64 s[0:1], s[0:1]
+; GFX9GISEL-NEXT: v_mov_b32_e32 v1, s2
+; GFX9GISEL-NEXT: s_xor_b64 exec, exec, s[0:1]
+; GFX9GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX9GISEL-NEXT: ; %bb.3: ; %if
; GFX9GISEL-NEXT: s_mov_b64 s[2:3], exec
; GFX9GISEL-NEXT: s_mov_b32 s6, 0
@@ -2297,13 +2302,14 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX9GISEL-NEXT: s_xor_b32 s6, s6, s8
; GFX9GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX9GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX9GISEL-NEXT: .LBB6_5: ; %endif
+; GFX9GISEL-NEXT: ; %bb.5:
+; GFX9GISEL-NEXT: v_mov_b32_e32 v1, s6
+; GFX9GISEL-NEXT: .LBB6_6: ; %endif
; GFX9GISEL-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX9GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX9GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX9GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX9GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX9GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9GISEL-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX9GISEL-NEXT: global_store_dword v0, v1, s[0:1]
; GFX9GISEL-NEXT: s_endpgm
;
; GFX1064DAGISEL-LABEL: divergent_cfg:
@@ -2349,7 +2355,7 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1064GISEL-LABEL: divergent_cfg:
; GFX1064GISEL: ; %bb.0: ; %entry
; GFX1064GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v0
-; GFX1064GISEL-NEXT: ; implicit-def: $sgpr6
+; GFX1064GISEL-NEXT: ; implicit-def: $sgpr2
; GFX1064GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc
; GFX1064GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
; GFX1064GISEL-NEXT: s_cbranch_execz .LBB6_2
@@ -2360,10 +2366,12 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1064GISEL-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
; GFX1064GISEL-NEXT: s_and_b32 s2, s2, 1
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064GISEL-NEXT: s_mul_i32 s6, s6, s2
+; GFX1064GISEL-NEXT: s_mul_i32 s2, s6, s2
; GFX1064GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX1064GISEL-NEXT: s_andn2_saveexec_b64 s[0:1], s[0:1]
-; GFX1064GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX1064GISEL-NEXT: s_or_saveexec_b64 s[0:1], s[0:1]
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s2
+; GFX1064GISEL-NEXT: s_xor_b64 exec, exec, s[0:1]
+; GFX1064GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX1064GISEL-NEXT: ; %bb.3: ; %if
; GFX1064GISEL-NEXT: s_mov_b64 s[2:3], exec
; GFX1064GISEL-NEXT: s_mov_b32 s6, 0
@@ -2374,13 +2382,14 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1064GISEL-NEXT: s_xor_b32 s6, s6, s8
; GFX1064GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX1064GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX1064GISEL-NEXT: .LBB6_5: ; %endif
+; GFX1064GISEL-NEXT: ; %bb.5:
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s6
+; GFX1064GISEL-NEXT: .LBB6_6: ; %endif
; GFX1064GISEL-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1064GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064GISEL-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX1064GISEL-NEXT: global_store_dword v0, v1, s[0:1]
; GFX1064GISEL-NEXT: s_endpgm
;
; GFX1032DAGISEL-LABEL: divergent_cfg:
@@ -2426,38 +2435,41 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1032GISEL-LABEL: divergent_cfg:
; GFX1032GISEL: ; %bb.0: ; %entry
; GFX1032GISEL-NEXT: v_cmp_le_u32_e32 vcc_lo, 16, v0
-; GFX1032GISEL-NEXT: ; implicit-def: $sgpr0
-; GFX1032GISEL-NEXT: s_and_saveexec_b32 s1, vcc_lo
-; GFX1032GISEL-NEXT: s_xor_b32 s1, exec_lo, s1
+; GFX1032GISEL-NEXT: ; implicit-def: $sgpr1
+; GFX1032GISEL-NEXT: s_and_saveexec_b32 s0, vcc_lo
+; GFX1032GISEL-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX1032GISEL-NEXT: s_cbranch_execz .LBB6_2
; GFX1032GISEL-NEXT: ; %bb.1: ; %else
-; GFX1032GISEL-NEXT: s_load_dword s0, s[4:5], 0x2c
+; GFX1032GISEL-NEXT: s_load_dword s1, s[4:5], 0x2c
; GFX1032GISEL-NEXT: s_mov_b32 s2, exec_lo
; GFX1032GISEL-NEXT: ; implicit-def: $vgpr0
; GFX1032GISEL-NEXT: s_bcnt1_i32_b32 s2, s2
; GFX1032GISEL-NEXT: s_and_b32 s2, s2, 1
; GFX1032GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1032GISEL-NEXT: s_mul_i32 s0, s0, s2
+; GFX1032GISEL-NEXT: s_mul_i32 s1, s1, s2
; GFX1032GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX1032GISEL-NEXT: s_andn2_saveexec_b32 s1, s1
-; GFX1032GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX1032GISEL-NEXT: s_or_saveexec_b32 s0, s0
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX1032GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s0
+; GFX1032GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX1032GISEL-NEXT: ; %bb.3: ; %if
; GFX1032GISEL-NEXT: s_mov_b32 s2, exec_lo
-; GFX1032GISEL-NEXT: s_mov_b32 s0, 0
+; GFX1032GISEL-NEXT: s_mov_b32 s1, 0
; GFX1032GISEL-NEXT: .LBB6_4: ; =>This Inner Loop Header: Depth=1
; GFX1032GISEL-NEXT: s_ff1_i32_b32 s3, s2
; GFX1032GISEL-NEXT: v_readlane_b32 s6, v0, s3
; GFX1032GISEL-NEXT: s_bitset0_b32 s2, s3
-; GFX1032GISEL-NEXT: s_xor_b32 s0, s0, s6
+; GFX1032GISEL-NEXT: s_xor_b32 s1, s1, s6
; GFX1032GISEL-NEXT: s_cmp_lg_u32 s2, 0
; GFX1032GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX1032GISEL-NEXT: .LBB6_5: ; %endif
-; GFX1032GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s1
-; GFX1032GISEL-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
-; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, s0
-; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1032GISEL-NEXT: ; %bb.5:
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX1032GISEL-NEXT: .LBB6_6: ; %endif
+; GFX1032GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX1032GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX1032GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1032GISEL-NEXT: global_store_dword v1, v0, s[2:3]
+; GFX1032GISEL-NEXT: global_store_dword v0, v1, s[0:1]
; GFX1032GISEL-NEXT: s_endpgm
;
; GFX1164DAGISEL-LABEL: divergent_cfg:
@@ -2508,7 +2520,7 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1164GISEL: ; %bb.0: ; %entry
; GFX1164GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
; GFX1164GISEL-NEXT: s_mov_b64 s[0:1], exec
-; GFX1164GISEL-NEXT: ; implicit-def: $sgpr6
+; GFX1164GISEL-NEXT: ; implicit-def: $sgpr2
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1164GISEL-NEXT: v_cmpx_le_u32_e32 16, v0
; GFX1164GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
@@ -2521,10 +2533,12 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1164GISEL-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
; GFX1164GISEL-NEXT: s_and_b32 s2, s2, 1
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-NEXT: s_mul_i32 s6, s6, s2
+; GFX1164GISEL-NEXT: s_mul_i32 s2, s6, s2
; GFX1164GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX1164GISEL-NEXT: s_and_not1_saveexec_b64 s[0:1], s[0:1]
-; GFX1164GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX1164GISEL-NEXT: s_or_saveexec_b64 s[0:1], s[0:1]
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s2
+; GFX1164GISEL-NEXT: s_xor_b64 exec, exec, s[0:1]
+; GFX1164GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX1164GISEL-NEXT: ; %bb.3: ; %if
; GFX1164GISEL-NEXT: s_mov_b64 s[2:3], exec
; GFX1164GISEL-NEXT: s_mov_b32 s6, 0
@@ -2536,13 +2550,14 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1164GISEL-NEXT: s_xor_b32 s6, s6, s8
; GFX1164GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX1164GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX1164GISEL-NEXT: .LBB6_5: ; %endif
+; GFX1164GISEL-NEXT: ; %bb.5:
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s6
+; GFX1164GISEL-NEXT: .LBB6_6: ; %endif
; GFX1164GISEL-NEXT: s_or_b64 exec, exec, s[0:1]
; GFX1164GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX1164GISEL-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX1164GISEL-NEXT: s_endpgm
;
; GFX1132DAGISEL-LABEL: divergent_cfg:
@@ -2592,41 +2607,45 @@ define amdgpu_kernel void @divergent_cfg(ptr addrspace(1) %out, i32 %in) {
; GFX1132GISEL-LABEL: divergent_cfg:
; GFX1132GISEL: ; %bb.0: ; %entry
; GFX1132GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GFX1132GISEL-NEXT: s_mov_b32 s1, exec_lo
-; GFX1132GISEL-NEXT: ; implicit-def: $sgpr0
+; GFX1132GISEL-NEXT: s_mov_b32 s0, exec_lo
+; GFX1132GISEL-NEXT: ; implicit-def: $sgpr1
; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1132GISEL-NEXT: v_cmpx_le_u32_e32 16, v0
-; GFX1132GISEL-NEXT: s_xor_b32 s1, exec_lo, s1
+; GFX1132GISEL-NEXT: s_xor_b32 s0, exec_lo, s0
; GFX1132GISEL-NEXT: s_cbranch_execz .LBB6_2
; GFX1132GISEL-NEXT: ; %bb.1: ; %else
-; GFX1132GISEL-NEXT: s_load_b32 s0, s[4:5], 0x2c
+; GFX1132GISEL-NEXT: s_load_b32 s1, s[4:5], 0x2c
; GFX1132GISEL-NEXT: s_mov_b32 s2, exec_lo
; GFX1132GISEL-NEXT: ; implicit-def: $vgpr0
; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1132GISEL-NEXT: s_bcnt1_i32_b32 s2, s2
; GFX1132GISEL-NEXT: s_and_b32 s2, s2, 1
; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-NEXT: s_mul_i32 s0, s0, s2
+; GFX1132GISEL-NEXT: s_mul_i32 s1, s1, s2
; GFX1132GISEL-NEXT: .LBB6_2: ; %Flow
-; GFX1132GISEL-NEXT: s_and_not1_saveexec_b32 s1, s1
-; GFX1132GISEL-NEXT: s_cbranch_execz .LBB6_5
+; GFX1132GISEL-NEXT: s_or_saveexec_b32 s0, s0
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX1132GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s0
+; GFX1132GISEL-NEXT: s_cbranch_execz .LBB6_6
; GFX1132GISEL-NEXT: ; %bb.3: ; %if
; GFX1132GISEL-NEXT: s_mov_b32 s2, exec_lo
-; GFX1132GISEL-NEXT: s_mov_b32 s0, 0
+; GFX1132GISEL-NEXT: s_mov_b32 s1, 0
; GFX1132GISEL-NEXT: .LBB6_4: ; =>This Inner Loop Header: Depth=1
; GFX1132GISEL-NEXT: s_ctz_i32_b32 s3, s2
; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1132GISEL-NEXT: v_readlane_b32 s6, v0, s3
; GFX1132GISEL-NEXT: s_bitset0_b32 s2, s3
-; GFX1132GISEL-NEXT: s_xor_b32 s0, s0, s6
+; GFX1132GISEL-NEXT: s_xor_b32 s1, s1, s6
; GFX1132GISEL-NEXT: s_cmp_lg_u32 s2, 0
; GFX1132GISEL-NEXT: s_cbranch_scc1 .LBB6_4
-; GFX1132GISEL-NEXT: .LBB6_5: ; %endif
-; GFX1132GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s1
-; GFX1132GISEL-NEXT: s_load_b64 s[2:3], s[4:5], 0x24
-; GFX1132GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, 0
+; GFX1132GISEL-NEXT: ; %bb.5:
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX1132GISEL-NEXT: .LBB6_6: ; %endif
+; GFX1132GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX1132GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-NEXT: global_store_b32 v1, v0, s[2:3]
+; GFX1132GISEL-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX1132GISEL-NEXT: s_endpgm
entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x()
@@ -3132,21 +3151,24 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX8GISEL-NEXT: s_mul_i32 s7, s3, s7
; GFX8GISEL-NEXT: .LBB9_2: ; %Flow
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8GISEL-NEXT: s_andn2_saveexec_b64 s[2:3], s[8:9]
+; GFX8GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[8:9]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s7
+; GFX8GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX8GISEL-NEXT: s_cbranch_execz .LBB9_4
; GFX8GISEL-NEXT: ; %bb.3: ; %if
; GFX8GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
; GFX8GISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX8GISEL-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
-; GFX8GISEL-NEXT: s_and_b32 s7, s6, 1
+; GFX8GISEL-NEXT: s_and_b32 s6, s6, 1
; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8GISEL-NEXT: s_mul_i32 s6, s4, s7
-; GFX8GISEL-NEXT: s_mul_i32 s7, s5, s7
+; GFX8GISEL-NEXT: s_mul_i32 s4, s4, s6
+; GFX8GISEL-NEXT: s_mul_i32 s5, s5, s6
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX8GISEL-NEXT: .LBB9_4: ; %endif
; GFX8GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s6
; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
-; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX8GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX8GISEL-NEXT: s_endpgm
@@ -3204,20 +3226,23 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX9GISEL-NEXT: s_mul_i32 s7, s3, s7
; GFX9GISEL-NEXT: .LBB9_2: ; %Flow
; GFX9GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9GISEL-NEXT: s_andn2_saveexec_b64 s[2:3], s[8:9]
+; GFX9GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[8:9]
+; GFX9GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX9GISEL-NEXT: v_mov_b32_e32 v1, s7
+; GFX9GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX9GISEL-NEXT: s_cbranch_execz .LBB9_4
; GFX9GISEL-NEXT: ; %bb.3: ; %if
; GFX9GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX9GISEL-NEXT: s_mov_b64 s[4:5], exec
; GFX9GISEL-NEXT: s_bcnt1_i32_b64 s4, s[4:5]
-; GFX9GISEL-NEXT: s_and_b32 s4, s4, 1
+; GFX9GISEL-NEXT: s_and_b32 s5, s4, 1
; GFX9GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9GISEL-NEXT: s_mul_i32 s6, s6, s4
-; GFX9GISEL-NEXT: s_mul_i32 s7, s7, s4
+; GFX9GISEL-NEXT: s_mul_i32 s4, s6, s5
+; GFX9GISEL-NEXT: s_mul_i32 s5, s7, s5
+; GFX9GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX9GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX9GISEL-NEXT: .LBB9_4: ; %endif
; GFX9GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX9GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX9GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX9GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX9GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX9GISEL-NEXT: s_endpgm
@@ -3276,20 +3301,23 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX1064GISEL-NEXT: s_mul_i32 s7, s3, s7
; GFX1064GISEL-NEXT: .LBB9_2: ; %Flow
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064GISEL-NEXT: s_andn2_saveexec_b64 s[2:3], s[8:9]
+; GFX1064GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[8:9]
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s7
+; GFX1064GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX1064GISEL-NEXT: s_cbranch_execz .LBB9_4
; GFX1064GISEL-NEXT: ; %bb.3: ; %if
; GFX1064GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX1064GISEL-NEXT: s_mov_b64 s[4:5], exec
; GFX1064GISEL-NEXT: s_bcnt1_i32_b64 s4, s[4:5]
-; GFX1064GISEL-NEXT: s_and_b32 s4, s4, 1
+; GFX1064GISEL-NEXT: s_and_b32 s5, s4, 1
; GFX1064GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1064GISEL-NEXT: s_mul_i32 s6, s6, s4
-; GFX1064GISEL-NEXT: s_mul_i32 s7, s7, s4
+; GFX1064GISEL-NEXT: s_mul_i32 s4, s6, s5
+; GFX1064GISEL-NEXT: s_mul_i32 s5, s7, s5
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX1064GISEL-NEXT: .LBB9_4: ; %endif
; GFX1064GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1064GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX1064GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1064GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX1064GISEL-NEXT: s_endpgm
@@ -3348,7 +3376,10 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX1032GISEL-NEXT: s_mul_i32 s7, s3, s7
; GFX1032GISEL-NEXT: .LBB9_2: ; %Flow
; GFX1032GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1032GISEL-NEXT: s_andn2_saveexec_b32 s2, s8
+; GFX1032GISEL-NEXT: s_or_saveexec_b32 s2, s8
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, s7
+; GFX1032GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s2
; GFX1032GISEL-NEXT: s_cbranch_execz .LBB9_4
; GFX1032GISEL-NEXT: ; %bb.3: ; %if
; GFX1032GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
@@ -3356,12 +3387,12 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX1032GISEL-NEXT: s_bcnt1_i32_b32 s3, s3
; GFX1032GISEL-NEXT: s_and_b32 s3, s3, 1
; GFX1032GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1032GISEL-NEXT: s_mul_i32 s6, s6, s3
-; GFX1032GISEL-NEXT: s_mul_i32 s7, s7, s3
+; GFX1032GISEL-NEXT: s_mul_i32 s4, s6, s3
+; GFX1032GISEL-NEXT: s_mul_i32 s5, s7, s3
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX1032GISEL-NEXT: .LBB9_4: ; %endif
; GFX1032GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s2
-; GFX1032GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1032GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX1032GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1032GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX1032GISEL-NEXT: s_endpgm
@@ -3428,21 +3459,24 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX1164GISEL-NEXT: s_mul_i32 s7, s3, s7
; GFX1164GISEL-NEXT: .LBB9_2: ; %Flow
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-NEXT: s_and_not1_saveexec_b64 s[2:3], s[8:9]
+; GFX1164GISEL-NEXT: s_or_saveexec_b64 s[2:3], s[8:9]
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s7
+; GFX1164GISEL-NEXT: s_xor_b64 exec, exec, s[2:3]
; GFX1164GISEL-NEXT: s_cbranch_execz .LBB9_4
; GFX1164GISEL-NEXT: ; %bb.3: ; %if
; GFX1164GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
; GFX1164GISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1164GISEL-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
-; GFX1164GISEL-NEXT: s_and_b32 s7, s6, 1
+; GFX1164GISEL-NEXT: s_and_b32 s6, s6, 1
; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-NEXT: s_mul_i32 s6, s4, s7
-; GFX1164GISEL-NEXT: s_mul_i32 s7, s5, s7
+; GFX1164GISEL-NEXT: s_mul_i32 s4, s4, s6
+; GFX1164GISEL-NEXT: s_mul_i32 s5, s5, s6
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX1164GISEL-NEXT: .LBB9_4: ; %endif
; GFX1164GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s6
-; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX1164GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1164GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX1164GISEL-NEXT: s_endpgm
@@ -3508,7 +3542,9 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX1132GISEL-NEXT: s_mul_i32 s7, s3, s7
; GFX1132GISEL-NEXT: .LBB9_2: ; %Flow
; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-NEXT: s_and_not1_saveexec_b32 s2, s8
+; GFX1132GISEL-NEXT: s_or_saveexec_b32 s2, s8
+; GFX1132GISEL-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
+; GFX1132GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s2
; GFX1132GISEL-NEXT: s_cbranch_execz .LBB9_4
; GFX1132GISEL-NEXT: ; %bb.3: ; %if
; GFX1132GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
@@ -3517,11 +3553,12 @@ define amdgpu_kernel void @divergent_cfg_i64(ptr addrspace(1) %out, i64 %in, i64
; GFX1132GISEL-NEXT: s_bcnt1_i32_b32 s3, s3
; GFX1132GISEL-NEXT: s_and_b32 s3, s3, 1
; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-NEXT: s_mul_i32 s6, s4, s3
-; GFX1132GISEL-NEXT: s_mul_i32 s7, s5, s3
+; GFX1132GISEL-NEXT: s_mul_i32 s4, s4, s3
+; GFX1132GISEL-NEXT: s_mul_i32 s5, s5, s3
+; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1132GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
; GFX1132GISEL-NEXT: .LBB9_4: ; %endif
; GFX1132GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s2
-; GFX1132GISEL-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
; GFX1132GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1132GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX1132GISEL-NEXT: s_endpgm
>From e25f7f02b04fa5eab193b435dd7f339f5525626a Mon Sep 17 00:00:00 2001
From: Vang Thao <Vang.Thao at amd.com>
Date: Thu, 16 Apr 2026 12:37:15 -0400
Subject: [PATCH 2/2] Remove unused check prefixes
---
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll | 21 +++++++------------
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll | 11 ++++------
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll | 21 +++++++------------
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll | 11 ++++------
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll | 11 ++++------
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll | 21 +++++++------------
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll | 11 ++++------
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll | 11 ++++------
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll | 11 ++++------
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll | 21 +++++++------------
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll | 11 ++++------
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll | 21 +++++++------------
12 files changed, 68 insertions(+), 114 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
index 0d0554266fdea..eddd57c8da852 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
@@ -3,14 +3,14 @@
; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX8GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=0 < %s | FileCheck -check-prefixes=GFX9DAGISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX9GISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1064DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1064GISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1032DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1032GISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1164DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1164GISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1132DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1132GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1064DAGISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1064GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1032DAGISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1032GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -global-isel=0 < %s | FileCheck -check-prefixes=GFX12DAGISEL %s
define amdgpu_kernel void @uniform_value(ptr addrspace(1) %out, i32 %in) {
@@ -3898,8 +3898,3 @@ endif:
store i64 %combine, ptr addrspace(1) %out
ret void
}
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; GFX10DAGISEL: {{.*}}
-; GFX10GISEL: {{.*}}
-; GFX11DAGISEL: {{.*}}
-; GFX11GISEL: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
index 10c5a7f2b42c2..0774b8b5617cc 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
@@ -7,10 +7,10 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1064GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1032DAGISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1032GISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1164DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1164GISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1132DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1132GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL %s
define amdgpu_kernel void @uniform_value(ptr addrspace(1) %out, i32 %in) {
; GFX8DAGISEL-LABEL: uniform_value:
@@ -3144,6 +3144,3 @@ endif:
store i64 %combine, ptr addrspace(1) %out
ret void
}
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; GFX11DAGISEL: {{.*}}
-; GFX11GISEL: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
index 1cca1d87c0826..eea174806f2cc 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
@@ -3,14 +3,14 @@
; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX8GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=0 < %s | FileCheck -check-prefixes=GFX9DAGISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX9GISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1064DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1064GISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1032DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1032GISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1164DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1164GISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1132DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1132GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1064DAGISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1064GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1032DAGISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1032GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -global-isel=0 < %s | FileCheck -check-prefixes=GFX12DAGISEL %s
@@ -3499,8 +3499,3 @@ endif:
store double %combine, ptr addrspace(1) %out
ret void
}
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; GFX10DAGISEL: {{.*}}
-; GFX10GISEL: {{.*}}
-; GFX11DAGISEL: {{.*}}
-; GFX11GISEL: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
index 400611e205c8a..6bc7e2873edca 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
@@ -7,10 +7,10 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1064GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1032DAGISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1032GISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1164DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1164GISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1132DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1132GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -global-isel=0 < %s | FileCheck -check-prefixes=GFX12DAGISEL %s
@@ -3581,6 +3581,3 @@ endif:
store double %combine, ptr addrspace(1) %out
ret void
}
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; GFX11DAGISEL: {{.*}}
-; GFX11GISEL: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
index a02736ec43174..29d03c068cb9a 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
@@ -7,10 +7,10 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1064GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1032DAGISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1032GISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1164DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1164GISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1132DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1132GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -global-isel=0 < %s | FileCheck -check-prefixes=GFX12DAGISEL %s
@@ -3581,6 +3581,3 @@ endif:
store double %combine, ptr addrspace(1) %out
ret void
}
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; GFX11DAGISEL: {{.*}}
-; GFX11GISEL: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
index 636ba88c5ff18..d36800f731f72 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
@@ -3,14 +3,14 @@
; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX8GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=0 < %s | FileCheck -check-prefixes=GFX9DAGISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX9GISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1064DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1064GISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1032DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1032GISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1164DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1164GISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1132DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1132GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1064DAGISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1064GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1032DAGISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1032GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -global-isel=0 < %s | FileCheck -check-prefixes=GFX12DAGISEL %s
@@ -3519,8 +3519,3 @@ endif:
store double %combine, ptr addrspace(1) %out
ret void
}
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; GFX10DAGISEL: {{.*}}
-; GFX10GISEL: {{.*}}
-; GFX11DAGISEL: {{.*}}
-; GFX11GISEL: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
index b02c6f60d4332..fda3c218a26ff 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
@@ -7,10 +7,10 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1064GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1032DAGISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1032GISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1164DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1164GISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1132DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1132GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL %s
define amdgpu_kernel void @uniform_value(ptr addrspace(1) %out, i32 %in) {
; GFX8DAGISEL-LABEL: uniform_value:
@@ -3334,6 +3334,3 @@ endif:
store i64 %combine, ptr addrspace(1) %out
ret void
}
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; GFX11DAGISEL: {{.*}}
-; GFX11GISEL: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
index 85b74fc1320fb..c01c069725151 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
@@ -7,10 +7,10 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1064GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1032DAGISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1032GISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1164DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1164GISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1132DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1132GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL %s
define amdgpu_kernel void @uniform_value(ptr addrspace(1) %out, i32 %in) {
; GFX8DAGISEL-LABEL: uniform_value:
@@ -3334,6 +3334,3 @@ endif:
store i64 %combine, ptr addrspace(1) %out
ret void
}
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; GFX11DAGISEL: {{.*}}
-; GFX11GISEL: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
index eee9c3785176b..837c9a87e4ae6 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
@@ -7,10 +7,10 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1064GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1032DAGISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1032GISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1164DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1164GISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1132DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1132GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL %s
define amdgpu_kernel void @uniform_value(ptr addrspace(1) %out, i32 %in) {
; GFX8DAGISEL-LABEL: uniform_value:
@@ -3145,6 +3145,3 @@ endif:
store i64 %combine, ptr addrspace(1) %out
ret void
}
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; GFX11DAGISEL: {{.*}}
-; GFX11GISEL: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
index 302d6bc3bfad4..71b33f9ddffa2 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
@@ -3,14 +3,14 @@
; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX8GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=0 < %s | FileCheck -check-prefixes=GFX9DAGISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX9GISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1064DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1064GISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1032DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1032GISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1164DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1164GISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1132DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1132GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1064DAGISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1064GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1032DAGISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1032GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -global-isel=0 < %s | FileCheck -check-prefixes=GFX12DAGISEL %s
define amdgpu_kernel void @uniform_value(ptr addrspace(1) %out, i32 %in) {
@@ -4174,8 +4174,3 @@ endif:
store i64 %combine, ptr addrspace(1) %out
ret void
}
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; GFX10DAGISEL: {{.*}}
-; GFX10GISEL: {{.*}}
-; GFX11DAGISEL: {{.*}}
-; GFX11GISEL: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
index 6787e7a970100..0a57975a1fa27 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
@@ -7,10 +7,10 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1064GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1032DAGISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1032GISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1164DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1164GISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1132DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1132GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL %s
define amdgpu_kernel void @uniform_value(ptr addrspace(1) %out, i32 %in) {
@@ -3275,6 +3275,3 @@ endif:
store i64 %combine, ptr addrspace(1) %out
ret void
}
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; GFX11DAGISEL: {{.*}}
-; GFX11GISEL: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
index 9ba154ca4ac3e..6a852f91da521 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
@@ -3,14 +3,14 @@
; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX8GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=0 < %s | FileCheck -check-prefixes=GFX9DAGISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX9GISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1064DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1064GISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 < %s | FileCheck -check-prefixes=GFX10DAGISEL,GFX1032DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX10GISEL,GFX1032GISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1164DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1164GISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1132DAGISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1132GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1064DAGISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1064GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1032DAGISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1032GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164DAGISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX1164GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1132DAGISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1132GISEL %s
define amdgpu_kernel void @uniform_value(ptr addrspace(1) %out, i32 %in) {
; GFX8DAGISEL-LABEL: uniform_value:
@@ -3580,8 +3580,3 @@ endif:
store i64 %combine, ptr addrspace(1) %out
ret void
}
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; GFX10DAGISEL: {{.*}}
-; GFX10GISEL: {{.*}}
-; GFX11DAGISEL: {{.*}}
-; GFX11GISEL: {{.*}}
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